TLC32041I_技术文档

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

N PACKAGE

(TOP VIEW)

14-Bit Dynamic Range ADC and DAC

Variable ADC and DAC Sampling Rate Up

to 19,200 Samples per Second

NU

RESET

EODR

NU

1

28

27

26

25

24

Switched-Capacitor Antialiasing Input Filter

and Output-Reconstruction Filter

NU

2

IN+

3

Serial Port for Direct Interface to TMS32011,

TMS320C17, TMS32020, and TMS320C25

Digital Signal Process

FSR

IN–

4

DR

AUX IN+

5

MSTR CLK

6

23 AUX IN–

Synchronous or Asynchronous ADC and

DAC Conversion Rate With Programmable

Incremental ADC and DAC Conversion

Timing Adjustments

7

22

21

20

19

18

17

16

15

V

OUT+

OUT–

DD

8

REF

DGTL GND

SHIFT CLK

EODX

9

V

CC+

CC–

10

11

12

13

14

ANLG GND

NU

Serial Port Interface to SN74299

Serial-to-Parallel Shift Register for Parallel

Interface to TMS32010, TMS320C15, or

Other Digital Processors

DX

WORD/BYTE

FSX

NU

600-Mil Wide N Package (C to C )

L

FN PACKAGE

(TOP VIEW)

2s Complement Format

CMOS Technology

PART

NUMBER

DESCRIPTION

4

3

2 1 28 27 26

Analoginterface circuit with internal reference.

Also a plug-in replacement for TLC32041.

TLC32040

5

25 IN–

DR

6

AUX IN+

AUX IN–

OUT+

24

23

22

21

20

19

MSTR CLK

Analog interface circuit without internal

reference

TLC32041

7

V

DD

8

REF

DGTL GND

SHIFT CLK

EODX

description

OUT–

9

V

10

CC+

The TLC32040 and TLC32041 are complete

analog-to-digital and digital-to-analog input/

output systems, each on a single monolithic

CMOS chip. This device integrates a bandpass

switched-capacitor antialiasing input filter, a

V

11

CC–

12 13 14 15 16 17 18

14-bit-resolution

A/D

converter,

four

microprocessor-compatible serial port modes, a

14-bit-resolution D/A converter, and a low-pass

switched-capacitor output-reconstruction filter.

NU – Nonusable; no external connection should be made to

these terminals.

AVAILABLE OPTIONS

PACKAGE

PLASTIC CHIP

T

A

PLASTIC DIP

(N)

CARRIER

(FN)

TLC32040CFN

TLC32041CFN

TLC32040CN

TLC32041CN

0°C to 70°C

TLC32040IN

TLC32041IN

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

description (continued)

The device offers numerous combinations of master clock input frequencies and conversion/sampling rates,

which can be changed via digital processor control.

Typical applications for this integrated circuit include modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling rate),

analog interface for digital signal processors (DSPs), speech recognition/storage systems, industrial process

control, biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and

instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS320C17,

TMS32020, and TMS320C25 digital signal processors, are provided. Also, when the transmit and receive

sections of the analog interface circuit (AIC) are operating synchronously, it can interface to two SN74299

serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the

TMS32010, TMS320C15, other digital signal processors, or external FIFO circuitry. Output data pulses are

emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate between

two transmitted bytes. A flexible control scheme is provided so that the functions of this integrated circuit can

be selected and adjusted coincidentally with signal processing via software control.

The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic transitional)

low-pass and high-pass filters, respectively and a fourth-order equalizer. The input filter is implemented in

switched-capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing

caused by sampled data filtering. When no filtering is desired, the entire composite filter can be switched out

of the signal path. A selectable, auxiliary, differential analog input is provided for applications where more than

one analog input is required.

The A/D and D/A converters each have 14 bits of resolution. The A/D and D/A architectures ensure no missing

codes and monotonic operation. An internal voltage reference is provided on the TLC32040 to ease the design

task and to provide complete control over the performance of this integrated circuit. The internal voltage

reference is brought out to a terminal and is available to the designer. Separate analog and digital voltage

supplies and grounds are provided to minimize noise and ensure a wide dynamic range. Also, the analog circuit

path contains only differential circuitry to keep noise to an absolute minimum. The only exception is the DAC

sample and hold, which utilizes pseudo-differential circuitry.

The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter

followed by a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed

by a continuous-time filter to eliminate images of the digitally encoded signal.

The TLC32040C and TLC32041C are characterized for operation from 0°C to 70°C, and the TLC32040I and

TLC32041I are characterized for operation from –40°C to 85°C.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

functional block diagram

Band-Pass Filter

M

U

X

Serial

Port

FSR

A/D

IN+

DR

M

U

X

IN–

EODR

AUX IN +

AUX IN –

Internal

Voltage

Reference

(TLC32040

only)

MSTR CLK

SHIFT CLK

WORD/BYTE

DX

Low-Pass Filter

FSX

+

OUT+

OUT–

–

D/A

EODX

Transmit Section

V

ANLG DTGL

GND

V

CC+ CC–

DD

GND (DIGITAL)

REF

RESET

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

ANLG GND

AUX IN+

NO.

17,18

24

Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.

I

Noninverting auxiliary analog input state. This input can be switched into the bandpass filter and A/D

converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs

replace the IN+ and IN– inputs. If the bit is a 0, the IN+ and IN– inputs are used (see the AIC DX data word

format section).

AUX IN–

DGTL GND

DR

23

9

I

Inverting auxiliary analog input (see the above AUX IN+ description)

Digital ground for all internal logic circuits. Not internally connected to ANLG GND.

5

O

I

DR is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits

from the AIC to the TMS320 serial port is synchronized with the SHIFT CLK signal.

DX

12

3

DX is used to receive the DAC input bits and timing and control information from the TMS320. This serial

transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT CLK signal.

EODR

O

End of data receive. See the WORD/BYTE description and the Serial Port Timing diagrams. During the

word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of A/D information

have been transmitted from the AIC to the TMS320 serial port. EODR can be used to interrupt a

microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable

external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus

communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,

EODR goes low after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept

low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going

signal to differentiate between the two bytes as to which is first and which is second. EODR does not occur

after secondary communication.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

Terminal Functions (continued)

TERMINAL

NAME

EODX

I/O

DESCRIPTION

NO.

11

O

End of data transmit. See the WORD/BYTE description and the Serial Port Timing diagram. During the

word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter

and control or register information have been transmitted from the TMS320 serial port to the AIC. EODX

can be used to interrupt a microprocessor upon the completion of serial communications. Also, EODX can

be used to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM,

and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel shift registers.

During the byte-mode timing, EODX goes low after the first byte has been transmitted from the TMS320

serial port to the AIC and is kept low until the second byte has been transmitted. The TMS32011 or

TMS320C17 can use this low-going signal to differentiate between the two bytes as to which is first and

which is second.

FSR

FSX

4

O

Framesyncreceive. Intheserialtransmissionmodes, whicharedescribedintheWORD/BYTEdescription,

FSR is held low during bit transmission. When FSR goes low, the TMS320 serial port begins receiving bits

from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes low. (See

Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after secondary

communication.

14

Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting bits to the AIC via

DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description, FSX

is held low during bit transmission (see the Serial Port Timing and Internal Timing Configuration diagrams).

IN+

IN–

26

25

6

I

Noninverting input to analog input amplifier stage

Inverting input to analog input amplifier stage

MSTR CLK

Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as the shift clock, the

switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration

diagram shows how these key signals are derived. The frequencies of these key signals are synchronous

submultiplesofthemasterclockfrequencytoeliminateunwantedaliasingwhenthesampledanalogsignals

are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal

Timing Configuration).

OUT+

OUT–

REF

22

21

8

O

Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or

high-impedance loads directly in either a differential or a single-ended configuration.

Inverting output of analog output power amplifier. OUT– is functionally identical with and complementary

to OUT+.

I/O

I

Internal voltage reference for the TLC32040. For the TLC32040 and TLC32041 an external voltage

reference can be applied to this terminal.

RESET

2

Reset. A reset function is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. This reset

function initiates serial communications between the AIC and DSP. The reset function initializes all AIC

registers including the control register. After a negative-going pulse on RESET, the AIC registers are

initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The

conversion rate adjust registers, TA’ and RA’, are reset to 1. The control register bits are reset as follows

(see AIC DX data word format section):

d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1

This initialization allows normal serial-port communication to occur between AIC and DSP.

SHIFT CLK

10

O

Shiftclock. SHIFT CLK is obtained by dividing the master clock signal frequency by four. SHIFT CLK is used

to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial

Port Timing and Internal Timing Configuration diagrams).

V

7

Digital supply voltage, 5 V ±5%

DD

20

19

Positive analog supply voltage, 5 V ±5%

Negative analog supply voltage, –5 V ±5%

CC+

CC–

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

Terminal Functions (continued)

TERMINAL

NAME

WORD/BYTE

I/O

DESCRIPTION

NO.

13

I

WORD/BYTE, in conjunction with a bit in the control register, is used to establish one of four serial modes.

These four serial modes are described below.

AIC transmit and receive sections are operated asynchronously.

The following description applies when the AIC is configured to have asynchronous transmit and receive

sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format section),

the transmit and receive sections are asynchronous.

L

Serial port directly interfaces with the serial port of the TMS32011 or TMS320C17 and

communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing

diagrams).

1. FSX or FSR is brought low.

2. One 8-bit byte is transmitted or one 8-bit byte is received.

3. EODX or EODR is brought low.

4. FSX or FSR emits a positive frame-sync pulse that is four shift clock cycles wide.

5. One 8-bit byte is transmitted or one 8-bit byte is received.

6. EODX or EODR is brought high.

7. FSX or FSR is brought high.

H

Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30

and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port

Timing diagrams):

1. FSX or FSR is brought low.

2. One 16-bit word is transmitted or one 16-bit word is received.

3. FSX or FSR is brought high.

4. EODX or EODR emits a low-going pulse.

AIC transmit and receive sections are operated synchronously.

If the appropriate data bit in the control register is a 1, the transmit and receive sections are configured to

be synchronous. In this case, the bandpass switched-capacitor filter and the A/D conversion timing are

derived from the TX counter A, TX counter B, and TA, TA’, and TB registers, rather than the RX counter A,

RX counter B, and RA, RA’, and RB registers. In this case, the AIC FSX and FSR timing are identical during

primary data communication; however, FSR is not asserted during secondary data communication since

there is no new A/D conversion result. The synchronous operation sequences are as follows (see Serial

Port Timing diagrams).

L

Serial port directly interfaces with the serial port of the TMS32011 or TMS320C17 and

communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing

diagrams):

1. FSX and FSR are brought low.

2. One 8-bit byte is transmitted and one 8-bit byte is received.

3. EODX and EODR are brought low.

4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide

5. One 8-bit byte is transmitted and one 8-bit byte is received.

6. EODX and EODR are brought high.

7. FSX and FSR are brought high.

H

Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30

and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port

Timing diagrams):

1. FSX and FSR are brought low.

2. One 16-bit word is transmitted and one 16-bit word is received.

3. FSX and FSR are brought high.

4. EODX or EODR emit low-going pulses.

Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional

NOR and AND gates will interface to two SN74299 serial-to-parallel shift registers. Interfacing the AIC to

the SN74299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel data

bus communications between the AIC and the digital signal processor. The operation sequence is the same

as the above sequence (see Serial Port Timing diagrams).

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

detailed description

analog input

Two sets of analog inputs are provided. Normally, the IN+ and IN– input set is used; however, the auxiliary input

set, AUX IN+ and AUX IN– , can be used if a second input is required. Each input set can be operated in either

differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain

for the IN+, IN–, AUX IN+, and AUX IN– inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either

input circuit can be selected via software control. It is important to note that a wide dynamic range is assured

by the differential internal analog architecture and by the separate analog and digital voltage supplies and

grounds.

A/D bandpass filter, A/D bandpass filter clocking, and A/D conversion timing

The A/D bandpass filter can be selected or bypassed via software control. The frequency response of this filter

is presented in the following pages. This response results when the switched-capacitor filter clock frequency

is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the

filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock

frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz.

The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many

options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX

counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master

clock input frequencies.

The A/D conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter

clock with the RX counter B. Thus, unwanted aliasing is prevented because the A/D conversion rate is an

integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are

synchronously locked.

A/D converter performance specifications

Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter

operating characteristics section of this data sheet. The realization of the A/D converter circuitry with

switched-capacitor techniques provides an inherent sample-and-hold.

analog output

Theanalogoutputcircuitryisananalogoutputpoweramplifier. Bothnoninvertingandinvertingamplifieroutputs

are brought out of this integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads

directly in either a differential or single-ended configuration.

D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing

The frequency response of this filter is presented in the following pages. This response results when the

low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter

is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output

on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.

The D/A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with

TX counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple

of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

asynchronous versus synchronous operation

If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC) are

operated asynchronously, the low-pass and band-pass filter clocks are independently generated from the

master clock signal. Also, the D/A and A/D conversion rates are independently determined. If the transmit and

receive sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass

filters. In synchronous operation, the A/D conversion timing is derived from, and is equal to, the D/A conversion

timing. (See description of WORD/BYTE in the Terminal Functions table.)

D/A converter performance specifications

Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter

operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized

with a switched-capacitor ladder.

system frequency response correction

The (sin x)/x correction circuitry is performed in the digital processor software. The system frequency response

can be corrected via DSP software to ±0.1-dB accuracy to band edge of 3000 Hz for all sampling rates. This

correction is accomplished with a first-order digital correction filter, which requires only seven TMS320

instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1%

and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x correction section for more details).

serial port

The serial port has four possible modes that are described in detail in the Terminal Functions table. These

modes are briefly described below and in the description for WORD/BYTE in the Terminal Functions Table.

The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with

the TMS32011 and TMS320C17.

The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with

the TMS32020 and the TMS320C25.

The transmit and receive sections are operated synchronously, and the serial port interfaces directly with

the TMS32011 and TMS320C17.

The transmit and receive sections are operated synchronously, and the serial port interfaces directly with

the TMS32020, TMS320C25, or two SN74299 serial-to-parallel shift registers, which can then interface in

parallel to the TMS320C10, TMS32015, to any other digital signal processor, or to external FIFO circuitry.

operation of TLC32040 with internal voltage reference

The internal reference of the TLC32040 eliminates the need for an external voltage reference and provides

overall circuit cost reduction. Thus, the internal reference eases the design task and provides complete control

over the performance of this integrated circuit. The internal reference is brought out to a terminal and is available

to the designer. To keep the amount of noise on the reference signal to a minimum, an external capacitor may

be connected between REF and ANLG GND.

operation of TLC32040 or TLC32041 with external voltage reference

REF can be driven from an external reference circuit if so desired. This external circuit must be capable of

supplying 250 µA and must be adequately protected from noise such as crosstalk from the analog input.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

reset

A reset function is provided to initiate serial communications between the AIC and DSP and allow fast,

cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the control

register. After a negative-going pulse onRESET, the AIC is initialized. This initialization allows normal serial port

communications activity to occur between AIC and DSP (see AIC DX data word format section).

loopback

This feature allows the user to test the circuit remotely. In loopback, OUT+ and OUT– are internally connected

to IN+ and IN–. Thus, the DAC bits (d15 to d2), which are transmitted to DX, can be compared with the ADC

bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits

on DX. However, in practice there is some difference in these bits due to the ADC and DAC output offsets.

In loopback, if IN+ and N– are enabled, the external signals on IN+ and IN– are ignored. If AUX IN+ and AUX

IN– are enabled, the external signals on these terminals are added to the OUT+ and OUT– signals in loopback

operation.

The loopback feature is implemented with digital signal processor control by transmitting the appropriate serial

port bit to the control register (see AIC DX data word format section).

explanation of internal timing configuration

All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock

input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing

the master clock input signal frequency by four.

Master Clock Frequency

SCF Clock Frequency

2

Contents of Counter A

SCF Clock Frequency

Contents of Counter B

Conversion Frequency

Shift Clock Frequency

Master Clock Frequency

4

TX counter A and TX counter B, which are driven by the master clock signal, determine the D/A conversion

timing. Similarly, RX counter A and RX counter B determine the A/D conversion timing. In order for the

switched-capacitor low-pass and band pass filters to meet their transfer function specifications, the frequency

of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are

not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz.

Thus, to obtain the specified filter responses, the combination of master clock frequency and TX counter A and

RX counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can

then be divided by the TX counter B and RX counter B to establish the D/A and A/D conversion timings.

TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter

B are reloaded every A/D conversion period. The TX counter B and RX counter B are loaded with the values

in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the

TA register, the TA register less the TA’ register, or the TA register plus the TA’ register. By selecting the TA

register less the TA’ register option, the upcoming conversion timing will occur earlier by an amount of time that

equals TA’ times the signal period of the master clock. By selecting the TA register plus the TA’ register option,

the upcoming conversion timing will occur later by an amount of time that equals TA’ times the signal period of

the master clock. Thus, the D/A conversion timing can be advanced or retarded. An identical ability to alter the

A/D conversion timing is provided. In this case, however, the RX counter A can be programmed via software

control with the RA register, the RA register less the RA’ register, or the RA register plus the RA’ register.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

explanation of internal timing configuration (continued)

The ability to advance or retard conversion timing is particularly useful for modem applications. This feature

allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance

signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem

frequencies.

If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both

the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A

and A/D conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive

sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA’ register, and RB

registers are not used.

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

MSTR CLK

5.184 MHz (1)

10.368 MHz (2)

SHIFT CLK

1.296 MHz (1)

2.592 MHz (2)

Divide by 4

20.736 MHz (1)

41.472 MHz (2)

TA’ Register

(6 bits)

(2’s compl)

XTAL

OSC

TMS320

DSP

TA Register

(5 bits)

Low-Pass/

Switched

Capacitor Filter

CLK= 288-kHz

Square Wave

Optional External Circuitry

for Full-Duplex Modems

Divide by 2

Adder/

Subtractor

(6 bits)

153.6 -kHz

Clock (1)

TB Register

(6 bits)

Commercial

Divide

by 135

External

Front-End

Full-Duplex

Split-Band

d , d = 0,0

d , d = 0,1

0 1

0

1

TX Counter B

‡

†

d , d = 1,1

d , d = 1,0

Filters

0

1

0 1

[TB = 40; 7.2 kHz

[TB = 36; 8.0 kHz

[TB = 30; 9.6 kHz

[TB = 20; 14.4 kHz

[TB = 15; 19.2 kHz

D/A

Conversion

Frequency

TX Counter A

[TA = 9 (1)]

[TA = 18 (2)]

(6 bits)

576-kHz

Pulses

RA’ Register

(6 bits)

(2’s compl)

RA Register

(5 bits)

Band-Pass

Switched

Divide by 2

Capacitor Filter

CLK= 288-kHz

Square Wave

Adder/

Subtractor

(6 bits)

RB Register

(6 bits)

d , d = 0,0

d , d = 0,1

0 1

0

1

RX Counter B

‡

d , d = 1,1

d , d = 1,0

0

1

[RB = 40; 7.2 kHz

[RB = 36; 8.0 kHz

[RB = 30; 9.6 kHz

[RB = 20; 14.4 kHz

[RB = 15; 19.2 kHz

A/D

Conversion

Frequency

RX Counter A

[RA = 9 (1)]

[RA = 18 (2)]

(6 bits)

576-kHz

Pulses

Master Clock Frequency

Contents of Counter A

SCF Clock Frequency

2

†

‡

Split-band filtering can alternatively be performed after the analog input function via software in the TMS320.

These control bits are described in the AIC DX data word format section.

NOTE A: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for commercially available modem split-band filter clock), popular speech

and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as

submultiples of the crystal oscillator frequency. Since these derived frequencies sre synchronous submultiples of the crystal frequency,

aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages.

Frequency 2 (41.472 MHz) is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital

signal processors.

Figure 1. Internal Timing Configuration

10

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AIC DR or DX word bit pattern

A/D or D/A MSB,

1st bit sent

1st bit sent of 2nd byte

D8 D7 D6 D5

A/D or D/A LSB

D15 D14 D13 D12 D11 D10 D9

D4

D3

D2

D1

D0

AIC DX data word format section

d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 COMMENTS

primary DX serial communication protocol

←d15 (MSB) through d2 go to the D/A

converter register

→

0

The TX and RX counter As are loaded with the TA

and RA register values. The TX and RX counter Bs

are loaded with TB and RB register values.

←d15 (MSB) through d2 go to the D/A

converter register

→

0

1

The TX and RX counter As are loaded with the TA +

TA’ and RA + RA’ register values. The TX and RX

counter Bs are loaded with TB and RB register

values. Bits d1 = 0 and d0 =1 cause the next D/A and

A/D conversion periods to be changed by the

addition of TA’ and RA’ master clock cycles, in which

TA’ and R/A’ can be positive or negative or zero (refer

to Table 1).

←d15 (MSB) through d2 go to the D/A

converter register

→

1

0

1

The TX and RX counter As are loaded with the TA –

TA’ and RA – RA’ register values. The TX and RX

counter Bs are loaded with TB and RB register

values. Bitsd1=1andd0=0causethenextD/A and

A/D conversion periods to be changed by the

subtraction of TA’ and RA’ master clock cycles, in

whichTA’andR/A’canbepositiveornegativeorzero

(refer to Table 1).

←d15 (MSB) through d2 go to the D/A

converter register

The TX and RX counter As are loaded with the TA

and RA register values. The TX and RX counter Bs

are loaded with the TB and RB register values. After

a delay of four shift clock cycles, a secondary

transmissionimmediatelyfollowstoprogramtheAIC

to operate in the desired configuration.

NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates

secondary communications upon completion of the primary communications.

Upon completion of the primary communication, FSX remains high for four SHIFT CLK cycles and then goes low and initiates the

secondary communication. The timing specifications for the primary and secondary communications are identical. In this manner, the

secondary communication, if initiated, is interleaved between successive primary communications. This interleaving prevents the

secondarycommunicationfrominterferingwiththeprimarycommunicationsandDACtiming, thuspreventingtheAICfromskippingaDAC

output. In the synchronous mode, FSR is not asserted during secondary communications.

11

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secondary DX serial communication protocol

x x | ← to TA register → | x x | ← to RA register → |

0

1

0

1

0

1

d13 and d6 are MSBs (unsigned binary)

d14 and d7 are 2’s complement sign bits

d14 and d7 are MSBs (unsigned binary)

x | ← to TA’ register → | x | ← to RA’ register

x | ← to TB register → | x | ← to RB register

→ |

x

d7 d6 d5 d4 d3 d2

Control

register

d2 = 0/1 deletes/inserts the bandpass filter

d3 = 0/1 disables/enables the loopback function

d4 = 0/1 disables/enables the AUX IN+ and AUX IN– terminals

d5 = 0/1 asynchronous/synchronous transmit receive sections

d6 = 0/1 gain control bits (see gain control section)

d7 = 0/1 gain control bits (see gain control section)

reset function

A reset function is provided to initiate serial communications between the AIC and DSP. The reset function

initializes all AIC registers, including the control register. After power has been applied to the AIC, a

negative-going pulse on RESET initializes the AIC registers to provide an 8-kHz A/D and D/A conversion rate

for a 5.184-MHz master clock input signal. The AIC, except the control register, is initialized as follows (see AIC

DX data word format section):

INITIALIZED

REGISTER

VALUE (HEX)

TA

9

1

TA’

TB

RA

RA’

RB

24

9

1

24

The control register bits are reset as follows (see AIC DX data word format section):

d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1

This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit and

receive sections are configured to operate synchronously and the user wishes to program different conversion

rates, only the TA, TA’, and TB register need to be programmed, since both transmit and receive timing are

synchronously derived from these registers (see the terminal descriptions and AIC DX word format sections).

The circuit shown below provides a reset on power up when power is applied in the sequence given under

power-upsequence. Thecircuitdependsonthepowersuppliesreachingtheirrecommendedvaluesaminimum

of 800 ns before the capacitor charges to 0.8 V above DGTL GND.

TLC32040/

TLC32041

5 V

V

CC+

200 kΩ

RESET

0.5 µF

V

CC–

–5 V

12

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power-up sequence

To ensure proper operation of the AIC, and as a safeguard against latch-up, it is recommended that a Schottky

diode with a forward voltage less than or equal to 0.4 V be connected from V to ANLG GND (see Figure 17).

CC–

Intheabsenceofsuchadiode, powershouldbeappliedinthefollowingsequence:ANLGGNDandDGTLGND,

, then V and V . Also, no input signal should be applied until after power up.

V

CC–

CC+

DD

AIC responses to improper conditions

The AIC has provisions for responding to improper conditions. These improper conditions and the response of

the AIC to these conditions are presented in Table 1 below.

AIC register constraints

The following constraints are placed on the contents of the AIC registers:

1. TA register must be ≥ 4 in word mode (WORD/BYTE = high).

2. TA register must be ≥ 5 in byte mode (WORD/BYTE = low).

3. TA’ register can be either positive, negative, or zero.

4. RA register must be ≥ 4 in word mode (WORD/BYTE = high).

5. RA register must be ≥ 5 in byte mode (WORD/BYTE = low).

6. RA’ register can be either positive, negative, or zero.

7. (TA register ± TA’ register) must be > 1.

8. (RA register ± RA’ register) must be > 1.

9. TB register must be > 1.

Table 1. AIC Responses To Improper Conditions

IMPROPER CONDITIONS

AIC RESPONSE

Reprogram TX counter A with TA register value

TA register + TA’ register = 0 or 1

TA register – TA’ register = 0 or 1

TA register + TA’ register < 0

MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX counter A, i.e., TA

register + TA’ register + 40 hex is loaded into TX counter A.

RA register + RA’ register = 0 or 1

RA register – RA’ register = 0 or 1

Reprogram RX counter A with RA register value

RA register + RA’ register = 0 or 1

MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX counter A, i.e., RA

register + RA’ register + 40 hex is loaded into RX counter A.

TA register = 0 or 1

RA register = 0 or 1

The AIC is shut down.

TA register < 4 in word mode

TA register < 5 in byte mode

RA register < 4 in word mode

RA register < 5 in byte mode

The AIC serial port no longer operates.

TB register = 0 or 1

Reprogram TB register with 24 hex

Reprogram RB register with 24 hex

Hold last DAC output

RB register = 0 or 1

AIC and DSP cannot communicate

13

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improper operation due to conversion times being too close together

If the difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the AIC operates

improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there is not enough

time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly

programmed or if the A + A’ register or A – A’ register result is too small. When incrementally adjusting the

conversion period via the A + A’ register options, the designer should be very careful not to violate this

requirement (see following diagram).

t

1

t

2

Frame Sync

FSX or FSR

Ongoing Conversion

t

2

– t

1/19.2 kHz

1

asynchronous operation — more than one receive frame sync occurring between two transmit

frame syncs

When incrementally adjusting the conversion period via the A + A’ or A – A’ register options, a specific protocol

is followed. The command to use the incremental conversion period adjust option is sent to the AIC during a

FSX frame sync. The ongoing conversion period is then adjusted. However, either receive conversion period

A or B may be adjusted. For both transmit and receive conversion periods, the incremental conversion period

adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between

t and t , the receive conversion period adjustment is performed during receive conversion period A. Otherwise,

1

2

the adjustment is performed during receive conversion period B. The adjustment command only adjusts one

transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive

conversion periods, another command must be issued during a subsequent FSX frame (see figure below).

t

1

FSX

Transmit Conversion Period

t

2

FSR

Receive

Conversion

Period A

Receive

Conversion

Period B

14

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asynchronous operation — more than one receive frame sync occurring between two receive frame syncs

When incrementally adjusting the conversion period via the A + A’ or A – A’ register options, a specific protocol

is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment

is performed near the end of the conversion period. The command to use the incremental conversion period

adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion period is then

adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as

shown in the following figure. If the adjustment command is issued during transmit conversion period A, receive

conversion period A is adjusted if there is sufficient time between t and t . Or, if there is not sufficient time

1

2

between t and t , receive conversion period B is adjusted. Or, the receive portion of an adjustment command

1

2

can be ignored if the adjustment command is sent during a receive conversion period, which is already being

or is adjusted due to a prior adjustment command. For example, if adjustment commands are issued during

transmit conversion periods A, B, and C, the first two commands can cause receive conversion periods A and

B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is

ignored since it was issued during receive conversion period B, which already is adjusted via the transmit

conversion period B adjustment command.

t

1

FSX

FSR

Transmit

Conversion

Period A

Transmit

Conversion

Period B

Transmit

Conversion

Period C

t

2

Receive Conversion Period A

Receive Conversion Period B

asynchronous operation — more than one set of primary and secondary DX serial communication occurring

between two receive frame sync (see AIC DX data word format section)

The TA, TA’, TB, and control register information that is transmitted in the secondary communications is always

accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t and

1

t , the TA, RA’, and RB register information, which is sent during transmit conversion period A, is applied to

2

receive conversion period A. Otherwise, this information is applied during receive conversion period B. If RA,

RA’, and RB register information has already been received and is being applied during an ongoing conversion

period, any subsequent RA, RA’, or RB information that is received during this receive conversion period is

disregarded (see diagram below).

t

1

Primary

Secondary

Primary

Secondary

Primary

Secondary

FSX

FSR

Transmit

Conversion

Period A

Transmit

Conversion

Period B

Transmit

Conversion

Period C

t

2

Receive Conversion

Period A

Receive Conversion Period B

15

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Table 2. Gain Control Table Analog Input Signal Required for Full-Scale A/D Conversion

CONTROL REGISTER BITS

A/D CONVERSION

†

INPUT CONFIGURATIONS

ANALOG INPUT

d6

1

d7

1

RESULT

±6 V

Full scale

Differential configuration

Analog input = IN+ – IN–

= AUX IN+ – AUX IN–

0

1

0

±3 V

Full scale

0

1

±1.5 V

1

±3 V

Half scale

Single-ended configuration

Analog input = IN+ – ANLG GND

= AUX IN+ – ANLG GND

0

1

0

±3 V

Full scale

0

1

±1.5 V

†

In this example, V is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full

ref

scale.

R

fb

R

fb

R

–

+

–

+

AUX IN+

AUX IN–

+

–

IN+

IN–

+

–

To Multiplexer

R

fb

R

fb

R

= R for d6 = 1, d7 = 1

d6 = 0, d7 = 0

= 2R for d6 = 1, d7 = 0

= 4R for d6 = 0, d7 = 1

fb

R

= R for d6 = 1, d7 = 1

d6 = 0, d7 = 0

= 2R for d6 = 1, d7 = 0

= 4R for d6 = 0, d7 = 1

fb

R

fb

R

fb

Figure 2. IN+ and IN– Gain

Control Circuitry

Figure 3. AUX IN+ and AUX IN–

Gain Control Circuitry

(sin x)/x correction section

The AIC does not have (sin x)/x correction circuitry after the digital-to-analog converter.The (sin x)/x correction

can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction

accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results,

which are shown below, are typical of the numerical correction accuracy that can be achieved for sample rates

of interest. The filter requires only seven instruction cycles per sample on the TMS320 DSPs. With a 200-ns

instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling

rates of 8000 Hz and 9600 Hz, respectively. This correction adds a slight amount of group delay at the upper

edge of the 300–3000-Hz band.

16

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(sin x)/x roll-off for a zero-order hold function

The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the

various sampling rates is shown in the table below.

Table 3. (sin x)/x Roll-Off

20 log

sin π f/f

π f/f

s

f

s

(Hz)

(f = 3000 Hz)

(dB)

7200

8000

9600

–2.64

–2.11

–1.44

–0.63

–0.35

14400

19200

The actual AIC (sin x)/x roll-off is slightly less than the above figures, because the AIC has less than a 100%

duty cycle hold interval.

correction filter

To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter shown below, is recommended.

+

u

y

(i + 1)

+

z – 1

(1 – p1)P2

p1

The difference equation for this correction filter is:

yi + 1 = p2(1 – p1) (u ) + p1 yi

i + 1

where the constant p1 determines the pole locations.

The resulting squared magnitude transfer function is:

p2²(1 p1)²

|H(f)|²

1

2p1 cos(2 f f_s)

p1²

17

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correction results

Table 4 below shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz

sampling rates.

Table 4. Correction Results

ERROR (dB)

= 8000 Hz

p1 = –0.14813

p2 = 0.9888

ERROR (dB)

= 9600 Hz

p1 = –0.1307

p2 = 0.9951

f

s

f

s

f (Hz)

300

600

–0.099

–0.089

–0.054

–0.002

0.041

–0.043

0

900

1200

1500

1800

2100

2400

2700

3000

0

0.079

0.043

0

0.100

0.091

–0.043

–0.102

–0.043

TMS320 software requirements

The digital correction filter equation can be written in state variable form as follows:

Y = k1 × Y + k2 × U

where

k1 = p1

k2 = (1 – p1) × p2

Y = filter state

U = next I/O sample

The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift)

will yield the correct result. With the assumption that the TMS320 processor page pointer and memory

configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with

the following program:

ZAC

LT K2

MPY U

LTA K1

MPY Y

APAC

SACH (dma), (shift)

18

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†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V

CC+

DD

Output voltage range, V

O

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V

I

Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V

Operating free-air temperature range, T : TLC32040C, TLC32041C . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

TLC32040I, TLC32041 . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C

stg

Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Voltage values for maximum ratings are with respect to V

..

CC–

recommended operating conditions

MIN NOM

MAX

5.25

UNIT

V

Supply voltage, V

(see Note 2)

4.75

–4.75

4.75

5

–5

5

CC+

CC–

–5.25

5.25

V

Digital supply voltage, V

(see Note 2)

V

DD

Digital ground voltage with respect to ANLG GND, DGTL GND

0

V

Reference input voltage, V

(see Note 2)

2

4

V

ref(ext)

High-level input voltage, V

V

+0.3

DD

0.8

V

IH

Low-level input voltage, V (see Note 3)

IL

–0.3

300

V

Load resistance at OUT+ and/or OUT–, R

Ω

L

Load capacitance at OUT+ and/or OUT–, C

MSTR CLK frequency (see Note 4)

100

pF

MHz

V

L

0.075

5

10.368

±1.5

20

Analog input amplifier common mode input voltage (see Note 5)

A/D or D/A conversion rate

kHz

TLC32040C, TLC32041C

TLC32040I, TLC32041I

0

70

Operating free-air temperature, T

°C

A

–40

85

NOTES: 2. Voltagesatanaloginputsandoutputs, REF, V

and V are with respect to DGTL GND.

, and V are with respect to ANLG GND. Voltagesatdigitalinputsandoutputs

CC+ CC–,

DD

3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for

logic voltage levels and temperature only.

4. The bandpass low-pass switched-capacitor filter response specifications apply only when the switched-capacitor clock frequency

is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of

switched-capacitor filter clock frequency to 288 kHz.

5. This range applies when (IN+ – IN–) or (AUX IN+ – AUX IN–) equals ± 6 V.

19

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electrical characteristics over recommended operating free-air temperature range, V

= 5 V,

CC+

V

= –5 V, V

= 5 V (unless otherwise noted)

CC–

DD

total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded

†

TYP

PARAMETER

High-level output voltage

Low-level output voltage

TEST CONDITIONS

MIN

MAX

UNIT

V

= 4.75 V,

I

= –300 µA

2.4

OH

DD

OH

= 2 mA

0.4

35

V

OL

DD

OL

TLC3204_C

TLC3204_I

TLC3204_C

TLC3204_I

I

Supply current from V

mA

CC+

40

–35

–40

7

I

Supply current from V

CC–

DD

f

= 5.184 MHz

mA

V

DD

MSTR CLK

V

ref

Internal reference output voltage

3

3.3

Temperature coefficient of internal reference voltage

Output resistance at REF

200

100

ppm/°C

kΩ

Vref

r

o

receive amplifier input

†

PARAMETER

TEST CONDITIONS

MIN

MAX

65

UNIT

mV

TYP

A/D converter offset error (filters bypassed)

A/D converter offset error (filters in)

25

65

mV

Common-mode rejection ratio at IN+, IN–, or AUX IN+,

AUX IN–

CMRR

See Note 6

55

dB

r

l

Input resistance at IN+, IN–, or AUX IN+,AUX IN–, REF

100

kΩ

transmit filter output

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Output offset voltage at OUT+, OUT–, (single-ended

relative to ANLG GND)

V

OO

V

OM

V

OM

15

75

mV

Maximum peak output voltage swing across R at OUT+

L

or OUT–, (single ended)

R

≥ 300 Ω, Offset voltage = 0

≥ 600 Ω

±3

±6

V

L

Maximum peak output voltage swing between R at OUT+

L

and OUT–, (differential output)

system distortion specifications, SCF clock frequency = 288 kHz

†

PARAMETER

TEST CONDITIONS

MIN

62

MAX

UNIT

TYP

Single ended

Differential

70

65

70

65

Attenuation of second harmonic of A/D

input signal

V = –0.5 dB to –24 dB referred to V

I

See Note 7

,

ref

dB

Single ended

Differential

Attenuation of third and higher harmonics

of A/D input signal

V = –0.5 dB to –24 dB referred to V

I

See Note 7

ref

dB

57

Single ended

Differential

Attenuation of second harmonic of D/A

input signal

V = –0 dB to –24 dB referred to V

I

See Note 7

,

ref

62

Single ended

Differential

Attenuation of third and higher harmonics

of D/A input signal

V = –0 dB to –24 dB referred to V

I

See Note 7

ref

57

†

All typical values are at T = 25°C.

A

NOTES: 6. The test condition is a 0-dBm, 1-kHz input signal with an 8-kHz conversion rate.

7. The test condition V is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V ). The load impedance for the DAC

I

ref

is 600 Ω.

20

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A/D channel signal-to-distortion ratio

†

= 4

A

= 1

A

= 2

A

v

TEST CONDITIONS

(see Note 7)

v

PARAMETER

UNIT

MIN

58

56

50

44

38

32

26

20

MAX

MIN

MAX

MIN

MAX

§

>58

§

V = –6 dB to –0.1 dB

>58

I

§

V = –12 dB to –6 dB

58

56

50

44

38

32

26

I

V = –18 dB to –12 dB

58

56

50

44

38

32

I

V = –24 dB to –18 dB

I

A/D channel signal-to-distortion ratio

V = –30 dB to –24 dB

dB

I

V = –36 dB to –30 dB

I

V = –42 dB to –36 dB

I

V = –48 dB to –42 dB

I

V = –54 dB to –48 dB

I

D/A channel signal-to-distortion ratio

TEST CONDITIONS

(see Note 7)

PARAMETER

MIN

UNIT

V = –6 dB to 0 dB

58

56

50

44

38

32

26

20

I

V = –12 dB to –6 dB

I

V = –18 dB to –12 dB

I

V = –24 dB to –18 dB

I

D/A channel signal-to-distortion ratio

V = –30 dB to –24 dB

dB

I

V = –36 dB to –30 dB

I

V = –42 dB to –36 dB

I

V = –48 dB to –42 dB

I

V = –54 dB to –48 dB

I

gain and dynamic range

‡

TYP

PARAMETER

TEST CONDITIONS

MIN

UNIT

dB

Absolute transmit gain tracking error

while transmitting into 600 Ω

–48-dB to 0-dB signal range, See Note 8

±0.05 ±0.15

0.2

Absolute receive gain tracking error

dB

Signal input is a –0.5-dB,

1-kHz sinewave

Absolute gain of the A/D channel

dB

Signal input is a 0-dB,

1-kHz sinewave

Absolute gain of the D/A channel

–0.3

dB

power supply rejection and crosstalk attenuation

‡

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

f = 0 to 30 kHz

30

45

V

or V

supply voltage

CC–

Idle channel, supply signal at 200 mV p-p

measured at DR (ADC output)

CC+

rejection ratio, receive channel

dB

f = 30 kHz to 50 kHz

V

or V supply voltage

f = 0 to 30 kHz

30

CC+

CC–

Idle channel, supply signal at 200 mV p-p

measured at OUT+

rejection ratio, transmit channel

(single ended)

dB

f = 30 kHz to 50 kHz

45

80

Crosswalk attenuation, transmit-to-receive (single ended)

†

‡

§

A is the programmable gain of the input amplifier.

v

All typical values are at T = 25°C.

A

A value >58 is overrange and signal clipping occurs.

NOTES: 7. The test condition V is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V ). The load impedance for the DAC

in ref

is 600 Ω.

8. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to V ).

ref

21

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delay distortion, SCF clock frequency = 288 kHz ±2%, input (IN+ – IN–) is ±3-V sinewave

Refer to filter response graphs for delay distortion specifications.

TLC32040 and TLC32041 bandpass filter transfer function (see curves),

SCF clock frequency = 288 kHz, ±2%, input (IN+ – IN–) is a ±3-V sinewave (see Note 9)

FREQUENCY

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

RANGE

f = 100 Hz

–42

–25

0.5

f = 170 Hz

Filter gain, (see Note 10)

Input signal reference is 0 dB

300 Hz ≤ f ≤ 3.4 kHz

f = 4 kHz

–0.5

dB

–16

–58

f ≥ 4.6 kHz

low-pass filter transfer function, SCF clock frequency = 288 kHz ±2% (see Note 9)

FREQUENCY

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

RANGE

f ≤ 3.4 kHz

–0.5

0.5

–4

f = 3.6 kHz

f = 4 kHz

f ≥ 4.4 kHz

Filter gain, (see Note 10)

Output signal reference is 0 dB

dB

–30

–58

serial port

†

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V

TYP

V

High-level output voltage

Low-level output voltage

Input current

I

= –300 µA

2.4

OH

= 2 mA

0.4

V

OL

I

±10

µA

pF

C

Input capacitance

15

i

Output capacitance

o

operating characteristics over recommended operating free-air temperature range, V

= 5 V,

CC+

V

= –5 V, V

= 5 V

CC–

DD

noise (measurement includes low-pass and bandpass switched-capacitor filters)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Single ended

Differential

200

300

20

µV rms

DX input = 00000000000000,

constant input code

Transmit noise

500 µV rms

dBrncO

300

20

475 µV rms

dBrncO

Receive noise (see Note 11)

Inputs grounded, gain = 1

†

All typical values are at T = 25°C.

A

NOTES: 9. The above filter specifications are for a switched-capacitor filter clock range of 288 kHz ±2%. For switched-capacitor filter clocks

at frequencies other than 288 kHz ±2%, the filter response is shifted by the ratio of switched-capacitor filter clock frequency to

288 kHz.

10. The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured

with respect to the average gain within the passband. The passbands are 300 to 3400 Hz and 0 to 3400 Hz for the bandpass and

low-pass filters respectively.

11. The noise is reffered to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure is correspondingly reduced.

The noise is computed by statistically evaluating the digital output of the A/D converter.

22

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timing requirements

serial port recommended input signals

MIN

MAX

UNIT

ns

t

Master clock cycle time

95

c(MCLK)

r(MCLK)

f(MCLK)

Master clock rise time

10

ns

Master clock fall time

ns

Master clock duty cycle

42%

800

20

58%

RESET pulse duration (see Note 12)

DX setup time before SCLK↓

DX hold time after SCLK↓

ns

t

su(DX)

t

h(DX)

c(SCLK)/4

serial port – AIC output signals, C = 30 pF for SHIFT CLK output, C = 15 pF for all other outputs

L

†

MIN TYP

MAX

UNIT

ns

%

t

Shift clock (SCLK) cycle time

Shift clock (SCLK) fall time

Shift clock (SCLK) rise time

Shift clock (SCLK) duty cycle

380

c(SCLK)

f(SCLK)

r(SCLK)

3

8

45

55

t

Delay from SCLK↑ to FSR/FSX/FSD↓

Delay from SCLK↑ to FSR/FSX/FSD↑

DR valid after SCLK↑

30

35

ns

d(CH-FL)

d(CH-FH)

d(CH-DR)

d(CH-EL)

d(CH-EH)

f(EODX)

90

8

Delay from SCLK↑ to EODX/EODR↓ in word mode

Delay from SCLK↑ to EODX/EODR↑ in word mode

EODX fall time

2

EODR fall time

8

f(EODR)

Delay from SCLK↑ to EODX/EODR↓ in byte mode

Delay from SCLK↑ to EODX/EODR↑ in byte mode

Delay from MSTR CLK↑ to SCLK↓

Delay from MSTR CLK↑ to SCLK↑

90

170

d(CH-EL)

d(CH-EH)

d(MH-SL)

d(MH-SH)

65

†

Typical values are at T = 25°C.

A

NOTE 12: RESET pulse duration is the amount of time that the reset terminal is held below 0.8 V after the power supplies have reached their

recommended values.

23

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SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

serial port – AIC output signals

†

TEST CONDITIONS

MIN TYP

MAX

UNIT

ns

%

t

Shift clock (SCLK) cycle time

380

c(SCLK)

f(SCLK)

r(SCLK)

Shift clock (SCLK) fall time

50

Shift clock (SCLK) rise time

Shift clock (SCLK) duty cycle

45

55

t

Delay from SCLK↑ to FSR/FSX↓

Delay from SCLK↑ to FSR/FSX↑

DR valid after SCLK↑

C

= 50 pF

52

ns

d(CH-FL)

d(CH-FH)

d(CH-DR)

d(CH-EL)

d(CH-EH)

f(EODX)

L

52

90

Delay from SCLK↑ to EODX/EODR↓ in word mode

Delay from SCLK↑ to EODX/EODR↑ in word mode

EODX fall time

90

15

EODR fall time

15

f(EODR)

Delay from SCLK↑ to EODX/EODR↓ in byte mode

Delay from SCLK↑ to EODX/EODR↑ in byte mode

Delay from MSTR CLK↑ to SCLK↓

Delay from MSTR CLK↑ to SCLK↑

100

d(CH-EL)

d(CH-EH)

d(MH-SL)

d(MH-SH)

65

†

Typical values are at T = 25°C.

A

24

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SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

t

f(SCLK)

t

c(SCLK)

r(SCLK)

2 V

SHIFT CLK

0.8 V

t

d(CH-FL)

t

d(CH-FH)

2 V

FSR, FSX

0.8 V

t

d(CH-DR)

2 V

D13

DR

DX

D15

D14

D9

D8

D7

D6

D2

D1

D0

t

su(DX)

Don’t Care

D15

D14 D13

D9

D8

D6

t

h(DX)

t

d(CH-EH)

d(CH-EL)

0.8 V

2 V

EODR, EODX

(a) BYTE-MODE TIMING

t

c(SCLK)

2 V

SHIFT CLK

0.8 V

0.8 V 0.8 V

t

d(CH-FH)

t

d(CH-FL)

FSX, FSR

DR

0.8 V

t

d(CH-DR)

D15

D14

D13

D12 D11

D2

D1

D0

t

su(DX)

Don’t Care

D15

D14

D12

t

D11

D1

D0

DX

t

d(CH-EL)

h(DX)

t

d(CH-EH)

2 V

EODR, EODX

0.8 V

(b) WORD-MODE TIMING

MSTR CLK

SHIFT CLK

t

d(MH-SL)

d(MH-SH)

(c) SHIFT-CLOCK TIMING

Figure 4. Serial Port Timing

25

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PARAMETER MEASUREMENT INFORMATION

CLK OUT

DEN

S0, G1

Valid

D0–D15

(a) IN INSTRUCTION TIMING

CLK OUT

WE

SN74LS138 Y1

SN74LS299 CLK

D0–D15

Valid

(b) OUT INSTRUCTION TIMING

Figure 5. TMS32010-TLC32040/TLC32041 Interface Timing

26

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SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

TYPICAL CHARACTERISTICS

AIC TRANSMIT CHANNEL FILTER

Magnitude

10

0

0.3

0.25

0.2

–10

–20

–30

–40

–50

–60

–70

–80

–90

Group Delay

0.15

0.1

See Note B

0.05

0

0.05

See Note A

See Note C

0.1

0.15

0.2

0

1

2

3

4

5

SCF clock frequency

288 kHz

Normalized Frequency – kHz ×

NOTES: A. Maximum relative delay (0 Hz to 600 Hz) = 125 µs

B. Maximum relative delay (600 Hz to 3000 Hz) = ± 50 µs

C. Absolute delay (600 Hz to 3000 Hz) = 700 µs

D. Test conditions are V

, V

, and V

within recommended operating conditions, SCF clock f = 288 kHz ±2% input = ±3-V

CC+ CC–

DD

sinewave, and T = 25°C.

A

Figure 6

27

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TYPICAL CHARACTERISTICS

TLC32040 AND TLC32041

RECEIVE CHANNEL FILTER

10

0

0.35

0.3

See Note A

Magnitude

0.25

0.2

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.15

0.1

Group Delay

0.05

0

0.05

0.1

See Note B

See Note C

2

0.15

0

1

3

4

5

SCF clock frequency

288 kHz

Normalized Frequency – kHz ×

NOTES: A. Maximum relative delay (200 Hz to 600 Hz) = 3350 µs

B. Maximum relative delay (600 Hz to 3000 Hz) = ± 50 µs

C. Absolute delay (600 Hz to 3000 Hz) = 1230 µs

D. Test conditions are V

, V

sinewave, and T = 25°C.

, and V

within recommended operating conditions, SCF clock f = 288 kHz ±2%, input = ±3-V

CC+ CC–

DD

A

Figure 7

28

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SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

TYPICAL CHARACTERISTICS

A/D SIGNAL-TO-DISTORTION RATIO

A/D GAIN TRACKING

(GAIN RELATIVE TO GAIN

AT 0-dB INPUT SIGNAL)

vs

INPUT SIGNAL

80

70

60

50

40

30

0.5

0.4

0.3

0.2

0.1

0

1-kHz Input Signal With an

8-kHz Conversion Rate

1-kHz Input Signal

8-kHz Conversion Rate

Gain = 4X

Gain = 1X

– 0.1

– 0.2

– 0.3

– 0.4

– 0.5

20

10

0

– 50

– 40

– 30

–20

–10

0

10

– 50

– 40

– 30

– 20

– 10

0

10

Input Signal Relative to V – dB

ref

Input Signal Relative to V – dB

ref

Figure 8

Figure 9

D/A GIAN TRACKING

vs

D/A CONVERTER SIGNAL-TO-DISTORTION RATIO

(GAIN RELATIVE TO GAIN

AT 0 0dB INPUT SIGNAL)

vs

INPUT SIGNAL

1.0

0.8

0.6

0.4

0.2

0

100

1-kHz Input Signal into 600 Ω

8-kHz Conversion Rate

1-kHz Input Signal into 600 Ω

8-kHz Conversion Rate

90

80

70

60

50

40

30

– 0.2

– 0.4

– 0.6

– 0.8

– 1

20

10

0

–50

–40

–30

–20

–10

0

10

–50

–40

–30

–20

–10

0

10

Input Signal Relative to V – dB

ref

Input Signal Relative to V – dB

ref

Figure 10

Figure 11

NOTE: Test conditions are V

, V

and within recommended operating conditions set clock f = 288 kHz ±2%, and T = 25°C.

CC+ CC– DD

A

29

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ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

TYPICAL CHARACTERISTICS

ATTENUATION OF THIRD HARMONIC OF A/D INPUT

ATTENUATION OF SECOND HARMONIC OF A/D INPUT

vs

INPUT SIGNAL

100

90

80

70

60

50

40

30

1-kHz Input Signal

8-kHz Conversion Rate

90

80

70

60

50

40

30

20

1-kHz Input Signal

10

0

8-kHz Conversion Rate

0

10

–50

–40

–30

–20

–10

–50

–40

–30

–20

–10

0

10

Input Signal Relative to V – dB

ref

Input Signal Relative to V – dB

ref

Figure 13

Figure 12

ATTENUATION OF SECOND HARMONIC OF D/A INPUT

ATTENUATION OF THIRD HARMONIC OF D/A INPUT

vs

INPUT SIGNAL

100

1-kHz Input Signal into 600 Ω

8-kHz Conversion Rate

1-kHz Input Signal into 600 Ω

8-kHz Conversion Rate

90

80

70

60

50

40

30

80

70

60

50

40

30

20

10

0

10

0

10

–50

–40

–30

–20

–10

0

10

–50

–40

–30

–20

–10

Input Signal Relative to V – dB

ref

Input Signal Relative to V – dB

ref

Figure 14

Figure 15

NOTE: Test conditions are V

, V

, and V

within recommended operating conditions set clock f = 288 kHz ±2%, and T = 25°C.

DD A

CC+ CC–

30

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TLC32040C, TLC32040I, TLC32041C, TLC32041I

ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

APPLICATION INFORMATION

FSX

DX

Q

2D

C2

TMS32010

SN74LS299

S1

Q

H

G2

S0

G1

DEN

TLC32040/

TLC32041

G1

A

Y1

Y0

CLK

A0/PA0

A1/PA1

A2/PA2

D8–D15

B

A-H SR

C

SHIFT CLK

SN74LS299

S1

SN74LS138

Q

H

G2

S0

G1

CLK

SN74LS74

C1

D0–D15

D0–D7

A-H

D0–D15

WE

SR

Q

1D

DR

MSTR CLK

EODX

CLKOUT

INT

Figure 16. TMS32010-TLC32040/TLC32041 Interface Circuit

31

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ANALOG INTERFACE CIRCUITS

SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995

APPLICATION INFORMATION

TMS32020/C25

TLC32040/TLC32041

MSTR CLK

CLKOUT

FSX

V

5 V

CC+

REF

FSX

C

DX

ANLG GND

†

BAT 42

FSR

C

DR

V

–5 V

5 V

CC–

CLKR

CLKX

SHIFT CLK

V

DD

0.1 µF

DGTL GND

C = 0.2 µF, Ceramic

†

Thomson Semiconductors

†

Figure 17. AIC Interface to the TMS32020/C25 Showing Decoupling Capacitors and Schottky Diode

V

CC

R

3 V Output

500 Ω

0.1 µF Ceraminc

TL431

0.01 µF

2500 Ω

For:

V

CC

V

CC

V

CC

= 12 V, R = 7200 Ω

= 10 V, R = 5600 Ω

= 5 V, R = 1600 Ω

Figure 18. External Reference Circuit For TLC32045

32

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IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

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型号：	TLC32041I
厂家：	TEXAS INSTRUMENTS
描述：	ANALOG INTERFACE CIRCUITS 模拟接口电路
文件：	总33页 (文件大小：453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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