TLC34058_技术文档

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

• LinEPIC 1-µm CMOS Process

• 125-MHz Pipelined Architecture

• Direct Interface to TMS340XX Graphics

Processors

• Standard Microprocessor Unit (MPU)

• Available Clock Rates . . . 80, 110, 125,

Palette Interface

135 MHz

• Multiplexed TTL Pixel Ports

• Dual-Port Color RAM

256 Words x 24 Bits

• Triple Digital-to-Analog Converters (DACs)

• Dual-Port Overlay Registers . . . 4 × 24 Bits

• 5-V Power Supply

• Bit Plane Read and Blink Masks

• EIA RS-343-A Compatible Outputs

• Functionally Interchangeable With

Brooktree Bt458

description

TheTLC34058color-paletteintegratedcircuitisspecificallydevelopedforhigh-resolutioncolorgraphicsinsuch

applications as CAE/CAD/CAM, image processing, and video reconstruction.

The architecture provides for the display of 1280 × 1024 bit-mapped color graphics (up to 8 bits per pixel

resolution) with 2 bits of overlay information. The TLC34058 has a 256-word × 24-bit RAM used as a lookup

table with three 8-bit video D/A converters.

On-chip features such as high-speed pixel clock logic minimize costly ECL interface. Multiple pixel ports and

internal multiplexing provide TTL-compatible interface (up to 32 MHz) to the frame buffer while maintaining

sophisticated color graphic data rates (up to 135 MHz). Programmable blink rates, bit plane masking and

blinking, color overlay capability, and a dual-port palette RAM are other key features. The TLC34058 generates

red, green, and blue signals compatible with EIA RS-343-A and can drive, without external buffering, 75-Ω

coaxial cables terminated at each end.

AVAILABLE OPTIONS

DAC

RESOLUTION

PACKAGE

Ceramic Grid Array (GA)

T

A

SPEED

Plastic Chip Carrier (FN)

TLC34058-80FN

80 MHz

110 MHz

125 MHz

135 MHz

8 Bits

TLC34058-80GA

TLC34058-110GA

TLC34058-125GA

TLC34058-135GA

0°C

To

70°C

TLC34058-110FN

TLC34058-125FN

TLC34058-135FN

LinEPIC is a trademark of Texas Instruments Incorporated.

Brooktree is a registered trademark of Brooktree Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

FN PACKAGE

(TOP VIEW)

11 10 9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

D0

D1

D2

D3

D4

D5

D6

12

13

14

15

16

17

18

74 P2B

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

P2C

P2D

P2E

P3A

P3B

P3C

P3D

P3E

GND

D7 19

CE 20

21

22

23

24

25

26

27

28

29

30

31

32

GND

V

DD

V

DD

C0

C1

CLK

LD

R/W

V

BLK

SYNC

P4A

P4B

P4C

P4D

DD

IOR

IOG

IOB

FS ADJ

COMP

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

84-pin GA package pin assignments

SIGNAL

BLK

PIN NO.

L9

SIGNAL

PIN NO.

SIGNAL

PIN NO.

PORT 5

POWER, REFERENCE

AND MPU INTERFACE

SYNC

LD

M10

M9

P5A

K11

L12

K12

J11

J12

P5B

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

C12

C11

A9

CLK

L8

P5C

CLK

M8

P5D

P5E

L7

PORT 0

P0A

PORT 6

M7

A7

G1

G2

H1

H2

J

P6A

H11

H12

G12

G11

F12

P0B

P6B

GND

COMP

FS ADJ

REF

CE

B12

B11

M6

B6

P0C

P6C

P0D

P6D

P0E

P6E

PORT 1

P1A

PORT 7

A6

J2

K1

L1

K2

L2

P7A

F11

E12

E11

D12

D11

A12

B10

C10

A5

P1B

P7B

P1C

P7C

P1D

P7D

P1E

P7E

R/W

C1

B8

PORT 2

P2A

OVERLAY SELECT 0

A8

K3

M1

L3

OL0A

OL0B

A1

C2

B1

C1

D2

C0

B7

P2B

DATA BUS

D0

P2C

OL0C

C3

B2

B3

A2

A3

B4

A4

B5

P2D

M2

M3

OL0D

D1

P2E

OL0E

D2

PORT 3

P3A

OVERLAY SELECT 1

OL1A

D3

L4

M4

L5

D1

E2

E1

F1

F2

D4

P3B

OL1B

D5

P3C

OL1C

D6

P3D

M5

L6

OL1D

D7

P3E

OL1E

PORT 4

P4A

DAC CURRENT OUTPUTS

M11

L10

L11

IOG

IOB

IOR

A10

P4B

A11

B9

P4C

P4D

K10

M12

P4E

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

functional block diagram

REF

FS ADJ

CLK

Reference

Amplifier

COMP

Load

Control

Mux

Control

Blink

Control

LD

8-Bit

D/A

Converter

40

10

40

10

40

10

8

2

8

2

P0–P7

(A–E)

IOR

IOG

IOB

256 Words

8

× 24 Bits

Palette

Ram

Input

Latch

Mux

Read Blink

Mask Mask

8-Bit

D/A

Converter

OL0–OL1

(A–E)

4 × 24

Overlay

Palette

SYNC

BLK

8-Bit

D/A

Converter

Registers

CE

To

R/W

C0

Bus

Control

Functions

C1

To

8

Address

Control

Functions

Address

Register

D0–D7

Red

Value

Green

Value

Blue

Value

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

Terminal Functions

PIN NAME

BLK

I/O

DESCRIPTION

I

Composite blank control. This TTL-compatible blanking input is stored in the input latch on the rising edge of LD. When

low, BLK drives the DAC outputs to the blanking level, as shown in Table 6. This causes the P0–P7 [A–E] and

OL0–OL1 [A–E] inputs to be ignored. When high, BLK allows the device to perform in the standard manner.

C0, C1

CE

I

Command control inputs. The inputs specify the type of write or read operation (see Tables 1, 2, 3, and 4). These

TTL-compatible inputs are latched on the falling edge of CE.

Chip enable. This TTL-compatible input control allows data to be stored and enables data to be written or read (see

Figure 1). When low, CE enables data to be written or read. When high, CE allows data to be internally latched on the

rising edge during write operations. Care should be taken to avoid transients on this input.

CLK

I

Clock. This input provides the pixel clock rate. CLK and CLK inputs are designed to be driven by ECL logic using a 5-V

single supply.

I

Clock. This input is the complement of CLK and also provides the pixel clock rate.

CLK

COMP

Compensation. This input is used to compensate the internal reference amplifier (see the video generation section).

A 0.1-µF ceramic capacitor is connected between this pin and V

(see Figure 4). The highest possible supply voltage

rather than to GND.

DD

rejection ratio is attained by connecting the capacitor to V

DD

D0–D7

FS ADJ

I

Data input bus. This TTL-compatible bus transfers data into or out of the device. The data bus is an 8-bit bidirectional

bus where D0 is the least significant bit.

Full-scale adjust control. A resistor R , (see Figure 4) which is connected between this pin and GND, controls the

set

magnitude of the full-scale video signal. Note that the proportional current and voltage relationships in Figure 3 are

maintained independent of the full-scale output current. The relationships between R

full-scale output currents are:

and the IOR, IOG, and IOB

set

R

(Ω) = 11294 × V (V) / IOG(mA)

set ref

IOR, IOB (mA) = 8067 × V (V) / R (Ω)

ref set

GND

Ground. All GND pins must be connected together.

IOR, IOG

IOB

O

I

Current outputs, red, green, and blue. High-impedance red, green, and blue video analog current outputs can directly

drive a 75-Ω coaxial terminated at each end (see Figure 4).

LD

Load control. This TTL-compatible load control input latches the P0–P7 [A–E], OL0–OL1 [A–E], BLK, and SYNC

inputs on its rising edge. The LD strobe occurs at 1/4 or 1/5 the clock rate and may be phase independent of the CLK

and CLK inputs. The LD duty cycle limits are specified in the timing requirements table.

OL0A–OL1A

OL0B–OL1B

OL0C–OL1C

OL0D–OL1D

OL0E–OL1E

l

Overlay selection inputs. These TTL-compatible selection inputs for the Palette overlay registers are stored in the input

latch on the rising edge of LD. These inputs (up to 2 bits per pixel), along with bit CR6 of the command register (refer

to the command register section and Table 5), specify whether the color information is selected from the palette RAM

or the overlay registers. If the color information is selected from the overlay registers, the OL0–OL1 [A–E] inputs

address a particular overlay register. The OL0–OL1 [A–D] or OL0–OL1 [A–E] inputs are simultaneously input to the

device (see the description of bit CR7 in the command register section). The OL0–OL1 [A] inputs are processed first,

then the OL0–OL1 [B] inputs, and so on. When obtaining the color information from the overlay registers, the P0–P7

[A – E] inputs are ignored. Unused inputs should be connected to GND.

P0A –P7A

P0B–P7B

P0C–P7C

P0D–P7D

P0E–P7E

l

Addressinputs. TheseTTL-compatibleaddressinputsforthePaletteRAMarestoredintheinputlatchontherisingedge

of LD. These address inputs (up to 8-bits per pixel) select one of 256 24-bit words in the palette RAM, which is

subsequently input to the red, green, and blue D/A converters as three 8-bit or 4-bit bytes. Four or five addresses are

simultaneously input to the P0–P7 [A–D] or P0–P7 [A–E] ports, respectively (see the description of bit CR7 in the

command register section). The word addressed by P0A–P7A is first sent to the DACs, then the word addressed by

P0B–P7B, and so on. Unused inputs should be connected to GND.

REF

I

Reference voltage. 1.235-V is supplied at this input. An external voltage reference circuit, shown in Figure 4, is sug-

gested.Generatingthereferencevoltagewitharesistornetworkisnotrecommendedsincelow-frequencypowersupply

noisewill directly couple into the DAC output signals. This input must be decoupled by connecting a 0.1-µF ceramic

capacitorbetween VREF and GND.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

Terminal Functions (continued)

PIN NAME

I/O

DESCRIPTION

I

R/W

Read/write input. This TTL-compatible control input is latched on the falling edge of CE (see Figure 1). When low, writes

data to the device. Data is internally latched on the rising edge of CE. When high, reads data from the device.

I

Composite sync control. This TTL-compatible sync control input is stored in the input latch on the rising edge of LD. When

low, SYNC turns off a 40 IRE current source on the IOG output, as shown in Figure 3. This input does not override any

control data input, as shown in Table 6. It should be brought low during the blanking interval only, as shown in Figure 3.

When high, SYNC allows the device to perform in the standard manner.

SYNC

V

DD

Supply voltage. All V

pins must be connected together.

DD

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

Voltage range on any digital input (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to V

Analog output short circuit duration to any power supply or common, I

Operating free-air temperature range, T

+ 0.5 V

DD

. . . . . . . . . . . . . . . . . . . . . unlimited

OS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: GA package . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and

functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND terminal.

recommended operating conditions

MIN NOM

4.75

–1

MAX

UNIT

V

Supply voltage, V

5

5.25

DD

CLK, CLK

V

DD

V

+0.5

V

DD

High-level Input voltage, V

IH

Other inputs

CLK, CLK

2

+0.5

–1.6

0.8

V

–0.5

V

Low-level Input voltage, V

IL

Other inputs

V

Reference voltage, V

ref

1.2 1.235

1.26

V

Output load resistance, R

37.5

Ω

L

FS ADJ resistor, R

set

523

0

Ω

Operating free-air temperature, T

70

°C

A

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature, R

= 523 Ω, V = 1.235 V (unless otherwise noted)

set

ref

†

PARAMETER

Input reference current

TEST CONDITIONS

MIN TYP

MAX

UNIT

µA

I

10

0.5

ref

f = 1 kHZ,

C8 = 0.1 µF (see Figure 4)

%

k

Supply voltage rejection ratio

SVR

%∆V

DD

V

= 5 V,

T

= 20°C

= 0°C

175

DD

A

80 MHz

= 5.25 V,

= 5 V,

T

A

400

420

435

T

= 20°C

T = 0°C

A

195

205

200

A

110 MHz

125 MHz

= 5.25 V,

= 5 V,

I

Supply current

mA

DD

T

= 20°C

T = 0°C

A

= 5.25 V,

= 5 V,

T

A

= 20°C

= 0°C

135 MHz

= 5.25 V,

T

A

435

1

CLK, CLK

V = 4 V

I

µA

pF

V

I

High-level input current

Low-level input current

IH

Other inputs V = 2.4 V

1

I

CLK, CLK

V = 0.4 V

I

–1

10

IL

Other inputs V = 0.4 V

I

C

Input capacitance, digital

f = 1 MHz,

V = 2.4 V

4

i

I

Input capacitance, CLK, CLK

High-level output voltage, D0–D7

Low-level output voltage, D0–D7

High-impedance-state output current

Output impedance

V = 4 V

I

i(CLK)

OH

OL

V

I

= –800 µA

2.4

OH

= 6.4 mA

0.4

10

V

OL

I

µA

kΩ

pF

OZ

z

50

13

o

C

Output capacitance (f = 1 MHz, I = 0)

20

o

O

†

All typical values are at T = 25°C.

A

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

timing requirements over recommended ranges of supply voltage and operating free-air

temperature, R

= 523 Ω, V = 1.235 V (see Note 2)

set

ref

†

VERSION

TIMING

PARAMETER

LIMIT

UNITS

REFERENCE

135 MHz

125 MHz

110 MHz

80 MHz

80

20

0

Clock frequency

LD frequency

–

MAX

MIN

135

33.75

0

125

31.25

0

110

27.5

0

MHz

ns

Setup time, R/W, C0, C1 high before CE ↓

Hold time, R/W, C0, C1 high after CE ↓

Pulse duration, CE low

1

2

15

50

25

35

0

15

50

25

35

0

15

50

25

35

0

15

50

25

50

0

ns

3

ns

Pulse duration, CE high

4

ns

Setup time, write data before CE ↑

Hold time, write data after CE ↓

Pixel and control setup time

Pixel and control hold time

Clock cycle time

8

ns

9

ns

10

11

12

13

14

15

16

17

3

4

ns

2

ns

7.4

3

8

9.09

4

12.5

5

ns

Pulse duration, CLK high

Pulse duration, CLK low

3.2

32

13

ns

3

4

5

ns

LD cycle time

29.6

12

36.36

15

50

20

ns

LD pulse duration high time

LD pulse duration low time

ns

†

See Figures 1 and 2.

NOTE 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are V

–1.8 V to

DD

V

–0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points are

DD

at the 50% signal level. Analog output loads are less than 10 pF. D0–D7 output loads are less than 40 pF.

operating characteristics over recommended ranges of supply voltage and operating free-air

temperature, R

= 523 Ω, V = 1.235 V (unless otherwise noted)

set

ref

analog outputs

†

TYP

PARAMETER

MIN

MAX

±1

UNIT

LSB

E

Integral linearity error (each DAC)

Differential linearity error

Gray scale error

L

±1

D

±5

White level relative to blank

White level relative to black

Black level relative to blank

Blank level on IOR, IOB

Blank level on IOG

17.69 19.05

16.74 17.62

20.4

18.5

1.9

mA

0.95

0

1.44

5

I

O

Output current

50

µA

mA

µA

6.29

0

7.6

5

8.96

50

Sync level on IOG

LSB size

69.1

2%

DAC to DAC matching

Output compliance voltage

5%

1.2

–1

V

†

All typical values are at T = 25°C

A

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, R

= 523 Ω, V = 1.235 V (see Note 2)

set

ref

†

VERSION

TIMING

PARAMETER

LIMIT

UNITS

REFERENCE

135 MHz

125 MHz

110 MHz

80 MHz

CE low to data bus enabled

5

6

MIN

MAX

TYP

MAX

TYP

MAX

MIN

10

75

15

20

2

10

75

15

20

2

10

75

15

20

2

10

100

15

20

3

ns

CE low to data valid

CE high to data bus disabled

7

ns

Analog output delay time (see Note 3)

Analog output rise or fall time (see Note 4)

Analog output setting time (see Note 5)

Glitch impulse (see Note 6)

18

19

20

ns

8

9

12

50

0

ns

50

0

50

0

50

0

pV-s

ns

Analog output skew

Pipeline delay

2

ns

6

clock

cycles

MAX

10

†

See Figures 1 and 2.

NOTES: 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are V

–1.8 to

DD

–0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points

V

DD

are at the 50% signal level. Analog output loads are less than 10 pF. D0–D7 output loads are less than 40 pF.

3. Measured from 50% point of rising clock edge to 50% point of full-scale transition.

4. Measured between 10% and 90% of full-scale transition.

5. Measured from 50% point of full-scale transition to output settling within ± 1

6. Glitch impulse includes clock and data feedthrough. The –3-dB test bandwidth is twice the clock rate.

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PARAMETER MEASUREMENT INFORMATION

t

h1

t

su1

R/W, C0, C1

CE

t

w1

t

w2

t

en2

t

dis

t

en1

D0–D7 (Read)

D0–D7 (Write)

t

su2

t

h2

Figure 1. Read/Write Timing Waveform

t

c2

t

w6

w5

LD

P0 –P7 (A–B),

Data

OL0–OL1 (A–B),

SYNC, BLK

t

su3

t

d

t

s

t

h3

IOR, IOG, IOB

t

c1

t

w3

CLK

t

w4

Figure 2. Video Input/Output Timing Waveform

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PARAMETER MEASUREMENT INFORMATION

RED, BLUE

mA

GREEN

mA

V

White Level

19.05 0.714 26.67 1.000

92.5 IRE

Black Level

Blank Level

1.44 0.054 9.05 0.340

0.00 0.000 7.62 0.286

7.5 IRE

40 IRE

Sync Level

0.00

NOTE A: The IRE (Institute of Radio Engineers – now IEEE) scale is used for defining the relative voltage levels of the sync, white, black, and

blank levels in a monitor circuit. The reference white level is set at 100 IRE units. The blanking level is set at φ IRE units. One IRE unit

is equivalent to 1/100 of the difference between the reference white level and the blanking level.

Figure 3. Composite Video Output Waveforms

COMP

C8

L1

V

DD

5 V (V

)

DD

C5–C7

C9

C2–C4

R4

C1

REF

C10

TLC34058

Z1

GND

R

R1

R2

R3

SET

FS ADJ

IOR

To

Video

Connector

IOG

IOB

LOCATION

DESCRIPTION

0.1-µF ceramic capacitor

VENDOR PART NUMBER

C1–C4, C8, C9

Erie RPE112Z5U104M50V

C5–C7

C10

0.01-µF ceramic chip capacitor AVX 12102T903QA1018

33-µF tantalum capacitor

ferrite bead

Mallory CSR13-K336KM

Fair-Rite 2743001111

Dale CMF-55C

L1

R1, R2, R3

R4

75-Ω 1% metal film resistor

1000-Ω 1% metal film resistor

523-Ω 1% metal film resistor

1.2-V diode

Dale CMF-55C

R

set

Z1

Dale CMF-55C

National Semiconductor

LM385Z-1.2

NOTE A: Theabovelistedvendornumbersarelistedonlyasaguide. Substitutionofdeviceswith

similar characteristics does not degrade the performance of the TLC34058.

Figure 4. Circuit Diagram

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PARAMETER MEASUREMENT INFORMATION

5 V

220 Ω

5 V

14

CLK

330 Ω

5 V

220 Ω

Monitor

Products

970E

CLK

LDA

Clock

Generator

330 Ω

TLC34058

7

LD

5 V

0.1 µF

1 kΩ

V

ref

REF

Figure 5. Generating the Clock, Load, and Voltage Reference Signals

V

DD

G0–G7

15 PF

C (stray + load)

R

L

BLK

SYNC

(IOG Only)

Figure 6. Equivalent Circuit of the Current Output (IOG)

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PRINCIPLES OF OPERATION

microprocessor unit (MPU) interface

As shown in the functional block diagram, the MPU has direct access to the internal control registers and color

overlay palettes via a standard MPU interface. Since the palette RAM and overlay registers have dual ports,

they can be updated without affecting the display refresh process. One port is allocated for updating or reading

data and the other for display.

palette RAM write or read

The palette RAM location is addressed by the internal 8-bit address register (ADDR0–7). The MPU can either

write to or read from this register. The register eliminates the need for external address multiplexers.

ADDR0–ADDR7 are updated via D0–D7. To address the red, green, and blue part of a particular RAM location,

the internal address register is provided with two additional bits, ADDRa and ADDRb. These address bits count

modulo 3 and are reset to 0 when the MPU accesses the internal address register.

After writing to or reading from the internal address register, the MPU executes three write or read cycles (red,

green and blue). The register ADDRab is incremented after each of these cycles so that the red, green, and blue

information is addressed from the correct part of the particular RAM location. During the blue write cycle, the

red, green, and blue color information is adjoined to form a 24-bit word, which is then written to the particular

RAM location. After the blue write/read cycle, the internal address register bits ADDR0–7 are incremented to

access the next RAM location. For an entire palette RAM write or read, the bits ADDR0–7 are reset to 00 after

accessing the FF (256) palette RAM location.

Two additional control bits, C0 and C1, are used to differentiate the palette RAM read/write function from other

operations that utilize the internal address register. C0 and C1 are respectively set high and low for writing to

or reading from the palette RAM. Table 1 summarizes this differentiation, along with other internal address

register operations. Note that C0 and C1 are each set low for writing to or reading from the internal address

register.

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PRINCIPLES OF OPERATION

Table 1. Writing to or Reading from Palette RAM

R/W

C1

L

C0

L

ADDRb

ADDRa

FUNCTION

write ADDR0–7: D0–D7 → ADDR0–7; 0 → ADDRa,b

write red color: D0–D7 → RREG; increment ADDRa,b

write green color: D0–D7 → GREG; increment ADDRa,b

L

X

L

X

L

H

L

H

write blue color: D0–D7 → BREG; increment ADDRa,b; increment ADDR0–7; write

palette RAM

L

H

L

H

L

H

X

L

X

L

read ADDR0–7: ADDR0–7 → D0–D7; 0 → ADDRa,b

H

read red color: R0–R7 → D0–D7; increment ADDRa,b

H

L

H

L

read green color: G0–G7 → D0–D7; increment ADDRa,b

read blue color: B0–B7 → D0–D7; increment ADDRa,b; increment ADDR0–7

H

X = irrelevant

overlay register write/read

With a few exceptions, the overlay register operation is identical to the palette RAM write/read operation (refer

to the palette RAM write/read section). Upon writing to or reading from the internal address register, the

additional address register ADDRab is automatically reset to 0. ADDRab counts modulo 3 as the red, green,

and blue information is written to or read from a particular overlay register. The four overlay registers are

addressed with internal address register values 00–03. After writing/reading blue information, the internal

address register bits ADDR0–7 are incremented to the next overlay location. After accessing overlay register

value 03, the internal address register does not reset to 00 but is advanced to 04.

For writing to or reading from the internal address register, C0 and C1 are set low. When accessing the overlay

registers, C0 and C1 are set high. Refer to Table 2 for quick reference.

Table 2. Writing to or Reading from Overlay Registers

R/W

C1

L

C0

L

ADDRb

ADDRa

FUNCTION

write ADDR0-7: D0–D7 → ADDR0–7; 0 → ADDRa,b

write red color: D0–D7 → RREG; increment ADDRa,b

write green color: D0–D7 → GREG; increment ADDRa,b

L

X

L

X

L

H

write blue color: D0–D7 → BREG; increment ADDRa,b; increment ADDR0–7; write

overlay register

L

H

L

H

L

H

L

H

X

L

X

L

read ADDR0–7: ADDR0–7 → D0–D7; 0 → ADDRa,b

H

read red color: R0–R7 → D0–D7; increment ADDRa,b

H

L

H

L

read green color: G0–G7 → D0–D7; increment ADDRa,b

read blue color: B0–B7 → D0–D7; increment ADDRa,b; increment ADDR0–7

H

X = irrelevant

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PRINCIPLES OF OPERATION

control register write/read

The four control registers are addressed with internal address register values 04–07. Upon writing to or reading

from the internal address register, the additional address bits ADDRab are automatically reset to 0. To facilitate

read-modify-write operations, the internal address register does not increment after writing to or reading from

the control registers. All control registers may be accessed at any time. When accessing the control registers,

C0 and C1 are respective set low and high. Refer to Table 3 for quick reference.

Table 3. Writing to or Reading from Control Registers

R/W

C1

L

C0

L

ADDRba

ADDRab

FUNCTION

write ADDR0–7: D0–D7 → ADDR0–7; 0 → ADDRa,b

write control register: D0–D7 → control register

read ADDR0–7: ADDR0–7 → D0–D7; 0 → ADDRa,b

read control register: control register → D0–D7

L

X

L

X

L

X

L

X

L

H

L

H

L

H

L

X = irrelevant

summary of internal address register operations

Table 4 provides a summary of operations that use the internal address register. Figure 1 presents the read/write

timing for the device.

If an invalid address is loaded into the internal address register, the device will ignore subsequent data from the

MPU during a write operation and will send incorrect data to the MPU during a read operation.

Table 4. Internal Address Register Operations

INTERNAL ADDRESS

REGISTER VALUE

(ADDR0–7) (HEX)

ADDRab

(counts

modulo 3)

C1

C0

MPU ACCESS

COLOR

00

01

11

red value

green value

blue value

red value

00–FF

00–03

L

H

color palette RAM

00

01

110

H

over color 0 to 3

green value

blue value

04

05

06

07

H

L

read mask register

blink mask register

command register

test register

interruption of display refresh pixel data (via simultaneous pixel data retrieval and MPU write)

IftheMPUiswritingtoaparticularpaletteRAMlocationoroverlayregister(duringthebluecycle)andthedisplay

refresh process is accessing pixel data from the same RAM location or overlay register, one or more pixels on

the display screen may be disturbed. If the MPU write data is valid during the complete chip enable period, a

maximum of one pixel will be disturbed.

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PRINCIPLES OF OPERATION

frame buffer interface and timing

An internal latch and multiplexer enables the frame buffer to send the pixel data to the device at TTL rates. On

the rising edges of LD, information for four or five consecutive pixels is latched into the device. This information

includes the palette RAM address (up to 8 bits), the overlay register address (up to 2 bits), and the sync and

blank information for each of the four or five consecutive pixels. The timing diagram for this pixel data input

transfer is shown in Figure 2, along with the video output waveforms (IOR, IOG, and IOB). Note that with this

architecture, the sync and blank timing can only be recognized with four- or five-pixel resolution.

The display refresh process follows the first-in first-out format. Color data is output from the device in the same

order in which palette RAM and overlay addresses are input. This process continues until all four or five pixels

have been output, at which point the cycle will repeat.

The overlay timing can be controlled by the pixel timing. However, this approach requires that the frame buffer

emit additional bit planes to control the overlay selection on a pixel basis. Alternatively, the overlay timing can

be controlled by external character or cursor generation timing (see the color selection section).

No phase relationship between the LD and CLK signals is required (see Figure 2). Therefore, the LD signal can

bederivedbyexternallydividingtheCLKsignalbyfourorfive. AnypropagationdelayinLDcausedbythedivider

circuitry will not render the device nonfunctional. Regardless of the phase relationship between LD and CLK,

the pixel, overlay, sync, and blank data are latched on the rising edge of LD.

The device has an internal load signal (not brought out to a pin), which is synchronous to CLK and will follow

LD by at least one and not more than four clock cycles. This internal load signal transfers the LD-latched data

into a second set of latches, which are then internally multiplexed at the pixel clock or CLK signal frequency.

For 4:1 or 5:1 multiplexing, a rising edge of LD should occur every four or five clock cycles. Otherwise, the

internal load signal generation circuitry cannot lock onto or synchronize with LD.

color selection

The read mask, blink mask, and command registers process eight bits of color information (P0–P7) and two

bits of overlay information (OL0–OL1) for each pixel every clock cycle. Control registers allow individual bit

planes to be enabled/disabled for display and/or blinked at one of four blink rates and duty cycles (see the

command register section, bits CR4–CR5).

By monitoring the BLK input to determine vertical retrace intervals, the device ensures that a color change due

to blinking occurs only during the nonactive display time. Thus, a color change does not occur in the middle of

the screen. A vertical retrace is sensed when BLK is low for at least 256 LD cycles. The color information is then

selected from the palette RAM or overlay registers, in accordance with the processed input pixel data.

Table 5 presents the effect of the processed input pixel data upon color selection. Note that P0 is the least

significantbit (LSB) of the color palette RAM. When CR6 is high and both OL1 and OL0 are low, color information

resides in the color palette RAM. When CR6 is low or either of the overlay inputs is high, the overlay registers

provide the DAC inputs.

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PRINCIPLES OF OPERATION

Table 5. Input Pixel Data versus Color Selection

COMMAND

REGISTER

BIT

OVERLAY

SELECT

INPUT

COLOR

ADDRESS

(HEX)

COLOR

INFORMATION

CR6

OL1

OL0

P7–P0

00

01

•

H

L

•

L

•

color palette entry 00

color palette entry 01

H

•

H

L

H

L

H

L

H

FF

XX

color palette entry FF

overlay register 0

overlay register 1

overlay register 2

overlay register 3

L

X

X = irrelevant

video generation

The TLC34058 presents 8 bits of red, green, and blue information from either the palette RAM or overlay

registers to the three 8-bit DACs during every clock cycle. The DAC outputs produce currents that correlate to

their respective color input data. These output currents are translated to voltage levels that drive the color CRT

monitor. The SYNC and BLK signals adjust the DAC analog output currents to generate specific output levels

that are required in video applications. Table 6 shows the effectofSYNCandBLKupon the DAC output currents.

Figure 3 presents the overall composite video output waveforms. Note that only the green output (IOG) contains

sync information.

The DAC architecture ensures monotonicity and reduced switching transients by using identical current sources

and routing their outputs to the DAC current output or GND. Utilizing identical current sources eliminates the

need for precision component ratios within the DAC ladder circuitry. An on-chip operational amplifier stabilizes

the DAC full-scale output current over temperature and power supply variations.

Table 6. Effects of Sync and Blank Upon DAC Output Currents (see Note 7)

IOG

(mA)

IOR, IOB

(mA)

DAC

INPUTS

DESCRIPTION

SYNC

BLK

WHITE

DATA

26.67

data + 9.05

data + 1.44

9.05

19.05

H

L

H

L

FF

data

00

data + 1.44

DATA w/o SYNC

BLACK

data + 1.44

1.44

0

H

L

BLACK w/o SYNC

BLACK

1.44

00

7.62

H

L

xx

SYNC

0

L

xx

NOTE 7: The data in this table was measured with full-scale IOG current = 26.67 mA, R

= 523 Ω, V = 1.235 V.

ref

set

command register

The MPU can write to or read from the command register at any time. The command register is not initialized.

CR0 corresponds to the D0 data bus line. Refer to Table 7 for quick reference.

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PRINCIPLES OF OPERATION

Table 7. Command Register

COMMAND

COMMAND REGISTER BIT

REGISTER

COMMAND REGISTER BIT DESCRIPTION

This bit selects either 4:1 or 5:1 multiplexing for the palette RAM and overlay register address,

FUNCTION

BIT

CR7

Multiplex Select Bit

low: selects 4:1 multiplexing SYNC, and BLK inputs. If 4:1 multiplexing is selected, the device ignores the ‘E’ palette RAM

high: selects 5:1 multiplexing and overlay register address inputs. These inputs should be connected to GND, and the LD

signal frequency should be 1/4 of the clock frequency. If 5:1 is specified, all of the palette

RAM and overlay register address inputs are used and the LD signal should be 1/5 of the

clock frequency.

CR6

RAM Enable Bit

low: use overlay register 0

high: use palette RAM

When the overlay select bits, OL0 and OL1, are both low, this bit causes the DACs color

information to be selected from overlay register 0 or the palette RAM.

CR5, CR4

Blink Rate Select Bits

00: 16 on, 48 off (25/75)

01: 16 on, 16 off (50/50)

10: 32 on, 32 off (50/50)

11: 64 on, 64 off (50/50)

OL1 Blink Enable Bit

low: disable blinking

These two bits select the blink rate cycle time and duty cycle. The on and off numbers specify

the blink rate cycle time as the number of vertical periods.

The numbers in parentheses specify the duty cycle in (on/off) percent.

CR3

CR2

CR1

CR0

If this bit is a high, the OL1 [A–E] inputs will toggle between a logic 0 and their input value at

the selected blink rate before latching the incoming pixel data. Simultaneously, command

register CR1 must be set high. If the CR2 bit is low, the OL0 [A–E] inputs will be unaffected.

high: enable blinking

OL0 Blink Enable Bit

low: disable blinking

high: enable blinking

If this bit is high, the OL0 [A–E] inputs will toggle between a logic 0 and their input value at the

selected blink rate before latching the incoming pixel data. Simultaneously, command register

CR0 must be set high. If the CR2 bit is low, the OL0 [A–E] inputs will be unaffected.

OL1 Display Enable Bit

low: disable

high: enable

If this bit is low, the OL1 [A–E] inputs are forced to a logic 0 before latching the incoming pixel

data. If the CR1 bit is high, the OL1 [A–E] inputs will be affected.

OL0 Display Enable Bit

low: disable

If this bit is low, the OL0 [A–E] inputs are forced to a logic 0 before latching the incoming pixel

data. If the CR0 bit is high, the OL0 [A–E] inputs will be affected.

high: enable

read mask register

The read mask register is used to enable (high) or disable (low) the eight bit planes (P0–P7) within the palette

RAM addresses. The enabling or disabling is accomplished by logic ANDing the read mask register with the

palette RAM address before addressing the palette RAM. Note that read mask register bit 0 corresponds to data

bus line D0. The MPU can write to or read from this register at any time. This register is not initialized.

blink mask register

The blink mask register is used to enable (high) or disable (low) the blinking of bit planes within the palette RAM

addresses. For example, if blink mask register bit n is set high, the true Pn value will address the palette RAM

during the on portion of the blink cycle. During the off part of the blink cycle, the Pn value will be replaced with

a 0 before the palette RAM is addressed. The blink rate cycle time and duty cycle is specified by command

register bits CR4 and CR5. If blink mask register bit n is set low, the true Pn value will always address the palette

RAM. Note that blink mask register bit 0 corresponds to data bus line D0. This register is not initialized.

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

PRINCIPLES OF OPERATION

test register

The test register allows the MPU to read the inputs to the DAC for diagnostic purposes. The MPU can write to

or read from this register at any time. This register is not initialized. Only the four least significant bits can be

written to, while all 8 bits can be read. Note that test register bit 0 corresponds to data bus line D0.

A function description of this register is presented in Table 8.

Table 8. Functional Description of Test Register

TR3–TR0

0100

D4–D7

FUNCTION

4 MSBs of blue data input

4 MSBs of green data input

4 MSBs of red data input

4 LSBs of blue data input

4 LSBs of green data input

4 LSBs of red data input

0010

MPU read or write D0–D3

0001

1100

1010

MPU read D0–D7

1001

To read the DAC inputs, the MPU must first load the test register’s four least significant bits. One of the test

register bits, b0 (red DAC), b1 (green DAC) or b2 (blue DAC), must be set high and the other two bits low. This

process determines whether the inputs to the red, green, or blue DAC will be read. The test register bit b3 must

be set high for reading the four most significant DAC inputs or low for reading the four least significant inputs.

The MPU then reads the test register while the test register’s four least significant bits contain the previously

written information. Note that either the device clock must be slowed down to the MPU cycle time or the same

pixel and overlay data must be continuously presented to the device during the entire MPU read cycle.

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

APPLICATION INFORMATION

device ground plane

Use of a four-layer PC board is recommended. All of the ground pins, voltage reference circuitry, power supply

bypass circuitry, analog output signals, and digital signals, as well as any output amplifiers, should have a

common ground plane.

device analog power plane (APP)

Thedeviceplusassociatedanalogcircuitryshouldhaveaseparateanalogpowerplane(APP)forV .TheAPP

DD

powers the device, voltage reference circuitry, and any output amplifiers. It should be connected to the overall

PCB power plane (V ) at a single point through a ferrite bead, which should be within 3 inches of the device.

DD

This connection is shown in Figure 4.

PCB power plane and PCB ground plane

The PCB power plane powers the digital circuitry. The PCB power plane and PCB ground planes should not

overlay the APP unless the plane-to-plane noise is common-mode.

supply decoupling

Bypass capacitors should have the shortest possible lead lengths to reduce lead inductance. For best results,

a parallel combination of 0.1-µF ceramic and 0.01-µF chip capacitors should be connected from each V

DD

to GND. If chip capacitors are not feasible, radial-lead ceramic capacitors may be substituted. These capacitors

should be located as close to the device as possible.

The performance of the internal power supply noise rejection circuitry decreases with noise frequency. If a

switching power supply is used for V , close attention must be paid to reducing power supply noise. To reduce

DD

such noise, the APP could be powered with a three-terminal voltage regulator.

digital interconnect

The digital inputs should be isolated from the analog outputs and other analog circuitry as much as possible.

Shielding the digital inputs will reduce noise on the power and ground lines. The lengths of clock and data lines

should be minimized to prevent high-frequency clock and data information from inducing noise into the analog

part of the video system. Active termination resistors for the digital inputs should be connected to the PCB power

plane, not the APP. These digital inputs should not overlay the device ground plane.

analog signal interconnect

Minimizing the lead lengths between groups of V

and GND minimizes inductive ringing. To minimize noise

DD

pickup due to reflections and impedance mismatch, the device should be located as close to the output

connectors as possible. The external voltage reference should also be as close to the device as possible, to

minimize noise pickup.

To maximize high-frequency supply voltage rejection, the video output signals should overlay the device ground

plane and not the APP.

Eachanalog output should have a 75-Ω load resistor connected to GND for maximum performance. Tominimize

reflections, the resistor connections between current output and ground should be as close to the device as

possible.

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC34058

256 × 24 COLOR PALETTE

SLAS050 – D3961, NOVEMBER 1991

APPLICATION INFORMATION

clock interfacing

To facilitate the generation of high-frequency clock signals, the CLK and CLK pins are designed to accept

differential signals that can be generated with 5-V (single supply) ECL logic. Due to noise margins of the CMOS

process, the CLK and CLK inputs must be differential signals. Connecting a single-ended clock signal to CLK

and connecting CLK to GND will not work.

The CLK and CLK pins require termination resistors (220-Ω to V

to the device as possible.

and 330-Ω to GND) that should be as close

DD

LD is typically generated by dividing the clock frequency by four (4:1 multiplexing) or five (5:1 multiplexing) and

translating the resulting signal to TTL levels. Since no phase relationship between the LD and CLK signals is

required, any propagation delay in LD caused by the divider circuitry will not affect device performance.

The pixel, overlay, sync and blank data are latched on the rising edge of LD. LD may also be used as the shift

clock for the video DRAMs. In short, LD provides the fundamental timing for the video system.

The Bt438 Clock Generator (from Brooktree) is recommended for generating the CLK, CLK, LD, and REF

signals. It supports both 4:1 and 5:1 multiplexing. Alternatively, the Bt438 can interface the device to a TTL clock.

Figure 5 illustrates the interconnection between the Bt438 and the device.

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

4-Apr-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CPGA

PLCC

CPGA

CFP

Drawing

5962-8992801XA

5962-8992801XC

TLC34058-110FN

TLC34058-110FNR

TLC34058-110MGA

TLC34058-110MGAB

TLC34058-110MHFG

TLC34058-135FN

TLC34058-80FN

OBSOLETE

GA

84

TBD

Call TI

GA

FN

GA

HFG

FN

PLCC

FN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

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型号：	TLC34058
厂家：	TEXAS INSTRUMENTS
描述：	256 Ã 24 COLOR PALETTE 256 ？ 24调色板
文件：	总26页 (文件大小：481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC34058 [TI]

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