TLC352CPWR [TI]
LinCMOS DUAL DIFFERENTAL COMPARATOR; 路LinCMOS DUAL高差比较器
| 型号： | TLC352CPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOS DUAL DIFFERENTAL COMPARATOR |
| 文件： | 总16页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002
TLC352C, TLC352I . . . D OR P PACKAGE
(TOP VIEW)
D
D
D
Single- or Dual-Supply Operation
Wide Range of Supply Voltages
1.5 V to 18 V
1OUT
1IN−
1IN+
GND
V
DD
1
2
3
4
8
7
6
5
2OUT
2IN−
2IN+
Very Low Supply Current Drain
150 µA Typ at 5 V
65 µA Typ at 1.4 V
D
D
D
D
D
Built-In ESD Protection
symbol (each comparator)
12
High Input Impedance . . . 10 Ω Typ
Extremely Low Input Bias Current 5 pA Typ
Ultrastable Low Input Offset Voltage
IN+
IN−
OUT
Input Offset Voltage Change at Worst-Case
Input Conditions Typically 0.23 µV/ Month,
Including the First 30 Days
D
D
D
Common-Mode Input Voltage Range
Includes Ground
Outputs Compatible With TTL, MOS, and
CMOS
Pin-Compatible With LM393
description
This device is fabricated using LinCMOS technology and consists of two independent voltage comparators,
each designed to operate from a single power supply. Operation from dual supplies is also possible if the
difference between the two supplies is 1.4 V to 18 V. Each device features extremely high input impedance
12
(typically greater than 10 Ω), which allows direct interface to high-impedance sources. The output are
n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND relationships.
The capability of the TLC352 to operate from 1.4-V supply makes this device ideal for low-voltage battery
applications.
The TLC352 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V
ESD rating tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling this
device as exposure to ESD may result in degradation of the device parametric performance.
The TLC352C is characterized for operation from 0°C to 70°C. The TLC352I is characterized for operation over
the industrial temperature range of − 40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
V
IO
max
T
A
SMALL-OUTLINE
(D)
PLASTIC DIP
(P)
AT 25°C
0°C to 70°C
5 mV
5 mV
TLC352CD
TLC352ID
TLC352CP
TLC352IP
− 40°C to 85°C
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC352 CDR).
LinCMOS is a trademark of Texas Instruments Incorporated.
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Copyright 2002, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋ ꢌꢍ ꢁ ꢋꢎ ꢏ ꢏꢐ ꢑꢐ ꢒꢀ ꢎ ꢍꢁ ꢂꢉ ꢈ ꢓꢍꢑꢍꢀꢉ ꢑ
SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002
equivalent schematic (each comparator)
Common to All Channels
V
DD
OUT
GND
IN−
IN+
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
ID
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
I
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 18 V
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T TLC352C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC352I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential voltages are with respect to the network ground.
2. Differential voltages are at IN+ with respect to IN −.
3. Short circuits from outputs to V
DD
can cause excessive heating and eventual device destruction.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING
FACTOR
DERATE
ABOVE T
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
POWER RATING POWER RATING
A
D
P
500 mW
500 mW
5.8 mW/°C
64°C
N/A
464 mW
500 mW
377 mW
500 mW
N/A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002
•
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Template Release Date: 7−11−94
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SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC352 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the V
accuracy.
test, rather than changing the input voltages, to provide greater
ICR
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes state.
5 V
1 V
5.1 kΩ
5.1 kΩ
+
−
+
−
Applied V
Limit
Applied V
Limit
IO
IO
V
O
V
O
− 4 V
(a) V WITH V = 0
IO IC
(b) V WITH V = 4 V
IO IC
Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋ ꢌꢍ ꢁ ꢋꢎ ꢏ ꢏꢐ ꢑꢐ ꢒꢀ ꢎ ꢍꢁ ꢂꢉ ꢈ ꢓꢍꢑꢍꢀꢉ ꢑ
SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002
PARAMETER INFORMATION
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
R5
1.8 kΩ, 1%
V
DD
C3 0.68 µF
U1b
1/4 TLC274CN
C2
U1c
1/4 TLC274CN
1 µF
R6
Buffer
+
−
5.1 kΩ
−
+
DUT
V
IO
(X100)
R7
1MΩ
R4
47 kΩ
R1
Integrator
240 kΩ
R8
1.8 kΩ, 1%
C4
0.1 µF
U1a
−
+
1/4 TLC274CN
C1
0.1 µF
Triangle
Generator
R9
10 kΩ, 1%
R10
100 Ω, 1%
R2
10 kΩ
R3
100 kΩ
Figure 2. Circuit for Input Offset Voltage Measurement
6
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SLCS016A − SEPTEMBER 1985 − REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the leading
edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The
offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change
state.
V
DD
5.1 kΩ
1 µF
Pulse Generator
DUT
50 Ω
C
L
(see Note A)
1 V
Input
Offset Voltage
Compensation
Adjustment
10 Ω
10 Turn
1 kΩ
0.1 mF
− 1 V
TEST CIRCUIT
Overdrive
Overdrive
Input
Input
100 mV
100 mV
90%
50%
10%
90%
10%
Low-to-High-
Level Output
50 %
High-to-Low-
Level Output
t
t
t
r
f
t
PLH
PHL
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
L
Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TLC352CD
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
352C
TLC352CDG4
TLC352CDR
TLC352CDRG4
TLC352CP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
352C
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
352C
SOIC
D
Green (RoHS
& no Sb/Br)
0 to 70
352C
PDIP
P
Pb-Free
(RoHS)
0 to 70
TLC352CP
TLC352CP
P352
TLC352CPE4
TLC352CPWR
TLC352CPWRG4
TLC352ID
PDIP
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
TSSOP
TSSOP
SOIC
PW
PW
D
2000
2000
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
P352
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
352I
TLC352IDG4
TLC352IDR
SOIC
D
75
Green (RoHS
& no Sb/Br)
352I
SOIC
D
2500
2500
50
Green (RoHS
& no Sb/Br)
352I
TLC352IDRG4
TLC352IP
SOIC
D
Green (RoHS
& no Sb/Br)
352I
PDIP
P
Pb-Free
(RoHS)
TLC352IP
TLC352IP
P352I
TLC352IPE4
TLC352IPW
PDIP
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
TSSOP
TSSOP
TSSOP
PW
PW
PW
150
150
2000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TLC352IPWG4
TLC352IPWR
Green (RoHS
& no Sb/Br)
P352I
Green (RoHS
& no Sb/Br)
P352I
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
TLC352IPWRG4
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
P352I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC352CDR
TLC352CPWR
TLC352IDR
SOIC
TSSOP
SOIC
D
PW
D
8
8
8
8
2500
2000
2500
2000
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
7.0
6.4
7.0
5.2
3.6
5.2
3.6
2.1
1.6
2.1
1.6
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
TLC352IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC352CDR
TLC352CPWR
TLC352IDR
SOIC
TSSOP
SOIC
D
PW
D
8
8
8
8
2500
2000
2500
2000
340.5
367.0
340.5
367.0
338.1
367.0
338.1
367.0
20.6
35.0
20.6
35.0
TLC352IPWR
TSSOP
PW
Pack Materials-Page 2
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