TLC354CDG4
更新时间：2024-10-29 15:10:53
品牌：TI
描述：Quad, Low Voltage, LinCMOS™ Differential Comparator 14-SOIC 0 to 70
概述
规格参数
数据手册
替代型号TLC354CDG4 概述
Quad, Low Voltage, LinCMOS™ Differential Comparator 14-SOIC 0 to 70 比较器 比较器
TLC354CDG4 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | SOIC-14 |
| 针数： | 14 | Reach Compliance Code： | compliant |
| ECCN代码： | EAR99 | HTS代码： | 8542.33.00.01 |
| 风险等级： | 5.73 | 放大器类型： | COMPARATOR |
| 最大平均偏置电流 (IIB)： | 0.0006 µA | 最大输入失调电压： | 6500 µV |
| JESD-30 代码： | R-PDSO-G14 | JESD-609代码： | e4 |
| 长度： | 8.65 mm | 湿度敏感等级： | 1 |
| 功能数量： | 4 | 端子数量： | 14 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 输出类型： | OPEN-DRAIN | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP14,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 峰值回流温度（摄氏度）： | 260 | 电源： | 5 V |
| 认证状态： | Not Qualified | 标称响应时间： | 650 ns |
| 座面最大高度： | 1.75 mm | 子类别： | Comparator |
| 最大压摆率： | 0.4 mA | 供电电压上限： | 18 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 3.9 mm |
| Base Number Matches： | 1 |
TLC354CDG4 数据手册
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PDF下载TLC354
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997
D, N, OR PW PACKAGE
(TOP VIEW)
Single- or Dual-Supply Operation
Wide Range of Supply Voltages
1.4 V to 18 V
1OUT
2OUT
3OUT
4OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
Very Low Supply Current Drain
300 µA Typ at 5 V
V
V
/GND
DD
DD–
130 µA Typ at 1.4 V
2IN–
2IN+
1IN–
1IN+
4IN+
4IN–
3IN+
3IN–
Built-In ESD Protection
12
High Input Impedance . . . 10 Ω Typ
8
Extremely Low Input Blas Current
5 pA Typ
Ultrastable Low Input Offset Voltage
Input Offset Voltage Change at Worst-Case
Input Conditions Typically 0.23 µV/Month,
Including the First 30 Days
symbol (each comparator)
IN+
IN–
Common-Mode Input Voltage Range
Includes Ground
OUT
Outputs Compatible With TTL, MOS, and
CMOS
Pin-Compatible With LM339
description
This device is fabricated using LinCMOS technology and consists of four independent differential voltage
comparators; each is designed to operate from a single power supply. Operation from dual supplies is also
possible if the difference between the two supplies is 1.4 V to 18 V. Each device features extremely high input
12
impedance (typically greater than 10 Ω), which allows direct interface to high-impedance sources. The
outputs are n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND
relationships. The capability of the TLC354 to operate from a 1.4-V supply makes this device ideal for
low-voltage battery applications.
The TLC354 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V
ESD rating tested under MIL-STD-833C, Method 3015. However, care should be exercised in handling this
device as exposure to ESD may result in degradation of the device parametric performance.
The TLC354C is characterized for operation from 0°C to 70°C. The TLC354I is characterized for operation over
the industrial temperature range of –40° to 85°C. The TLC354M is characterized for operation over the full
military temperature range –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
FORM
(Y)
V
max
IO
T
A
SMALL OUTLINE
PLASTIC DIP
(P)
TSSOP
(PW)
AT 25°C
(D)
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
5 mV
5 mV
5 mV
TLC354CD
TLC354ID
TLC354MD
TLC354CN
TLC354IN
TLC354MN
TLC354CPW TLC354Y
—
—
—
—
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC354CDR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC354
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997
equivalent schematic (each comparator)
Common to All Channels
V
DD
OUT
V
/
DD–
GND
IN+
IN–
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
ID
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
I
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 18 V
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : TLC354C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC354I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC354M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential voltages are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN–.
3. Short circuits from outputs to V
can cause excessive heating and eventual device destruction.
DD
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING
FACTOR
DERATE
ABOVE T
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
POWER RATING POWER RATING POWER RATING
A
D
N
500 mW
7.6 mW/°C
9.2 mW/°C
5.6 mW/°C
84°C
96°C
25°C
500 mW
500 mW
448 mW
494 mW
500 mW
N/A
190 mW
230 mW
N/A
500 mW
PW
700 mW
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC354
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997
TLC364Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC354C. Thermal compression or
ultrasonic bonding can be used on the doped-aluminum bonding pads. Chips can be mounted with conductive
epoxy or a gold-silicon preform.
V
DD
(3)
BONDING PAD ASSIGNMENTS
(7)
(6)
1IN+
1IN–
+
–
(1)
(13)
(11)
(10)
(12)
(9)
1OUT
(5)
(4)
+
2IN+
2IN–
(2)
2OUT
3 IN+
–
(14)
(1)
(9)
(8)
+
–
(8)
(7)
(14)
3OUT
65
3IN–
(11)
(10)
+
–
4IN+
4IN–
(13)
4OUT
(12)
/GND
V
DD–
(6)
(4)
(5)
(3)
(2)
CHIP THICKNESS: 15 TYPICAL
90
BONDING PADS: 4 × 4 MINIMUM
T
= 150°C
JMAX
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
TLC354C
TLC354I
TLC354M
UNIT
MIN
1.4
0
MAX
MIN
1.4
0
MAX
MIN
1.4
0
MAX
Supply voltage, V
16
0.2
3.5
8.5
70
16
0.2
3.5
8.5
85
16
0.2
3.5
8.5
125
V
DD
V
DD
V
DD
V
DD
= 1.4 V
= 5 V
Common-mode input voltage, V
0
0
0
V
IC
= 10 V
0
0
0
Operating free-air temperature, T
0
–40
–55
°C
A
electrical characteristics at specified free-air temperature, V
= 1.4 V
DD
TLC354C
TLC354I
TYP
2
TLC354M
†
PARAMETER
Input offset voltage
Input offset current
Input bias current
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
5
MIN
MAX
MIN
TYP
MAX
5
25°C
2
5
7
2
V
IO
V
IC
= V
ICR
min, See Note 4
mV
Full range
25°C
6.5
10
1
5
1
5
1
5
pA
nA
pA
nA
I
I
IO
MAX
0.3
0.6
1
2
10
20
25°C
IB
MAX
Common-mode input voltage
range
0 to
0.2
0 to
0.2
0 to
0.2
V
ICR
25°C
V
V
V
= 5 V
25°C
Full range
25°C
0.1
0.1
0.1
nA
OH
I
High-level output current
V
ID
= 1 V
OH
= 15 V
1
200
200
1
200
200
1
200
200
µA
OH
100
100
100
V
Low-level output voltage
Low-level output current
V
ID
V
ID
V
ID
= –0.5 V,
= –0.5 V,
= 0.5 V,
I
= 0.6 mA
mV
mA
µA
OL
OL
Full range
25°C
I
I
V
OL
= 300 mV
1
1.6
1
1.6
1
1.6
OL
25°C
130
300
400
130
300
400
130
300
400
Supply current
(four comparators)
No load
DD
Full range
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC354C, –40°C to 85°C for TLC354I, and –55°C
to 125°C for the TLC354M. MAX is 70°C for TLC354C, 85°C TLC354I, and 125°C for the TLC354M. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 1.25 V or below 150 mV with a 10-kΩ resistor between the output and V . They
DD
can be verified by applying the limit value to the input and checking for the appropriate output state.
electrical characteristics at specified free-air temperature, V
= 5 V
DD
TLC354C
TLC354I
TYP MAX
TLC354M
TYP MAX
†
PARAMETER
Input offset voltage
Input offset current
Input bias current
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
MIN
MIN
25°C
Full range
25°C
2
1
5
5
2
5
7
2
1
5
5
V
IO
V
IC
= V
min, See Note 5
ICR
mV
6.5
10
1
5
pA
nA
pA
nA
I
IO
MAX
0.3
0.6
1
2
10
20
25°C
I
IB
MAX
0 to
0 to
0 to
25°C
V
–1
V
–1
V
–1
DD
DD
DD
Common-mode input
voltage range
V
ICR
V
0 to
0 to
0 to
Full range
V
–1.5
V
–1.5
V
–1.5
DD
DD
DD
V
V
= 5 V
25°C
Full range
25°C
0.1
0.1
0.1
nA
OH
I
High-level output current
V
ID
= 1 V
OH
= 15 V
1
400
700
1
400
700
1
400
700
µA
OH
150
150
150
V
Low-level output voltage
Low-level output current
V
ID
V
ID
V
ID
= –1 V,
= –1 V,
= 1 V,
I
= 4 mA
mV
mA
mA
OL
OL
Full range
25°C
I
I
V
OL
= 1.5 mV
6
16
6
16
6
16
OL
25°C
0.3
0.6
0.8
0.3
0.6
0.8
0.3
0.6
0.8
Supply current
(four comparators)
No load
DD
Full range
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70 °C for TLC354C, –40°C to 85°C for TLC354I, and –55°C to
125°C for the TLC354M. MAX is 70°C for TLC354C, 85°C TLC354I, and 125°C for the TLC354M. IMPORTANT: See Parameter Measurement Information.
NOTE 5: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and V . They can
DD
be verified by applying the limit value to the input and checking for the appropriate output state.
switching characteristics, V
= 5 V, T = 25°C
A
DD
TLC354C, TLC354I
TLC354M
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
650
200
MAX
100-mV input step with 5-mV overdrive
TTL-level input step
R
C
connected to 5 V through 5.1 kΩ,
L
L
Response time
ns
‡
= 15 pF ,
See Note 6
‡
C
includes probe and jig capacitance.
L
NOTE 6: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
TLC354
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997
electrical characteristics at specified free-air temperature, V = 1.4 V, T = 25°C (unless otherwise
DD
A
noted)
TLC354Y
PARAMETER
Input offset voltage
TEST CONDITIONS
UNIT
MIN
TYP
MAX
V
IO
V
IC
= V min, See Note 4
ICR
2
1
5
5
mV
pA
pA
I
I
Input offset current
Input bias current
IO
IB
0 to
0.2
V
ICR
Common-mode input voltage range
V
I
High-level output current
Low-level output voltage
Low-level output current
V
ID
V
ID
V
ID
V
ID
= 1 V,
V
= 5 V
0.1
100
1.6
nA
mV
mA
µA
OH
OH
= 0.6 mA
V
= –0.5 V,
= –0.5 V,
= 0.5 V,
I
200
300
OL
OL
I
V
= 300 mV
1
OL
DD
OL
No load
I
Supply current (four comparators)
130
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 1.25 V or below 150 mV with a 10-kΩ resistor
between the output and V . They can be verified by applying the limit value to the input and checking for the appropriate output state.
DD
electrical characteristics at specified free-air temperature, V
noted)
= 5 V, T = 25°C (unless otherwise
DD
A
TLC354Y
PARAMETER
TEST CONDITIONS
= V min, See Note 5
UNIT
MIN
TYP
MAX
V
IO
Input offset voltage
V
IC
2
1
5
5
mV
pA
pA
ICR
I
I
Input offset current
Input bias current
IO
IB
0 to
V
ICR
Common-mode input voltage range
V
V
–1
DD
I
High-level output current
Low-level output voltage
Low-level output current
V
ID
V
ID
V
ID
V
ID
= 1 V,
V
= 5 V
0.1
150
16
nA
mV
mA
mA
OH
OH
= 4 mA
V
= –1 V,
= –1 V,
= 1 V,
I
400
0.6
OL
OL
I
I
V
= 1.5 mV
6
OL
OL
No load
Supply current (four comparators)
0.3
DD
NOTE 5: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor
between the output and V . They can be verified by applying the limit value to the input and checking for the appropriate output state.
DD
switching characteristics, V
= 5 V, T = 25°C
A
DD
TLC354Y
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
100-mV input step with 5-mV overdrive
TTL-level input step
650
R
C
connected to 5 V through 5.1 kΩ,
L
L
Response time
ns
‡
= 15 pF ,
See Note 6
200
‡
C
includes probe and jig capacitance.
L
NOTE 6: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC354
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC354 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the V
accuracy.
test, rather than changing the input voltages, to provide greater
ICR
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes state.
5 V
1 V
5.1 kΩ
5.1 kΩ
Applied V
Limit
Applied V
Limit
IO
IO
V
O
V
O
–4 V
(a) V WITH V = 0
IO IC
(b) V WITH V = 4 V
IO IC
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC354
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
Figure 2 illustrates a practicle circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
C3
0.68 µF
R5
1.8 kΩ, 1%
V
DD
U1b
1/4 TLC274CN
C2
1 µF
U1c
1/4 TLC274CN
R6
5.1 kΩ
Buffer
+
–
–
OUT
V
R4
47 kΩ
IO
(X100)
R7
1 MΩ
+
R1
Integrator
240 kΩ
C4
R8
0.1 µF
1.8 kΩ, 1%
U1a
+
–
1/4 TLC274CN
C1
0.1 µF
Triangle
Generator
R9
10 kΩ, 1%
R10
100 Ω, 1%
R2
10 kΩ
R3
100 kΩ
Figure 2. Test Circuit for Input Offset Voltage Measurement
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC354
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the trailing
edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input
offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3)
so that the circuit is just at the transition point. Then a low signal, for example, 105-mV or 5-mV overdrive, causes
the output to change.
V
DD
1 µF
5.1 kΩ
Pulse Generator
OUT
C
L
50 Ω
(see Note A)
1 V
Input
Offset Voltage
Compensation
Adjustment
10 Ω
10 Turn
1 kΩ
0.1 µF
–1 V
TEST CIRCUIT
Overdrive
Input
100 mV
Overdrive
Input
100 mV
90%
10%
90%
50%
10%
50%
Low-to-High-
Level Ouptut
High-to-Low-
Level Ouptut
t
t
t
r
f
t
PLH
PLH
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
L
Figure 3. Response, Rise, and Fall Times Test Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
TLC354CD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
TLC354C
TLC354CDG4
TLC354CN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
D
N
50
25
Green (RoHS
& no Sb/Br)
0 to 70
TLC354C
TLC354CN
P354
PDIP
Pb-Free
(RoHS)
0 to 70
TLC354CPW
TLC354CPWG4
TLC354CPWR
TLC354CPWRG4
TLC354ID
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90
Green (RoHS
& no Sb/Br)
0 to 70
90
Green (RoHS
& no Sb/Br)
0 to 70
P354
2000
2000
50
Green (RoHS
& no Sb/Br)
0 to 70
P354
Green (RoHS
& no Sb/Br)
0 to 70
P354
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
TLC354I
TLC354I
TLC354IDG4
TLC354IN
SOIC
D
50
Green (RoHS
& no Sb/Br)
PDIP
N
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC354CPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TLC354CPWR
2000
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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Copyright © 2014, Texas Instruments Incorporated
TLC354CDG4 CAD模型
封装焊盘图
TLC354CDG4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| TLC354CD | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 类似代替 |
|
| TLC339MDRG4 | TI | LinCOMS MICROPOWER QUAD COMPARATORS | 类似代替 |
|
TLC354CDG4 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| TLC354CN | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 获取价格 |
|
| TLC354CPW | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 获取价格 |
|
| TLC354CPWR | TI | Quad, Low Voltage, LinCMOS™ Differential Comparator 14-TSSOP 0 to 70 | 获取价格 |
|
| TLC354D | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 获取价格 |
|
| TLC354ID | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 获取价格 |
|
| TLC354IDG4 | TI | Quad, Low Voltage, LinCMOS™ Differential Comparator 14-SOIC -40 to 85 | 获取价格 |
|
| TLC354IDR | TI | QUAD COMPARATOR, 7000uV OFFSET-MAX, 650ns RESPONSE TIME, PDSO14, GREEN, SOIC-14 | 获取价格 |
|
| TLC354IN | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 获取价格 |
|
| TLC354MD | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 获取价格 |
|
| TLC354MN | TI | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS | 获取价格 |
|
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