TLC372_V01 [TI]

LinCMOS DUAL DIFFERENTIAL COMPARATORS;


型号：	TLC372_V01
厂家：	TEXAS INSTRUMENTS
描述：	LinCMOS DUAL DIFFERENTIAL COMPARATORS
文件：	总29页 (文件大小：1583K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

TLC372C, TLC372I, TLC372M, TLC372Q

D, P, OR PW PACKAGE

TLC372M . . . JG PACKAGE

(TOP VIEW)

Single or Dual-Supply Operation

Wide Range of Supply Voltages 2 V to 18 V

Low Supply Current Drain

150 µA Typ at 5 V

Fast Response Time . . . 200 ns Typ for

TTL-Level Input Step

1OUT

1IN−

1IN+

GND

2OUT

2IN−

2IN+

Built-in ESD Protection

High Input Impedance . . . 10 Ω Typ

Extremely Low Input Bias Current

5 pA Typ

TLC372M . . . FK PACKAGE

(TOP VIEW)

Ultrastable Low Input Offset Voltage

Input Offset Voltage Change at Worst-Case

Input Conditions Typically 0.23 µV/Month,

Including the First 30 Days

20 19

1IN−

Common-Mode Input Voltage Range

Includes Ground

2OUT

Output Compatible With TTL, MOS, and

CMOS

2IN−

1IN+

9 10 11 12 13

Pin-Compatible With LM393

description

This device is fabricated using LinCMOS

technology and consists of two independent

voltage comparators, each designed to operate

from a single power supply. Operation from dual

supplies is also possible if the difference between

the two supplies is 2 V to 18 V. Each device

features extremely high input impedance

NC − No internal connection

TLC372M

U PACKAGE

(TOP VIEW)

1OUT

1IN−

(typically greater than 10 Ω), allowing direct

interfacing with high-impedance sources. The

outputs are n-channel open-drain configurations

and can be connected to achieve positive-logic

wired-AND relationships.

2OUT

2IN−

2IN+

1IN+

GND

The TLC372 has internal electrostatic discharge

(ESD) protection circuits and has been classified

with a 1000-V ESD rating using human body

model testing. However, care should be exercised

in handling this device as exposure to ESD may

result in a degradation of the device parametric

performance.

symbol (each comparator)

IN+

OUT

IN −

The TLC372C is characterized for operation from 0°C to 70°C. The TLC372I is characterized for operation from

−40°C to 85°C. The TLC372M is characterized for operation over the full military temperature range of −55°C

to 125°C. The TLC372Q is characterized for operation from −40°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.

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ꢚ ꢙ ꢘ ꢇꢡ ꢘ ꢖꢡ ꢥ ꢘ ꢖꢖ ꢘ ꢇ ꢙꢦꢢ ꢓꢖ ꢕ ꢡꢜꢛ ꢙꢆꢕꢇ ꢞꢖ ꢕꢛ ꢝꢚ ꢚꢆ ꢇꢧ ꢡꢕꢝ ꢚ ꢇꢕꢙ ꢇꢝ ꢛꢝ ꢚꢚ ꢘꢖ ꢆꢠ ꢦ ꢆꢇꢛ ꢠꢜꢡ ꢝ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

equivalent schematic (each comparator)

Common to All Channels

OUT

GND

IN +

IN −

(1)

AVAILABLE OPTIONS

PACKAGED DEVICES

max

SMALL

CHIP

CARRIER

(FK)

CERAMIC

DIP

PLASTIC

DIP

CERAMIC

FLAT PACK

(U)

TSSOP

(PW)

AT 25°C

OUTLINE

(2)

(D)

(JG)

(P)

0°C to 70°C

−40°C to 85°C

−55°C to 125°C

−40°C to 125°C

5 mV

TLC372CD

TLC372ID

TLC372MD

TLC372QD

—

TLC372CP

TLC372IP

TLC372MP

TLC372QP

TLC372CPW

—

TLC372MFK

—

TLC372MJG

—

TLC372MU

—

1.For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web

site at www.ti.com.

2.The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V

Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited

Package thermal impedance, θ (see Notes 6 and 7): D package . . . . . . . . . . . . . . . . . . . . . . . . . . 97.1°C/W

P package . . . . . . . . . . . . . . . . . . . . . . . . . . 84.6°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W

Package thermal impedance, θ (see Notes 6 and 7): FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6°C/W

JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W

U package . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7°C/W

Operating free-air temperature range, T : TLC372C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

TLC372I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

TLC372M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

TLC372Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U package . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 3. All voltage values except differential voltages are with respect to network ground.

4. Differential voltages are at IN+ with respect to IN −.

5. Short circuits from outputs to V

can cause excessive heating and eventual device destruction.

6. ^{Maximum power dissipation is a function of T (max),}θ , and T . The maximum allowable power dissipation at any allowable

ambient temperature is P ^{= (T (max) − T )/}θ . Operating at the absolute maximum T of 150°C can affect reliability.

7. The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).

recommended operating conditions

TLC372C

TLC372I

TLC372M

TLC372Q

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Supply voltage, V

3.5

8.5

3.5

8.5

3.5

8.5

125

3.5

8.5

125

= 5 V

Common-mode input voltage, V

= 10 V

Operating free-air temperature, T

−40

−55

−40

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Template Release Date: 7−11−94

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

electrical characteristics at specified free-air temperature, V

noted)

= 5 V, T = 25°C (unless otherwise

TLC372Y

†

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

Input offset voltage

= V

ICR

min, See Note 4

Input offset current

Input bias current

0 to

−1

ICR

Common-mode input voltage range

High-level output current

Low-level output voltage

Low-level output current

= 1 V,

= 5 V

0.1

150

µA

= 4 mA

= −1 V,

= 1 V,

400

300

= 1.5 V

No load

Supply current (two comparators)

150

†

All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement

Information.

NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor

between the output and V . They can be verified by applying the limit value to the input and checking for the appropriate output state.

PARAMETER MEASUREMENT INFORMATION

The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.

Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force

the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the

following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are

offered.

To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown

in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With

the input polarity reversed, the output should be low.

A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can

be slewed as shown in Figure 1(b) for the V

accuracy.

test, rather than changing the input voltages, to provide greater

ICR

5 V

1 V

5.1 kΩ

−

Applied V

Limit

Applied V

Limit

−4 V

(a) V WITH V = 0

IO IC

(b) V WITH V = 4 V

IO IC

Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PARAMETER MEASUREMENT INFORMATION

A close approximation of the input offset voltage can be obtained by using a binary search method to vary the

differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but

opposite in polarity, to the input offset voltage, the output changes states.

Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the

comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a

triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual

dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input

is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop

reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which

can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input

exactly equals the input offset voltage.

Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement

easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is

suggested that their tolerance level be 1% or lower.

Measuring the extremely low values of input current requires isolation from all other sources of leakage current and

compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage

can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from

the measurement obtained with a device in the socket to obtain the actual input current of the device.

0.68 µF

1.8 kΩ, 1%

U1b

1/4 TLC274C

1 µF

U1c

1/4 TLC274CN

5.1 kΩ

Buffer

−

DUT

1 MΩ

(X100)

47 kΩ

240 kΩ

1.8 kΩ, 1%

Integrator

0.1 µF

U1a

−

1/4 TLC274CN

0.1 µF

Triangle

Generator

10 kΩ, 1%

R10

100 Ω, 1%

10 kΩ

100 kΩ

Figure 2. Circuit for Input Offset Voltage Measurement

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PARAMETER MEASUREMENT INFORMATION

Response time is defined as the interval between the application of an input step function and the instant when the

output reaches 50% of its maximum value. Response time, low-to-high level output, is measured from the leading

edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input

pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The

offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit

is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change

state.

1 µF

5.1 kΩ

Pulse

Generator

DUT

50 Ω

1 V

(see Note A)

Input Offset Voltage

Compensation Adjustment

10 Ω

10 Turn

1 kΩ

−1 V

0.1 µF

TEST CIRCUIT

Overdrive

100 mV

Input

Overdrive

Input

100 mV

90%

50%

10%

90%

50%

Low-to-High-

Level Output

High-to-Low-

Level Output

10%

PLH

PHL

VOLTAGE WAVEFORMS

NOTE A: C includes probe and jig capacitance.

Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PRINCIPLES OF OPERATION

LinCMOS process

The LinCMOS process is a Linear polysilicon-gate complementary-MOS process. Primarily designed for

single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance

analog functions, from operational amplifiers to complex mixed-mode converters.

While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.

This short guide is intended to answer the most frequently asked questions related to the quality and reliability

of LinCMOS products. Further questions should be directed to the nearest Texas Instruments field sales office.

electrostatic discharge

CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only

for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to

CMOS devices. It can occur when a device is handled without proper consideration for environmental

electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational

amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision

for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.

To prevent voltage buildup, each pin is protected by internal circuitry.

Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more

transistors break down at voltages higher than the normal operating voltages but lower than the breakdown

voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the

shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are

small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as

tens of picoamps.

To overcome this limitation, Texas Instruments design engineers developed the patented ESD-protection circuit

shown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating

leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of Texas

Instruments’s ESD- protection circuit is presented on the next page.

All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection

circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through

a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor

(charged device model). These tests simulate both operator and machine handling of devices during normal

test and assembly operations.

Input

To Protected Circuit

Figure 4. LinCMOS ESD-Protection Schematic

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PRINCIPLES OF OPERATION

input protection circuit operation

Texas Instruments’ patented protection circuitry allows for both positive-and negative-going ESD transients.

These transients are characterized by extremely fast rise times and usually low energies, and can occur both

when the device has all pins open and when it is installed in a circuit.

positive ESD transients

Initial positive charged energy is shunted through Q1 to V . Q1 turns on when the voltage at the input rises

above the voltage on the V

pin by a value equal to the V of Q1. The base current increases through R2

with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2

to exceed its threshold level (V ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to V

is now shunted through the n-channel enhancement-type MOSFET Q2 to V . If the voltage on the input pin

continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is

dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the

gate oxide voltage of the circuit to be protected.

negative ESD transients

The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1

and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is −0.3 V to −1 V (the forward

voltage of D1 and D2).

circuit-design considerations

LinCMOS products are being used in actual circuit environments that have input voltages that exceed the

recommended common-mode input voltage range and activate the input protection circuit. Even under normal

operation, these conditions occur during circuit power up or power down, and in many cases, when the device

is being used for a signal conditioning function. The input voltages can exceed V

and not damage the device

ICR

only if the inputs are current limited. The recommended current limit shown on most product data sheets is

5 mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current.

Normal operation and correct output state can be expected even when the input voltage exceeds the positive

supply voltage. Again, the input current should be externally limited even though internal positive current limiting

is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current

to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input

current. This base current is forced into the V

producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input

pin and into the device I

or the V

supply through R2

voltage is below the V of Q2.

When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage

states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be

severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and

no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is

required (see Figure 7).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢅ

ꢆ

ꢁ

ꢇ

ꢂ

ꢈ

ꢉ

ꢊ 

ꢋ ꢌꢍ ꢁ ꢋꢎ ꢏ ꢏꢐ ꢑꢐ ꢒꢀ ꢎ ꢍꢁ ꢂꢉ ꢈꢓꢍꢑꢍꢀꢉ ꢑꢊ

SLCS114E − NOVEMBER 1983 − REVISED JULY 2008

PRINCIPLES OF OPERATION

circuit-design considerations (continued)

INPUT CURRENT

POSITIVE INPUT VOLTAGE

NEGATIVE INPUT VOLTAGE

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

= 25°C

+ 4

+ 8

+ 12

−0.3

−0.5

−0.7

−0.9

Input Voltage (V)

Figure 5

Figure 6

Positive Voltage Input Current Limit:

+V − V − 0.3 V

5 mA

R =

Negative Voltage Input Current Limit:

| −V | − 0.3 V

R =

TLC372

−

5 mA

ref

See Note A

NOTE A: If the correct output state is required when the negative input is less than GND, a schottky clamp is required.

Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

5962-87658012A

ACTIVE

LCCC

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

87658012A

TLC372MFKB

5962-8765801PA

5962-9554901NXD

5962-9554901NXDR

TLC372CD

ACTIVE

CDIP

SOIC

PDIP

SNPB

N / A for Pkg Type

Level-1-260C-UNLIM

N / A for Pkg Type

-55 to 125

0 to 70

8765801PA

TLC372M

2500

Green (RoHS

& no Sb/Br)

NIPDAU

Q372M

372C

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLC372CDR

2500

Green (RoHS

& no Sb/Br)

0 to 70

372C

TLC372CDRG4

TLC372CP

Green (RoHS

& no Sb/Br)

0 to 70

372C

Green (RoHS

& no Sb/Br)

0 to 70

TLC372CP

P372

TLC372CPS

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

0 to 70

TLC372CPSG4

TLC372CPSR

TLC372CPSRG4

TLC372CPW

Green (RoHS

& no Sb/Br)

0 to 70

P372

2000

150

2000

Green (RoHS

& no Sb/Br)

0 to 70

P372

Green (RoHS

& no Sb/Br)

0 to 70

P372

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

P372

TLC372CPWR

TLC372CPWRG4

TLC372ID

Green (RoHS

& no Sb/Br)

0 to 70

P372

Green (RoHS

& no Sb/Br)

0 to 70

P372

Green (RoHS

& no Sb/Br)

-40 to 85

372I

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2020

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2500

(1)

(2)

(3)

(4/5)

(6)

TLC372IDR

TLC372IDRG4

TLC372IP

ACTIVE

SOIC

PDIP

SOIC

LCCC

Green (RoHS

& no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 85

-55 to 125

372I

ACTIVE

Green (RoHS

& no Sb/Br)

NIPDAU

Green (RoHS

& no Sb/Br)

TLC372IP

372M

TLC372MD

Green (RoHS

& no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

TLC372MDG4

TLC372MDR

TLC372MDRG4

TLC372MFKB

Green (RoHS

& no Sb/Br)

NIPDAU

372M

2500

Green (RoHS

& no Sb/Br)

NIPDAU

-55 to 125

372M

Green (RoHS

& no Sb/Br)

NIPDAU

372M

TBD

POST-PLATE

5962-

87658012A

TLC372MFKB

TLC372MJG

ACTIVE

CDIP

TBD

SNPB

N / A for Pkg Type

-55 to 125

TLC372MJG

TLC372MJGB

8765801PA

TLC372M

TLC372MP

ACTIVE

PDIP

Pb-Free

(RoHS)

NIPDAU

N / A for Pkg Type

-55 to 125

TLC372MP

TLC372MUB

TLC372QD

ACTIVE

CFP

TBD

Call TI

N / A for Pkg Type

-55 to 125

-40 to 125

TLC372MUB

372Q

SOIC

Green (RoHS

& no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

TLC372QDG4

TLC372QDR

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

372Q

2500

Green (RoHS

& no Sb/Br)

TLC372QDRG4

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2020

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC372, TLC372M :

Catalog: TLC372

•

Enhanced Product: TLC372-EP, TLC372-EP

•

Military: TLC372M

•

NOTE: Qualified Version Definitions:

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2020

Catalog - TI's standard catalog product

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

Military - QML certified for Military and Defense Applications

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Sep-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

5962-9554901NXDR

TLC372CDR

SOIC

2500

2000

2500

330.0

12.4

16.4

12.4

6.4

8.35

7.0

6.4

5.2

6.6

3.6

5.2

2.1

2.5

1.6

2.1

8.0

12.0

8.0

12.0

16.0

12.0

TLC372CPSR

TLC372CPWR

TLC372IDR

TSSOP

SOIC

TLC372MDR

TLC372MDRG4

TLC372QDR

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

25-Sep-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

5962-9554901NXDR

TLC372CDR

SOIC

2500

2000

2500

350.0

340.5

367.0

340.5

350.0

338.1

367.0

338.1

350.0

43.0

20.6

38.0

35.0

20.6

43.0

TLC372CPSR

TLC372CPWR

TLC372IDR

TSSOP

SOIC

TLC372MDR

TLC372MDRG4

TLC372QDR

Pack Materials-Page 2

PACKAGE OUTLINE

U0010A

CFP - 2.03 mm max height

CERAMIC FLATPACK

.27 MAX

GLASS

.005 MIN

TYP

.010 .002

PIN 1 ID

.045 MAX

TYP

8X .050 .005

.27 MAX

GLASS

10X .017 .002

+.019

.241

5X .32 .01

-.003

.005 .001

+.013

.067

-.012

.045

.026

4225582/A 01/2020

NOTES:

1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.280 (7,11)

0.245 (6,22)

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.063 (1,60)

0.015 (0,38)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.023 (0,58)

0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

6X 0.65

3.1

2.9

NOTE 3

1.95

0.30

0.19

4.5

4.3

1.2 MAX

0.1

C A

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

TYP

SYMM

6X (0.65)

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

SYMM

6X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLC372_V01 [TI]

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