TLC551Y [TI]
LinCMOSE TIMERS; LinCMOSE定时器
| 型号： | TLC551Y |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOSE TIMERS |
| 文件： | 总16页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
D, DB, P, OR PW PACKAGE
(TOP VIEW)
Very Low Power Consumption
1 mW Typ at V = 5 V
DD
Capable of Operation in Astable Mode
GND
TRIG
OUT
V
DD
1
2
3
4
8
7
6
5
DISCH
THRES
CONT
CMOS Output Capable of Swinging Rail
to Rail
RESET
High Output-Current Capability
Sink 100 mA Typ
functional block diagram
Source 10 mA Typ
CONT
Output Fully Compatible With CMOS, TTL,
and MOS
RESET
5
4
V
8
DD
Low Supply Current Reduces Spikes
During Output Transitions
R
6
R1
R
THRES
TRIG
3
OUT
1
Single-Supply Operation From 1 V to 15 V
S
Functionally Interchangeable With the
NE555; Has Same Pinout
R
2
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2
R
1
7
DISCH
description
GND
The TLC551 is a monolithic timing circuit
fabricated using the TI LinCMOS process. The
RESET can override TRIG, which can override THRES.
timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared
to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result,
more accurate time delays and oscillations are possible. Power consumption is low across the full range of
power supply voltage.
Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs
should be tied to an appropriate logic level to prevent false triggering.
Whilethe CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.
The TLC551C is characterized for operation from 0°C to 70°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044A – FEBRUARY 1984 – REVISED MAY 1997
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP FORM
(Y)
SMALL
OUTLINE
(D)
V
SSOP
(DB)
PLASTIC DIP
(P)
TSSOP
(PW)
DD
RANGE
T
A
0°C to 70°C
1 V to 16 V TLC551CD TLC551CDBLE
TLC551CP
TLC551CPWLE
TLC551Y
The D package is available taped and reeled. Add the suffix R (e.g., TLC551CDR). The DB and PW packages are only
available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC551CDBLE). Chips are
tested at 25°C.
FUNCTION TABLE
RESET
VOLTAGE
TRIGGER
THRESHOLD
DISCHARGE
SWITCH
OUTPUT
†
†
†
VOLTAGE
Irrelevant
<MIN
VOLTAGE
Irrelevant
Irrelevant
>MAX
<MIN
Low
High
Low
On
Off
On
>MAX
>MAX
>MAX
>MAX
>MAX
<MIN
As previously established
†
For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.
TLC551Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC551. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CONT
(5)
RESET
(4)
V
DD
(8)
R
(6)
R1
(3)
THRES
TRIG
OUT
R
S
1
50
R
(2)
R
(7)
DISCH
(1)
GND
64
RESET can override TRIG, which can override THRES.
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
T max = 150°C
J
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent schematic
COMPONENT COUNT
Transistors
Resistors
39
5
THRES
V
DD
CONT
OUT
DISCH
GND
TRIG
RESET
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
DD
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to V
Sink current, discharge or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
I
DD
Source current, output, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network GND.
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
T
A
T = 70°C
A
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D
DB
P
725 mW
525 mW
1000 mW
525 mW
5.8 mW/°C
4.2 mW/°C
8.0 mW/°C
4.2 mW/°C
464 mW
336 mW
640 mW
336 mW
PW
recommended operating conditions
MIN
1
MAX
15
UNIT
V
Supply voltage, V
DD
Operating free-air temperature range, T
0
70
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, V
= 1 V
DD
†
PARAMETER
TEST CONDITIONS
T
A
MIN
0.475
0.45
TYP
MAX
0.85
UNIT
25°C
Full range
25°C
0.67
V
IT
Threshold voltage
V
0.875
10
75
I
IT
Threshold current
Trigger voltage
Trigger current
Reset voltage
Reset current
pA
V
70°C
25°C
0.15
0.1
0.33 0.425
V
I(TRIG)
I(TRIG)
Full range
25°C
0.45
10
75
I
pA
V
70°C
25°C
0.4
0.3
0.7
1
1
V
I(RESET)
I(RESET)
Full range
25°C
10
75
I
pA
70°C
Control voltage (open circuit) as a percentage of
supply voltage
70°C
66.7%
0.02
25°C
Full range
25°C
0.15
0.2
Discharge switch on-stage voltage
Discharge switch off-stage voltage
High-level output voltage
Low-level output voltage
Supply current
I
= 100 µA
V
nA
V
OL
0.1
0.5
70°C
25°C
0.6
0.6
0.98
V
V
I
I
= –10 µA
= 100 µA
OH
OH
Full range
25°C
0.03
15
0.2
0.25
100
150
V
OL
OL
Full range
25°C
I
See Note 2
µA
DD
Full range
†
Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, V
= 2 V
DD
†
PARAMETER
TEST CONDITIONS
T
A
MIN
0.95
0.85
TYP
MAX
1.65
1.75
UNIT
25°C
Full range
25°C
1.33
V
IT
Threshold voltage
V
10
75
I
IT
Threshold current
Trigger voltage
Trigger current
Reset voltage
Reset current
pA
V
70°C
25°C
0.4
0.3
0.67
0.95
1.05
V
I(TRIG)
I(TRIG)
Full range
25°C
10
75
I
pA
V
70°C
25°C
0.4
0.3
1.1
1.5
1.8
V
I(RESET)
I(RESET)
Full range
25°C
10
75
I
pA
70°C
Control voltage (open circuit) as a percentage of
supply voltage
70°C
66.7%
0.03
25°C
Full range
25°C
0.2
Discharge switch on-stage voltage
Discharge switch off-stage voltage
High-level output voltage
Low-level output voltage
Supply current
I
= 1 mA
V
nA
V
OL
0.25
0.1
0.5
1.9
70°C
25°C
1.5
1.5
V
V
I
I
= –300 µA
OH
OH
Full range
25°C
0.07
65
0.3
0.35
250
400
= 1 mA
V
OL
OL
Full range
25°C
I
See Note 2
µA
DD
Full range
†
Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, V
= 5 V
DD
†
PARAMETER
TEST CONDITIONS
T
A
MIN
2.8
TYP
MAX
3.8
UNIT
25°C
Full range
25°C
3.3
V
IT
Threshold voltage
V
2.7
3.9
10
75
I
IT
Threshold current
Trigger voltage
Trigger current
Reset voltage
Reset current
pA
V
70°C
25°C
1.36
1.26
1.66
1.96
2.06
V
I(TRIG)
I(TRIG)
Full range
25°C
10
75
I
pA
V
70°C
25°C
0.4
0.3
1.1
1.5
1.8
V
I(RESET)
I(RESET)
Full range
25°C
10
75
I
pA
70°C
Control voltage (open circuit) as a percentage of
supply voltage
70°C
66.7%
0.14
25°C
Full range
25°C
0.5
0.6
Discharge switch on-stage voltage
Discharge switch off-stage voltage
High-level output voltage
I
= 10 mA
V
nA
V
OL
0.1
0.5
4.8
70°C
25°C
4.1
4.1
V
V
I
I
I
I
= –1 mA
= 8 mA
OH
OH
OL
OL
OL
Full range
25°C
0.21
0.13
0.08
170
0.4
0.5
Full range
25°C
0.3
Low-level output voltage
Supply current
= 5 mA
V
OL
Full range
25°C
0.4
0.3
= 3.2 mA
Full range
25°C
0.35
350
500
I
See Note 2
µA
DD
Full range
†
Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, V
= 15 V
DD
†
PARAMETER
TEST CONDITIONS
T
A
MIN
9.45
9.35
TYP
MAX
10.55
10.65
UNIT
25°C
V
IT
Threshold voltage
V
Full range
25°C
10
75
5
I
IT
Threshold current
Trigger voltage
Trigger current
Reset voltage
Reset current
pA
V
70°C
25°C
4.65
4.55
5.35
5.45
V
I(TRIG)
I(TRIG)
Full range
25°C
10
75
I
pA
V
70°C
25°C
0.4
0.3
1.1
1.5
1.8
V
I(RESET)
I(RESET)
Full range
25°C
10
75
I
pA
70°C
Control voltage (open circuit) as a percentage of
supply voltage
70°C
66.7%
0.77
25°C
Full range
25°C
1.7
1.8
Discharge switch on-stage voltage
Discharge switch off-stage voltage
I
= 100 mA
V
OL
0.1
0.5
nA
70°C
25°C
12.5
12.5
13.5
13.5
14.2
14.2
14.2
I
I
I
I
I
I
= –10 mA
= –5 mA
= –1 mA
= 100 mA
= 50 mA
= 10 mA
OH
OH
OH
OL
OL
OL
Full range
25°C
14.6
14.9
1.28
0.63
0.12
360
V
OH
High-level output voltage
V
Full range
25°C
Full range
25°C
3.2
3.6
1
Full range
25°C
V
OL
Low-level output voltage
Supply current
V
Full range
25°C
1.3
0.3
0.4
600
800
Full range
25°C
I
See Note 2
µA
DD
Full range
†
Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
operating characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
DD
A
PARAMETER
TEST CONDITIONS
MIN
TYP
1%
0.1
20
MAX
3%
0.5
75
UNIT
‡
Initial error of timing interval
V
C
= 5 V to 15 V,
R = R = 1 kΩ to 100 kΩ,
A B
See Note 3
DD
T
= 0.1 µF,
Supply voltage sensitivity of timing interval
Rise time, output pulse
%/V
ns
t
t
r
R
= 10 MΩ,
C
R
= 10 pF
L
L
Fall time, output pulse
15
60
f
R
C
= 470 Ω,
= 200 pF
= 200 Ω,
A
T
B
f
Maximum frequency in astable mode
1.2
1.8
MHz
max
See Note 3
‡
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.
NOTE 3: R , R , and C are as defined in Figure 3.
A
B
T
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at V
= 5 V, T = 25°C
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
V
V
IT
Threshold voltage
Threshold current
Trigger voltage
2.8
3.3
10
3.8
I
IT
pA
V
V
1.36
0.4
1.66
1.96
I(TRIG)
I(TRIG)
I
Trigger current
10
pA
V
Reset voltage
Reset current
1.1
10
1.5
0.5
V
I(RESET)
I
pA
I(RESET)
Control voltage (open circuit) as a percentage of supply voltage
Discharge switch on-state voltage
66.7%
0.14
0.1
I
= 10 mA
V
nA
V
OL
Discharge switch off-state current
V
V
High-level output voltage
I
I
I
I
= – 1 mA
= 8 mA
4.1
4.8
OH
OH
OL
OL
OL
0.21
0.13
0.08
170
0.4
0.3
0.3
350
Low-level output voltage
= 5 mA
V
OL
= 3.2 mA
I
Supply current
See Note 2
µA
DD
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES (TO DISCHARGE
OUTPUT FROM TRIGGER AND THRESHOLD
SHORTED TOGETHER)
DISCHARGE SWITCH ON-STATE RESISTANCE
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
600
100
I
C
≥ 1 mA
O(on)
≈ 0
70
L
V
DD
= 2 V, I = 1 mA
O
500
T
A
= 25°C
40
V
DD
= 5 V, I = 10 mA
O
400
300
20
10
7
V
DD
= 15 V, I = 100 mA
O
t
PHL
‡
200
100
4
t
PLH
2
1
0
0
2
4
6
8
10 12 14 16 18 20
0
25
50
75
100
V
– Supply Voltage – V
DD
T
– Free-Air Temperature – °C
A
‡
The effects of the load resistance on these values must be
taken into account separately.
Figure 1
Figure 2
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
V
DD
0.1 µF
t
c(L)
t
c(H)
R
R
A
B
V
DD
0.1 µF
t
5
8
V
DD
PHL
CONT
4
R
L
RESET
2/3 V
DD
TLC551
7
DISCH
Output
3
OUT
6
2
1/3 V
DD
THRES
TRIG
C
L
GND
GND
C
T
1
t
PLH
CIRCUIT
TRIGGER AND THRESHOLD VOLTAGE WAVEFORM
Figure 3. Astable Operation
Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor C
T
B
charges through R and R to the threshold voltage level (approximately 0.67 V ) and then discharges through R
A
B
DD
only to the value of the trigger voltage level (approximately 0.33 V ). The output is high during the charging cycle
DD
(t
) and low during the discharge cycle (t
). The duty cycle is controlled by the values of R , and R , and C , as
c(H)
c(L) A B T
shown in the equations below.
t
C
C
(R
R
R ) In 2 (In 2
B
0.693)
c(H)
T
A
t
In 2
t
c(L)
Period
T
t
B
C
t
(R
t
2R ) In 2
B
c(H)
c(L)
T
A
c(L)
R
R
B
2R
Output driver duty cycle
1 –
t
R
R
c(H)
c(L)
A
B
t
c(H)
B
2R
Output waveform duty cycle
t
t
c(H)
c(L)
A
B
The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay times from TRIG and THRES to DISCH. These
delay times add directly to the period and create differences between calculated and actual values that increase with
frequency. In addition, the internal on-state resistance r during discharge adds to R to provide another source of
on
B
timing error in the calculation when R is very low or r is very high.
B
on
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
The equations below provide better agreement with measured values.
–t
PLH
t
t
C
(R
R ) In 3 –exp
t
c(H)
c(L)
T
A
B
PHL
C
(R
r
)
on
T
B
–t
PHL
C
(R
r
) In 3 –exp
on
t
T
B
PLH
C
(R
R )
T
A
B
These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number
or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely
high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted
t
t
c(H)
t
c(H)
with good results. Duty cycles less than 50%
require that
<1 and possibly R ≤ r . These
A on
t
t
c(H)
c(L)
c(L)
conditions can be difficult to obtain.
In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT. An input voltage
between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides good results.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
DIM
3,30
2,70
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /C 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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