TLC5618CP [TI]
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS; 可编程双路12位数字 - 模拟转换器
| 型号： | TLC5618CP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS |
| 文件： | 总26页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
Programmable Settling Time to 0.5 LSB
2.5 µs or 12.5 µs Typ
Input Data Update Rate of 1.21 MHz
Monotonic Over Temperature
Two 12-Bit CMOS Voltage Output DACs in
an 8-Pin Package
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
Simultaneous Updates for DAC A and
DAC B
Single Supply Operation
3-Wire Serial Interface
applications
Battery Powered Test Instruments
Digital Offset and Gain Adjustment
High-Impedance Reference Inputs
Voltage Output Range . . . 2 Times the
Reference Input Voltage
Battery Operated/Remote Industrial
Controls
Software Powerdown Mode
Internal Power-On Reset
TMS320 and SPI Compatible
Machine and Motion Control Devices
Cellular Telephones
Low Power Consumption:
3 mW Typ in Slow Mode,
8 mW Typ in Fast Mode
D, P, OR JG PACKAGE
(TOP VIEW)
DIN
SCLK
CS
V
DD
1
2
3
4
8
7
6
5
description
OUT B
REFIN
AGND
The TLC5618 is a dual 12-bit voltage output
digital-to-analog converter (DAC) with buffered
reference inputs (high impedance). The DACs
have an output voltage range that is two times the
reference voltage, and the DACs are monotonic.
The device is simple to use, running from a single
supply of 5 V. A power-on reset function is
incorporated in the device to ensure repeatable
start-up conditions.
OUT A
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
NC
NC
4
5
6
7
8
18
17
16
15
14
Digital control of the TLC5618 is over a 3-wire
CMOS-compatible serial bus. The device re-
ceives a 16-bit word for programming and
producing the analog output. The digital inputs
feature Schmitt triggers for high noise immunity.
Digital communication protocols include the
SPI , QSPI , and Microwire standards.
SCLK
NC
OUTB
NC
CS
REFIN
NC
NC
9
10 11 12 13
Two versions of the device are available. The
TLC5618 does not have an internal state machine
and is dependent on all external timing signals. The TLC5618A has an internal state machine that counts the
number of clocks from the falling edge of CS and then updates and disables the device from accepting further
data inputs. The TLC5618A is recommended for TMS320 and SPI processors, and the TLC5618 is
recommended only for SPI or 3-wire serial port processors. The TLC5618A is backward-compatible and
designed to work in TLC5618 designed systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
description (continued)
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLC5618C is characterized for operation from 0°C to 70°C. The TLC5618I is characterized for operation
from –40°C to 85°C. The TLC5618Q is characterized for operation from –40°C to 125°C. The TLC5618M is
characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
†
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
CERAMIC DIP
(JG)
20 PAD LCC
(FK)
T
A
TLC5618CD
TLC5618ACD
TLC5618CP
TLC5618ACP
—
—
—
—
0°C to 70°C
TLC5618ID
TLC5618AID
TLC5618IP
TLC5618AIP
—
—
—
—
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
TLC5618AQD
—
—
—
—
—
TLC5618AMJG
TLC5618AMFK
†
The D package is available in tape and reel by adding R to the part number
(e.g., TLC5618CDR)
DEVICE
TLC5618
TLC5618A
COMPATIBILITY
SPI, QSPI and Microwire
TMS320Cxx, SPI, QSPI, and Microwire
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
functional block diagram
DAC A
_
6
+
+
_
DAC
REFIN
4
OUT A
(Voltage Output)
×2
5
AGND
R
R
Power-Up
Reset
12-Bit DAC Register Latch A
Control
Logic
3
CS
(LSB)
(MSB)
2
4
SCLK
Program
Bits
1
12 Data Bits
DIN
16-Bit Shift Register
Double
Buffer
Latch
12-Bit DAC Register Latch B
_
+
DAC
+
_
7
OUT B
(Voltage Output)
DAC B
×2
R
R
Terminal Functions
TERMINAL
NAME
AGND
I/O
DESCRIPTION
NO.
5
Analog ground
CS
3
I
I
Chip select, active low
Serial data input
DIN
1
OUT A
OUT B
REFIN
SCLK
4
O
O
I
DAC A analog output
DAC B analog output
7
6
Reference voltage input
Serial clock input
2
I
V
DD
8
Positive power supply
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Digital input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
Reference input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
Output voltage at OUT from external source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
+ 0.3 V
+ 0.3 V
+ 0.3 V
DD
DD
DD
Continuous current at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature range, T : TLC5618C, TLC5618AC . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC5618I, TLC5618AI . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC5618AQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
TLC5618AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
‡
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
FK
JG
P
635 mW
5.08 mW/°C
11.00 mW/°C
8.40 mW/°C
9.61 mW/°C
407 mW
330 mW
—
1375 mW
880 mW
715 mW
275 mW
210 mW
—
1050 mW
672 mW
546 mW
1202 mW
769 mW
625 mW
‡
This is the inverse of the traditional Junction-to-Ambient thermal Resistance (RΘ ). Thermal Resistances are not production tested and are for
informational purposes only.
JA
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, V
DD
4.5
5
5.5
High-level digital input voltage, V
IH
V
V
= 5 V
= 5 V
0.7 V
V
DD
DD
Low-level digital input voltage, V
IL
0.3 V
V
DD
DD
–1.1
Reference voltage, V to REFIN terminal
ref
2
2.048
V
DD
V
Load resistance, R
2
0
kΩ
L
TLC5618C, TLC5618AC
TLC5618I, TLC5618AI
TLC5618AQ
70
–40
–40
–55
85
125
125
Operating free-air temperature, T
°C
A
TLC5618AM
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,
DD
V
= 2.048 V (unless otherwise noted)
ref(REFIN)
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
bits
Resolution
12
Integral nonlinearity (INL), end point adjusted
Differential nonlinearity (DNL)
V
= 2.048 V,
= 2.048 V,
= 2.048 V,
= 2.048 V,
See Note 1
See Note 2
See Note 3
See Note 4
±4
± 1
LSB
ref(REFIN)
V
±0.5
LSB
ref(REFIN)
E
E
Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
V
±12
mV
ZS
ref(REFIN)
V
3
ppm/°C
ref(REFIN)
% of FS
voltage
Gain error
V
= 2.048 V,
= 2.048 V,
See Note 5
See Note 6
±0.29
G
ref(REFIN)
Gain error temperature coefficient
V
1
ppm/°C
ref(REFIN)
Zero scale
65
Slow
Fast
Gain
65
65
65
PSRR Power-supply rejection ratio
See Notes 7 and 8
dB
Zero scale
Gain
NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
4. Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
(T
) – E
(T
)]/V × 10 /(T
– T
).
min
ZS max
ZS min
ref max
5. Gain error is the deviation from the ideal output (V – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
ref
6
6. Gain temperature coefficient is given by: E TC = [E (T
max
) – E (T
)]/V × 10 /(T
min ref max
– T
).
min
G
G
G
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the V
this signal imposed on the zero-code output voltage.
from 4.5 V to 5.5 V dc and measuring the proportion of
DD
8. Gain-errorrejection ratio (EG-RR) is measured by varying the V
from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
DD
OUT A and OUT B output specifications
PARAMETER
Voltage output range
TEST CONDITIONS
= 10 kΩ
MIN
TYP
MAX
–0.4
UNIT
V
O
R
0
V
V
L
DD
±0.29
% of FS
voltage
Output load regulation accuracy
V
= 4.096 V,
R = 2 kΩ
L
O(OUT)
V
V
= V
= V
,
,
Fast
Slow
Fast
Slow
38
23
O(A OUT)
O(B OUT)
DD
DD
I
Output short circuit sink current
mA
mA
OSC(sink)
Input code zero
V
V
= 0 V,
= 0 V,
–54
–29
O(A OUT)
O(B OUT)
I
Output short circuit source current
OSC(source)
Full-scale code
I
I
Output sink current
V
V
= 0.25 V
= 4.2 V
5
5
mA
mA
O(sink)
O(OUT)
Output source current
O(source)
O(OUT)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,
DD
V
= 2.048 V (unless otherwise noted) (continued)
ref(REFIN)
reference input (REFIN)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–2
UNIT
V
V
I
Input voltage range
Input resistance
0
V
DD
R
C
10
5
MΩ
pF
i
i
Input capacitance
Reference feedthrough
REFIN = 1 V at 1 kHz + 1.024 V dc (see Note 9)
pp
–60
dB
Slow
Fast
0.5
1
Reference input bandwidth (f – 3 dB)
REFIN = 0.2 V + 1.024 V dc
pp
MHz
NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
at 1 kHz.
input = 1.024 V dc + 1 V
pp
ref(REFIN)
digital inputs (DIN, SCLK, CS)
PARAMETER
High-level digital input current
TEST CONDITIONS
V = V
MIN
TYP
MAX
±1
UNIT
µA
I
I
IH
I
DD
Low-level digital input current
Input capacitance
V = 0 V
I
±1
µA
IL
C
8
pF
i
power supply
PARAMETER
TEST CONDITIONS
= 5.5 V,
MIN
TYP
0.6
1.6
1
MAX
1
UNIT
V
DD
Slow
Fast
No load,
I
Power supply current
mA
DD
2.5
All inputs = 0 V or V
DD
Power down supply current
D13 = 0 (see Table 2)
µA
operating characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,
DD
V
= 2.048 V (unless otherwise noted)
ref(REFIN)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 2.048 V,
C
R
= 100 pF,
= 10 kΩ,
ref(REFIN)
Slow
Fast
Slow
Fast
0.3
0.5
L
L
T
= 25°C,
SR+
SR–
Output slew rate, positive
V/µs
A
2.4
0.15
1.2
3
0.25
1.5
V
O
from 10% to 90%
Code 32 to Code 4096,
V
= 2.048 V,
C
R
= 100 pF,
= 10 kΩ,
ref(REFIN)
L
L
T
= 25°C,
Output slew rate, negative
Output settling time
V/µs
A
V
O
from 10% to 90%
= 100 pF,
L
Code 4096 to Code 32,
C
Slow
Fast
Slow
Fast
12.5
2.5
2
To ±0.5 LSB,
R
t
t
µs
µs
s
See Note 10
= 10 kΩ,
L
C
L
= 100 pF,
Output settling time,
code-to-code
To ±0.5 LSB,
= 10 kΩ,
s(c)
See Note 11
R
2
L
DIN = All 0s to all 1s,
= 100 kHz
CS = V
,
DD
Glitch energy
5
nV–s
dB
f
(SCLK)
V
= 1 V at 1 kHz and 10 kHz + 1.024 V dc,
pp
ref(REFIN)
Input code = 10 0000 0000
S/(N+D) Signal to noise + distortion
78
NOTES: 10. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
operating characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,
DD
V
= 2.048 V (unless otherwise noted) (continued)
ref(REFIN)
digital input timing requirements
MIN NOM
MAX
UNIT
ns
t
t
t
t
t
t
t
Setup time, DIN before SCLK low
Hold time, DIN valid after SCLK low
Setup time, CS low to SCLK low
5
5
su(DS)
ns
h(DH)
5
ns
su(CSS)
su(CS1)
su(CS2)
w(CL)
Setup time, SCLK ↓ to CS ↑, external end-of-write
Setup time, SCLK ↑ to CS ↓, start of next write cycle
Pulse duration, SCLK low
10
5
ns
ns
25
25
ns
Pulse duration, SCLK high
ns
w(CH)
t
Delay time, CLK↑ to data disable (TLC5618A only)
5
20
ns
d(CS1)
CS
t
t
su(CSS)
su(CS1)
t
t
w(CH)
t
w(CL)
su(CS2)
SCLK
(see Note A)
t
t
su(DS)
h(DH)
D14
D15
D13
D12
D11 D0
DIN
DAC Data
Bits (12)
Program Bits (4)
t
s
DAC A/B
OUT
≤ Final Value ±0.5 LSB
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.
Figure 1. Timing Diagram for the TLC5618
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
Internally Generated
Disable at This Time
t
d(CS1)
CS
t
t
su(CSS)
su(CS1)
t
t
w(CH)
t
w(CL)
su(CS2)
SCLK
(see Note A)
su(DS)
(see Note A)
16th Falling Edge
D12
t
t
h(DH)
D14
D15
D13
D11 D0
DIN
DAC Data
Bits (12)
Program Bits (4)
t
s
DAC A/B
OUT
≤ Final Value ±0.5 LSB
Internal
Latch
Control
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.
Figure 2. Timing Diagram for TLC5618A Only
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OUTPUT SINK CURRENT (FAST MODE)
OUTPUT SOURCE CURRENT (FAST MODE)
vs
vs
OUTPUT LOAD VOLTAGE
OUTPUT LOAD VOLTAGE
–60
40
35
30
25
V
= 5 V,
DD
Input Code = 4095
–50
–40
20
15
–30
–20
10
5
–10
0
V
= 5 V,
DD
Input Code = 0
0
–5
2.5
3
3.5
4
4.5
4.5
1.5
2
0
0.5
1
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Load Voltage – V
Output Load Voltage – V
Figure 3
Figure 4
OUTPUT SINK CURRENT (SLOW MODE)
OUTPUT SOURCE CURRENT (SLOW MODE)
vs
vs
OUTPUT LOAD VOLTAGE
OUTPUT LOAD VOLTAGE
25
–30
20
15
–25
–20
10
5
–15
–10
0
–5
0
V
= 5 V,
V
= 5 V,
DD
Input Code = 0
DD
Input Code = 4095
–0
2.5
3
3.5
4
4.5
1.5
2
0
0.5
1
2.5
3
3.5
4
4.5
0
0.5
1
1.5
2
Output Load Voltage – V
Output Load Voltage – V
Figure 5
Figure 6
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
RELATIVE GAIN (FAST MODE)
vs
TEMPERATURE
FREQUENCY
5
0
1.6
1.4
Fast Mode
1.2
1
–5
–10
–15
0.8
0.6
Slow Mode
–20
–25
–30
0.4
V
V
T
A
= 5 V,
CC
V
V
T
A
= 5 V,
DD
= 0.2 V
+ 2.048 Vdc,
1000
REFIN
PP
= 2.048 V,
0.2
0
REFIN
= 25°C
= 25°C
100
10 K
–60 –40 –20
0
20 40 60 80 100 120 140
Temperature – °C
f – Frequency – kHz
Figure 7
Figure 8
RELATIVE GAIN (SLOW MODE)
TOTAL HARMONIC DISTORTION (SLOW MODE)
vs
vs
FREQUENCY
FREQUENCY
5
0
95
90
85
80
–5
–10
–15
–20
–25
–30
–35
–40
75
70
V
V
T
A
= 5 V,
CC
= 0.2 V
+2.048 Vdc,
1000
REFIN
PP
= 25°C
65
100
10 K
1
10
100
f – Frequency – kHz
f – Frequency – kHz
Figure 9
Figure 10
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE (SLOW MODE)
SIGNAL-TO-NOISE RATIO (SLOW MODE)
vs
vs
FREQUENCY
FREQUENCY
85
80
75
85
80
75
70
65
60
70
65
1
10
100
1
10
100
f – Frequency– kHz
f – Frequency– kHz
Figure 11
Figure 12
TOTAL HARMONIC DISTORTION (FAST MODE)
TOTAL HARMONIC DISTORTION + NOISE (FAST MODE)
vs
vs
FREQUENCY
FREQUENCY
95
85
80
90
75
85
80
75
70
65
1
10
100
1
10
100
f – Frequency – kHz
f – Frequency – kHz
Figure 13
Figure 14
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO (FAST MODE)
vs
FREQUENCY
85
80
75
70
65
1
10
100
f – Frequency – kHz
Figure 15
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
TYPICAL CHARACTERISTICS
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
500
1000
1500
2000
2500
3000
3500
4095
Samples
Figure 16. Differential Nonlinearity With Input Code
1
0.5
0
–0.5
–1
–1.5
–2
–2.5
–3.0
0
500
1000
1500
2000
2500
3000
3500
4095
Samples
Figure 17. Integral Nonlinearity With Input Code
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
general function
The TLC5618 uses a resistor string network buffered with an op amp to convert 12-bit digital data to analog
voltage levels (see functional block diagram and Figure 18). The output is the same polarity as the reference
input (see Table 1).
CODE
REFIN
4096
The output code is given by: 2 V
An internal circuit resets the DAC register to all 0s on power up.
+
_
REFIN
Resistor
String
DAC
×2
DIN
CS
+
_
OUT
R
SCLK
R
AGND
V
DD
5 V
0.1 µF
Figure 18. TLC5618 Typical Circuit
Table 1. Binary Code Table (0 V to 2 V
Output) Gain = 2
,
REFIN
INPUT
OUTPUT
4095
4096
:
1111
1111
1111
2 V
REFIN
:
2049
4096
1000
1000
0111
0000
0000
0001
0000
1111
2 V
REFIN
2048
4096
2 V
V
REFIN
2 V
REFIN
2047
4096
1111
REFIN
:
:
1
4096
0000
0000
0000
0000
0001
0000
2 V
REFIN
0 V
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pF
loadcapacitance. Settlingtimeisasoftwareselectable12.5µs or 2.5 µs, typicaltowithin±0.5LSBoffinalvalue.
external reference
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5618 timing. The maximum serial clock rate is:
1
f
20 MHz
(SCLK)max
t
t
w CH min
w CL min
The digital update rate is limited by the chip-select period, which is:
t
16
t
t
t
p(CS)
w CH
w CL
su CS1
This equals an 810-ns or 1.23-MHz update rate. However, the DAC settling time to 12 bits limits the update rate
for full-scale input step transitions.
serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in, most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot beclocked
into the input register.
The 16 bits of data can be transferred with the sequence shown in Figure 19.
16 Bits
Program Bits
D14 D13
MSB (Input Word)
Data Bits
D15
D12
D11
12 Data Bits
D0
MSB (Data)
LSB (Data, Input Word)
Figure 19. Input Data Word Format
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
Table 2 shows the function of program bits D15 – D12.
Table 2. Program Bits D15 – D12 Function
PROGRAM BITS
DEVICE FUNCTION
D15
D14
D13
D12
Write to latch A with serial interface register data
and latch B updated with buffer latch data
1
X
X
X
0
0
X
X
0
X
X
X
X
0
0
1
Write to latch B and double buffer latch
Write to double buffer latch only
12.5 µs settling time
X
X
X
X
X
X
X
X
1
2.5 µs settling time
X
X
Powered-up operation
1
Power down mode
function of the latch control bits (D15 and D12)
Three data transfers are possible. All transfers occur immediately after CS goes high and are described in the
following sections.
latch A write, latch B update (D15 = high, D12 = X)
The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to
latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output
updates of both DACs.
To DAC A
Latch A
Serial
Interface
Register
Double
Buffer Latch
D12 = X
D15 = High
To DAC B
Latch B
Figure 20. Latch A Write, Latch B Update
latch B and double-buffer 1 write (D15 = low, D12 = low)
The SIR data are written to both latch B and the double buffer. Latch A is unaffected.
To DAC A
Latch A
Serial
Interface
Register
Double
Buffer Latch
D12 = Low
D15 = Low
To DAC B
Latch B
Figure 21. Latch B and Double-Buffer Write
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
double-buffer-only write (D15 = low, D12 = high)
The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
To DAC A
Latch A
Serial
Interface
Register
Double
Buffer
D12 = High
D15 = Low
To DAC B
Latch B
Figure 22. Double-Buffer-Only Write
purpose and use of the double buffer
Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change
after a single write. This is achieved by the two following steps.
1. A double-buffer-only write is executed to store the new DAC B data without changing the DAC A and B
outputs.
2. Following the previous step, a write to latch A is executed. This writes the SIR data to latch A and also
writes the double-buffer contents to latch B. Thus both DACs receive their new data at the same time,
and so both DAC outputs begin to change at the same time.
Unless a double-buffer-only write is issued, the latch B and double-buffer contents are identical. Thus, following
a write to latch A or B with another write to latch A does not change the latch B contents.
operational examples
changing the latch A data from zero to full code
Assuming that latch A starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit D15
on the left, D0 on the right)
1X0X 1111 1111 1111
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The other X can be
zero or one (don’t care).
The latch B contents and the DAC B output are not changed by this write unless the double-buffer contents are
different from the latch B contents. This can only be true if the last write was a double-buffer-only write.
changing the latch B data from zero to full code
Assuming that latch B starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit D15
on the left, D0 on the right).
0X00 1111 1111 1111
to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The data (bits D0
to D11) are written to both the double buffer and latch B.
The latch A contents and the DAC A output are not changed by this write.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
double-buffered change of both DAC outputs
Assuming that DACs A and B start at zero code (e.g., after power-up), if DAC A is to be driven to mid-scale and
DAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows:
First,
0d01 1111 1111 1111
is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code into the double
buffer but does not change the latch B contents and the DAC B output voltage. The latch A contents and the
DAC A output are also unaffected by this write operation.
Changing from fast to slow or slow to fast mode changes the supply current which can glitch the outputs, and
so D14 (designated by d in the above data word) should be set to maintain the speed mode set by the previous
write.
Next,
1X0X 1000 0000 0000
is written (bit D15 on the left, D0 on the right) to the serial interface. Bit D14 can be zero to select slow mode
or one to select fast mode. The other X can be zero or one (don’t care). This writes the mid-scale code
(100000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both DAC
outputs thus begin to rise after the second write.
DSP serial interface
Utilizing a simple 3-wire serial interface shown in Figure 23, the TLC5618A can be interfaced to TMS320
compatibleserialports. The5618Ahasaninternalstatemachinethatwillcount16clocksafterreceivingafalling
edge of CS and then disable further clocking in of data until the next falling edge is received on CS. Therefore
CS can be connected directly to the FS pins of the serial port and only the leading falling edge of the DSP will
be used to start the write process. The TLC5618A is designed to be used with the TMS320Cxx DSP in burst
mode serial port transmit operation.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
V
CC
FSR
FSX
CS
Analog
Output
OUT A
TLC5618A
TMS320C203
DSP
Analog
Output
CLKX
CLKR
OUT B SCLK
DX
DIN
REFIN
GND
2.5 V dc
To Source
Ground
Figure 23. Interfacing The TLC5618A to the TMS320C203 DSP
general serial interface
Both the TLC5618 and TLC5618A are compatible with SPI, QSPI, or Microwire serial standards. The hardware
connections are shown in Figures 24 and 25. The TLC5618A has an internal state machine that will count 16
clocks after the falling edge of CS and then internally disable the device. The internal edge is ORed together
with CS so that the rising edge can be provided to CS prior to the occurrence of the internal edge to also disable
the device.
The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.
SK
SO
I/O
SCLK
DIN
Microwire
Port
TLC5618,
TLC5618A
CS
Figure 24. Microwire Connection
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
SCK
SCLK
DIN
MOSI
TLC5618,
TLC5618A
SPI/QSPI
Port
I/O
CS
CPOL = 1, CPHA = 0
Figure 25. SPI/QSPI Connection
linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 26.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 26. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. The code is
calculated from the maximum specification for the negative offset.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground
currents are well-managed.
A0.1-µFceramicbypasscapacitorshouldbeconnectedbetweenV andAGNDandmountedwithshortleads
DD
as close as possible to the device. Use of ferrite beads may further isolate the system analog and digital power
supplies.
Figure 27 shows the ground plane layout and bypassing technique.
Analog Ground Plane
1
2
3
4
8
7
6
5
0.1 µF
Figure 27. Power-Supply Bypassing
saving power
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.
ac considerations/analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to
REFIN, and monitoring the DAC output.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
MECHANICAL DATA
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINALS SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.740
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Falls within JEDEC MS-004
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
MECHANICAL DATA
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
PLASTIC DUAL-IN-LINE PACKAGE
MECHANICAL DATA
P (R-PDIP-T8)
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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