TLC5911PZP [TI]
LED DRIVER; LED驱动器
| 型号： | TLC5911PZP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LED DRIVER |
| 文件： | 总30页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
Drive Capability and Output Counts
– 80 mA (Current Sink) x 16 Bits
Protection
– Watchdog Timer (WDT) Function (Turn
Output Off When Scan Signal Stopped)
– Thermal Shutdown (TSD) Function (Turn
Output Off When Junction Temperature
Exceeds Limit)
Constant Current Output Range
– 5 to 80 mA (Current Value Setting for All
Output Terminals Using External Resistor
and Internal Brightness Control Register)
LOD
Constant Current Accuracy
– LED Open Detection (Detection for LED
Disconnection)
– ±4 % (Maximum Error Between Bits)
Voltage Applied to Constant Current Output
Terminals
– Minimum 0.4 V (Output Current 5 mA to
‡
Data Input/Output
– Port A (for Data Display)
– Clock Synchronized 10 Bit Parallel Input
(Schmitt-Triggered Input)
– Clock Synchronized 10 Bit Parallel
Output (3-State Output)
– Port B (for Dot Correction Data)
– Clock Synchronized 7 Bit Parallel Input
(Schmitt-Triggered Input)
40 mA)
– Minimum 0.7 V (Output Current 40 mA to
80 mA)
1024 Gray Scale Display
– Pulse Width Control 1024 Steps
†
Brightness Adjustment
– All Output Current Adjustment for 64
Steps (Adjustment for Brightness
Deviation Between LED Modules)
– Output Current Adjustment by Output
(OUT0 to OUT15) for 128 Steps
(Adjustment for Brightness Deviation
Between Dots)
– Brightness Control by 16 Steps
Frequency Division Gray Scale Control
Clock (Brightness Adjustment for Panel)
– Clock Synchronized 7 Bit Parallel Output
Input/Output Signal Level
– CMOS Level
Power Supply Voltage
– 4.5 V to 5.5 V (Logic, Analog and
Constant Current)
– 3 V to 5.5 V (Interface)
Maximum Output Voltage . . . 15 V
Data Transfer Rate . . . 20 MHz (Max)
Gray Scale Clock Generation
– Gray Scale Control Clock Generation by
Internal PLL or External Input Selectable
Gray Scale Clock Frequency
– 16 MHz (Max) Using Internal PLL
– 8 MHz (Max) Using External Clock
Clock Invert/Noninvert Selectable at
Cascade Operation
– Clock Invert Selectable to Reduce
Changes in Duty Ratio
Operating Free-Temperature Range
–20°C to 85°C
100-Pin Package HTQFP (P = 4.7 W,
D
T = 25°C)
A
†
‡
Adjustable for these functions independently.
Allows to write all the data at port A by setting.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
description
The TLC5911 is a constant current driver incorporating shift register, data latch, and constant current circuitry
with a current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display
using pulse width control. The output current is maximum 80 mA with 16 bits, and the current value of constant
current output can be set by one external resistor. The device has two channel I/O ports. The brightness
deviation between LED modules (ICs) can be adjusted by external data input from the display data port, and
the brightness control for the panel can be accomplished by the brightness adjustment circuitry. Independent
of these functions, the device incorporates the shift register and data latch to correct the deviation between
LEDs by adjusting the output current using data from the dot correction data port. Moreover, the device
incorporates WDT circuitry, which turns constant current output off when the scan signal stops during the
dynamic scanning operation, and TSD circuitry, which turns constant current output off when the junction
temperature exceeds the limit. Also the LED open detection (LOD) circuitry is used to make error signal output
at the LED disconnection.
pin assignments
PZP PACKAGE
(TOP VIEW)
GNDLED
OUT0
OUT1
GNDLED
OUT2
OUT3
GNDLED
OUT4
OUT5
GNDLED
OUT6
1
2
3
4
5
6
7
8
VCOIN
RBIAS
MAG0
MAG1
MAG2
PDOUT
GSPOL
GSCLK
BLANK
XENABLE
XOE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OUT7
GNDLED
OUT8
DCLK
XLATCH
DCCLK
XDCLAT
RSEL0
RSEL1
LEDCHK
NC
WDTRG
XDOWN1
XDOWN2
BOUT
OUT9
GNDLED
OUT10
OUT11
GNDLED
OUT12
OUT13
GNDLED
OUT14
OUT15
GNDLED
XGSOUT
XPOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
functional block diagram
XOE
BCENA
DCLK
DPOL
DOUT(9–0)
XDPOUT
DCLK
Control
XENABLE
DIN(9–0),
XLATCH
1 x 10 bit B.C.
Data Shift Register
Data Latch
16 x 10 bit
Data Shift Register
RSEL(1–0)
..........
16 x 10 bit
Data Latch
DCDIN(6–0),
XDCLAT,
DCCLK
..........
XPOUT
XGSOUT
MAG(2–0), GSPOL,
GSCLK, RBIAS,
VCOIN, PDOUT
10 bit
Clock Countor
16 x 10 bit
Data Comparator
PLL
BLANK
BOUT
..........
OUT0
· · ·
OUT15
16 bit
LED Driver+LOD
WDCAP
WDTRG
WDT
TSD
XDOWN1
XDOWN2
LEDCHK
XDOWN2TST
..........
TSENA
16 bit
Current Controller
..........
IREF
16 x 7 bit
D.C. Data Latch
DCENA
..........
16 x 7 bit
D.C. Data Shift Register
DCDOUT(6–0)
Legend:
B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels.
D.C. (Dot Control): Adjustment for brightness deviation between dots.
NOTE: All the input terminals are with Schmitt triggered inverter except RBIAS, VCOIN, PDOUT, IREF and WDCAP.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
functional block diagram for shift register and data latch
XOE
10 16
10 16
DATA
S/R
DATA
LATCH
DATA
Comparator
10
†
DCLK
DPOL
XENABLE
a
DCLK
Controller
A
B
b
c
a
DCCLK
A
10
10
b
c
L
10
DOUT(9–0)
H
10
a
b
c
HI–Z
10
7
A
B
DIN(9–0)
10
10
10
B.C.
S/R
B.C.
LATCH
Clock Counter
Current Controller
DCDIN(6–0)
a
A
B
XLATCH
XDCLAT
b
c
7
DCDOUT(6–0)
‡
7
7
16
7 16
RSEL(1–0)
D.C.
S/R
D.C.
LATCH
H
7
16
DATA
Comparator
L
7
16
BCENA
DCENA
Default
†
‡
Connecting to 16th 10-bit Bus
Connecting to 16th 7-bit Bus
Legend:
B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels.
D.C. (Dot Control): Adjustment for brightness deviation between dots.
RSEL
CONNECTION
RSEL1
RSEL0
L
L
L
H
L
A – a, B – c
A – b, B – c
A – c
H
H
H
INHIBIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
equivalent input and output schematic diagrams
Input
VCCIF
DOUT0–9, DCDOUT0–6, XGSOUT, XPOUT, BOUT
VCCLOG
OUTPUT
INPUT
GNDLOG
GNDLOG
OUTn
XDOWN1, XDOWN2
XDOWN1, XDOWN2
OUTn
GNDLOG
GNDLED
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Brightness control enable. When BCENA is low, the brightness control latch is set to the
default value. The output current value in this status is 100% of the value set by an external
resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to
brightness control latch is enabled.
BCENA
94
I
Blank (Light off). When BLANK is high, all output of the constant current driver are turned
off. When GSPOL is high, all the output is turned on (LED on) synchronizing to the falling
edge of GCLK after next rising edge of GSCLK when BLANK goes from high to low. When
GSPOL is low, all the output is turned on (LED on) synchronizing to the rising edge of GCLK
after next falling edge of GSCLK when BLANK goes from high to low.
BLANK
67
I
BOUT
53
62
O
I
BLANK buffered output
Clock input for data transfer. The input data is from DCDIN (port B) . The output data at
DCDOUT. All data on the shift register for dot correction data from DCDIN is shifted by 1 bit
and is synchronized to the rising edge of DCCLK.
DCCLK
DCDIN0 –
DCDIN6
86,87,88,
89,90,91,92
Input for 7 bit parallel data (port B). These terminals are used as shift register input for dot
correction data.
I
O
I
DCDOUT0 –
DCDOUT6
34,35,36,
37,38,39,40
Output for 7 bit parallel data (port B). These terminals are used as shift register output for
dot correction data.
Latchenablefordotcorrectiondata. WhenDCENAislow, thelatchissettothedefaultvalue.
At this time, the output current value is 100% of the value set by an external resistor.
DCENA
95
64
Clock input for data transfer. The input data is from DIN (port A) , all the data on the shift
register selected by RSEL0, 1 and the output data at DOUT are shifted by 1 bit and
synchronizedtoDCLK. NotethatwhethersynchronizingtotherisingorfallingedgeofDCLK
is dependent on the value of DPOL.
DCLK
I
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Input for 10 bit parallel data (port A). These terminals are inputs for shift register for gray
scale data, brightness control, and dot correction data. The register selected is determined
by RSEL0, 1.
76,77,78,79,80,
81,82,83,84,85
DIN0 – DIN9
I
Output for 10 bit parallel data (port A). These terminals are outputs for shift register for gray
scale data, brightness control, and dot correction data. The register selected is determined
by RSEL0, 1.
41,42,43,44,45,
46,47,48,49,50
DOUT0 – DOUT9
DPOL
O
I
Selects the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When
DPOL is low, the falling edge of DCLK is valid.
96
GNDANA
GNDLOG
28
98
Analog ground (Internally connected to GNDLOG and GNDLED)
Logic ground (Internally connected to GNDANA and GNDLED)
1,4,7,10,13,
16,19,22,25
GNDLED
LED driver ground (Internally connected to GNDANA and GNDLED)
Clock input for gray scale. When MAG0 through MAG2 are all low, GSCLK is used for pulse
widthcontrol.WhenMAG0throughMAG2arenotlow,GSCLKisusedforPLLtimingcontrol.
The gray scale display is accomplished by lighting the LED until the number of GSCLK or
PLL clocks counted is equal to the data latched.
GSCLK
68
I
Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid.
When GSPOL is low, the falling edge of GSCLK is valid.
GSPOL
IREF
69
32
I
Constant current value setting. LED current is set to the desired value by connecting an
external resistor between IREF and GND. The 38 times current is compared to current
across the external resistor sink on the output terminal.
I/O
LED disconnection detection enable. When LEDCHK is high, the LED disconnection
detection is enabled and XDOWN2 is valid. When LEDCHK is low, the LED disconnection
detection is disabled.
LEDCHK
58
I
I
PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is
set .
MAG0 – MAG2
NC
73,72,71
57
No internal connection
2,3,5,6,8,9,11,
12,14,15,17,18,
20,21,23,24
OUT0 – DOUT15
O
Constant current output
PDOUT
RBIAS
70
74
I/O
I/O
Resistor connection for PLL feedback adjustment
Resistor connection for PLL oscillation frequency setting
Input/output port selection and shift register data latch switching.
When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected to
port A, and the dot correction register latch is selected to port B.
When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to
port A, and the dot correction register latch is selected to port B.
RSEL0
RSEL1
60
59
I
When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port A
and no register latch is selected to port B.
TEST1 – TEST3
THERMAL PAD
TSENA
97,99,100
I
I
TEST. Factory test terminal. These terminals should be connected to GND.
Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.
TSD enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled.
Analog power supply voltage
Package bottom
31
33
93
26
75
VCCANA
VCCLOG
Logic power supply voltage
VCCLED
LED driver power supply voltage
VCOIN
I/O
I/O
Capacitance connection for PLL feedback adjustment
WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor
betweenWDCAPandGND. WhenWDCAPisdirectlyconnectedtoGND, theWDTfunction
is disabled. In this case, WDTRG should be tied to high or low level.
WDCAP
30
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
WDTRG
NO.
WDT trigger input. By applying a scan signal to this terminal, the scan signal can be
monitoredbyturningtheconstantcurrentoutputoffandprotectingtheLEDfromthedamage
of burning when the scan signal stops during the constant period designed.
56
I
Data latch for dot correction. When XDCLAT is high, data on the shift register for dot
correction data from DCDIN (port B) goes through latch. When XDCLAT is low, the data is
latched. Accordingly, if data on the shift register is changed during XDCLAT high, the new
value is latched (level latch).
XDCLAT
61
55
I
Shutdown. XDOWN1 is configured as open collector. It goes low when the constant current
output is shut down by the WDT or TSD function.
XDOWN1
O
LED disconnection detection output. XDOWN2 is configured as open collector. XDOWN2
goes low when a LED disconnection is detected.
XDOWN2
XDPOUT
54
29
27
O
O
I
DPOL output inverted
Test for XDOWN2. When XDWN2TST is low, XDOWN2 goes low. (This terminal is internally
pulled up with 50 kΩ)
XDWN2TST
DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the
validedge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred.
XENABLE
XGSOUT
66
52
I
Clock output for gray scale. When MAG0 through MAG2 are all low, a clock with GSCLK
inverted appears on this terminal. When MAG0 through MAG2 are not low., PLLCLK
appears on this terminal.
O
Latch. When XLATCH is high, data on shift register from DIN (port A) goes through latch.
WhenXLATCH is low, data is latched. Accordingly, if the data on the shift register is changed
during XLATCH high, this new value is latched (level latch).
XLATCH
63
I
Data output enable. When XOE is low, the DOUT0–9 terminals are driven. When XOE is
high, the DOUT0–9 terminals go to a high-impedance state.
XOE
65
51
I
XPOUT
O
GSPOL output inverted
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Logic supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
CC(LOG)
Supply voltage for constant current circuit, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Analog supply voltage, V
CC(LED)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
CC(ANA)
Output current (DC), I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mA
OL(C)
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V
I
Output voltage range, V
, V
, V
, V
and V
– 0.3 V to VCCLOG+ 0.3 V
(XGSOUT)
(DOUT) (DCDOUT) (BOUT) (XPOUT)
Output voltage range, V and V
Storage temperature range, T
Continuous total power dissipation at (or below) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W
Power dissipation rating at (or above) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.2m W/°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 16 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
O
(XDOWNn)
str
A
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GNDLOG terminal.
recommended operating conditions
dc characteristics
MIN
4.5
4.5
4.5
NOM
MAX
5.5
UNIT
Logic supply voltage, V
CC(LOG)
5
5
5
V
V
V
Supply voltage for constant current circuit, V
CC(LED)
5.5
Analog power supply, V
CC(ANA)
5.5
V
V
V
V
=
(DIFF1)
– V
– V
– V
CC(LOG)
CC(LOG)
CC(ANA)
CC(ANA)
CC(LED)
CC(LED)
Voltage between V , V
CC (DIFF1)
–0.3
–0.3
0
0
0.3
0.3
V
V
=
(DIFF2)
GND(LOG) – GND(ANA)
GND(LOG) – GND(LED)
GND(ANA) – GND(LED)
Voltage between GND, V
(DIFF2)
V
V
Voltage applied to constant current
output, V
OUT0 to OUT15 off
15
O
High–level input voltage, V
IH
0.8 V
V
V
V
CC(LOG)
CC(LOG)
Low–level input voltage, V
GND(LOG)
0.2 V
IL
CC(LOG)
V
= 4.5 V,
CC(LOG)
High–level output current, I
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
BOUT, XGSOUT, XPOUT
–1
OH
mA
V
= 4.5 V,
CC(LOG)
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
BOUT, XGSOUT, XPOUT
1
Low–level output current, I
OL
V
= 4.5 V, XDOWN1, XDOWN2
5
80
85
mA
mA
°C
(CCLOG)
OUT0 to OUT15
Constant output current, I
5
OL(C)
Operating free–air temperature range, T
–20
A
PLL capacitance, C
(VCO)
1
µF
PLL resistor, R
At 16 MHz oscillation
22
30
kΩ
kΩ
(BIAS)
(PD)
PLL resistor, R
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
recommended operating conditions (continued)
accharacteristics, V
=V
=V
=4.5Vto5.5 V, TA =– 20 to85°C (unless otherwise noted)
CC(LOG)
CC(ANA)
CC(LED)
MIN
TYP
MAX
20
UNIT
At single operation
DCLK, DCCLK clock frequency, f
/f
(DCLK) (DCCLK)
MHz
At cascade operation
15
DCLK, DCCLK pulse duration (high- or low-level), t
GSCLK clock frequency, f
/t
w(h) w(l)
20
40
ns
MHz
ns
8
(GSCLK)
GSCLK pulse duration (high- or low-level), t
/t
w(h) w(l)
PLLCLK clock frequency, f
(PLLCLK)
16
8
MHz
MHz
ns
WDT clock frequency, f
(WDT)
WDT pulse duration (high- or low-level), t
/t
40
30
w(h) w(l)
XLATCH, XDCLAT pulse duration (high-level), t
ns
w(h)
Rise/fall time, t /t
r f
100
ns
DINn – DCLK
5
5
DCDINn – DCCLK
BLANK – GSCLK
XENABLE – DCLK
XLATCH – DCLK
XLATCH – GSCLK
XDCLAT – DCCLK
RSEL – DCLK
RSEL – DCCLK
RSEL – XLATCH
RSEL – XDCLAT
10
15
10
10
10
10
15
30
15
Setup time, t
ns
su
DINn – DCLK
15
15
20
30
20
20
20
20
10
DCDINn – DCCLK
XENABLE – DCLK
XLATCH – DCLK
XDCLAT – DCCLK
RSEL – DCLK
RSEL – DCCLK
RSEL – XLATCH
RSEL – XDCLAT
Hold time, t
ns
h
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
electrical characteristics, LEDCHK = L, MIN/MAX: V
= V
= V
= 4.5 V to 5.5 V,
CC(LOG)
CC(ANA)
CC(LED)
T = –20 to 85°C, TYP: V
= V
= V
= 5 V, T = 25°C (unless otherwise noted)
A
CC(LOG)
CC(ANA)
CC(LED) A
PARAMETER
TEST CONDITIONS
= –1 mA, DOUTn, DCOUTn, XGSOUT,
MIN
TYP
MAX
UNIT
I
V
OH
XPOUT, BOUT
CC(LOG)
–0.5
V
V
High-level output voltage
V
OH
I
= 1 mA, DOUTn, DCOUTn, XGSOUT,
OL
XPOUT, BOUT
0.5
Low-level output voltage
Input current
V
OL
I
= 5 mA, XDOWN1, XDOWN2
0.5
OL
V = V or GND(LOG)
CC(LOG)
I
I
±1
µA
I
Input signal is static,
TSENA = H, WDCAP = OPEN,
No PLL is used
1
3
mA
Input signal is static,
TSENA = H, WDCAP = OPEN,
PLL multiple ratio = 1042
I
Supply current (logic)
mA
(LOG)
Data transfer,
DCLK = 20 MHz, GSCLK = 8 MHz
No PLL is used
35
39
45
49
Data transfer,
DCLK = 20 MHz, GSCLK = 15 kHz
PLL multiple ratio = 1042
mA
mA
BLANK = L, R
BLANK = L, R
= 1200 Ω
= 600 Ω
= 1200 Ω
= 600 Ω
6.5
13
12
20
8
15
20
35
(IREF)
I
I
Supply current (analog)
(ANA)
(IREF)
LED turn off, R
LED turn off, R
(IREF)
(IREF)
Supply current
(constant current driver)
V
= 1 V, R
= 1200 Ω
O
(IREF)
mA
12
20
40
80
20
35
45
90
(LED)
all output bits turn on
V
= 1 V, R = 600 Ω
O
(IREF)
all output bits turn on
Constant output current
(includes error between bits)
V
R
= 1 V, V = 1.2 V,
O
(IREF)
= 1200 W
I
I
35
70
mA
mA
OL(C1)
(IREF)
Constant output current
(includes error between bits)
V
R
= 0.7 V, V
= 1.2 V
O
(IREF)
= 600 W
OL(C2)
(IREF)
OUT0 to OUT15 (V
= 15 V)
0.1
1
µA
µA
OUTn
XDOWN1, 2 (V
= 15 V)
XDOWNn
I
Constant output leakage current
OL(K)
DOUTn, DCDOUTn
(V = VCCLOG or GND)
1
µA
OUTn
V
=V
=V
CC(LOG) CC(ANA) CC(LED)
Constant output current error
between bit
∆I
OL(C)
V
O
= 1 V, R = 600 W
± 1% ± 4%
(IREF)
All output bits turn on
Changes in constant output current
depend on supply voltage
V
V
= 1 V, R
= 600 W,
O
(IREF)
= 1.2 V
I∆
I∆
± 1% ± 4%
± 1% ± 3%
V
V
OL(C1)
IREF
Changes in constant output current
depend on output voltage
V
V
= 1 V to 3 V, R
= 600 Ω,
O
IREF
(IREF)
= 1.2 V, 1 bit output turn on
OL(C2)
T
T
TSD detection temperature
WDT detection temperature
Voltage reference
Junction temperature
No external capacitor
150
5
160
10
170
15
°C
ms
V
(tsd)
(wdt)
V
BCENA = L, R
(IREF)
= 9.6 kΩ,
1.2
(IREF)
Voltage applied to LED
disconnection detection
V
0.2
0.3
0.4
2%
V
(LEDDET)
R
C
= 22 kΩ, R
= 0.1 µF
= 30 kΩ,
(PD)
(BIAS)
(VCO)
P
PLL jitter
0.4%
(LLJITTER)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
switching characteristics, C =15pF, MIN/MAX: V
= V
=V
=4.5Vto5.5V, T
L
CC(LOG)
CC(ANA)
A
CC(LED)
A
= –20 to 85°C, TYP: V
= V
= V
= 5 V, T = 25°C (unless otherwise noted)
CC(LOG)
CC(ANA) CC(LED)
PARAMETER
TEST CONDITIONS
MIN
TYP
12
12
110
10
10
130
30
50
20
7
MAX
30
UNIT
DOUTn, DCDOUTn
t
t
Rise time
Fall time
XGSOUT, BOUT, XPOUT
OUTn (see Figure 1)
DOUTn, DCDOUTn
30
ns
r
30
XGSOUT, BOUT, XPOUT
OUTn (see Figure 1)
OUTn+1 – OUTn
30
ns
f
45
70
40
BLANK↑ – OUT0
40
10
BLANK – BOUT
GSCLK – OUT0 (see Note 2)
GSCLK – XGSOUT
DCLK – DOUTn
10
15
15
15
10
10
10
20
30
30
30
20
15
20
40
45
t
d
Propagation delay time
ns
DCLK – DCDOUTn
DCCLK – DCDOUTn
XOE↓ – DOUTn (see Note 3)
XOE↑ – DOUTn (see Note 3)
RSEL – DOUTn
45
45
35
25
40
LEDCHK – XDOWN2
1000
NOTES: 2. MAG0 to MAG2 are all low level.
3. Until DOUT is turned on (drive) or turned off (Hi-Z).
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
CC
51 Ω
V
CC
IREF
OUTn
GND
600 Ω
15 pF
Figure 1. Rise Time and Fall Time Test Circuit for OUTn
V
or V
or V
100%
IH
OH
V
IH
IL
90%
10%
50%
0%
V
V
IL
OL
t
t
r
f
t
d
V
or V
or V
100%
V
V
100%
IH
OH
IH
50%
0%
50%
0%
V
IL
OL
IL
t
t
w(l)
w(h)
Figure 2. Timing Requirements
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
setting for output constant current value
On the constant current output terminals (OUT0–15), approximately 38 times the current which flows through
the external resistor, R (connected between IREF and GND), can flow. The external resistor value is
(IREF)
calculated using the following equation:
R
(Ω) 38 × 1.2 (V) / I (A) where both BCENA and DCENA are low.
(IREF)
OL(C)
Note that more current flows if IREF is connected to GND directly.
constant output current operation
The constant current output turns on (sink constant current), if GSPOL is high and if all the gray scale data
latched into the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge
of the gray scale clock when BLANK goes from high to low. After that, the number of the falling edge is counted
by the 10-bit gray scale counter. Then, the output counted corresponding to the gray scale data is turned off
(stop to sink constant current). The gray scale clock can be selected, as discussed in later section, from GSCLK
or by internal PLL circuitry. If the shift register for the gray scale is updated during XLATCH high, the data on
the gray scale data latch is also updated affecting the number of the gray scale of constant current output.
Accordingly, during the on-state of the constant current output, XLATCH should be kept at a low level and the
gray scale data latch should be held.
input/output port and shift register selection
The TLC5911 supplies two parallel input ports such as DIN (10 bits : port A) and DCDIN (7 bits: port B). The
DIN and DCDIN ports also supply DCLK and DCCLK for the shift clock, XLATCH and XDCLAT for latch, and
DOUT and DCDOUT for output, respectively. The device has three kinds of shift register latchs such as the gray
scale data, brightness control, and dot correction. The port and shift registers can be selected by RSEL0 and
RSEL1. The selection of the shift registers will be done by RESL0 and RSEL1 as shown in Table 1. Note that
the RSELn setting is done at DCLK low and DPOL high (DCLK is high when DPOL is low). When only port A
is used, DCDIN, DCDOUT, DCCLK, and XDCLAT should be connected to GND.
Table 1. Shift Register Latch Selection
SELECTED SHIFT REGISTER LATCH
PORT A
PORT B
DCDIN, DCCLK, XDCLAT
Dot correction
RSEL1
RSEL0
DIN, DCLK, XLATCH, DOUT
Gray scale data displayed
Brightness control
DCDOUT
L
L
L
H
L
Dot correction
Dot correction
Dot correction
N/A (inhibit)
Dot correction
H
H
Dot correction (see Note 4)
N/A (inhibit)
Not connected
H
N/A (inhibit)
NOTE 4: Zero is output to DOUT7 through DOUT9.
shift register latch for gray scale data
The shift register latch for the gray scale data is configured with 16 × 10 bits. The gray scale data, configured
with 10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023
(00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on (light off). On
the other hand, when the gray scale data is 1023, the time is longest, and it turns on during the time of the 1023
clocks from the gray scale clock. The configuration of the shift register and the latch for gray scale data is shown
in Figure 3.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
Latch for Gray Scale Data
OUT15
Data
OUT14
OUT1
Data
OUT0
Data
Data
XLATCH
(10 bits)
(10 bits)
(10 bits)
(10 bits)
Shift Register for Gray Scale Data
16th byte
DIN9 MSB
DIN0 LSB
15th byte
DIN9 MSB
DIN0 LSB
2nd byte
DIN9 MSB
DIN0 LSB
1st byte
DIN9 MSB
DIN0 LSB
DCLK
DOUT0 to 9
DIN0 to 9
Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data
shift register latch for brightness control
The shift register latch for brightness control is configured with 1 × 10 bits. Using the shift register latch for the
brightness control, the division ratio of the gray scale clock can be set and the output current value on constant
current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not
initialized. When these functions are used, data should be written to the shift register latch prior to lighting-on
(BLANK=L). Also, it is prohibited from rewriting the latch value for the brightness control when the constant
current output is turned on. When these functions are not used, the latch value can be set to the default value
setting of BCENA at low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current
control to maintain compatibility with the TLC5901/02/03 family. The configuration of the shift register and the
latch for brightness control is shown in Figure 4.
Latch for Brightness Control
Gray Scale Clock Division Ratio Data Set
Current Data Adjusted On Constant Current Output
XLATCH
(see Note A)
0
0
0
0
1
1
1
1
1
1
MSB
LSB
MSB
LSB
Shift Register for Brightness Control
DCLK
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
DIN9
DOUT0 to 9
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DIN0 to 9
NOTE A: Indicates default value at BCENA low.
Figure 4. Relationship Between Shift Register and Latch for Brightness Control
shift register latch for dot correction
The shift register latch for dot correction is configured with 16 × 7 bits. Using the shift register latch for dot
correction, the current value on the constant current output can be set individually. When powered up, the latch
data is indeterminate and the shift register is not initialized. When these functions are used, data should be
written to the shift register latch prior to lighting-on (BLANK=L). Also, rewriting the latch value for dot correction
when the constant current output is turned on is inhibited. When these functions are not used, the latch value
can be set to the default value setting of DCENA at low level (connect to GND). The configuration of the shift
register and the latch for dot correction is shown in Figure 5.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
Latch for Dot Correction
OUT15
Data
OUT14
Data
OUT1
OUT0
Data
Data
XDCLAT
(7 bits)
(7 bits)
(7 bits)
(7 bits)
Shift Register for Dot Correction
16th byte
15th byte
2nd byte
1st byte
DCCLK
DCDIN6 MSB
DCDIN0 LSB
DCDIN6 MSB
DCDIN0 LSB
DCDIN6 MSB
DCDIN0 LSB
DCDIN6 MSB
DCDIN0 LSB
DCDOUT0 to 6
DCDIN0 to 6
Using Port B (RSEL0=L or H, RSEL1=L)
Latch for Dot Correction
OUT15
Data
OUT14
Data
OUT1
Data
OUT0
Data
XLATCH
(7 bits)
(7 bits)
(7 bits)
(7 bits)
Shift Register for Dot Correction
16th byte
DIN6 MSB
DIN0 LSB
15th byte
DIN6 MSB
DIN0 LSB
2nd byte
DIN6 MSB
DIN0 LSB
1st byte
DIN6 MSB
DIN0 LSB
DCLK
DOUT0 to 6
DIN0 to 6
Using Port A (RSEL0=L, RSEL1=H)
Figure 5. Relationship Between the Shift Register and the Latch for Dot Correction
write data to shift register latch
The shift register latch written is selected using the RSEL0 and RSEL1 terminal. At port A, the data is applied
to the DIN data input terminal, clocked into the shift register and synchronized to the rising edge of DCLK after
XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal, clocked into the shift
register, and synchronized to the rising edge of DCCLK. The shift register for the gray scale data is configured
with 16 × 10 bits and the shift register for dot correction is configured with 16 × 7 bits resulting in sixteen times
DCLK. The shift register for the brightness control is configured with 1 × 10 bits resulting in one times DCLK.
At the number of DCLK input for each case, data can be written into the shift register. In this condition, when
the XLATCH at port A or the XDCLAT at port B is pulled high, data in the shift register is clocked into the latch
(data through). When the XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
brightness control function
By writing data into the brightness control latch, current on all the constant current outputs can be adjusted to
control the variation of brightness between ICs. The division ratio for the gray scale clock can be set to control
the variation of brightness for the total panel system. Furthermore, by writing data into the dot correction latch,
current on each constant current output can be adjusted.
output current adjustment on all constant current outputs – brightness adjustment between ICs
By using the lower 6 bits of the brightness control latch, output current can be adjusted in 64 steps as 1 step
of 0.8% of the current ratio between 100% and 50.8% when the output current is set to 100% of an external
resistor (note that the current value is lower if the constant current output is corrected using the dot correction
function). By using this function, the brightness control between modules (ICs) can be adjusted sending the
desired data externally even if ICs are mounted on a print-circuit board. When BCENA is pulled low, the output
current is set to 100%.
Table 2. Relative Current Ratio For Total Constant Current Output
CURRENT RATIO
V
IREF
(TYP)
20 (mA)
80 (mA)
CODE
%
50.8
10.2
40.6
MSB 000000 LSB
0.60
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
99.2
100
19.8
20.0
79.7
80.0
111110
1.19
1.20
†
111111
†
BCENA is low.
frequency division ratio setting for gray scale clock – panel brightness adjustment
By using the upper 4 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/16.
If the gray scale clock is set to 16 times the speed of frequency (1024×16=16384) during horizontal scanning
time, the brightness can be adjusted in 16 steps by selecting the frequency division ratio. By using this function,
the total panel brightness can be adjusted at once, and applied to the brightness of day or night. When BCENA
is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can be adjusted
as shown in Table 3.
Table 3. Relative Brightness Ratio For Total Constant Current Output
RELATIVE
BRIGHTNESS RATIO
(%)
FREQUENCY DIVISION
CODE
RATIO
†
MSB 0000 LSB
1/1
6.3
.
.
.
.
.
.
.
.
.
.
.
.
1110
1111
1/15
1/16
93.8
100
†
BCENA is low.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
output current adjustment on each constant current output – LED brightness adjustment
Byusingthedotcorrectionlatch, theoutputcurrentoneachconstantcurrentoutputcanbeadjustedin128steps
as 1 step of 0.8% of the current ratio between 100% and 0% when the output current is set to 100% of an external
resistor at 7Fh of the latched value and the lower 6 bits of the brightness control register. By using this function,
the brightness deviation from the LED brightness variation can be minimized. When DCENA is pulled low, the
output current is set to 100% without the dot correction.
Table 4. Relative Current Ratio By Constant Current Output
CODE
CURRENT RATIO %
I
=40 (mA)
OL(C)
MSB 0000000 LSB
0.0
0.0
.
.
.
.
.
.
.
.
.
.
.
.
1111110
99.2
100
39.7
40
†
1111111
DCENA is low.
†
clock edge selection
The high speed clock signal is diminished due to the duty ratio change through the multiple stages of the IC or
module as shown in Figure 6.
IN
A
OUT
IN
A
A’
OUT
OUT’
IN
IN’
A
A’
OUT
OUT
a) Propagate through multiple stages buffer
with slow falling edge
b) Insert inverter between buffers
Figure 6. Clock Edge Selection
In Figure 6a, if the falling edge at the internal buffer is behind the rising edge, the clock will disappear if a multiple
cascade connection is made. To resolve this problem, the duty ratio can be held unchanged using the
connection as shown in Figure 6b if the valid clock edge can be selected (arrow in Figure 6). Note that the clock
delay is not avoided even in this case.
The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function,
the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL,
thusthedegradationforthedutyratiocanbereduced. TherelationshipbetweeneachsignalisshowninTable 5.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
Table 5. Valid Edge For DCLK and GSCLK
DPOL
DCLK valid edge
DCLK↑
Operation at XENABLE = H
H
L
Pull DCLK to low level
Pull DCLK to high level
DCLK↓
GSPOL
GSCLK valid edge
GSCLK↑
PLL operation
H
L
Synchronize to the high level of DCLK
Synchronize to the low level of DCLK
GSCLK↓
The device supplies the XPOUT and XGSOUT output terminals for the cascade operation which inverts GSPOL
and GSCLK respectively. It also supplies the BOUT output terminal as a buffered BLANK to make timing easy
with GSCLK and XGSOUT.
gray scale clock generation
When MAG<0:2> are all low, the clock input from the GSCLK terminal is used as the gray scale clock with no
change, and except for this case the internal PLL generates the clock for the gray scale control clock. When
using the PLL, the gray scale clock is generated by adjusting the clock to have the same number of pulses as
the multiple ratio of the GSCLK reference period (when GSCLK and GSPOL are kept at the same level). The
ratio in this case is determined depending on MAG0 through MAG2 as shown in Table 6.
When using the PLL, the internal PLLCLK is clocked out at the XGSOUT terminal. Therefore, the clock can be
utilized for other devices on the same print-circuit board. Note that the number of ICs connected is limited
depending on the frequency.
Table 6. PLL Multiple Ratio
MAG2
MAG1
MAG0
MULTIPLE RATIO
XGSOUT
L
L
L
L
L
H
L
1 (Signal to control GSCLK by GSPOL)
Inverted GSCLK
8
2 +6(=262)
9
2 +10(=522)
L
H
H
L
10
2
L
H
L
+18(=1042)
+34(=2082)
+66(=4162)
+130(=8322)
+258(=16642)
PLLCLK
11
12
H
H
H
H
2
(Gray scale clock is internally generated)
L
H
L
2
13
2
H
H
14
2
H
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
gray scale clock generation (continued)
MAG<2:0>
GSPOL
Except all low level
Except all low level
GSCLK
XGSOUT
PLLCLK
Same number of pulse as ratio
a) GSPOL is low
Same number of pulse as ratio
a) GSPOL is high
Figure 7. Gray Scale Clock Generation
The oscillation frequency bandwidth as referenced for the PLL can be set by an external resistor connected
between RBIAS and GND. The relation between the external resistor and the oscillation frequency is shown
in Table 7.
Table 7. PLL Oscillation Frequency
RBIAS
22 kΩ
30 kΩ
62 kΩ
12 0kΩ
FREQUENCY
13 to 16 MHz
8 to 14 MHz
4 to 9 MHz
3 to 5 MHz
Notethatittakes30msforthePLLtobestabilized. Furthermore, tomakethePLLoperationstabilized, aresistor
and a capacitor connection is required between VCOIN, PDOUT and GND. The recommended values are
shown in the Figure 8.
PDOUT
VCOIN
C(
R(
pd)
VCO)
Recommeded Value
0.1 to 1 µF 22 to 62 kΩ
R
(pd)
C(
VCO)
Figure 8. Resistor and Capacitor Connection
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
protection
This device incorporates WDT and TSD functions. If the WDT or TSD functions, the constant current output is
stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be
detected immediately. Since the XDOWN1 output is configured as open collector, outputs of multiple ICs are
brought together.
WDT (watchdog timer)
The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapsed after the
signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (a signal to the control
line displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned
off preventing the LED from burning and damage caused by continuous LED turn on at the dynamic scanning
operation. The detection time can be set using an external capacitor, C1. The typical value is approximately 10
ms without capacitor, 160 ms with a1000 pF capacitor, and 1500 ms with a 0.01 µF capacitor. During static
operation, the WDT function is disabled connecting the WDCAP to GND (high or low level should be applied
to WDTRG). Note that normal operations will be resumed changing the WDTRG level when WDT functions.
WDT operational time T (ms) 10 + 0.15 x C1 (pF)
Time (ms)
1500
TLC5911
Scan Signal
WDTRG
WDCAP
160
10
C1
0
0.001
0.01
C1 – External Capacitor – µF
Figure 9. WDT Operational Time and Usage Example
TSD (thermal shutdown)
When the junction temperature exceeds the limit, TSD functions and turns the constant current output off, and
XDOWN1 goes low. When TSD is used, TSENA is pulled high. When TSD is not used, TSENA is pulled low.
To recover from the constant current output off-state to normal operations, the power supply should be turned
off or TSENA should be pulled low once.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
LOD function (LED open detection)
When LEDCHK is low, the LED disconnection detection function is disabled and XDOWN2 goes to a
high-impedance state. When LEDCHK is high, the LED disconnection detection function is enabled, and
XDOWN2 goes low if any LED is disconnected while monitoring the OUTn terminals to be turned on. This
function is operational for sixteen OUTn terminals individually. To determine which constant current output is
disconnected, the level of XDOWN2 is checked 16 times from OUT0 to OUT15 turning one constant current
output on. The power supply voltage should be set so the constant current output applied is above 0.4 V when
the LED is turned on normally. Also, since approximately 1000 ns is required from turning the constant current
output on to XDOWN2 output, the gray scale data to be turned on during that period should be applied.
Table 8 is an example of XDOWN2 output status using four LEDs .
Table 8. XDOWN2 Output Example
LED NUMBER
LED STATUS
OUTn
1
2
3
4
GOOD
ON
NG
ON
NG
GOOD
ON
NG
ON
NG
DETECTION RESULT
XDOWN2
GOOD
GOOD
LOW (by case 2, 4)
LED NUMBER
LED STATUS
OUTn
1
2
3
4
GOOD
ON
NG
ON
NG
GOOD
OFF
NG
OFF
GOOD
DETECTION RESULT
XDOWN2
GOOD
GOOD
LOW (by case 2)
LED NUMBER
LED STATUS
OUTn
1
2
3
4
GOOD
OFF
NG
GOOD
OFF
NG
OFF
GOOD
OFF
GOOD
DETECTION RESULT
XDOWN2
GOOD
GOOD
HIGH-IMPEDANCE
noise reduction
concurrent switching noise reduction
Concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time. To
preventthisnoise, thedevicehasdelayoutputterminalssuchasXGSOUT, BOUTforGSCLK(grayscaleclock),
and BLANK (blanking signal) respectively. By connecting these outputs to the GSCLK and BLANK terminals
of next stage IC, it allows differences in the switching time between ICs. When GSCLK is output to GSOUT
through the device, duty will be changed between input and output. The number of stages to be connected will
be limited depending on the frequency.
delay between constant current output
The constant current output has a delay time of approximately 20 ns between outputs. It means approximately
300 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for the reduction
of concurrent switching noise.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
others
power supply
The following should be taken into consideration:
VCCLOG, VCCANA and VCCLED should be supplied by a single power supply to minimize voltage
differences between these terminals.
The bypass capacitor should be located between the power supply and GND to eliminate the variation of
power supply voltage.
GND
Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally
connected to reduce noise influence.
thermal pad
ThethermalpadshouldbeconnectedtoGNDtoeliminatethenoiseinfluence, sinceitisconnectedtothebottom
side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with
better thermal conductivity.
power rating free-air temperature
3.2
4.7
2.3
1.48
0
0
–20
0
25
85
T
A
– Free-Air Temperature – °C
NOTES: A. The IC is mounted on PCB.
3
PCB size : 102 × 76 × 1.6 [mm ], four layers with the internal two layers being plane. The thermal pad is soldered to the PCB
2
pattern of 10 × 10 [mm ]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
=V =V =5 V, I = 80 mA, I is a typical value.
V
CC(LOG) CC(ANA) CC(LED) CC
OL(C)
B. The thermal impedance will be varied depending on the mounting conditions. Since the PZP package established a low
thermalimpedancebyradiatingheatfromthethermalpad, thethermalpadshouldbesolderedtothepatternwithalowthermal
impedance.
C. The material for the PCB should be selected considering the thermal characteristics since the temperature will rise around
the thermal pad.
Figure 10. Power Rating
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
PRINCIPLES OF OPERATION
90
80
70
60
50
40
30
20
10
0
0.1
1.0
10.0
R
(kΩ)
(IREF)
Conditions : V = 1 V, V
O
= 1.2 V
(IREF)
V
(V)
(IREF)
I
(mA)
38
OL(C)
R
(k
)
(IREF)
46
R
(k
)
(IREF)
I
(mA)
OL(C)
NOTE: The brightness control and dot corrected value are set at 100%.
The resistor, R , should be located as close as possible to the IREF terminal to avoid noise influence.
(IREF)
Figure 11. Current on Constant Current Output vs External Resistor
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RSEL0
RSEL1
DPOL
XOE
XENABLE
t
t
(XENABLE–DCLK)
(DIN–DCLK)
1/f
(DCLK)
t (XENABLE–DCLK)
h
su
DCLK
t
(DCLK)
D0E_A
t
(DCLK)
w(h)
su
w(l)
DIN0
DIN9
D00_A
D90_A
D01_A
D02_A
D0F_A D00_B
D9F_A D90_B
D0D_B D0E_B
D9D_B D9E_B
D0F_B
D00_C
D90_C
D01_C
D91_C
D91_A
D92_A
D9E_A
D9F_B
t (DIN–DCLK)
h
t (XLATCH–DCLK)
h
t
(XLATCH–DCLK)
su
XLATCH
t
(XLATCH)
w(h)
HI–Z
HI–Z
DOUT0
DOUT9
D00_A
D01_A
D0E_A
D9E_A
D0F_A
D00_B
D90_B
D90_A
D91_A
D9F_A
t (XOE↓–DOUT)
d
t (DCLK–DOUT)
d
t (XOE↑–DOUT)
d
DPOL
DCLK
DPOL and DCLK can be replaced with the combination of these signals enclosed by the parenthesis (Both are inverted each other).
Figure 12. Timing Diagram (Shift Register for Gray Scale Data)
BCENA
RSEL0
RSEL1
XOE
t
(RSEL–XLATCH)
su
t (RSEL–XLATCH)
h
t (XOE↓–DOUT)
d
DPOL
XENABLE
t
(RSEL–DCLK)
su
t
(RSEL–DCLK)
su
DCLK
DIN0
D0_A
D9_A
D0_B
D9_B
D0_C
D9_C
D0_J
D9_J
D0_K
D9_K
D0_L
D9_L
D0_M
D9_M
D0_N
D9_N
D0_O
D9_O
DIN9
t (XLATCH–DCLK)
h
XLATCH
t
(XLATCH)
w(h)
Default Value 1
Default Value 1
Default Value 0
D<5:0>_A
BCL_0–5
(Brightness Control Latch-Internal Signal)
BCL_6–9
Default Value 0
D<9:6>_A
t (DCLK–DOUT)
d
t (XOE↑–DOUT)
d
t
(RSEL–DOUT)
su
HI–Z
DOUT0
DOUT9
D0_A
D0_C
D9_C
D0_E
D0_F
D0_G
D9_G
D0_H
D0_I
HI–Z
D9_A
D9_E
D9_F
D9_H
D9_I
DPOL and DCLK can be replaced with signals inverted each other same as shift register for gray scale data.
Figure 13. Timing Diagram (Shift Register for Brightness Control)
DCENA
RSEL0
RSEL1
t
(XENABLE–DCLK)
su
t
(RSEL–XDCLAT)
su
t (RSEL–XDCLAT)
h
t
(RSEL–DCCLK)
su
t
(RSEL–DCCLK)
su
DCCLK
DCDIN0
DCDIN5
D0_A
D5_A
D0_B
D0_C
D5_C
D0_J
D5_J
D0_K
D5_K
D0_L
D5_L
D0_M
D0_N
D5_N
D0_O
D5_O
D5_B
D5_M
t (XDCLAT–DCCLK)
h
XDCLAT
t
(XDCLAT)
w(h)
Dx<15:0>_A
t (DCCLK–DCDOUT)
DCL_0–15
Default Value “1”
(Note)
Default Value “1”
(Dot Correction Latch-Internal Signal: 6 bit x 16)
d
D0_A
D0_C
D0_E
D0_F
D0_G
D0_H
D5_H
D0_I
DCDOUT0
DCDOUT5
D5_A
D5_C
D5_E
D5_F
D5_G
D5_I
NOTE : RegistervalueisimmediatelybeforeDCLAT↓.
Figure 14. Timing Diagram (Shift Register for Dot Correction: Using Port B)
RSEL0
RSEL1
XOE
t
(RSEL–XLATCH)
su
t (RSEL–XLATCH)
h
t (XOE↓–DOUT)
d
DPOL
XENABLE
t
(RSEL–DCLK)
su
t
(RSEL–DCLK)
su
DCLK
DIN0
DIN9
D0_A
D9_A
D0_B
D9_B
D0_C
D9_C
D0_J
D9_J
D0_K
D9_K
D0_L
D9_L
D0_M
D9_M
D0_N
D0_O
D9_O
...
...
D9_N
t (XLATCH–DCLK)
h
XLATCH
t
w(h)
(XLATCH)
D0_C
t
(RSEL–DOUT)
su
t (DCLK–DOUT)
d
t (XOE↑–DOUT)
d
HI–Z
HI–Z
DOUT0
DOUT5
D0_A
D0_E
D0_F
D0_G
D0_H
D0_I
D5_I
D5_A
D5_C
D5_E
D5_F
D5_G
D5_H
t (XOE↓–DOUT)
d
DOUT
<9:6>
HI–Z
t (DCLK–DCDOUT)
d
DCDOUT0
DCDOUT5
D0_A
D0_C
D5_C
D0_E
D5_E
D0_F
D5_F
D0_G
D0_H
D5_H
D0_I
D5_I
...
D5_A
D5_G
DPOL and DCLK can be replaced with signals inverted each other same as shift register for gray scale data.
Figure 15. Timing Diagram (Shift Register for Dot Correction: Using Port A)
XLATCH
t
(XLATCH–GSCLK)
su
BLANK
GSPOL
1/f(
GSCLK)
t
(BLANK–GSCLK)
su
t (BLANK–OUT0)
d
GSCLK
1/f(
WDT)
t
(GSCLK)
w(l)
t
(GSCLK)
w(h)
WDTRG
t
t
(WDTRG)
(WDTRG)
w(h)
w(l)
t
wdt
t (BLANK–OUT0)
t (GSCLK–OUT0)
d
t (GSCLK–OUT0)
d
d
(SeeNote1)
t (OUTn+1–OUTn)
OFF
ON (See Note1)
OFF
OFF
(SeeNote1)
OUT0
t (OUTn+1–OUTn)
d
d
ON (See Note1)
ON (See Note1)
(SeeNote1)
(SeeNote1)
(SeeNote1)
OFF
OFF
OFF
OUT1
(SeeNote1)
OUT15
OFF
OFF
OFF
HI–Z
XDOWN1
XDOWN2
(See Note2)
(See Note2)
(See Note2)
t (GSCLK–XDOWN2)
d
t (BLANK–BOUT)
d
BOUT
t (GSCLK–XGSOUT)
d
XGSOUT
LEDCHK
t (LEDCHK–XDOWN2)
d
t (LEDCHK–XDOWN2)
d
GSPOL, GSCLK and XGSOUT can be replaced with signals inverted each other.
NOTE 1: ON or OFF, or ON time is varied depend on the gray scale data and BLANK.
NOTE 2: When LED is disconnected.
Figure 16. Timing Diagram (Constant Current Output) – MAG0 to MAG2 Are All Zero
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
M
0,50
75
0,08
0,17
51
50
76
Thermal Pad
(see Note D)
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
0,25
0,15
15,80
0°–7°
0,05
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146929/A 04/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.The dimensions of the thermal
pad are 2 mm × 2 mm (maximum). The pad is centered on the bottom of the package.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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