TLC5922DAP [TI]
LED DRIVER; LED驱动器
| 型号： | TLC5922DAP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LED DRIVER |
| 文件： | 总16页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
LED DRIVER
DESCRIPTION
FEATURES
•
•
16 Channels
The TLC5922 is a constant-current sink driver with 128
steps of adjustable current value (dot-correction). Each
of the 16 channels has an individually controlled
dot-correction and an ON/OFF state. Both the ON/OFF
and dot-correction have their respective modes set via
1 port of serial I/F. The maximum current value of the
constant-current output of all 16 channels is pro-
grammed by a single external resistor. An external
processor programs each of the 16 channels of the
TLC5922 with the desired ON/OFF state and
dot-correction value through a single serial interface.
After all data is loaded, the processor then latches the
information into the TLC5922 and enables the outputs.
Drive Capability
– 0 to 80 mA (Constant-Current Sink) x 16 ch
•
Constant Current Accuracy
– ±1% (typ)
•
•
•
•
•
•
•
•
•
1 Port of Serial Data Input/Output
Fast Switching Output: Tr / Tf = 10ns (typ)
CMOS Input/Output
30 MHz Data Transfer Rate
Vcc = 3 V to 5.5 V
Operating Temperature = -20°C to 85 °C
LED Supply Voltage up to 17 V
32-pin HTSSOP (PowerPADTM) Package
The TLC5922 includes two error flags. First is the LED
open detection (LOD) which indicates a broken LED at
an output terminal. The second is a thermal error flag
(TEF) which indicates an over temperature condition.
The TLC5922 has two methods to communicate these
error flags to the external processor. One method is on
a dedicated output pin, XDOWN. The other method is
through the serial data output pin, SOUT.
Dot Correction
– 128-Step For Each Individual 16 ch
•
•
Controlled In-Rush Current
Error Information
– LOD: LED Open Detection
– TEF: Thermal Error Flag
APPLICATIONS
•
•
LED Display
LED Signboard
FUNCTIONAL BLOCK DIAGRAM
VCC
0
1
SIN
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
FF
FF
FF
FF
FF
FF
1
0
SCLK
0
1
SOUT
D
Q
D Q
D
Q
D
Q
D
Q
D Q
LAT
LAT
LAT
LAT
LAT
LAT
1
0
XLAT
SW0
SW1
SW15
16
DC15[6]
XDOWN
IREF
16[output] Constant
Current Driver
DC0[1]
DC0[0]
with Dot Correction
BLANK
BLANK
GND
OUT0
OUT15
PGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
cludetestingofallparameters.
Copyright © 2003, Texas Instruments Incorporated
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
(1)
ORDERING INFORMATION
(1)
TA
PACKAGE
PART NUMBER
-20 °C to 85 °C
4 mm x 4 mm, 32-pin HTSSOP
TLC5922DAP
(1)
The DAP package is available in tape and reel. Add R suffix (TLC5922DAPR) to order quantities of 2000 parts per reel.
DAP PACKAGE
(TOP VIEW)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
BLANK
XLAT
SCLK
SIN
PGND
OUT0
OUT1
PGND
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
VCC
IREF
2
3
MODE
XDOWN
SOUT
PGND
OUT15
OUT14
PGND
OUT13
OUT12
OUT11
OUT10
PGND
OUT9
4
5
6
7
8
9
10
11
12
13
14
15
16
OUT8
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
Blank(Light OFF). When BLANK=H, All OUTx outputs are forced OFF. When BLANK=L,
ON/OFF of OUTx outputs are controlled by input data.
BLANK
2
2
GND
IREF
1
Ground
31
I/O
I
Reference current terminal
Mode select. When MODE=L, SIN, SOUT, SCLK, XLAT are connected to ON/OFF control
logic. When MODE=H, SIN, SOUT, SCLK, XLAT are connected to dot-correction logic.
MODE
30
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
7
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
8
10
11
12
13
15
16
17
18
20
21
22
23
25
26
6, 9, 14, 19,
24, 27
PGND
Power ground
2
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Data shift clock. Note that the internal connections are switched by MODE (pin #30). At
SCLK↑, the shift-registers selected by MODE shift the data.
SCLK
4
I
SIN
5
I
Data input of serial I/F
SOUT
VCC
28
32
29
O
Data output of serial I/F
Power supply voltage
XDOWN
O
I
Error output. XDOWN is open drain terminal. XDOWN gets L when LOD or TEF detected.
Data latch. Note that the internal connections are switched by MODE (pin #30). At XLAT↑, the
latches selected by MODE get new data.
XLAT
3
(1)
ABSOLUTE MAXIMUM RATINGS
(2)
See
UNIT
(2)
Supply voltage
VCC
- 0.3 V to 6 V
90 mA
Output current (dc)
Input voltage range
IL(LC)
(2)
(2)
V(BLANK), V(XLAT), V(SCLK), V(SIN)
V(MODE)
,
- 0.3 V to VCC + 0.3 V
Output voltage range
ESD rating
V(SOUT), V(XDOWN)
V(OUT0) - V(OUT15)
- 0.3 V to VCC + 0.3 V
-0.3 V to 18.0 V
2 kV
HBM (JEDEC JESD22-A114, Human
Body Model)
CDM (JEDEC JESD22-C101,
Charged Device Model)
500 V
Storage temperature range, Tstg
-40°C to 150°C
3.9 W
Continuous total power dissipation at (or below) TA = 25°C
Power dissipation rating at (or above) TA = 25°C
31.4 mW/°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
(2)
RECOMMENDED OPERATING CONDITIONS
DC CHARACTERISTICS
MIN
NOM MAX
UNIT
V
Supply voltage, VCC
3
5.5
Voltage applied to output, VO (Out0 - Out15)
High-level input voltage, VIH
Low-level input voltage, VIL
17
V
0.8 VCC
GND
VCC
V
0.2 VCC
-1
V
High-level output current, IOH
VCC = 5 V at SOUT
mA
mA
mA
°C
Low-level output current, IOL
VCC = 5 V at SOUT, XDOWN
OUT0 to OUT15
1
Constant output current, IO(LC)
Operating free-air temperature range, TA
80
85
(1)
-20
(1)
Please contact TI sales for slightly extended temperature range.
3
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
AC CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = -20°C to 85°C (unless otherwise noted)
MIN TYP
MAX UNIT
fSCLK
twh0/twl0
twh1
tsu0
tsu1
tsu2
tsu3
th0
Clock frequency
SCLK
30 MHz
ns
CLK pulse duration
XLAT pulse duration
SCLK=H/L
20
20
10
10
10
10
10
10
10
10
XLAT=H
ns
SIN - SCLK↑
SCLK↑-XLAT↓
MODE↑↓-SCLK↑
MODE↑↓-XLAT↓
SCLK↑-SIN
ns
ns
Setup time
Hold time
ns
ns
ns
th1
XLAT↓-SCLK↑
SCLK↑-MODE↑↓
XLAT↓-MODE↑↓
ns
th2
ns
th3
ns
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = - 20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
VOH
VOL
II
High-level output voltage
IOH = - 1 mA, SOUT
VCC0.5V
V
Low-level output voltage
Input current
IOL = 1 mA, SOUT
0.5
1
V
VI = VCC or GND, BLANK, XLAT,SCLK, SIN, MODE
-1
µA
No data transfer, All output OFF, VO = 1 V, R(IREF) = 10
kΩ
6
No data transfer, All output OFF, VO = 1 V, R(IREF) = 1.3
kΩ
12
25
ICC
Supply current
mA
Data transfer 30 MHz, All output ON, VO = 1 V, R(IREF)
=
1.3 kΩ
Data transfer 30 MHz, All output ON, VO = 1 V, R(IREF)
600 kΩ
=
(1)
36
80
65
IOLC
Constant output current
Leakage output current
All output ON, VO= 1 V, R(IREF) = 600Ω
70
90
mA
µA
µA
%
All output OFF, VO= 15 V, R(IREF) = 600Ω , OUT0 to
IOKL0
IOKL1
∆IOLC
0.1
10
OUT15
VXDOWN = 5.5 V, No TEF and LOD
All output ON, VO = 1 V, R(IREF) = 600 Ω, OUT0 to
OUT15
Constant current error
Power supply rejection ratio
Load regulation
±1
± 4
All output ON, VO = 1 V, R(IREF) = 600 Ω, OUT0 to
OUT15
∆IOLC1
∆IOLC2
± 1
± 2
± 4
± 6
%/V
%/V
All output ON, VO = 1 V to 3 V, R(IREF) = 600 Ω, OUT0 to
OUT15
(2)
TTEF
Thermal error flag threshold
LED open detection threshold
Reference voltage output
Junction temperature, rising temperature
150
180
°C
V
V(LOD)
VIREF
0.3
R(IREF) = 600 Ω
1.22
V
(1)
(2)
Measured at device start-up temperature. Once the IC is operatiing (self heating), lower ICC values will be seen. See Figure 12.
Not tested. Specified by design.
4
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
SWITCHING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
10
MAX
20
UNIT
SOUT(see
OUTx, VCC = 5 V, TA = 60°C, DCx = 7F (see
(1)
)
tr
tf
Rise time
ns
(2)
(2)
)
30
SOUT(see
)
20
Fall time
ns
OUTx, VCC = 5 V, TA = 60°C, DCx = 7F (see
)
10
30
(3)
SCLK↑ - SOUT↑↓ (see
)
300
300
60
(3)
MODE↑↓ - SOUT↑↓ (see
)
(4)
BLANK↓ - OUT0↑↓ (see
)
Propagation delay
time
ns
ns
(4)
tpd
XLAT↑ - OUT0↑↓ (see
OUTx↑↓-XDOWN↑↓ (see
)
60
(5)
)
1000
1000
30
(6)
)
XLAT↑-IOUT(dot-correction) (see
(4)
Output delay time
OUTn↑↓-OUT(n+1)↑↓ (see
)
14
22
(1)
See Figure 4. Defined as from 10% to 90%
See Figure 5. Defined as from 10% to 90%
See Figure 4, Figure 9and Figure 10
See Figure 5 and Figure 9
See Figure 5, Figure 6, and Figure 9
See Figure 5 and Figure 10
(2)
(3)
(4)
(5)
(6)
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
(Note: Resistor values are equivalent resistance and not tested).
VCC
400 W
INPUT
GND
Figure 1. Input Equivalent Circuit (BLANK, XLAT, SCLK, SIN, MODE)
10 W
SOUT
GND
Figure 2. Output Equivalent Circuit
20 W
XDOWN
GND
Figure 3. Output Equivalent Circuit (XDOWN)
5
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
SOUT
15 pF
Figure 4. Test Circuit for Tr0, Tf1, Td0, Td1
51 Ω
OUTn
15 pF
Figure 5. Test Circuit for Tr1, Tf1, Td2, Td3, Td5, Td6
470 kΩ
XDOWN
Figure 6. Test Circuit for Td4
PRINCIPLES OF OPERATION
Setting Constant-Current Value
The maximum programmable output current for all 16 outputs is set by a single resistor, R(IREF), which is placed
between IREF and GND. The current flowing through R(IREF) is sampled by the TLC5922 and multiplied by a
scaling factor of 40 to set the maximum output current for all outputs. The voltage on IREF is set by an internal
band gap with a nominal value of 1.22V. The maximum programmable output current is set by Equation 1:
V
IREF
I
+
40
MAX
R
IREF
(1)
where:
VIREF = 1.22V
RIREF = User selected external resistor (RIREF should not be smaller than 600Ω)
Setting Dot-Correction
The TLC5922 has the capability to adjust the brightness of each channel, OUT0,...,OUT15. This capability is
called dot-correction. The external processor programs each of the 16 channels of the TLC5922 with a 7 bit word
that adjusts each respective output from 0% to 100% of the maximum output current, Imax. The 7 bits provides
27 (= 128) programmable current values. Equation 2 below determines the output current for each output:
I
DC
n
MAX
I
+
Outn
127
(2)
6
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
PRINCIPLES OF OPERATION (continued)
where:
IMax = the maximum programmable current of each output
DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127)
n = 0, 1, 2 ... 15
Forcing OFF the Constant Current Outputs
The BLANK input pin is used to disable all OUTx constant-current output terminals. When BLANK is a logic 1, all
OUTx are forced off, regardless of any other logic operations.
Internal Register Definitions
The TLC5922 has two separate serial data shift-registers and two separate data-latches. The first combination of
registers and latches controls the ON/OFF function of the output. These are referred to as the EN_REG registers
and EN_LATCHn latches, where n= 0,1...15 and specifies the output channel. There are 16 EN_REG registers
and 16 EN_LATCHn latches. Both are one bit each. Figure 7 shows how these are connected.
The second combination of registers and latches controls the dot-correction value for each output. These are
referred to as the DC_REG registers and DC_LATCHn latches, where n=0,1...15 and specifies the output
channel. There are 112 DC_REG data shift-registers (1 bit each) and 16 DC_LATCHn latches (seven bits each).
Figure 8 shows how these are connected.
All data to the TLC5922 comes from the SIN pin. The MODE pin determines whether the inputs and outputs of
the TLC5922 are connected to the ON/OFF logic or the dot-correction logic. When MODE is a logic 0, all data is
connected to the ON/OFF logic. When MODE is a logic 1, all data is connected to the dot-correction logic.
Each rising edge of the SCLK pin shifts the data in either the EN_REG or DC_REG registers. Each rising edge
of the XLAT pin transfers the data from the selected registers (either EN_REG or DC_REG) and latches it into
the selected latch (EN_LATCHn or DC_LATCHn).
Turning ON/OFF the Constant Current Outputs
The TLC5922 EN_LATCHn data-latches hold the ON/OFF information for each output. When the MODE input is
low, the processor can access both the EN_LATCHn and EN_REG registers. The 16 cascaded EN_REG shift
registers transfer ON/OFF data from SIN to SOUT output at each rising edge of the SCLK pin. XLAT is held low
when the ON/OFF data is clocked into the TLC5922. When all data is clocked in, the rising edge of the XLAT pin
transfers and latches the ON/OFF data into the EN_LATCHn latches. Each of the 16 EN_LATCHn data-latches
holds a 1 bit digital code that turns each of the 16 outputs on or off. The processor must clock in 16 bits of data
to fully program the ON/OFF setting for all 16 outputs. The ON/OFF data becomes valid on the OUTn outputs
when BLANK goes low.
During the XLAT=H(MODE=L), shift-register loads the LOD status of each 16 outputs (and the controller can
read the LOD status from SOUT). Note that incoming data from the controller is latched at XLAT↑(MODE=L),
and afterwards, the shift-register loads LOD status during XLAT=H(MODE=L).
7
TLC5922
www.ti.com
SLVS486–SEPTEMBER 2003
PRINCIPLES OF OPERATION (continued)
SIN
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
SOUT
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
SCLK
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
XLAT
Figure 7. Shift Register and Data Latch for ON/OFF Setting
Delay Between Outputs
The TLC5922 has graduated delay circuits between outputs. In Figure 7, these delay circuits can be found
between OUTn and constant current block. The fixed delay time is 20 ns (TYP), OUT0 has no delay, OUT1 has
20 ns delay, OUT2 has 40 ns delay. This delay prevents large inrush currents, which reduce power supply
bypass capacitor requirements when the outputs turn on.
Setting Dot-Correction
The TLC5922 DC_LATCHn data latches hold the dot-correction information for each output. When the MODE
input is high, the processor can access both the DC_LATCHn and DC_REG registers. The 112 cascaded
DC_REG shift registers transfer dot-correction data from SIN to SOUT output at each rising edge of the SCLK
pin. XLAT is held low when the dot-correction data is clocked into the TLC5922. When all data is clocked in, the
rising edge of the XLAT pin transfers and latches the dot-correction data into the DC_LATCHn latches. Each of
the 16 DC_LATCHn data-latches holds a 7 bit digital code to adjust the constant current value for each of the 16
outputs. The processor must clock in 112 bits of data to fully program the dot-correction for all 16 channnels.
SIN
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
SOUT
FF
FF
FF
FF
FF
FF
FF
FF
FF
SCLK
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
LAT
XLAT
Bit 0 Bit 1 −−−− Bit 6
(LSB) (MSB)
7[bit] Digital=>Analog
Bit 0 Bit 1 −−−− Bit 6
(MSB)
7[bit] Digital=>Analog
Bit 0 Bit 1 −−−− Bit 6
(MSB)
(LSB)
(LSB)
7[bit] Digital=>Analog
Figure 8. Shift Register and Data Latch for Dot-Correction
8
TLC5922
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SLVS486–SEPTEMBER 2003
PRINCIPLES OF OPERATION (continued)
Error Information Output
The open-drain output, XDOWN, is used to report both of the TLC5922 error flags. (Note: the XDOWN output
must be pulled to VCC with a pullup resistor)
During normal operating conditions, an internal FET connected to the XDOWN pin is turned off. The voltage on
XDOWN is pulled up to VCC through the pullup resistor. If TEF or LOD is detected (see following sections), the
internal FET is turned on, and XDOWN is pulled to GND.
Since XDOWN is an open-drain output, multiple ICs can be OR’ed together and pulled up to VCC with a single
pullup resistor. This reduces the number of signals needed to report a system error.
TEF: Thermal Error Flag
The TLC5922 provides a temperature error flag (TEF) circuit to indicate an over-temperature condition of the IC.
If the junction temperature exceeds the threshold temperature (160oC typ), the TEF circuit trips and pulls
XDOWN to ground.
LOD: LED Open Detection
The TLC5922 provides an LED open detection circuit (LOD). This circuit reports an error if any one of the 16
LEDs is open, or is disconnected from the circuit. The LOD circuit trips when two conditions are met
simultaneouly: When OUTn is programmed to be on, and when the voltage at OUTn is less than 0.3V (Note: the
voltage at each OUTn is sampled 1µS after being turned on).
An LOD failure is reported in two ways. First, the LOD circuit only monitors OUTn when the OUTn is turned on.
Each OUTn is individually monitored. The state of all 16 outputs are OR’ed together and reported at the XDOWN
pin.
Second, the LOD circuit may also be monitored from the SOUT pin. When the MODE pin is low and the XLAT
pin goes high, the 16 bits of ON/OFF data get transferred from the EN_REG registers to the EN_LATCHn
latches. At the same time, the LOD status of each output is transferred to the EN_REG registers. These 16 bits
of LOD data are then clocked out of the SOUT pin as the new ON/OFF data is clocked into the SIN pin. This
reporting scheme allows the processor to determine the state of each LED.
9
TLC5922
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SLVS486–SEPTEMBER 2003
PRINCIPLES OF OPERATION (continued)
Figure 9. Timing Chart Example for ON/OFF Setting to Dot-Correction
10
TLC5922
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SLVS486–SEPTEMBER 2003
PRINCIPLES OF OPERATION (continued)
Figure 10. Timing Chart Example for Dot-Correction to ON/OFF Setting
11
TLC5922
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SLVS486–SEPTEMBER 2003
PRINCIPLES OF OPERATION (continued)
Power Rating - Free-Air Temperature
Figure 11 shows total power dissipation. Figure 12 shows supply current versus free-air temperature.
Power Dissipation
vs
Temperature
3.9
3.2
1.48
2
−20
0
25
85
T
A
− Free- Air Temperature − °C
Figure 11
Supply Current1
vs
Free-Air Temperature
70
60
50
40
30
20
10
0
−50 −30 −10 10 30 50 70 90 110 130 150
T
A
− Free- Air Temperature − °C
1. Data Transfer = 30 MHz / All Outputs, ON/VO = 1 V / RIREF = 600 Ω / AVDD = 5 V
Figure 12
12
TLC5922
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SLVS486–SEPTEMBER 2003
PRINCIPLES OF OPERATION (continued)
Constant Output Current - Reference Resistor
Figure 13 shows the maximum output current, IOLC, versus R(IREF) . In Figure 13, R(IREF) is the value of the
resistor between IREF terminal to ground, and IOLC is the constant output current of OUT0,.....OUT15.
Reference Resistor
vs
Output Current
100 k
48.8 k
V
Outn
= 1 V
DC = 127
10 k
9.76 k
4.88 k
2.44 k
1.63 k
1.22 k
976
1 k
813
697
100
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
I
− Output Current − mA
OLC
Figure 13
13
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Thermal Pad Mechanical Data
DAP (R–PDSO–G32)
THERMAL INFORMATION
The DAP PowerPAD™ package incorporates an exposed thermal die pad that is designed to be attached directly
to an external heat sink. When the thermal die pad is soldered directly to the printed circuit board (PCB), the PCB
can be used as a heatsink. In addition, through the use of thermal vias, the thermal die pad can be attached directly
to a ground plane or special heat sink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to
Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and
Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available
at www.ti.com. See Figure 1 for DAP package exposed thermal die pad dimensions.
32
1
Exposed Thermal
Die Pad
3,91
3,31
17
16
4,11
3,35
Bottom View
PPTD001
NOTE: All linear dimensions are in millimeters.
Figure 1. DAP Package Exposed Thermal Die Pad Dimensions
PowerPAD is a trademark of Texas Instruments.
1
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