TLC59282DBQ [TI]
16-Channel, Constant-Current LED Driver with 4-Channel Grouped Delay; 16通道恒流LED驱动器， 4通道分组延迟
| 型号： | TLC59282DBQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Channel, Constant-Current LED Driver with 4-Channel Grouped Delay |
| 文件： | 总25页 (文件大小：1076K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC59282
www.ti.com
SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
16-Channel, Constant-Current LED Driver with 4-Channel Grouped Delay
Check for Samples: TLC59282
1
FEATURES
APPLICATIONS
2
•
16 Channels, Constant-Current Sink Output
with On/Off Control
•
•
•
Video Displays
Message Boards
Illumination
•
Capability (Constant-Current Sink):
35 mA (VCC ≤ 3.6 V), 45 mA (VCC > 3.6 V)
•
•
•
LED Power-Supply Voltage up to 17 V
VCC = 3 V to 5.5 V
DESCRIPTION
The TLC59282 is a 16-channel, constant-current sink
driver. Each channel can be individually controlled via
a simple serial communications protocol that is
compatible with 3.3 V or 5 V CMOS logic levels,
depending on the operating VCC. Once the serial
data buffer is loaded, a rising edge on LATCH
transfers the data to the LEDx outputs. The BLANK
pin can be used to turn off all OUTn outputs during
power-on and output data latching to prevent
unwanted image displays during these times. The
constant-current value of all 16 channels is set by a
single external resistor. Multiple TLC59282s can be
cascaded together to control additional LEDs from the
same processor.
Constant-Current Accuracy:
–
Channel-to-Channel = ±0.6% (typ),
±2% (max)
–
Device-to-Device = ±1% (typ), ±3% (max)
•
Low Saturation Voltage: 0.31 V at 20 mA (typ)
TA = +25℃, One Channel On
–
•
•
•
•
CMOS Logic Level I/O
Data Transfer Rate: 35 MHz
BLANK Pulse Width: 30 ns
Four-Channel Grouped Delay for
Noise Reduction
•
Operating Temperature: –40°C to +85°C
VLED
VLED
VLED
VLED
¼
¼
¼
¼
¼
¼
¼
¼
OUT0
OUT15
SOUT
OUT0
SIN
OUT15
SOUT
DATA
SIN
SCLK
VCC
VCC
SCLK
SCLK
LAT
LAT
Controller
LAT
VCC
GND
VCC
GND
BLANK
BLANK
IREF
BLANK
IREF
TLC59282
TLC59282
ICn
IC1
RIREF
RIREF
3
Typical Application Circuit (Multiple Daisy-Chained TLC59282s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TLC59282
SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
TLC59282DBQR
TLC59282DBQ
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 2500
Tube, 50
TLC59282
SSOP-24/QSOP-24
TLC59282RGER
TLC59282RGE
Tape and Reel, 3000
Tape and Reel, 250
TLC59282
QFN-24
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
TLC59282
–0.3 to +6
50
UNIT
V
VCC
IOUT
VIN
Supply voltage
Output current (dc)
Input voltage range
OUT0 to OUT15
mA
V
SIN, SCLK, LAT, BLANK, IREF
SOUT
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to +18
+150
V
VOUT
Output voltage range
OUT0 to OUT15
V
TJ(MAX)
TSTG
Operating junction temperature
Storage temperature range
°C
°C
V
–55 to +150
4000
Human body model (HBM)
ESD rating
Charged device model (CDM)
1000
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
TLC59282
THERMAL METRIC(1)
DBQ
24 PINS
73.2
RGE
24 PINS
46.8
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
44.6
48.6
38.9
23.0
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12.3
1.2
ψJB
39.7
22.9
θJCbot
n/a
6.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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TLC59282
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SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC59282
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
VO
Supply voltage
3
5.5
V
V
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
OUT0 to OUT15
17
VIH
VIL
IOH
IOL
0.7 × VCC
VCC
V
GND
0.3 × VCC
V
SOUT
SOUT
–1
mA
mA
1
OUT0 to OUT15,
3 V ≤ VCC < 3.6 V
2
2
35
45
mA
mA
IOLC
Constant output sink current
OUT0 to OUT15,
3.6 V ≤ VCC < 5.5 V
TA
TJ
Operating free-air temperature range
Operating junction temperature range
–40
–40
+85
°C
°C
+125
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (SCLK)
TWH0
TWL0
TWH1
TWH2
TWL2
TSU0
Data shift clock frequency
SCLK
SCLK
35
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
20
60
30
4
SCLK
Pulse duration
LAT
BLANK
BLANK
SIN–SCLK↑
LAT↓–SCLK↑
SIN–SCLK↑
LAT↓–SCLK↑
Setup time
Hold time
TSU1
10
4
TH0
TH1
10
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ELECTRICAL CHARACTERISTICS
At VCC = 3 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC59282
PARAMETER
TEST CONDITIONS
IOH = –1 mA at SOUT
MIN
TYP
MAX
VCC
0.4
1
UNIT
V
VOH
VOL
IIN
High-level output voltage
Low-level output voltage
Input current
V
CC – 0.4
IOL = 1 mA at SOUT
V
VIN = VCC or GND at SIN and SCLK
–1
μA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
RIREF = open
ICC0
0.1
4.5
7
1
6
mA
mA
mA
mA
mA
μA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
RIREF = 3 kΩ (IOUT = 16.8 mA target)
ICC1
Supply current (VCC
)
All OUTn = ON, SIN/SCLK/LAT/BLANK = low,
VOUTn = 1 V, RIREF = 3 kΩ
ICC2
15
All OUTn = ON, SIN/SCLK/LAT/BLANK = low,
VOUTn = 1 V, RIREF = 1.5 kΩ (IOUT = 33.6mA target)
ICC3
16
34
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15 (see Figure 6), TA = +25°C
IOLC
Constant output current
Output leakage current
32.1
33.7
35.3
0.1
±2
OUTn = OFF, VOUTn = VOUTfix = 17 V, BLANK = high,
RIREF = 1.5 kΩ at OUT0 to OUT15 (see Figure 6)
IOLKG
ΔIOLC0
ΔIOLC1
ΔIOLC2
ΔIOLC3
Constant-current error
(channel-to-channel)(1)
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15
±0.6
±1
%
Constant-current error
(device-to-device)(2)
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15, TA = +25°C
±3
%
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15, VCC = 3 V to 5.5 V
Line regulation(3)
Load regulation(4)
±0.5
±1
±1
%/V
%/V
All OUTn = ON, VOUTn = 1 V to 3V, VOUTfix = 1 V,
RIREF = 1.5 kΩ
±3
VIREF
RPUP
Reference voltage output
Pull-up resistor
RIREF = 1.5 kΩ, TA = +25°C
1.18
250
250
1.205
500
1.23
750
750
V
BLANK
LAT
kΩ
kΩ
RPDWN
Pull-down resistor
500
(1) The deviation of each output from the average of OUT0–OUT15 constant-current. Deviation is calculated by the formula:
IOUTn
D (%) =
- 1 ´ 100
(IOUT0 + IOUT1 + ... + IOUT14 + IOUT15
)
16
.
(2) The deviation of the OUT0–OUT15 constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15
)
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
1.205
IOUT(IDEAL) = 41.9 ´
RIREF
(3) Line regulation is calculated by this equation:
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3 V)
D (%/V) =
100
´
(IOUTn at VCC = 3 V)
5.5 V - 3 V
(4) Load regulation is calculated by the equation:
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
D (%/V) =
100
3 V - 1 V
´
(IOUTn at VOUTn = 1 V)
4
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SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
SWITCHING CHARACTERISTICS
At VCC = 3 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 130 Ω, RIREF = 1.5 kΩ, and VLED = 5.5 V. Typical values at VCC
= 3.3 V and TA = +25°C, unless otherwise noted.
TLC59282
PARAMETER
TEST CONDITIONS
SOUT (see Figure 5)
MIN
TYP
5
MAX
12
UNIT
ns
tR0
tR1
tF0
tF1
tD0
tD1
tD2
Rise time
OUTn (see Figure 4)
10
5
30
ns
SOUT (see Figure 5)
12
ns
Fall time
OUTn (see Figure 4)
10
8
30
ns
SCLK↑ to SOUT↑↓
20
ns
LAT↑ or BLANK↑↓ to OUT0/OUT7/OUT8/OUT15 on/off
LAT↑ or BLANK↑↓ to OUT1/OUT6/OUT9/OUT14 on/off
18
38
36
ns
69
ns
Propagation delay time
Output on-time error(1)
LAT↑ or BLANK↑↓ to OUT2/OUT5/OUT10/OUT13
on/off
tD3
58
78
102
135
15
ns
ns
ns
LAT↑ or BLANK↑↓ to OUT3/OUT4/OUT11/OUT12
on/off
tD4
On/off latch data = all '1', 30 ns BLANK low level
one-shot pulse input
tON_ERR
–15
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low level one-shot pulse width (TWL2).
tOUT_ON indicates the actual on-time of the constant-current output.
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
SIN
LSB
MSB
16-Bit Shift Register
(1 Bit x 16 Channels)
SOUT
SCLK
0
15
¼
MSB
LSB
LAT
Output On/Off Data Latch
(1 Bit x 16 Channels)
0
15
¼
BLANK
16-Channel Constant-Current Sink Driver
with 4-Channel Grouped Delay
IREF
GND
GND
¼
OUT0 OUT1
OUT14 OUT15
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DEVICE INFORMATION
SSOP-24/QSOP-24
DBQ PACKAGE
(TOP VIEW)
QFN-24
RGE PACKAGE
(TOP VIEW)
GND
SIN
1
2
3
4
5
6
7
8
9
24 VCC
23 IREF
SCLK
LAT
22 SOUT
1
2
3
4
5
6
18 BLANK
21
20
19
18
17
16
BLANK
OUT15
OUT14
OUT13
OUT12
OUT11
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
17 OUT15
16 OUT14
15 OUT13
14 OUT12
13 OUT11
OUT0
OUT1
OUT2
OUT3
OUT4
Thermal Pad
(Bottom Side)
OUT5 10
OUT6 11
OUT7 12
15 OUT10
14 OUT9
13 OUT8
NOTE: Thermal pad is not connected to GND internally. The
thermal pad must be connected to GND via the PCB pattern.
6
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SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
TERMINAL FUNCTIONS
TERMINAL
NAME
SIN
DBQ
RGE
I/O
DESCRIPTION
Serial data input for driver on/off control; Schmitt buffer input. When SIN is high, data '1' are
written into the LSB of the 16-bit shift register at the SCLK rising edge.
2
23
I
Serial data shift clock; Schmitt buffer input. All data in the 16-bit shift register are shifted toward
the MSB by 1-bit synchronization of SCLK.
SCLK
3
24
I
Level triggered latch; Schmitt buffer input. The data in the 16-bit shift register continue to transfer
to the output on/off data latch while LAT is high. Therefore, if the data in the 16-bit shift register
are changed when LAT is high, the data in the data latch are also changed. The data in the data
latch are held when LAT is low. This pin is internally pulled down to GND with a 500 kΩ (typ)
resistor.
LAT
4
1
I
Blank, all outputs; Schmitt buffer input. When BLANK is high, all constant-current outputs
(OUT0–OUT15) are forced off. When BLANK is low, all constant-current outputs are controlled by
the data in the output on/off data latch. This pin is internally pulled up to VCC with a 500 kΩ (typ)
resistor.
BLANK
21
18
I
Constant-current value setting, OUT0–OUT15 sink constant-current is set to desired value by
connection to an external resistor between IREF and GND.
IREF
23
22
5
20
19
2
I/O
O
Serial data output. This output is connected to the MSB of the 16-bit shift register. SOUT data
changes at the rising edge of SCLK.
SOUT
OUT0
Constant-current output. Each output can be tied together with others to increase the
constant-current. Different voltages can be applied to each output.
O
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
VCC
6
3
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Power-supply voltage
Power ground
7
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
24
1
7
8
9
10
11
12
13
14
15
16
17
21
22
GND
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
OUTPUT
GND
GND
Figure 1. SIN, SCLK, LAT, BLANK
Figure 2. SOUT
OUTn
GND
Figure 3. OUT0 Through OUT15
TEST CIRCUITS
RL
CL
VCC
GND
VCC
VCC
IREF
OUTn
VLED
(1)
SOUT
GND
VCC
RIREF
(1)
CL
(1) CL includes measurement probe and jig capacitance.
(1) CL includes measurement probe and jig capacitance.
Figure 4. Rise Time and Fall Time Test Circuit for
OUTn
Figure 5. Rise Time and Fall Time Test Circuit for
SOUT
VCC
OUT0
VCC
IREF
OUTn
RIREF
GND OUT15
VOUTn
VOUTfix
Figure 6. Constant-Current Test Circuit for OUTn
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SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
TIMING DIAGRAMS
TWH0, TWL0, TWH1, TWH2, TWL2
:
VCC
INPUT(1) 50%
GND
TWH
TWL
TSU0, TSU1, TH0, TH1
:
VCC
CLOCK
INPUT(1)
50%
GND
TSU
TH
VCC
DATA/CONTROL
INPUT(1)
50%
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 7. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4
:
VCC
INPUT(1)
50%
GND
tD
VOH or VOUTn
90%
50%
10%
OUTPUT
VOL or VOUTn
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
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DATA
0A
DATA
15B
DATA
14B
DATA DATA
13B
12B
DATA
11B
DATA
3B
DATA DATA
2B 1B
DATA
0B
DATA
15C
DATA
14C
DATA DATA DATA
13C 12C 11C
DATA
10C
SIN
SCLK
LAT
TH0
TH1
TSU0
TWH0
TSU1
1
2
3
4
5
1
2
3
TWL0
4
5
6
13
14
15
16
TWH1
Shift Register
LSB Data (Internal)
DATA
0A
DATA DATA
15B
14B
DATA DATA
13B
12B
DATA DATA
3B
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA DATA
13C 12C
DATA
11C
Shift Register
LSB+1 Data (Internal)
DATA
1A
DATA DATA
0A
15B
DATA DATA
14B
13B
DATA DATA
4B
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA DATA
14C 13C
DATA
12C
Shift Register
MSB-1 Data (Internal)
DATA
14A
DATA DATA
13A
12A
DATA DATA
11A
10A
DATA DATA
2A
1A
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA DATA
11B 10B
DATA
9B
Shift Register
MSB Data (Internal)
DATA
15A
DATA DATA
14A
13A
DATA DATA
11A
DATA DATA
3A
2A
DATA
1A
DATA
15B
DATA
14B
DATA
13B
DATA DATA
12B 11B
DATA
10B
12A
Output On/Off Control
Data Latch (Internal)
Previous On/Off Control Data
Latest On/Off Control Data
DATA
15A
DATA DATA
14A 13A
DATA
12A
DATA DATA
2A 1A
DATA
0A
DATA
15B
DATA
14B
DATA
13B
DATA DATA
12B 11B
DATA
10B
SOUT
BLANK
OFF
tWH2
tD0
tR0/tF0
tWL2
tD1
tD1
OFF
OUT0/7/8/15(1)
ON
ON
tOUTON
OFF
tD2
tD2
OFF
OUT1/6/9/14(1)
ON
ON
tD3
tD3
OFF
OFF
OUT2/5/10/13(1)
ON
ON
ON
tF1
tD4
tD4
OFF
OFF
OUT3/4/11/12(1)
ON
tR1
(1) Output on/off data = FFFFh.
(2) tON_ERR = tOUTON – TWL2
.
Figure 9. Timing Diagram
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SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR
vs OUTPUT CURRENT
OUTPUT CURRENT vs
OUTPUT VOLTAGE
100 k
10 k
1 k
50
45
40
35
30
25
20
15
10
5
TA = +25°C
IO = 40 mA
IO = 45 mA
IO = 35 mA
IO = 30 mA
25245
10098
IO = 20 mA
5049
3366
IO = 10 mA
IO = 5 mA
2020
2524
IO = 2 mA
1262
1122
1683
1443
1010
50
0
0
0.5
1
1.5
2
2.5
3
0
10
20
30
40
Output Voltage (V)
Output Current (mA)
Figure 10.
Figure 11.
OUTPUT CURRENT vs
OUTPUT VOLTAGE
ΔIOLC vs AMBIENT TEMPERATURE
40
39
38
37
36
35
34
33
32
31
30
4
3
2
1
0
IO = 35 mA
IO = 35 mA
-1
TA = -40°C
TA = +25°C
TA = +85°C
-2
-3
-4
VCC = 3.3 V
VCC = 5 V
0
0.5
1
1.5
2
2.5
3
-40
-20
0
20
40
60
80
100
Output Voltage (V)
Ambient Temperature (°C)
Figure 12.
Figure 13.
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
ΔIOLC vs OUTPUT CURRENT
4
3
TA = +25°C
CH1-BLANK
(30 ns)
CH1 (2 V/div)
2
CH2-OUT0
(BLANK = 30 ns)
1
CH2 (2 V/div)
CH3 (2 V/div)
0
-1
-2
-3
-4
IOLC = 35 mA, TA = +25°C
RL = 130 W, CL = 15 pF
VCC = 3.3 V, VLED = 5.5 V
VCC = 3.3 V
VCC = 5 V
CH3-OUT3
(BLANK = 30 ns)
Time (20 ns/div)
0
10
20
30
40
50
Output Current (mA)
Figure 14.
Figure 15.
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DETAILED DESCRIPTION
SETTING FOR THE CONSTANT SINK CURRENT VALUE
The constant-current values are determined by an external resistor (RIREF) placed between IREF and GND. The
resistor (RIREF) value is calculated by Equation 1.
VIREF (V)
´ 41.9
RIREF (kW) =
IOLC (mA)
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.205 V)
(1)
IOLC must be set in the range of 2 mA to 35 mA when VCC is less than 3.6 V. Also, when VCC is equal to 3.6 V or
greater, IOLC must be set in the range of 2 mA to 45 mA. The constant sink current characteristic for the external
resistor value is shown in Figure 10. Table 1 describes the constant-current output versus external resistor value.
Table 1. Constant-Current Output versus External Resistor Value
IOLC (mA, Typical)
RIREF (kΩ)
1.12
45 (VCC > 3.6 V only)
40 (VCC > 3.6 V only)
1.26
35
30
25
20
15
10
5
1.44
1.68
2.02
2.52
3.37
5.05
10.1
2
25.2
CONSTANT-CURRENT DRIVER ON/OFF CONTROL
When BLANK is low, the corresponding output is turned on if the data in the on/off control data latch are '1' and
remains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in Table 2.
Table 2. On/Off Control Data Truth Table
CONSTANT-CURRENT OUTPUT
OUTPUT ON/OFF DATA
STATUS
0
1
Off
On
When the IC is initially powered on, the data in the 16-bit shift register and output on/off data latch are not set to
the respective default value. Therefore, the output on/off data must be written to the data latch before turning the
constant-current output on. BLANK should be at a high level when powered on because the constant-current
may be turned on as a result of random data in the output on/off data latch.
The output on/off data corresponding to any unconnected OUTn outputs should be set to '0' before turning on the
remaining outputs. Otherwise, the supply current (ICC) increases while the LEDs are on.
12
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TLC59282
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SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
REGISTER CONFIGURATION
The TLC59282 has a 16-bit shift register and an output on/off data latch. Both the shift register and data latch
are 16 bits long and are used to turn the constant-current outputs on and off. Figure 16 shows the shift register
and data latch configuration. The data at the SIN pin are shifted in to the LSB of the 16-bit shift register at the
rising edge of the SCLK pin; SOUT data change at the rising edge of SCLK.
The output on/off data in the 16-bit shift register continue to transfer to the output on/off data latch while LAT is
high. Therefore, if the data in the 16-bit shift register are changed when LAT is high, the data in the data latch
are also changed. The data in the data latch are held when LAT is low. When the IC initially powers on, the data
in the output on/off shift register and latch are not set to the default values; on/off control data must be written to
the on/off control data latch before turning the constant-current output on. BLANK should be high when the IC is
powered on because the constant-current may be turned on at that time as a result of random values in the
on/off data latch. All constant-current outputs are forced off when BLANK is high. The OUTn on/off are controlled
by the data in the output on/off data latch. The timing diagram and truth table for writing data are shown in
Figure 17 and Table 3.
16-Bit Shift Register (1 Bit ´ 16 Channels)
MSB
15
LSB
0
14
13
12
11
4
3
2
1
SIN
On/Off Data On/Off Data On/Off Data On/Off Data
On/Off Data On/Off Data
On/Off Data On/Off Data
¼
¼
for
for
for
for
for
for
for
for
SOUT
OUT15
OUT14
OUT13
OUT12
OUT3
OUT2
OUT1
OUT0
SCLK
MSB
15
LSB
0
14
13
12
11
4
3
2
1
On/Off Data On/Off Data On/Off Data On/Off Data
for for for for
OUT15 OUT14 OUT13 OUT12
On/Off Data On/Off Data
for for
OUT3 OUT2
On/Off Data On/Off Data
¼
for
OUT1
for
LAT
OUT0
Output On/Off Data Latch (1 Bit ´ 16 Channels)
16 Bits
To Constant-Current Driver Control Block
Figure 16. 16-Bit Shift Register and Output On/Off Data Latch Configuration
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
SIN
D2
D1
D0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
LAT
BLANK
OUT0
OUT1
OUT2
OUT3
D0
D1
OFF
ON
OFF
ON
OFF
ON
D2
D3
OFF
ON
OFF
ON
OUT15
SOUT
D15
Don’t Care
D15
Figure 17. Operation Timing Diagram
Table 3. Truth Table in Operation
SCLK
LAT
High
Low
High
—
BLANK
Low
SIN
OUT0…OUT7…OUT15
Dn…Dn – 7…Dn – 15
No change
SOUT
Dn – 15
Dn – 14
Dn – 13
Dn – 13
Dn – 13
↑
↑
↑
↓
↓
Dn
Low
Dn + 1
Dn + 2
Dn + 3
Dn + 3
Low
Dn + 2…Dn – 5…Dn – 13
Dn + 2…Dn – 5…Dn – 13
Off
Low
—
High
NOISE REDUCTION
Large surge currents may flow through the IC and the board if all 16 outputs turn on or off simultaneously. These
large current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits.
The TLC59282 independently turns on or off the outputs for each color group with a 20 ns (typ) delay time; see
Figure 9. The output current sinks are grouped into four groups. The first group that is turned on/off are
OUT0/7/8/15; the second group that is turned on/off are OUT1/6/9/14; the third group that is turned on/off are
OUT2/5/10/13; and the fourth group is OUT3/4/11/12. Both turn-on and turn-off are delayed. However, the state
of each output is controlled by the data in the output on-off data latch and BLANK level.
14
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TLC59282
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SBVS152C –DECEMBER 2010–REVISED OCTOBER 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2011) to Revision C
Page
•
Added Low Saturation Voltage Features bullet .................................................................................................................... 1
Changes from Revision A (December 2010) to Revision B
Page
•
•
•
•
•
•
•
Changed Constant-Current Accuracy Features bullet .......................................................................................................... 1
Added RGE package information to Package/Ordering Information table ........................................................................... 2
Added RGE package to Thermal Information table .............................................................................................................. 2
Changed Input current parameter test conditions in Electrical Characteristics table ........................................................... 4
Added RGE pin out and footnote to Device Information section .......................................................................................... 6
Added RGE information to Terminal Functions table ........................................................................................................... 7
Deleted Figure 11, POWER DISSIPATION RATE vs FREE-AIR TEMPERATURE .......................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TLC59282DBQ
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SSOP
SSOP
VQFN
VQFN
DBQ
24
24
24
24
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TLC59282
TLC59282DBQR
TLC59282RGER
TLC59282RGET
ACTIVE
ACTIVE
ACTIVE
DBQ
RGE
RGE
2500
3000
250
Green (RoHS
& no Sb/Br)
-40 to 85
TLC59282
Green (RoHS
& no Sb/Br)
-40 to 85
TLC
59282
Green (RoHS
& no Sb/Br)
-40 to 85
TLC
59282
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC59282RGER
TLC59282RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC59282RGER
TLC59282RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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相关型号：
TLC59282RGET
16-channel constant current LED driver with 4-channel Grouped delay 24-VQFN -40 to 85
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