TLC59283 [TI]
16-Channel, Constant-Current LED Driver with Pre-Charge FET; 16通道恒流LED驱动器，预充电FET
| 型号： | TLC59283 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Channel, Constant-Current LED Driver with Pre-Charge FET |
| 文件： | 总25页 (文件大小：777K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC59283
www.ti.com
SBVS199A –JUNE 2012–REVISED JUNE 2012
16-Channel, Constant-Current LED Driver with Pre-Charge FET
Check for Samples: TLC59283
1
FEATURES
2
•
16-Channel, Constant-Current Sink Output
with On and Off Control
APPLICATIONS
•
•
Video Displays
•
Constant-Current Sink Capability:
35 mA (VCC ≤ 3.6 V), 45 mA (VCC > 3.6 V)
Message Boards
•
•
•
LED Power-Supply Voltage: Up to 10 V
VCC = 3 V to 5.5 V
DESCRIPTION
The TLC59283 is a 16-channel, constant-current sink
light-emitting diode (LED) driver. Each channel can
be individually controlled with
communications protocol that is compatible with 3.3-V
or 5-V CMOS logic levels, depending on the
operating VCC. When the serial data buffer is loaded,
a LAT rising edge transfers the data to the OUTn
outputs. The BLANK pin can be used to turn off all
OUTn outputs during power-on and output data
latching to prevent unwanted image displays during
these times. The constant-current value of all 16
channels is set by a single external resistor.
Constant-Current Accuracy:
a simple serial
–
Channel-to-Channel:
±1.4% (typ), ±3% (max)
–
Device-to-Device: ±2% (typ), ±4% (max)
•
•
•
•
•
•
CMOS Logic Level I/O
Data Transfer Rate: 35 MHz
BLANK Pulse Width: 50 ns
Pre-Charge FET for Ghosting Reduction
Grouped Switching Delay for Noise Reduction
Operating Temperature: –40°C to +85°C
Each constant-current output has a pre-charge field-
effect transistor (FET) that can reduce ghosting on
the multiplexing (dynamic) drive LED display. Multiple
TLC59283s can be cascaded together to control
additional LEDs from the same processor.
VLED
+
SW
COMn
COMn
COM1
COM0
VLED
SW
COM1
VLED
SW
COM0
¼
¼
¼
OUT0
SIN
OUT15
SOUT
OUT0
SIN
OUT15
SOUT
DATA
SCLK
SCLK
LAT
SCLK
LAT
LAT
Controller
BLANK
VCC
VCC
BLANK
BLANK
VCC
GND
VCC
GND
IREF
IREF
Device 1
Device n
RIREF
RIREF
3
Typical Application Circuit (Multiple Daisy-Chained TLC59283s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TLC59283
SBVS199A –JUNE 2012–REVISED JUNE 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
TLC59283DBQR
TLC59283DBQ
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 2500
Tube, 50
TLC59283
SSOP-24 and QSOP-24
TLC59283RGER
TLC59283RGE
Tape and Reel, 3000
Tape and Reel, 250
TLC59283
QFN-24
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
MIN
MAX
VCC
VIN
Supply
–0.3
+6
V
V
Input range, SIN, SCLK, LAT, BLANK, IREF
Output range, SOUT
–0.3 VCC + 0.3
–0.3 VCC + 0.3
Voltage
V
VOUT
Output range, OUT0 to OUT15
Output (dc), OUT0 to OUT15
Operating junction
–0.3
+11
+50
V
Current
IOUT
mA
°C
°C
V
TJ(MAX)
Tstg
+150
+150
2000
2000
Temperature
Storage range
–55
Human body model (HBM)
Charged device model (CDM)
Electrostatic discharge ratings
ESD
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
TLC59283
THERMAL METRIC(1)
DBQ
24 PINS
91.5
RGE
24 PINS
42.9
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
55.2
55.3
44.9
21.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
16.8
1.9
ψJB
44.5
21.8
θJCbot
N/A
8.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SBVS199A –JUNE 2012–REVISED JUNE 2012
RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C, unless otherwise noted.
TLC59283
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
DC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC
VO
Supply voltage
3
5.5
V
V
Voltage applied to output
OUT0 to OUT15
10
VCC
VIH
VIL
IOH
IOL
High
SIN, SCLK, LAT, BLANK
SIN, SCLK, LAT, BLANK
SOUT
0.7 × VCC
GND
V
Input voltage
Low
High
Low
0.3 × VCC
–2
V
mA
mA
mA
mA
°C
°C
Output current
SOUT
2
OUT0 to OUT15, 3 V ≤ VCC ≤ 3.6 V
OUT0 to OUT15, 3.6 V < VCC ≤ 5.5 V
2
2
35
IOLC
Constant output sink current
45
TA
TJ
Operating free-air
Operating junction
–40
–40
+85
Temperature range
+125
AC CHARACTERISTICS (VCC = 3 V to 5.5 V)
fCLK (SCLK)
tWH0
tWL0
tWH1
tWH2
tWL2
tSU0
Data shift clock frequency
SCLK
35
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
10
10
20
100
50
4
SCLK
Pulse duration
LAT
BLANK
BLANK
SIN↑↓ – SCLK↑
LAT↓ – SCLK↑
SIN↑↓ – SCLK↑
LAT↓ – SCLK↑
Setup time
Hold time
tSU1
10
4
tH0
tH1
10
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ELECTRICAL CHARACTERISTICS
All minimum and maximum specifications are at TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted.
Typical specifications are at TA = +25°C and VCC = 3.3 V.
TLC59283
PARAMETER
High
Low
TEST CONDITIONS
MIN
TYP
MAX
VCC
0.4
UNIT
V
VOH
VOL
IOH = –2 mA at SOUT
IOL = 2 mA at SOUT
IO = –10 µA
VCC – 0.4
Output voltage
V
VPCHG
VIREF
IIN
Pre-charged voltage
Reference voltage output
Input current
VCC – 2.0 VCC – 1.4 VCC – 0.8
1.208
V
RIREF = 1.5 kΩ, TA = +25°C
V
VIN = VCC or GND at SIN and SCLK
–1
1
2
μA
mA
ICC0
SIN, SCLK, LAT = GND, BLANK = VOUTn = VCC, RIREF = open
1
3
SIN, SCLK, LAT = GND, BLANK = VOUTn = VCC
RIREF = 3 kΩ (IOUT = 17.6 mA target)
,
ICC1
ICC2
ICC3
IOLC
4
8
mA
mA
mA
mA
Supply current (VCC
)
All OUTn = ON, SIN, SCLK, LAT, BLANK = GND,
VOUTn = 0.8 V, RIREF = 3 kΩ
6
7
All OUTn = ON, SIN, SCLK, LAT, BLANK = GND,
VOUTn = 0.8 V, RIREF = 1.5 kΩ (IOUT = 35.3 mA target)
11
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
TA = +25°C (see Figure 8)
Constant output current
Output leakage current
32.9
35.3
37.7
TJ = +25°C
0.1
0.2
0.5
μA
μA
μA
All OUTn = OFF, VOUTn = VOUTfix = 10 V,
BLANK = VCC, RIREF = 1.5 kΩ (see Figure 8)
IOLKG0
TJ = +85°C
TJ = +125°C
0.07
±1.4
Channel-to-
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
TA = +25°C (see Figure 8)
ΔIOLC0
ΔIOLC1
ΔIOLC2
ΔIOLC3
±3
±4
±1
±1
%
%
channel(1)
Constant-
current error
Device-to-
device(2)
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
TA = +25°C (see Figure 8)
±2
±0.05
±0.5
All OUTn = ON, VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ,
Line regulation(3)
Load regulation(4)
%/V
%/V
VCC = 3 V to 5.5 V
All OUTn = ON, VOUTn = 0.8 V to 3 V, VOUTfix = 0.8 V,
RIREF = 1.5 kΩ
RPUP
Pull-up
BLANK
LAT
250
250
500
500
750
750
kΩ
kΩ
Resistor
RPDWN
Pull-down
VCC = 5.0 V, VOUTn = 0 V, OUT0 to OUT15,
BLANK = VCC, TA = +25°C
RPCHG
Pre-charge FET on-resistance
3
6
kΩ
(1) The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
IOUTn
D (%) =
- 1 ´ 100
(IOUT0 + IOUT1 + ... + IOUT14 + IOUT15
)
16
(2) The deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15
)
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
1.208 V
IOUT(IDEAL) = 43.8 ´
RIREF
(3) Line regulation is calculated by this equation:
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3 V)
D (%/V) =
100
´
(IOUTn at VCC = 3 V)
5.5 V - 3 V
(4) Load regulation is calculated by the equation:
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
D (%/V) =
100
3 V - 1 V
´
(IOUTn at VOUTn = 1 V)
4
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SBVS199A –JUNE 2012–REVISED JUNE 2012
SWITCHING CHARACTERISTICS
All minimum and maximum specifications are at TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 110 Ω,
RIREF = 1.5 kΩ, and VLED = 5.0 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
TLC59283
PARAMETER
TEST CONDITIONS
SOUT (see Figure 7)
MIN
TYP
3
MAX
UNIT
ns
tR0
tR1
tF0
tF1
tD0
tD1
10
Rise time
OUTn (see Figure 6)
44
3
ns
SOUT (see Figure 7)
10
ns
Fall time
OUTn (see Figure 6)
44
11
60
ns
SCLK↑ to SOUT↑↓
20
ns
LAT↑ or BLANK↑↓ to OUT0 on or off, TA = +25°C
100
ns
Propagation delay time
Output on-time error(1)
Grouped OUTn on or off to next group on or off,
TA = +25°C
tD2
2
ns
ns
Output on or off latch data = all '1', 50-ns BLANK GND
level pulse, VCC = 3.3 V, TA = +25°C
tON_ERR
–45
45
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low level one-shot pulse width (tWL2).
tOUT_ON indicates the actual on-time of the constant-current output.
PIN CONFIGURATIONS
DBQ PACKAGE
SSOP-24 AND QSOP-24
RGE PACKAGE
QFN-24
(TOP VIEW)
(TOP VIEW)
GND
SIN
1
2
3
4
5
6
7
8
9
24 VCC
23 IREF
SCLK
LAT
22 SOUT
21 BLANK
20 OUT15
19 OUT14
18 OUT13
17 OUT12
16 OUT11
15 OUT10
14 OUT9
13 OUT8
1
2
3
4
5
6
18 BLANK
17 OUT15
16 OUT14
15 OUT13
14 OUT12
13 OUT11
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT0
OUT1
OUT2
OUT3
OUT4
Thermal Pad
(Bottom Side)
OUT5 10
OUT6 11
OUT7 12
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the printed circuit board (PCB)
pattern.
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PIN DESCRIPTIONS
PIN
NUMBER
NAME
DBQ
RGE
I/O
DESCRIPTION
All outputs empty (blank); Schmitt buffer input. When BLANK is high, all constant-current outputs
(OUT0 to OUT15) are forced off and all pre-charge FETs are turned on. When BLANK is low, all
constant-current outputs are controlled by the data in the output on or off data latch and all pre-
charge FETs are turned off. This pin is internally pulled up to VCC with a 500-kΩ (typ) resistor.
BLANK
21
18
I
GND
IREF
1
22
20
—
Power ground
Constant-current value setting, the OUT0 to OUT15 sink constant-current outputs are set to the
desired values by connecting an external resistor between IREF and GND.
23
I/O
Level-triggered latch; Schmitt buffer input. The data in the 16-bit shift register continue to transfer
to the output on or off data latch while LAT is high. Therefore, if the data in the 16-bit shift register
are changed when LAT is high, the data in the data latch are also changed. The data in the data
latch are held when LAT is low. This pin is internally pulled down to GND with a 500-kΩ (typ)
resistor.
LAT
4
5
1
2
I
Constant-current output. Each output can be tied together with others to increase the constant-
current. Different voltages can be applied to each output.
OUT0
O
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
6
3
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
7
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
7
8
9
10
11
12
13
14
15
16
17
Serial data shift clock; Schmitt buffer input.
All data in the 16-bit shift register are shifted toward the MSB by a 1-bit SCLK synchronization.
SCLK
3
24
I
Serial data input for driver on or off control; Schmitt buffer input.
When SIN is high, the LSB is set to '1' for only one SCLK input rising edge. If two SCLK rising
edges are input while SIN is high, then the 16-bit shift register LSB and LSB+1 are set to '1'.
When SIN is low, the LSB is set to '0' at the SCLK input rising edge.
SIN
2
23
I
Serial data output. This output is connected to the 16-bit shift register MSB. SOUT data changes
at the SCLK rising edge.
SOUT
VCC
22
24
19
21
O
—
Power-supply voltage
6
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SBVS199A –JUNE 2012–REVISED JUNE 2012
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
SIN
LSB
MSB
16-Bit Shift Register
(1 Bit x 16 Channels)
SOUT
SCLK
0
15
¼
MSB
LSB
LAT
BLANK
IREF
Output On or Off Data Latch
(1 Bit x 16 Channels)
0
15
¼
ALLOFF
16-Channel Constant-Current Sink Driver
with Grouped Switching Delay
VCC - 1.4 V
(typ)
Timing
Control
GND
GND
Pre-Charge
FETs
¼
OUT0
OUT1
OUT14
OUT15
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PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
SOUT
GND
GND
Figure 1. SIN and SCLK
Figure 4. SOUT
VCC
VCC
LAT
(1)
OUTn
GND
GND
Figure 2. LAT
(1) n = 0 to 15.
Figure 5. OUT0 Through OUT15
VCC
BLANK
GND
Figure 3. BLANK
8
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SBVS199A –JUNE 2012–REVISED JUNE 2012
TEST CIRCUITS
RL
VCC
GND
VCC
IREF
OUTn
VLED
CL
RIREF
Figure 6. OUTn Rise and Fall Time Test Circuit
VCC
SOUT
VCC
CL
GND
Figure 7. SOUT Rise and Fall Time Test Circuit
VCC
OUT0
VCC
IREF
OUTn
RIREF
GND OUT15
VOUTn
VOUTfix
Figure 8. OUTn Constant-Current Test Circuit
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TIMING DIAGRAMS
tWH0, tWL0, tWH1, tWH2, tWL2
:
VCC
Input(1)
50%
GND
tWH
tWL
tSU0, tSU1, tH0, tH1
:
VCC
SCLK(1)
50%
GND
VCC
tSU
tH
Data and Control
Clock(1)
50%
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Input Timing Diagram
(1)
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tON_ERR
:
VCC
Input(2)
50%
GND
tWL2
tD
VOH or VOUTn
90%
Output
50%
10%
VOL or VOUTn
tOUT_ON
tR or tF
(1) tON_ERR is calculated by tOUTON – tWL2
.
(2) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 10. Output Timing Diagram
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SBVS199A –JUNE 2012–REVISED JUNE 2012
DATA
0A
DATA
15B
DATA DATA DATA DATA
14B 12B 11B
13B
DATA
3B
DATA DATA
2B 1B
DATA
0B
DATA
15C
DATA
14C
DATA DATA DATA
13C 12C 11C
DATA
10C
SIN
SCLK
LAT
tH0
tH1
tSU0
tWH0
tSU1
1
2
3
4
5
1
2
3
4
5
6
13
14
15
16
tWH1
tWL0
Shift Register
LSB Data (Internal)
DATA
0A
DATA DATA
15B
14B
DATA DATA
13B
12B
DATA DATA
3B
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA DATA DATA
13C 12C 11C
Shift Register
LSB+1 Data (Internal)
DATA
1A
DATA DATA
0A
15B
DATA DATA
14B
13B
DATA DATA
4B
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA DATA DATA
14C 13C 12C
Shift Register
MSB-1 Data (Internal)
DATA
14A
DATA DATA
13A
12A
DATA DATA
11A
10A
DATA DATA
2A
1A
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA DATA DATA
11B 10B 9B
Shift Register
MSB Data (Internal)
DATA
15A
DATA DATA
14A
13A
DATA DATA
11A
DATA DATA
3A
2A
DATA
1A
DATA
15B
DATA
14B
DATA
13B
DATA DATA DATA
12B 11B 10B
12A
Output On or Off Control
Data Latch (Internal)(1)
Previous On or Off Control Data
Latest On or Off Control Data
DATA
15A
DATA DATA
14A 13A
DATA
12A
DATA DATA
2A 1A
DATA
0A
DATA
15B
DATA
14B
DATA
13B
DATA DATA DATA
10B
SOUT
12B
11B
tD0
tR0/tF0
tWH2
BLANK
tWL2
tD1
tD1
OFF
OFF
ON
ON
OUT0
ON
tOUTON
tD2
OFF
tD2
OFF
OUT1, 15
ON
tF1
tR1
OFF
OFF
ON
OUT7, 9
ON
tD2
tD2
OFF
ON
OFF
ON
OUT8
ON
ON
ON
Pre-Charge FET
OFF
OFF
(1) Output on or off data = FFFFh.
(2) tON_ERR = tOUTON – tWL2
.
Figure 11. Data Write and Output On or Off Timing Diagram
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TYPICAL CHARACTERISTICS
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
REFERENCE RESISTOR
vs OUTPUT CURRENT
OUTPUT CURRENT vs
OUTPUT VOLTAGE (VCC = 3.3 V)
50
45
40
35
30
25
20
15
10
5
100
10
1
IO = 35 mA
IO = 30 mA
IO = 20 mA
IO = 10 mA
IO = 5 mA
IO = 2 mA
VCC = 3.3 V
VOUTn = 0.8 V
TA = +25°C
26.5
10.6
5.29
3.53
2.65
2.12
1.76
1.51
1.32
1.18
50
0
0
0.5
1
1.5
2
2.5
3
0
10
20 30
Output Current (mA)
40
Output Voltage (V)
G000
G020
Figure 12.
Figure 13.
OUTPUT CURRENT vs
OUTPUT VOLTAGE (VCC = 5.0 V)
OUTPUT CURRENT vs OUTPUT VOLTAGE
(VCC = 3.3 V, Magnified)
55
39
38
37
36
35
34
33
32
31
VCC = 5.0 V,VOUTn = 0.8 V,TA = +25°C
VCC = 3.3 V
VOUTn = 0.8 V
IO = 35 mA
50
45
40
35
30
25
20
15
10
5
IO = 45 mA
IO = 40 mA
IO = 35 mA
IO = 30 mA
IO = 20 mA
IO = 10 mA
TA = −40°C
TA = +25°C
TA = +85°C
IO = 5 mA
IO = 2 mA
2.5
0
0
0.5
1
1.5
2
3
0
0.5
Output Voltage (V)
1
1.5
Output Voltage (V)
G001
G004
Figure 14.
Figure 15.
OUTPUT CURRENT vs OUTPUT VOLTAGE
(VCC = 5.0 V, Magnified)
ΔIOLC vs AMBIENT TEMPERATURE
39
38
37
36
35
34
33
32
31
3
2
VOUTn = 0.8 V
IO = 20 mA
VCC = 5.0 V
VOUTn = 0.8 V
IO = 35 mA
1
0
−1
−2
−3
TA = −40°C
TA = +25°C
TA = +85°C
VCC = 3.3 V
VCC = 5.0 V
0
0.5
Output Voltage (V)
1
1.5
−40
−20
0
20
40
60
80 100
G005
G006
Ambient Temperature (°C)
Figure 16.
Figure 17.
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SBVS199A –JUNE 2012–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VCC = 3.3 V, unless otherwise noted.
SUPPLY CURRENT vs OUTPUT CURRENT
SUPPLY CURRENT vs AMBIENT TEMPERATURE
12
12
VCC = 5.0 V
VCC = 3.3 V
VCC = 3.3 V
VCC = 5.0 V
11
10
9
11
10
9
8
8
7
7
SIN = 17.5 MHz
SCLK = 35 MHz
All Outputs On
IO = 35 mA
SIN = 17.5 MHz
SCLK = 35 MHz
All Outputs On
TA = +25°C
6
6
5
5
−40
4
−20
0
20
40
60
80
100
0
10
20 30
Output Current (mA)
40
50
G008
Ambient Temperature (°C)
G018
Figure 18.
Figure 19.
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1-BLANK
(50 ns)
Channel 1
(5 V/div)
Channel 2
(2 V/div)
CH2-OUT0
(BLANK = 50 ns)
Channel 3
(2 V/div)
IO = 35 mA
TA = +25°C
RL = 110 W
CL = 15 pF
CH3-OUT1
(BLANK = 50 ns)
Channel 4
(2 V/div)
CH4-OUT2
(BLANK = 50 ns)
VCC = 5 V
VLED = 5 V
Time (20 ns/div)
G021
Figure 20.
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DETAILED DESCRIPTION
CONSTANT SINK CURRENT VALUE SETTING
The constant-current values are determined by an external resistor (RIREF) placed between IREF and GND. The
resistor (RIREF) value is calculated by Equation 1.
VIREF (V)
RIREF (kW) =
´ 43.8
IOLC (mA)
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.208 V)
(1)
IOLC must be set in the range of 2 mA to 35 mA when VCC is less than 3.6 V. Also, when VCC is equal to 3.6 V or
greater, IOLC must be set in the range of 2 mA to 45 mA. The constant sink current characteristic for the external
resistor value is illustrated in Figure 12. Table 1 describes the constant-current output versus external resistor
value.
Table 1. Constant-Current Output versus External Resistor Value
IOLC (mA)
RIREF (kΩ, Typical)
45 (VCC > 3.6 V only)
1.18
1.32
1.51
1.76
2.12
2.65
3.53
5.29
10.6
26.5
40 (VCC > 3.6 V only)
35
30
25
20
15
10
5
2
CONSTANT-CURRENT DRIVER ON OR OFF CONTROL
When BLANK is low, the corresponding output is turned on if the data in the on or off control data latch are '1'
and remains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in
Table 2.
Table 2. Output On or Off Control Data Truth Table
CONSTANT-CURRENT OUTPUT
OUTPUT ON OR OFF DATA
STATUS
0
1
Off
On
When the device is initially powered on, the data in the 16-bit shift register and output on or off data latch are not
set to default values. Therefore, the output on or off data must be written to the data latch before turning the
constant-current output on. BLANK should be high when powered on because the constant-current may be
turned on as a result of random data in the output on or off data latch.
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REGISTER CONFIGURATION
The TLC59283 has a 16-bit shift register and an output on or off data latch. Both the shift register and data latch
are 16 bits long and are used to turn the constant-current outputs on and off. Figure 21 shows the shift register
and data latch configuration. The data at the SIN pin are shifted into the 16-bit shift register LSB at the rising
edge of the SCLK pin; SOUT data change at the SCLK rising edge.
16-Bit Shift Register (1 Bit ´ 16 Channels)
MSB
15
LSB
0
14
13
12
11
4
3
2
1
SIN
On or Off
Data for
OUT15
On or Off
Data for
OUT14
On or Off
Data for
OUT13
On or Off
Data for
OUT12
On or Off
Data for
OUT3
On or Off
Data for
OUT2
On or Off
Data for
OUT1
On or Off
Data for
OUT0
¼
SOUT
SCLK
¼
MSB
15
LSB
0
14
13
12
11
4
3
2
1
On or Off
Data for
OUT15
On or Off
Data for
OUT14
On or Off
Data for
OUT13
On or Off
Data for
OUT12
On or Off
Data for
OUT3
On or Off
Data for
OUT2
On or Off
Data for
OUT1
On or Off
Data for
OUT0
¼
LAT
Output On or Off Data Latch (1 Bit ´ 16 Channels)
16 Bits
To Constant-Current Driver Control Block
Figure 21. 16-Bit Shift Register and Output On or Off Data Latch Configuration
The output on or off data in the 16-bit shift register continue to transfer to the output on or off data latch while
LAT is high. Therefore, if the data in the 16-bit shift register are changed when LAT is high, the data in the data
latch are also changed. The data in the data latch are held when LAT is low. When the device initially powers on,
the data in the output on or off shift register and latch are not set to default values; on or off control data must be
written to the on or off control data latch before turning the constant-current output on. All constant-current
outputs are forced off when BLANK is high. The OUTn on or off outputs are controlled by the data in the output
on or off data latch. The writing data truth table and timing diagram are shown in Table 3 and Figure 22,
respectively.
Table 3. Truth Table in Operation
SCLK
LAT
High
Low
High
—
BLANK
Low
SIN
OUT0…OUT7…OUT15
Dn…Dn – 7…Dn – 15
No change
SOUT
Dn – 15
Dn – 14
Dn – 13
Dn – 13
Dn – 13
↑
↑
↑
↓
↓
Dn
Low
Dn + 1
Dn + 2
Dn + 3
Dn + 3
Low
Dn + 2…Dn – 5…Dn – 13
Dn + 2…Dn – 5…Dn – 13
Off
Low
—
High
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
SIN
D2
D1
D0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
LAT
BLANK
OUT0
OUT1
OUT2
OUT3
D0
D1
OFF
ON
OFF
ON
OFF
ON
D2
D3
OFF
ON
OFF
ON
OUT15
SOUT
D15
Don’t Care
D15
Figure 22. Operation Timing Diagram
NOISE REDUCTION
Large surge currents may flow through the device and board if all 16 outputs turn on or off simultaneously. These
large current surges can induce detrimental noise and electromagnetic interference (EMI) into other circuits. The
TLC59283 independently turns on or off the outputs for each group with a 1-ns (typ) delay time; see Figure 11.
The 16 outputs are grouped into nine groups of either one or two outputs: group 1 (OUT0), group 2 (OUT1 and
OUT15), group 3 (OUT2 and OUT14), group 4 (OUT3 and OUT13), group 5 (OUT4 and OUT12), group 6 (OUT5
and OUT11), group 7 (OUT6 and OUT10), group 8 (OUT7 and OUT9), and group 9 (OUT9). Both turn-on and
turn-off times are delayed when BLANK transitions from low to high or high to low. Also when output-on and -off
data are changed at the LAT rising edge while BLANK is low, both turn-on and turn-off times are delayed.
However, the state of each output is controlled by the data in the output on or off data latch and the BLANK
level.
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SBVS199A –JUNE 2012–REVISED JUNE 2012
Internal Pre-Charge FET
The internal pre-charge FET prevents ghosting of multiplexed LED modules. One cause of this phenomenon is
the parasitic capacitance charging current of the constant-current outputs (OUTn) and PCB wiring connected to
OUTn through the LED. One of the mechanisms is shown in Figure 23.
In Figure 23, the constant-current driver turns LED0-0 on at (1) and off at (2). After LED0-0 is turned off, the
OUT0 voltage is pulled up to VCHG by LED0-0. This OUT0 node has some parasitic capacitance (such as the
constant-current driver output capacitance and the board layout capacitance shown as C0-2). After LED0-0 turns
off, SWPMOS0 is turned off, SWNMOS0 is turned on for COM0, and COM0 is pulled down to GND. Because
there is a parasitic capacitance between COM0 and OUT0, the OUT0 voltage is also pulled down to GND.
Afterwards, SWPMOS1 is turned on for the next common line (COM1). When SWPMOS1 turns on, the OUT0
voltage is pulled up from the ground voltage to VLED – VF. The charge current (ICHRG) flows to the parasitic
capacitor (C0) through LED1-0, causing the LED to briefly turn on and creating a ghosting effect of LED1-0.
VLED
(LED Power-Supply)
COM0 is VLED level.
ON
OFF
ON
SW
PMOS0
COM0 is GND level.
SW
PMOS1
SW
NMOS0
LED1-1
LED1-2
OFF
ON
COM1
COM1 is VLED level.
SW
PMOS1
¼
OFF
ON
Parasitic Capacitor
C2
SW
NMOS1
COM1 is GND level.
LED1-0
SW
NMOS1
C0
C1
OFF
High
Low
ON
VLED
ICHRG
BLANK
OUT0
SW
PMOS0
COM0
OFF
VLED
SW
NMOS0
OUT0
Voltage
VCHG
GND
LED0-0
LED0-1
LED0-2
¼
VLED - VF
OUT0
OUT1
OUT2
20 mA
LED0-0
Current
Ordinal
LED Driver
OUT0
ON
OUT1
ON
OUT2
ON
0 mA
20 mA
0 mA
¼
LED1-0
Current
Constant-Current
Output
(1) (2)
(3)
(4)
Ghost phenomenon is observed
when COM1 goes up to VLED.
OUT0 voltage is pulled down to GND side
by the coupling with LED lamp capacitor
between COM0 and OUT0.
Figure 23. LED Ghost-Lighting Phenomenon Mechanism
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The TLC59283 has an internal pre-charge FET to prevent ghosting, as shown in Figure 24. When a small delay
after PWM control for a single common line completes, the FET pulls OUTn up to VCC. The charge current does
not flow to C0 through LED1-0 when SWMOS1 is turned on and the ghosting is eliminated at (3). However,
depending on the LED anode voltage, the number of LEDs in series, the LED forward voltage, and the
TLC59283 VCC supply voltage, there may not be a great enough ghost-canceling effect.
VLED
(LED Power-Supply)
SW
PMOS1
COM0 is VLED level.
LED1-1
LED1-2
ON
SW
PMOS0
COM1
OFF
COM0 is GND level.
¼
ON
SW
NMOS0
Parasitic Capacitor
C2
SW
NMOS1
OFF
LED1-0
COM1 is VLED level.
ON
SW
PMOS1
C0
C1
VLED
OFF
COM1 is GND level.
Disappearing ICHRG
ON
SW
PMOS0
SW
NMOS1
OFF
COM0
High
Low
ON
BLANK
OUT0
SW
NMOS0
LED0-0
LED0-1
LED0-2
OFF
ON
¼
OUT0
OUT1
OUT2
PCHGON
Signal
OFF
Pre-Charge FET
VCC
VCC - 1.4 V (typ)
VLED
OUT0
Voltage
VCHG
VLED - VF
PCHGON
Timing
Control
GND
BLANK
20 mA
0 mA
LED0-0
Current
OUT0
ON
OUT0
ON
OUT0
ON
¼
20 mA
0 mA
LED1-0
Current
Constant-Current
Output
TLC59283
LED Driver
(1) (2)
(3)
(4)
Ghost phenomenon not seen
Figure 24. LED Ghost-Lighting Mechanism by Pre-Charge FET
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLC59283DBQ
TLC59283DBQR
TLC59283RGER
TLC59283RGET
ACTIVE
ACTIVE
SSOP/QSOP
SSOP/QSOP
VQFN
DBQ
DBQ
RGE
RGE
24
24
24
24
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
2500
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
PREVIEW
PREVIEW
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC59283DBQR
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jun-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP/QSOP DBQ 24
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TLC59283DBQR
2500
Pack Materials-Page 2
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