TLC5928PW [TI]
16-Channel, Constant-Current LED Driver with LED Open Detection; 16通道恒流LED驱动器，具有LED开路检测
| 型号： | TLC5928PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Channel, Constant-Current LED Driver with LED Open Detection |
| 文件： | 总27页 (文件大小：1032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5928
www.ti.com ................................................................................................................................................. SBVS120A–JULY 2008–REVISED SEPTEMBER 2008
16-Channel, Constant-Current LED Driver with LED Open Detection
1
FEATURES
APPLICATIONS
•
•
•
LED Video Displays
Message Boards
Illumination
23
•
16 Channels, Constant Current Sink Output
with On/Off Control
•
•
35-mA Capability (Constant Current Sink)
10-ns High-Speed Constant Current Switching
Transient Time
DESCRIPTION
The TLC5928 is a 16-channel, constant current sink
LED driver. Each channel can be turned on/off by
writing serial data to an internal register. The constant
current value of all 16 channels is set by a single
external resistor.
•
•
•
•
Low On-Time Error
LED Power-Supply Voltage up to 17 V
VCC = 3.0 V to 5.5 V
Constant Current Accuracy:
–
–
Channel-to-Channel = ±1%
Device-to-Device = ±1%
The TLC5928 has two error detection circuits: one for
LED open detection (LOD) and one for a pre-thermal
warning (PTW). LOD detects
a
broken or
•
•
•
•
CMOS Logic Level I/O
disconnected LED and LEDs shorted to GND while
the constant current output is on. PTW indicates a
high temperature condition.
35-MHz Data Transfer Rate
20-ns BLANK Pulse Width
Readable Error Information:
–
–
LED Open Detection (LOD)
Pre-Thermal Warning (PTW)
•
Operating Temperature: –40°C to +85°C
VLED
VLED
VLED
VLED
¼
¼
¼
¼
¼
¼
¼
¼
OUT0
OUT15
SOUT
OUT0
SIN
OUT15
SOUT
DATA
SIN
SCLK
VCC
VCC
SCLK
SCLK
LAT
LAT
Controller
LAT
VCC
GND
VCC
GND
BLANK
BLANK
IREF
BLANK
IREF
TLC5928
TLC5928
ERROR
READ
IC1
ICn
RIREF
RIREF
3
Typical Application Circuit (Multiple Daisy-Chained TLC5928s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLC5928
SBVS120A–JULY 2008–REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
TLC5928DBQR
TLC5928DBQ
TRANSPORT MEDIA, QUANTITY
Tape and Reel, 2500
Tube, 50
TLC5928
SO-24
TLC5928PWR
TLC5928PW
Tape and Reel, 2000
Tube, 60
TLC5928
TLC5928
TLC5928
TSSOP-24
HTSSOP-24 PowerPAD™
QFN-24(2)
TLC5928PWPR
TLC5928PWP
TLC5928RGER
TLC5928RGE
Tape and Reel, 2000
Tube, 60
Tape and Reel, 3000
Tape and Reel, 250
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Shaded cells indicate product preview device.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
TLC5928
–0.3 to +6.0
40
UNIT
V
VCC
IOUT
VIN
Supply voltage: VCC
Output current (dc)
Input voltage range
OUT0 to OUT15
mA
V
SIN, SCLK, LAT, BLANK, IREF
SOUT
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to +18
+150
V
VOUT
Output voltage range
OUT0 to OUT15
V
TJ(MAX)
TSTG
Operating junction temperature
Storage temperature range
°C
°C
kV
V
–55 to +150
2
Human body model (HBM)
ESD rating
Charged device model (CDM)
500
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
OPERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
PACKAGE
SO-24
14.3 mW/°C
9.6 mW/°C
28.9 mW/°C
24.8 mW/°C
1782 mW
1194 mW
3611 mW
3106 mW
1140 mW
764 mW
927 mW
621 mW
1878 mW
1615 mW
TSSOP-24
HTSSOP-24(1)
QFN-24(2)
2311 mW
1988 mW
(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
(2) The package thermal impedance is calculated in accordance with JESD51-5.
2
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Product Folder Link(s): TLC5928
TLC5928
www.ti.com ................................................................................................................................................. SBVS120A–JULY 2008–REVISED SEPTEMBER 2008
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC5928
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
VO
VIH
VIL
IOH
IOL
IOLC
TA
Supply voltage
3.0
5.5
17
V
V
Voltage applied to output
High-level input voltage
OUT0 to OUT15
0.7 × VCC
GND
VCC
V
Low-level input voltage
0.3 × VCC
–1
V
High-level output current
Low-level output current
Constant output sink current
Operating free-air temperature range
Operating junction temperature range
SOUT
SOUT
mA
mA
mA
°C
°C
1
OUT0 to OUT15
2
–40
–40
35
+85
TJ
+125
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (SCLK)
TWH0
TWL0
TWH1
TWH2
TWL2
TSU0
Data shift clock frequency
SCLK
SCLK
35
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
20
20
20
4
SCLK
Pulse duration
LAT
BLANK
BLANK
SIN–SCLK↑
LAT↑–SCLK↑
SIN–SCLK↑
LAT↑–SCLK↑
Setup time
Hold time
TSU1
100
3
TH0
TH1
10
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TLC5928
SBVS120A–JULY 2008–REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5928
PARAMETER
TEST CONDITIONS
IOH = –1 mA at SOUT
MIN
TYP
MAX
VCC
0.4
1
UNIT
V
VOH
VOL
IIN
High-level output voltage
Low-level output voltage
Input current
VCC – 0.4
IOL = 1 mA at SOUT
0
V
VIN = VCC or GND at SIN, SCLK, LAT, and BLANK
–1
µA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
RIREF = 27 kΩ
ICC1
ICC2
ICC3
ICC4
IOLC
1
4.5
7
2
8
mA
mA
mA
mA
mA
SIN/SCLK/LAT = low, BLANK = high, VOUTn = 1 V,
RIREF = 3 kΩ
Supply current (VCC
)
SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,
RIREF = 3 kΩ
18
40
37
SIN/SCLK/LAT/BLANK = low, VOUTn = 1 V,
RIREF = 1.5 kΩ
16
34
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
(see Figure 6), at OUT0 to OUT15
Constant output current
Output leakage current
31
All OUTn for constant current driver, all outputs off
BLANK = high, VOUTn = VOUTfix = 17 V, RIREF = 1.5 kΩ
(see Figure 6), at OUT0 to OUT15
IOLKG
0.1
µA
Constant current error
(channel-to-channel)(1)
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15
ΔIOLC
±1
±1
±3
±6
±1
±3
%
%
Constant current error
(device-to-device)(2)
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15
ΔIOLC1
ΔIOLC2
ΔIOLC3
All OUTn = ON, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
at OUT0 to OUT15
Line regulation(3)
Load regulation(4)
±0.5
±1
%/V
%/V
All OUTn = ON, VOUTn = 1 V to 3V, VOUTfix = 1 V,
RIREF = 1.5 kΩ, at OUT0 to OUT15
T(PTW)
VLOD
Pre-thermal warning threshold
LED open detection threshold
Reference voltage output
Junction temperature(5)
+125
0.25
1.16
+138
0.30
1.20
+150
0.35
1.24
°C
V
All OUTn = ON
VIREF
RIREF = 1.5 kΩ
V
(1) The deviation of each output from the average of OUT0–OUT15 constant current. Deviation is calculated by the formula:
IOUTn
D (%) =
- 1 ´ 100
(IOUT0 + IOUT1 + ... + IOUT14 + IOUT15
)
16
.
(2) The deviation of the OUT0–OUT15 constant current average from the ideal constant current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15
)
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
1.20
IOUT(IDEAL) = 42 ´
RIREF
(3) Line regulation is calculated by this equation:
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
D (%/V) =
100
´
(IOUTn at VCC = 3.0 V)
5.5 V - 3 V
(4) Load regulation is calculated by the equation:
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
100
3 V - 1 V
D (%/V) =
´
(IOUTn at VOUTn = 1 V)
(5) Not tested. Specified by design.
4
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Product Folder Link(s): TLC5928
TLC5928
www.ti.com ................................................................................................................................................. SBVS120A–JULY 2008–REVISED SEPTEMBER 2008
SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 130 Ω, RIREF = 1.5 kΩ, and VLED = 5.5 V. Typical values at
VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5928
PARAMETER
TEST CONDITIONS
SOUT (see Figure 5)
MIN
TYP
5
MAX
15
UNIT
ns
tR0
tR1
tF0
tF1
tD0
Rise time
OUTn (see Figure 4)
SOUT (see Figure 5)
OUTn (see Figure 4)
SCLK↑ to SOUT
10
5
30
ns
15
ns
Fall time
10
8
30
ns
20
ns
LAT↑ or BLANK↓ to OUTn sink current on
(see Figure 10)
tD1
12
12
30
30
+8
ns
ns
ns
Propagation delay time
Output on-time error(1)
LAT↑ or BLANK↑ to OUTn sink current off
(see Figure 10)
tD2
On/off latch data = all '1', 20 ns BLANK low level
one-shot pulse input (see Figure 4)
tON_ERR
–8
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – BLANK low level one-shot pulse width (TWL2).
tOUT_ON indicates the actual on-time of the constant current driver.
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
SIN
LSB
MSB
On/Off Control Shift Register
(1 Bit x 16 Channels)
SCLK
SOUT
0
15
16
16
MSB
LSB
LAT
On/Off Control Data Latch
(1 Bit x 16 Channels)
0
15
BLANK
16
SID Latch
IREF
GND
16-Channel Constant Current Sink Driver
16
Thermal
Detection
16-Channel LED Open Detection
GND
¼
OUT0 OUT1
OUT14 OUT15
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TLC5928
SBVS120A–JULY 2008–REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
DEVICE INFORMATION
SO-24 AND TSSOP-24
DBQ AND PW PACKAGES
(TOP VIEW)
HTSSOP-24 PowerPAD
PWP PACKAGE
(TOP VIEW)
GND
1
2
3
4
5
6
7
8
9
24 VCC
GND
SIN
1
2
3
4
5
6
7
8
9
24 VCC
SIN
SCLK
LAT
23 IREF
23 IREF
22 SOUT
21 BLANK
20 OUT15
19 OUT14
18 OUT13
17 OUT12
16 OUT11
15 OUT10
14 OUT9
13 OUT8
SCLK
LAT
22 SOUT
21 BLANK
20 OUT15
19 OUT14
18 OUT13
17 OUT12
16 OUT11
15 OUT10
14 OUT9
13 OUT8
OUT0
OUT1
OUT2
OUT3
OUT4
OUT0
OUT1
OUT2
OUT3
OUT4
Thermal Pad
(Bottom Side)
TLC5928
TLC5928
OUT5 10
OUT6 11
OUT7 12
OUT5 10
OUT6 11
OUT7 12
QFN-24(1)
RGE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
18 BLANK
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
17 OUT15
16 OUT14
15 OUT13
14 OUT12
13 OUT11
Thermal Pad
(Bottom Side)
TLC5928
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the PCB pattern.
(1) Product preview device.
6
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Product Folder Link(s): TLC5928
TLC5928
www.ti.com ................................................................................................................................................. SBVS120A–JULY 2008–REVISED SEPTEMBER 2008
TERMINAL FUNCTIONS
TERMINAL
DBQ/PW/
NAME
SIN
PWP
RGE
I/O
DESCRIPTION
Serial data input for driver on/off control. When SIN = high level, data '1' are written into LSB
of the on/off control shift register at the rising edge of SCLK.
2
23
I
Serial data shift clock. Schmitt buffer input. All data in the on/off control shift register are
shifted toward the MSB by 1-bit synchronization of SCLK. A rising edge on SCLK is allowed
100 ns after a rising edge of LAT.
SCLK
LAT
3
4
24
1
I
I
Edge triggered latch. The data in the on/off control data shift register are transferred to the
on/off control data latch at this rising edge. At the same time, the data in the on/off control shift
register are replaced with LED open detection (LOD) and pre-thermal warning (PTW) data.
LAT must be toggled only once after the shift data are updated to avoid the on/off control latch
data being replaced with LOD and PTW data in the shift register.
Blank, all outputs. When BLANK = high level, all constant current outputs (OUT0–OUT15) are
forced off. When BLANK = low level, all constant current outputs are controlled by the on/off
control data in the data latch. LOD and PTW data are latched into the SID data latch at the
rising edge of BLANK and are present at the output of the SID data latch when BLANK is low.
BLANK
21
18
I
Constant current value setting, OUT0–OUT15 sink constant current is set to desired value by
connection to an external resistor between IREF and GND.
IREF
23
22
5
20
19
2
I/O
O
Serial data output. This output is connected to the MSB of the on/off data shift register. SOUT
data changes at the rising edge of SCLK.
SOUT
OUT0
Constant current output. Each output can be tied together with others to increase the constant
current. Different voltages can be applied to each output.
O
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
VCC
6
3
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Power-supply voltage
Power ground
7
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
24
1
7
8
9
10
11
12
13
14
15
16
17
21
22
GND
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TLC5928
SBVS120A–JULY 2008–REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
GND
SOUT
GND
Figure 1. SIN, SCLK, LAT, BLANK
Figure 2. SOUT
OUTn
GND
Figure 3. OUT0 Through OUT15
TEST CIRCUITS
RL
CL
VCC
GND
VCC
VCC
IREF
OUTn
SOUT
GND
VLED
VCC
(1)
(1)
CL
RIREF
(1) CL includes measurement probe and jig capacitance.
(1) CL includes measurement probe and jig capacitance.
Figure 4. Rise Time and Fall Time Test Circuit for OUTn
Figure 5. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
OUTn
VCC
IREF
RIREF
GND OUT15
VOUTn
VOUTFIX
Figure 6. Constant Current Test Circuit for OUTn
8
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TLC5928
www.ti.com ................................................................................................................................................. SBVS120A–JULY 2008–REVISED SEPTEMBER 2008
TIMING DIAGRAMS
TWH0, TWL0, TWH1, TWH2, TWL2
:
VCC
INPUT(1) 50%
GND
TWH
TWL
TSU0, TSU1, TH0, TH1
:
VCC
CLOCK
INPUT(1)
50%
GND
VCC
TSU
TH
DATA/CONTROL
INPUT(1)
50%
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 7. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2
:
VCC
INPUT(1)
50%
GND
tD
VOH or VOUTn
90%
50%
10%
OUTPUT
VOL or VOUTn
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
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TLC5928
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DATA
0A
DATA
15B
DATA
14B
DATA DATA
13B
12B
DATA
11B
DATA
3B
DATA DATA
2B 1B
DATA
0B
DATA
15C
DATA
14C
DATA DATA DATA
13C 12C 11C
DATA
10C
SIN
SCLK
LAT
TH0
TH1
TSU0
TWH0
TSU1
1
2
3
4
5
1
2
3
TWL0
4
5
6
13
14
15
16
TWH1
Shift Register
LSB Data (Internal)
DATA
0A
LOD
0
DATA DATA
15B
DATA DATA
13B
12B
DATA DATA
3B
2B
DATA DATA
0B
DATA
15C
DATA
14C
DATA DATA
13C 12C
DATA
11C
LOD 0A or PTW_A
LOD 1A or PTW_A
14B
1B
Shift Register
LSB+1 Data (Internal)
DATA
1A
LOD
1
LOD
0
DATA
15B
DATA DATA
13B
DATA DATA
3B
DATA
2B
LOD
0A
DATA
15C
DATA DATA
14C
DATA
12C
14B
4B
13C
Shift Register
MSB-1 Data (Internal)
DATA
14A
LOD
14
LOD
13
LOD
12
LOD
11
LOD
10
LOD
1
LOD
0
DATA
15B
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD
9A
LOD 14A or PTW_A
LOD 15A or PTW_A
Shift Register
MSB Data (Internal)
DATA
15A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD
0
DATA
15B
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
On/Off Control
Latch Data (Internal)
Previous Grayscale Latch Data
Latest Grayscale Latch Data
DATA
15A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD
0
DATA
15B
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD 15A or PTW_A
SOUT
tD0
tR0/tF0
tWH2
BLANK
tWL2
tD2
ON
tD1
OFF
OFF
OUTn(1)
ON
ON
tOUTON
tD1
tD2
OFF
OFF
OUTn(2)
ON
ON
tF1
tD1
OFF
OFF
OUTn(3)
ON
ON
tR1
OFF
OFF
OUTn(4)
ON
(1) On/off latched data are '1'.
(2) On/off latched data are changed from '1' to '0' at the second LAT signal.
(3) On/off latched data are changed from '0' to '1' at the second LAT signal.
(4) On/off latched data are '0'.
Figure 9. Timing Diagram
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TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR
vs OUTPUT CURRENT
POWER DISSIPATION RATE
vs FREE-AIR TEMPERATURE
100000
10000
1000
4000
3000
2000
1000
0
TLC5928PWP
25200
10080
TLC5928RGE
5040
TLC5928DBQ
3360
2520
2016
TLC5928PW
1680
1440
30
0
5
10
15
20
25
-40
0
20
60
80
100
-20
40
Output Current (mA)
Free-Air Temperature (°C)
Figure 10.
Figure 11.
OUTPUT CURRENT vs
OUTPUT VOLTAGE
OUTPUT CURRENT vs
OUTPUT VOLTAGE
40
35
30
25
20
15
10
5
40
39
38
37
36
35
34
33
32
31
30
IO = 30 mA
IO = 35 mA
IO = 30 mA
TA = +25°C
IO = 20 mA
IO = 10 mA
IO = 5 mA
TA = -40°C
IO = 2 mA
TA = +25°C
TA = +85°C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
Figure 12.
Figure 13.
ΔIOLC vs AMBIENT TEMPERATURE
ΔIOLC vs OUTPUT CURRENT
4
3
4
3
IO = 35 mA
TA = +25°C
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
-40
-20
0
20
40
60
80
100
0
10
20
30
40
Ambient Temperature (°C)
Output Current (mA)
Figure 15.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
CONSTANT CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1-BLANK
(20 ns)
CH1 (2 V/div)
CH2-OUT0
(BLANK = 20 ns)
CH2 (2 V/div)
CH3 (2 V/div)
CH3-OUT15
(BLANK = 20 ns)
IOLC = 35 mA
TA = +25°C
RL = 130 W
CL = 15 pF
VLED = 5.5 V
Time (12.5 ns/div)
Figure 16.
12
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DETAILED DESCRIPTION
SETTING FOR THE CONSTANT SINK CURRENT VALUE
The constant current values are determined by an external resistor (RIREF) placed between IREF and GND. The
resistor (RIREF) value is calculated by Equation 1.
VIREF (V)
RIREF (kW) =
´ 42
IOLC (mA)
(1)
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V)
IOLC must be set in the range of 2 mA to 35 mA. The constant sink current characteristic for the external resistor
value is shown in Figure 10. Table 1 describes the constant current output versus external resistor value.
Table 1. Constant Current Output versus External Resistor Value
IOLCMax (mA, Typical)
RIREF (kΩ)
1.44
35
30
25
20
15
10
5
1.68
2.02
2.52
3.36
5.04
10.1
2
25.2
CONSTANT CURRENT DRIVER ON/OFF CONTROL
When BLANK is low, the corresponding output is turned on if the data in the on/off control data latch are '1' and
remains off if the data are '0'. When BLANK is high, all outputs are forced off. This control is shown in Table 2.
Table 2. On/Off Control Data Truth Table
ON/OFF CONTROL LATCH DATA
CONSTANT CURRENT OUTPUT STATUS
0
1
Off
On
When the IC is initially powered on, the data in the on/off control shift register and data latch are not set to the
respective default value. Therefore, the on/off control data must be written to the data latch before turning the
constant current output on. BLANK should be at a high level when powered on because the constant current
may be turned on as a result of random data in the on/off control latch.
The on/off data corresponding to any unconnected OUTn outputs should be set to ‘0’ before turning on the
remaining outputs. Otherwise, the supply current (ICC) increases while the LEDs are on.
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REGISTER CONFIGURATION
The TLC5928 has an on/off control data shift register and data latch. Both the on/off control shift register and
latch are 16 bits long and are used to turn on/off the constant current drivers. Figure 17 shows the shift register
and latch configuration. The data at the SIN pin are shifted in to the LSB of the shift register at the rising edge of
the SCLK pin; SOUT data change at the rising edge of SCLK. The timing diagram for data writing is shown in
Figure 18. The driver on/off is controlled by the data in the on/off control data latch.
The on/off data are latched into the data latch by a rising edge of LAT after the data are written into the on/off
control shift register by SIN and SCLK. At the same time, the data in the on/off control shift register are replaced
with LED open detection (LOD) and pre-thermal warning (PTW) data. Therefore, LAT must be input only once
after the on/off data update to avoid the on/off control data latch being replaced with LOD and PTW data in the
shift register. When the IC is initially powered on, the data in the on/off control shift register and latch are not set
to the default values; on/off control data must be written to the on/off control data latch before turning the
constant current output on. BLANK should be high when the IC is powered on because the constant current may
be turned on at that time as a result of random values in the on/off data latch. All constant current outputs are
forced off when BLANK is high.
On/Off Control Shift Register (1 Bit ´ 16 Channels)
MSB
15
LSB
0
14
13
12
11
4
3
2
1
SIN
On/Off Data On/Off Data On/Off Data On/Off Data
On/Off Data On/Off Data
On/Off Data On/Off Data
¼
¼
for
for
for
for
for
for
for
for
SOUT
OUT15
OUT14
OUT13
OUT12
OUT3
OUT2
OUT1
OUT0
SCLK
MSB
15
LSB
0
14
13
12
11
4
3
2
1
On/Off Data On/Off Data On/Off Data On/Off Data
On/Off Data On/Off Data
On/Off Data On/Off Data
¼
for
for
for
for
for
for
for
for
LAT
OUT15
OUT14
OUT13
OUT12
OUT3
OUT2
OUT1
OUT0
On/Off Control Data Latch (1 Bit ´ 16 Channels)
16 Bits
To Constant Current Driver Control Block
Figure 17. On/Off Control Shift Register and Latch Configuration
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DATA
0A
DATA
15B
DATA
14B
DATA
13B
DATA
12B
DATA
11B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
15C
DATA
14C
DATA DATA DATA
13C 12C 11C
DATA
10C
SIN
SCLK
1
2
3
4
5
13
14
15
16
1
2
3
4
5
6
LAT
Shift Register
LSB Data (Internal)
DATA
0A
LOD
0
DATA
15B
DATA
14B
DATA DATA
13B
12B
DATA
3B
DATA
2B
DATA DATA
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
LOD 0A or PTW_A
1B
Shift Register
LSB+1 Data (Internal)
DATA
1A
LOD
1
LOD
0
DATA
15B
DATA DATA
13B
DATA
4B
DATA
3B
DATA
2B
LOD
0A
DATA
15C
DATA
14C
DATA
13C
DATA
12C
LOD 1A or PTW_A
14B
Shift Register
MSB-1 Data(Internal)
DATA
14A
LOD
14
LOD
13
LOD
12
LOD
11
LOD
10
LOD
1
LOD
0
DATA
15B
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD
9A
LOD 14A or PTW_A
LOD 15A or PTW_A
Shift Register
MSB Data(Internal)
DATA
1A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD DATA
15B
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
0
On/Off Control
Latch Data (Internal)
Previous Grayscale Latch Data
Latest Grayscale Latch Data
DATA
1A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
2
LOD
1
LOD
0
DATA
15B
LOD
14A
LOD
13A
LOD
12A
LOD
11A
LOD
10A
LOD 15A or PTW_A
SOUT
BLANK
OFF
OUTn(1)
OFF
ON
ON
OFF
OUTn(2)
OFF
ON
ON
OFF
OFF
OUTn(3)
OFF
ON
ON
OFF
OFF
OUTn(4)
OFF
ON
(1) On/off latched data are '1'.
(2) On/off latched data are changed from '1' to '0' at the second LAT signal.
(3) On/off latched data are changed from '0' to '1' at the second LAT signal.
(4) On/off latched data are '0'.
Figure 18. On/Off Control Operation
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LED OPEN DETECTION (LOD) AND PRE-THERMAL WARNING (PTW)
The LED open detection (LOD) circuit checks the voltage of each active (that is, on) constant current sink output
(OUT0 through OUT15) to detect open LEDs and LEDs shorted to GND while BLANK is low. The LOD bits in the
status information data register (SID) are set to '1' if the voltage of the corresponding OUTn pin is less than the
LED open detection threshold (VLOD = 0.3 V, typ). The status information data can be read from the SOUT pin.
To avoid false detection of open LEDs, the LED driver design must ensure that the constant-current sink output
voltage is greater than 0.3 V when the outputs are on. Also, the output on-time must be 1 µs or greater to
correctly read the valid LOD status.
The PTW function indicates that the IC junction temperature is too high. The PTW bit in the SID data is set to '1'
while the IC junction temperature exceeds the temperature threshold (T(PTW) = +138 °C, typ). If the IC junction
temperature decreases below the temperature of T(PTW), the SID data are set depending on the LOD function.
The constant current outputs are not forced off during PTW conditions, so the controller should take appropriate
action (such as reducing the duty cycle of effected channels).
The LOD and PTW data are latched into the SID latch with the rising edge of BLANK and do not change until
BLANK goes low. The SID data latched in the latch are transferred into the on/off shift register with a rising edge
of LAT. SID can be shifted out from SOUT with rising edges of SCLK. The data in the on/off control shift register
are replaced with the LOD and PTW data at the rising edge of LAT. Therefore, LAT should be input only once
after the shift data are updated to avoid the on/off control data latch information from being replaced with LOD
and PTW data in the shift register. A timing diagram for LOD, PTW, and SID is shown in Figure 19.
BLANK
OUTn OFF
OUTn
OUTn ON
VOUTn
If the voltage of OUTn (VOUTn) is less than VLOD (0.3 V, typ) when OUTn is on,
GND
then the LOD circuit reports error information to the LOD data latch
and the error information is set as '1' to the bit that corresponds with
the error OUTn in the LOD data latch.
LOD circuit needs 1ms to detect LED
open correctly as maximum.
LOD Circuit Data
(Internal)
Latest Error Information From LOD Circuit
No Error Information
No Error Information
LOD and PTW data are always copied into
SID data latch while BLANK is low level.
TJ < T(PTW)
:
TJ < T(PTW)
:
PTW Circuit Data
(Internal)
Normal Temperature
Normal Temperature
TJ ³ T(PTW): High Temperature
LOD and PTW data of from before
BLANK goes high are held in the
SID data latch at the rising edge of BLANK.
Previous LOD and PTW Data
SID Data Latch
(Internal)
PTW Error
Latest Error Information From LOD and PTW Circuit
No Error Information
Figure 19. LOD/PTW/SID timing
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STATUS INFORMATION DATA (SID)
The latched LED open detection (LOD) error and pre-thermal warning (PTW) in the SID data latch are shifted out
onto the SOUT pin with each rising edge of SCLK. If a PTW is reported, all LOD error bits are set to '1'. The SID
data are written over the data in the on/off control shift register at the rising edge of LAT. Therefore, the previous
data in the on/off control shift register are lost when SID information is latched in. Figure 20 shows the SID bit
assignments. See Figure 7 for the read timing of SID.
When the IC is powered on, the initial LOD data are invalid. Therefore, LOD data must be read after the rising
edge of BLANK. Table 3 shows a truth table for LOD and PTW.
Table 3. LOD and PTW Truth Table
CONDITION
SID DATA
LED is connected (VOUTn > VLOD
)
'0' (low level at SOUT)
LED open detection (LODn)
Pre-termal warning (PTW)
LED is opened or shorted to GND
(VOUTn ≤ VLOD and output on)
'1' (high level at SOUT); set to the bit that has an
LED error condition
IC temperature is low (IC temperature ≤ T(PTW)
)
Depend LED open error
IC temperature is high (IC temperature > T(PTW)
)
All bits = '1' (high level at SOUT)
SID Data Latch (1 Bit ´ 16 Channels)
MSB
LSB
15
14
13
12
11
4
3
2
1
0
OUT15
LOD Data
(LOD 15)
OUT15
LOD Data
(LOD 14)
OUT15
LOD Data
(LOD 13)
OUT15
LOD Data
(LOD 12)
OUT15
LOD Data
(LOD 3)
OUT15
LOD Data
(LOD 2)
OUT15
LOD Data
(LOD 1)
OUT15
LOD Data
(LOD 0)
¼
All Bits Become ‘1’ When the IC is in a PTW (Pre-Thermal Warning) Condition
¼
MSB
15
LSB
0
14
13
12
11
4
3
2
1
SIN
On/Off Data On/Off Data On/Off Data On/Off Data
for
OUT14
On/Off Data On/Off Data
for
OUT2
On/Off Data On/Off Data
for
OUT0
¼
for
OUT15
for
OUT13
for
OUT12
for
OUT3
for
OUT1
SOUT
SCLK
The 16 bits in the SID latch are loaded into the on/off shift register at the rising edge of LAT.
SID Control Shift Register (1 Bit ´ 16 Channels)
Figure 20. Status Information Data Configuration
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2008
PACKAGING INFORMATION
Orderable Device
TLC5928DBQ
TLC5928DBQR
TLC5928PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
24
24
24
24
24
24
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
DBQ
PW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
HTSSOP
HTSSOP
TSSOP
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC5928PWP
TLC5928PWPR
TLC5928PWR
PWP
PWP
PW
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLC5928DBQR
TLC5928PWPR
SSOP/
QSOP
DBQ
24
24
2500
2000
330.0
16.4
6.5
9.0
8.3
2.1
1.6
8.0
8.0
16.0
16.0
Q1
Q1
HTSSOP PWP
330.0
16.4
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC5928DBQR
TLC5928PWPR
SSOP/QSOP
HTSSOP
DBQ
PWP
24
24
2500
2000
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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相关型号：
TLC5929
16-Channel, Constant-Current LED Driver with 7-Bit Global Brightness Control, Power-Save Mode
TI
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