TLC5929 [TI]
16-Channel, Constant-Current LED Driver with 7-Bit Global Brightness Control, Power-Save Mode; 16通道恒流LED驱动器，提供7位全局亮度控制，节电模式
| 型号： | TLC5929 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Channel, Constant-Current LED Driver with 7-Bit Global Brightness Control, Power-Save Mode |
| 文件： | 总36页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5929
www.ti.com
SBVS159 –APRIL 2011
16-Channel, Constant-Current LED Driver with 7-Bit Global Brightness Control,
Power-Save Mode, and Full Self-Diagnosis for LED Lamp
Check for Samples: TLC5929
1
FEATURES
•
•
2-ns Delayed Switching Between Each
Channel Minimizes Inrush Current
23
•
16 Constant-Current Sink Output Channels
with On/Off Control
Operating Temperature: –40°C to +85°C
•
Current Capability:
APPLICATIONS
–
–
40 mA (VCC ≤ 3.6 V)
50 mA (VCC > 3.6 V)
•
•
•
Variable Message Signs (VMS)
Illumination
•
•
•
•
Global Brightness Control: 7-Bit (128 Steps)
Power-Supply Voltage Range: 3.0 V to 5.5 V
LED Power-Supply Voltage: Up to 10 V
Constant-Current Accuracy:
LED Video Displays
DESCRIPTION
The TLC5929 is a 16-channel constant current sink
LED driver. Each channel can be turned on or off by
writing data to an internal register. The constant
current value of all 16 channels is set by a single
external resistor with 128 steps for the global
brightness control (BC).
–
–
Channel-to-Channel = ±1% (typ)
Device-to-Device = ±2% (typ)
•
•
•
Data Transfer Rate: 33 MHz
BLANK Pulse Width: 40 ns (min)
LED Open Detection (LOD)/LED Short
Detection (LSD) with Invisible Detection Mode
(IDM)
The TLC5929 has six error flags: LED open detection
(LOD), LED short detection (LSD), output leakage
detection (OLD), reference current terminal short
detection (ISF), pre-thermal warning (PTW) and
thermal error flag (TEF). In addition, the LOD and
LSD functions have invisible detection mode (IDM)
that can detect those errors even when the output is
off. The error detection results can be read via a
serial interface port.
•
Output Leakage Detection (OLD) Detects 3 µA
Leak
•
•
•
•
•
Pre-Thermal Warning (PTW)
Thermal Shutdown (TSD)
Current Reference Terminal Short Flag (ISF)
Power-Save Mode with 10-µA Consumption
Undervoltage Lockout Sets the Default Data
The TLC5929 also has a power-save mode that sets
the total current consumption to 10 µA (typ) when all
outputs are off.
Typical Application Circuit (Multiple Daisy-Chained TLC5929s)
VLED
¼
¼
¼
¼
¼
¼
¼
¼
OUT0
SIN
OUT15
SOUT
OUT0
SIN
OUT15
SOUT
DATA
SCLK
LAT
VCC
VCC
SCLK
LAT
SCLK
LAT
TLC5929
TLC5929
ICn
IC1
VCC
GND
VCC
GND
BLANK
BLANK
IREF
BLANK
IREF
Controller
RIREF
RIREF
3
SID Read
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TLC5929
SBVS159 –APRIL 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE-LEAD
TLC5929DBQR
TLC5929DBQ
TLC5929PWPR
TLC5929PWP
Tape and Reel, 2500
Tube, 50
SSOP/QSOP-24
DBQ
PWP
TLC5929
Tape and Reel, 2000
Tube, 60
HTSSOP-24 PowerPAD™
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
MIN
MAX
UNIT
V
VCC
–0.3
+6.0
Voltage(2)
SIN, SCLK, LAT, BLANK, IREF, SOUT
OUT0 to OUT15
–0.3 VCC + 0.3
V
–0.3
0
+11
+65
V
Current
OUT0 to OUT15
mA
°C
°C
V
Operating junction, TJ (max)
Storage, TSTG
–40
–55
+150
+150
4000
2000
Temperature
Human body model (HBM)
Charged device model (CDM)
Electrostatic Discharge Ratings
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to device ground terminal.
THERMAL INFORMATION
TLC5929
THERMAL METRIC(1)
DBQ
24 PINS
85.3
PWP
24 PINS
37.6
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
48.8
24.5
38.6
11.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.9
0.5
ψJB
38.3
11.3
θJCbot
N/A
5.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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TLC5929
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SBVS159 –APRIL 2011
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC5929
NOM
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
VO
Supply voltage
3.0
3.3
5.5
V
V
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
OUT0 to OUT15
SIN, SCLK, LAT, BLANK
SIN, SCLK, LAT, BLANK
SOUT
10
VIH
VIL
IOH
IOL
0.7 × VCC
VCC
V
GND
0.3 × VCC
V
–2
mA
mA
SOUT
2
OUT0 to OUT15,
3 V ≤ VCC < 3.6 V
40
50
mA
mA
IOLC
Constant output sink current
OUT0 to OUT15,
3.6 V ≤ VCC < 5.5 V
TA
TJ
Operating free-air temperature range
Operating junction temperature range
–40
–40
+85
°C
°C
+125
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (SCLK)
tWH0
tWL0
tWH1
tWH2
tWL2
tSU0
Data shift clock frequency
SCLK
SCLK
33
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
20
40
40
5
SCLK
Pulse duration
(see Figure 4 and Figure 6)
LAT
BLANK
BLANK
SIN to SCLK↑
LAT↑ to SCLK↑
SIN to SCLK↑
LAT↑ to SCLK↑
Setup time
(see Figure 4 and Figure 6)
tSU1
200
3
tH0
Hold time
(see Figure 4 and Figure 6)
tH1
10
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ELECTRICAL CHARACTERISTICS
At VCC = 3 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5929
PARAMETER
TEST CONDITIONS
IOH = –2 mA at SOUT
MIN
TYP
MAX
VCC
0.4
UNIT
V
VOH
High-level output voltage
Low-level output voltage
LED open detection threshold
V
CC – 0.4
VOL
IOL = 2 mA at SOUT
V
VLOD
VLSD0
VLSD1
VLSD2
VLSD3
VIREF
IIN
All OUTn = on
0.25
0.30
0.35
V
All OUTn = on, detection voltage code = 0h
All OUTn = on, detection voltage code = 1h
All OUTn = on, detection voltage code = 2h
All OUTn = on, detection voltage code = 3h
RIREF = 1.3 kΩ
0.32 × VCC 0.35 × VCC 0.38 × VCC
0.42 × VCC 0.45 × VCC 0.48 × VCC
0.52 × VCC 0.55 × VCC 0.58 × VCC
0.62 × VCC 0.65 × VCC 0.68 × VCC
V
V
LED short detection threshold
V
V
Reference voltage output
Input current
1.175
1.205
1.235
1
V
VIN = VCC or GND at SIN, SCLK, LAT, and BLANK
–1
μA
SIN/SCLK/LAT = low, BLANK = high, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = open
ICC0
2
5
3
7
mA
mA
SIN/SCLK/LAT = low, BLANK = high, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)
ICC1
SIN/SCLK/LAT/BLANK = low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)
ICC2
ICC3
ICC4
5
9
7
11
14
mA
mA
mA
SIN/SCLK/LAT/BLANK = low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.6 kΩ
(IOUT = 41.3 mA target)
Supply current (VCC
)
VCC = 5.0 V, SIN/SCLK/LAT/BLANK = low,
All OUTn = on, VOUTn = 0.8 V, BC = 7Fh,
RIREF = 1.3 kΩ (IOUT = 50.8 mA target)
11
VCC = 5.0 V, SIN/SCLK/LAT/BLANK = low,
All OUTn = on, VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.3
kΩ (IOUT = 50.8 mA target), all output data off with
power-save mode enabled
ICC5
10
40
µA
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ
IOLC0
IOLC1
38.5
47.3
41.3
50.8
44.1
54.3
mA
mA
Constant output sink current
(OUT0 to OUT15, see Figure 3)
VCC = 5.0 V, All OUTn = on, VOUTn = VOUTfix = 1 V,
BC = 7Fh, RIREF = 1.3 kΩ
IOLKG0
IOLKG1
IOLKG2
TJ = +25°C
0.1
0.2
0.8
μA
μA
μA
Output leakage current
(OUT0 to OUT15, see Figure 3) 10 V, RIREF = 1.6 kΩ
BLANK = high, VOUTn = VOUTfix =
TJ = +85°C(1)
TJ = +125°C(1)
0.3
Constant-current error
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ, TA = +25°C
ΔIOLC0
(channel-to-channel, OUT0 to
±1
±3
±4
%
%
OUT15)(2)
Constant-current error
(device-to-devicel, OUT0 to
OUT15)(3)
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ, TA = +25°C
ΔIOLC1
±2
(1) Not tested; specified by design.
(2) The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
IOLC(n)
- 1
(IOLC(0) + IOLC(1) + ... + IOLC(14) + IOLC(15)
)
D (%) = 100 ´
16
.
(3) The deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value. Deviation is calculated by the
formula:
(IOLC(0) + IOLC(1) + ... IOLC(14) + IOLC(15)
)
- (Ideal Output Current)
D (%) = 100 ´
16
Ideal Output Current
Ideal current is calculated by the formula:
1.205
IOLC(IDEAL) = 54.8 ´
RIREF
4
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SBVS159 –APRIL 2011
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 3 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5929
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ
ΔIOLC2
ΔIOLC3
Line regulation(4)
±0.1
±1
%/V
All OUTn = on, VOUTn = 0.8 V to 3 V, VOUTfix = 0.8 V,
BC = 7Fh, RIREF = 1.6 kΩ
Load regulation(5)
±0.5
±3
%/V
TTEF
THYS
TPTW
Thermal error flag threshold
Thermal error flag hysteresis
Pre-thermal warning threshold
Junction temperature(6)
Junction temperature(6)
Junction temperature(6)
150
5
165
10
180
20
°C
°C
°C
125
138
150
(4) Line regulation is calculated by the formula:
(IOLC(n) at VCC = 5.5 V) - (IOLC(n) at VCC = 3.0 V)
D (%) = 100 ´
2.5 ´ (IOLC(n) at VCC = 3.0 V)
Where 2.5 is the difference between the maximum and minimum VCC voltage.
(5) Load regulation is calculated by the equation:
(IOLC(n) at VOUTn = 3 V) - (IOLC(n) at VOUTn = 0.8 V)
D (%) = 100 ´
2.2 ´ (IOLC(n) at VOUTn = 0.8 V)
Where 2.2 is the difference between the maximum and minimum VCC voltage.
(6) Not tested; specified by design.
SWITCHING CHARACTERISTICS (See Figure 1, Figure 2, and Figure 5 through Figure 7)
At VCC = 3 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1.3 kΩ, and VLED = 5.0 V.
Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5929
PARAMETER
TEST CONDITIONS
MIN
TYP
3
MAX
10
UNIT
ns
tR0
tR1
tF0
tF1
tD0
SOUT
Rise time
OUTn, BC = 7Fh, TA = +25°C
SOUT
23
3
60
ns
10
ns
Fall time
OUTn, BC = 7Fh, TA = +25°C
SCLK↑ to SOUT↑↓
31
15
60
ns
25
ns
LAT↑ or BLANK↑↓ to OUT0 sink current on/off,
BC = 7Fh
tD1
35
3
65
11
ns
ns
ns
µs
ns
tD2
Propagation delay
OUTn on/off to OUTn + 1 on/off, BC = 7Fh
LAT↑ to power-save mode by data writing for all output
off
tD3
300
20
tD4
SCLK↑ to normal mode operation
Output on/off data = all '1', BLANK low pulse = 40 ns, BC
= 7Fh
tON_ERR
Output on-time error(1)
–30
20
Internal oscillator
frequency
fOSC
12
20
28
MHz
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – 40 ns. tOUTON is the actual on-time of OUTn.
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PARAMETER MEASUREMENT INFORMATION
TEST CIRCUITS
RL
CL
VCC
GND
VCC
IREF
OUTn
VLED
(1)
RIREF
(1) CL includes measurement probe and jig capacitance.
Figure 1. Rise Time and Fall Time Test Circuit for OUTn
VCC
SOUT
VCC
(1)
CL
GND
(1) CL includes measurement probe and jig capacitance.
Figure 2. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
OUTn
VCC
IREF
RIREF
GND OUT15
VOUTn
VOUTfix
Figure 3. Constant-Current Test Circuit for OUTn
6
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SBVS159 –APRIL 2011
PARAMETER MEASUREMENT INFORMATION (continued)
TIMING DIAGRAMS
tWH0, tWL0, tWH1, tWH2, tWL2
:
VIH
Input(1) 50%
VIL
tWH
tWL
tSU0, tSU1, tH0, tH1
:
VIH
SCLK Input(1)
50%
VIL
tSU
tH
VIH
SIN/LAT Input(1)
50%
VIL
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 4. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2
:
VIH
Input(1)
50%
VIL
tD
VOH or VOUTnH
90%
50%
10%
Output
VOL or VOUTnL
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 5. Output Timing
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PARAMETER MEASUREMENT INFORMATION (continued)
DATA
0A
DATA
16B
DATA
15B
DATA DATA
14B
13B
DATA
12B
DATA
3B
DATA DATA
2B 1B
DATA
0B
DATA
16C
DATA
15C
DATA DATA DATA
14C 13C 12C
DATA
11C
SIN
SCLK
LAT
tH0
tH1
tSU0
tWH0
tSU1
1
2
3
4
5
1
2
3
4
5
6
14
15
16
17
tWH1
tWL0
Shift Register
DATA
0A
SID
DATA DATA
DATA DATA
14B
13B
DATA DATA
3B
2B
DATA DATA
DATA
DATA
DATA DATA
14C 13C
DATA
12C
Selected SID 0B
Selected SID 1B
0A
16B
15B
1B
0B
16C
15C
LSB Data (Internal)
Shift Register
DATA
1A
SID
1A
SID
0A
DATA
16B
DATA DATA
DATA DATA
DATA DATA
2B 1B
SID
0B
DATA
16C
DATA DATA
DATA
13C
15B
14B
4B
3B
15C
14C
LSB + 1 Data (Internal)
Shift Register
DATA
15A
SID
15A
SID
14A
SID
13A
SID
12A
SID
11A
SID
1A
SID
0A
DATA DATA
SID
14B
SID
13B
SID
12B
SID
11B
SID
10B
Selected SID 15B
16B
15B
MSB - 1 Data (Internal)
Shift Register
DATA
SID
15A
SID
14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
DATA 16B
16A
MSB Data (Internal)
Output On/Off
DATA 15A to DATA 0A
DATA 15B to DATA 0B
Data Latch (Internal)
Control
Latest Control Data
Data Latch (Internal)
DATA
16A
SID
15A
SID
14A
SID
13A
SID
12A
SID
2A
SID
SID
SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
DATA 16B
SOUT
1A
0A
tD0
tR0/tF0
tWH2
BLANK
tWL2
tD1
ON
tD1
VOUTnH
OFF
OFF
(1)
VOUTnL
ON
OUTn
ON
tOUTON
OFF
tD2
tD2
ON
OFF
OUTn + 1(1)
ON
ON
tD1
OFF
OFF
(2)
ON
OUTn
ON
tF1
tD1
OFF
OFF
OFF
OFF
(3)
ON
ON
tR1
OUTn
ON
OFF
OFF
OFF
(4)
OUTn
ON
(1) On/off latched data is '1'.
(2) On/off latched data change from '1' to '0' at second LAT signal.
(3) On/off latched data change from '0' to '1' at second LAT signal.
(4) On/off latched data is '0'.
Figure 6. Write for On/Off Data and Output Timing
8
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SBVS159 –APRIL 2011
PARAMETER MEASUREMENT INFORMATION (continued)
Low
SIN
SCLK
LAT
1
2
3
15 16
17
1
2
3
4
5
6
BLANK
Don’t Care
‘1’
PSMODE Bit in
Control Data Latch
(Internal)
Previous On/Off Data
All Data are ‘0’
On/Off Control
Data Latch (Internal)
OFF
OFF
OUT0
OUT1
ON
OFF
OFF
ON
OFF
ON
OFF
OUT15
Power-Save
Mode
Normal Mode
Normal Mode
Power-Save Mode
Normal Mode
tD3
tD4
More Than 100mA
ICC
(VCC Current)
Less Than 100mA
Figure 7. Power-Save Mode Timing
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PIN CONFIGURATIONS
SSOP/QSOP-24
DBQ PACKAGE
(TOP VIEW)
GND
SIN
1
2
3
4
5
6
7
8
9
24 VCC
23 IREF
SCLK
LAT
22 SOUT
21 BLANK
20 OUT15
19 OUT14
18 OUT13
17 OUT12
16 OUT11
15 OUT10
14 OUT9
13 OUT8
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5 10
OUT6 11
OUT7 12
HTSSOP-24
PWP PACKAGE
(TOP VIEW)
GND
SIN
1
2
3
4
5
6
7
8
9
24 VCC
23 IREF
SCLK
LAT
22 SOUT
21 BLANK
20 OUT15
19 OUT14
18 OUT13
17 OUT12
16 OUT11
15 OUT10
14 OUT9
13 OUT8
OUT0
OUT1
OUT2
OUT3
OUT4
PowerPAD
(Bottom Side)
OUT5 10
OUT6 11
OUT7 12
10
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SBVS159 –APRIL 2011
PIN DESCRIPTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
Blank all outputs. When BLANK is high, all constant-current outputs (OUT0 to OUT15) are forced off.
BLANK
21
I
When BLANK is low, all constant-current outputs are controlled by the on/off control data in the data
latch.
Maximum current programming terminal. A resistor connected between IREF and GND sets the
maximum current for every constant-current output. When this terminal is directly connected to GND,
all outputs are forced off. The external resistor should be placed close to the device and must be in the
range of 1.32 kΩ to 66.0 kΩ.
IREF
LAT
23
4
I/O
I
Data latch. The rising edge of LAT latches the data from the common shift register into the output
on/off data latch. At the same time, the data in the common shift register are replaced with SID, which
is selected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID)
section for more details.
GND
1
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Ground
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Constant-current sink outputs. Multiple outputs can be configured in parallel to increase the
constant-current capability. Different voltages can be applied to each output.
Serial data shift clock. Data present on SIN are shifted to the LSB of the 17-bit shift register with the
SCLK rising edge. Data in the shift register are shifted toward the MSB at each SCLK rising edge. The
MSB data of the common shift register appear on SOUT.
SCLK
SIN
3
2
I
I
Serial data input for the 17-bit common shift register. When SIN is high, a '1' is written to the LSB of
the common shift register at the rising edge of SCLK.
Serial data output of the 17-bit common shift register. SOUT is connected to the MSB of the 17-bit shift
register. Data are clocked out at the rising edge of SCLK.
SOUT
VCC
22
24
O
—
Power-supply voltage
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FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
16-bit LOD, LSD, or OLD data
Reset
UVLO
LSB
MSB
SIN
SOUT
Load
Select
Common Shift Register
0
16
Bit16
SCLK
2
16
LSB
MSB
All Off
Output On/Off Data Latch
16
0
15
16
MSB
LSB
Function Control Data Latch
(Global Brightness Control, LSD Voltage Select,
Loaded Error Select, and Other Function Controls)
16
LAT
2
15
BC
0
7
3
1
Error
Select
BLANK
SID
Selector
2
2
To all
Analog
Circuits
Power-
Save
Control
IDM Timing
Control
OSC
Temp
Error
Status
ISF
Reset
165°C
138°C
Thermal
Detector
16
2
SID
Holder
On/Off Control with Output Delay
16
ISF
BC
Reference
Current
Control
IREF
16-Channel, Constant-Current Sink Driver
with 7-Bit Global Brightness Control
16
Error
Select
VLSD
Select
LED Open Detection (LOD)
LED Short Detection (LSD)
Output Leakage Detection (OLD)
Detection
Voltage
GND
GND
OUT0
OUT1
OUT2
OUT13 OUT14 OUT15
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TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR
vs OUTPUT CURRENT
OUTn CURRENT vs
OUTPUT VOLTAGE (+3.3 V)
60
50
40
30
20
10
0
100
10
1
VCC = 3.3 V, BC = 7Fh, VOUTn = 0.8 V
66.0
33.0
IOLCMax = 40 mA
13.2
IOLCMax = 30 mA
6.60
IOLCMax = 20 mA
4.40
3.30
2.64
2.20
IOLCMax = 2 mA
IOLCMax = 10 mA
IOLCMax = 5 mA
1.89
1.65
40
IOLCMax = 1 mA
1.47
1.32
0
0.5
1.0
1.5
2.0
2.5
3.0
0
10
20
30
50
Output Voltage (V)
IOLCMax (V)
Figure 8.
Figure 9.
OUTn CURRENT vs
OUTPUT VOLTAGE (+3.3 V)
OUTn CURRENT vs
OUTPUT VOLTAGE (+5 V)
46
45
44
43
42
41
40
39
38
60
50
40
30
20
10
0
VCC = 3.3 V
VCC = 5 V, BC = 7Fh, VOUTn = 0.8 V, (50 mA = 1 V)
BC = 7Fh
RIREF = 1.58 kW
IOLCMax = 50 mA
IOLCMax = 40 mA
VOUTn = 0.8 V
IOLCMax = 30 mA
IOLCMax = 20 mA
TA = -40°C
TA = +25°C
TA = +85°C
IOLCMax = 2 mA
IOLCMax = 10 mA
IOLCMax = 5 mA
IOLCMax = 1 mA
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
Figure 10.
Figure 11.
CONSTANT-CURRENT ERROR
OUTn CURRENT vs
OUTPUT VOLTAGE (+5 V)
vs OUTPUT CURRENT SET BY RIREF or BC DATA
(Channel-to-Channel)
56
55
54
53
52
51
50
49
48
3
2
VCC = 5 V
BC = 7Fh
BC = 7Fh
VOUTn = 0.8 V
RIREF = 1.28 kW
(50 mA = 1 V)
VOUTn = 1 V
1
0
-1
-2
-3
TA = -40°C
TA = +25°C
TA = +85°C
VCC = 3.3 V
VCC = 5 V
0
0.5
1.0
1.5
2.0
2.5
3.0
0
10
20
30
40
50
Output Voltage (V)
Output Current (mA)
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
CONSTANT-CURRENT ERROR
vs AMBIENT TEMPERATURE (Channel-to-Channel)
GLOBAL BRIGHTNESS
CONTROL LINEARITY
3
2
60
50
40
30
20
10
0
RIREF = 1.6 kW
VCC = 3.3 V
VCC = 5 V
IO = 2 mA
VOUTn = 0.8 V
IO = 5 mA
1
IO = 10 mA
IO = 20 mA
IO = 40 mA
IO = 50 mA
0
-1
-2
-3
VCC = 3.3 V
VCC = 5 V
-40
-20
0
20
40
60
80
100
0
16
32
48
64
80
96
112
128
Temperature (°C)
BC Data (Decimal)
Figure 14.
Figure 15.
SUPPLY CURRENT
vs OUTPUT CURRENT SET BY RIREF
SUPPLY CURRENT
vs AMBIENT TEMPERATURE
16
14
12
10
8
14
12
10
8
BC = 7Fh
RIREF = 1.6 kW
SIN = 17.5 MHz
SCLK = 35 MHz
All Outputs On
6
6
BC = 7Fh
RIREF = 1.6 kW
4
4
SIN = 17.5 MHz
SCLK = 35 MHz
All Outputs On
VCC = 3.3 V
VCC = 3.3 V
VCC = 5 V
2
2
VCC = 5 V
0
0
0
10
20
30
40
50
-40
-20
0
20
40
60
80 100
Output Current (mA)
Ambient Temperature (°C)
Figure 16.
Figure 17.
SUPPLY CURRENT IN POWER-SAVE MODE
vs AMBIENT TEMPERATURE
CONSTANT-CURRENT OUTPUT
VOLTAGE WAVEFORM
30
25
20
15
10
5
CH1 (5 V/div)
CH2 (2 V/div)
BC = 7Fh
CH1-BLANK
RIREF = 1.6 kW
CH2-OUT0
SIN = SCLK = Low
Power-Save Mode
CH3 (2 V/div)
CH4 (2 V/div)
CH3-OUT1
CH4-OUT15
VLED = 5 V
RL = 100W
CL = 15pF
VCC = 3.3 V
VCC = 3.3 V
VCC = 5 V
BC = 7Fh
RIREF = 1.6 kW
0
Time (20ns/div)
-40
-20
0
20
40
60
80
100
Ambient Temperature (°C)
Figure 18.
Figure 19.
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DETAILED DESCRIPTION
MAXIMUM CONSTANT SINK CURRENT
The maximum output current of each channel (IOLCMax) is programmed by a single resistor (RIREF) that is placed
between the IREF and GND pins. The current value can be calculated by Equation 1:
VIREF
RIREF
=
´ 54.8
IOLCMax
Where:
VIREF = the internal reference voltage on IREF (typically 1.205 V when the global brightness control data are
at maximum.
IOLCMax = 1 mA to 40 mA for VCC ≤ 3.6 V, or 1 mA to 50 mA for VCC > 3.6 V at OUT0 to OUT15 with BC =
7Fh
(1)
IOLCMax is the highest current for each output. Each output sinks IOLCMax current when it is turned on with the
maximum global brightness control (BC) data. Each output sink current can be reduced by lowering the global
brightness control value. RIREF must be between 1.32 kΩ and 66.0 kΩ in order to hold IOLCMax between 50 mA
(typ) and 1 mA (typ). Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved
by setting IOLCMax to 1 mA or higher and then using the global brightness control to lower the output current.
Figure 8 and Table 1 show the characteristics of the constant-current sink versus the external resistor, RIREF
.
Table 1. Maximum Constant Current Output versus
External Resistor Value
IOLCMax (mA)
RIREF (kΩ, typ)
1.32
50 (VCC > 3.6 V only)
45 (VCC > 3.6 V only)
1.47
40
35
30
25
20
15
10
5
1.65
1.89
2.20
2.64
3.30
4.40
6.60
13.2
2
33.0
1
66.0
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GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION
The TLC5929 has the ability to adjust the output current of all constant current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) can be set with
a 7-bit word. The global BC adjusts all output currents in 128 steps from 0% to 100%. where 100% corresponds
to the maximum output current set by RIREF. Equation 2 calculates the actual output current. BC data can be set
via the serial interface.
IOLCMax (mA) ´ BC
IOLCn (mA) =
127
Where:
IOLCMax = the maximum constant-current value for each output determined by RIREF
BC = the global brightness control value in the control data latch (0h to 7Fh)
.
(2)
Table 2 shows the BC data versus the constant-current ratio against IOLCMAx
.
Table 2. BC Data versus Constant-Current Ratio Against IOLCMAx
BC DATA
RATIO OF OUTPUT
CURRENT TO IOLCMax
(%)
IOLC
IOLC
BINARY
000 0000
000 0001
000 0010
∙ ∙ ∙
DECIMAL
HEX
00
(mA, IOLCMax= 40mA, typ) (mA, IOLCMax= 1mA, typ)
0
0
0
0
1
01
0.8
0.31
0.63
∙ ∙ ∙
0.01
0.02
∙ ∙ ∙
2
02
1.6
∙ ∙ ∙
125
126
127
∙ ∙ ∙
7D
7E
7F
∙ ∙ ∙
111 1101
111 1110
111 1111
98.4
99.2
100.0
39.4
39.7
40.0
0.98
0.99
1.00
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REGISTER AND DATA LATCH CONFIGURATION
The TLC5929 has one common shift register and two control data latches. The common shift register is 17-bits
long and the two control data latches are 16-bits long. When the MSB of the common shift register is '0' and LAT
shows a rising edge, the lower 16 bits of the common shift register are copied into the output on/off data latch.
When the MSB is '1' and LAT shows a rising edge, the lower 16 bits are copied into the control data latch.
Figure 20 shows the configuration of the common shift register and the two control data latches.
SID 16 Bits
Common Shift Register (17 Bits)
MSB
LSB
Latch Common Common Common Common Common
Select Data Bit Data Bit Data Bit Data Bit Data Bit
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
SIN
SOUT
SCLK
Bit
15
14
13
12
11
4
3
2
1
0
16
15
14
13
12
11
3
2
1
0
4
Lower 16 Bits
Output On/Off Data Latch (16 Bits)
MSB
LSB
This latch pulse
comes from the
OUTON OUTON OUTON OUTON OUTON
14
OUTON OUTON OUTON OUTON OUTON
3
LAT pin when the
MSB of the Common
Shift Register is ‘0’.
15
13
12
11
4
2
1
0
15
14
13
12
11
3
2
1
0
4
16 Bits
To
Output On/Off
Control Circuit
16 Bits
Control Data Latch (16 Bits)
MSB
LSB
This latch pulse
comes from the
Power-
IDM
IDM
IDM
IDM
LSD
LSD
SID
Load
SID
Load
Brightness
Control
Enable Time 1 Time 0 Select 1 Select 0 Voltage 1 Voltage 0 Control 1 Control 0 (BC) 6
Brightness
Control
LAT pin when the
MSB of the Common
Shift Register is ‘1’.
Save Working Working Current Current
Detect
Detect
(BC) 0
15
14
13
12
11
10
9
7
6
0
8
1 Bit
2 Bits
2 Bits
2 Bits
2 Bits
7 Bits
To
To
IDM
To
IDM
To
LSD
To
SID
To
Output
Power-Save
Mode
Control Circuit Control Circuit
Working Time
Current
Control Circuit
Circuit
Data Load
Control Circuit
Constant-Current
Control Circuit
Figure 20. Common Shift Register and Control Data Latches Configuration
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Common Shift Register
The 17-bit common shift register is used to shift data from the SIN pin into the TLC5929. The data shifted into
the register are used for the output on/off control, global BC, and the control functions. The LSB of the common
shift register is connected to SIN and the MSB is connected to SOUT. On each rising edge of SCLK, the data on
SIN are shifted into the LSB and all 17 bits are shifted towards the MSB. The register MSB is always connected
to SOUT.
In addition, the status information data (SID) selected by the load select data in the control data latch are loaded
to the lower 16 bits of the common shift register when a rising edge is input on LAT and the MSB of the shift
register is '0'.
When the device is powered on, all 17 bits of the common shift register are set to '0'.
Output On/Off Data Latch
The output on/off data latch is 16 bits long and sets the on or off status for each constant-current output.
When BLANK is low, the output corresponding to the specific bit in the output on/off data latch is turned on if the
data is '1' and remains off if the data is '0'. When BLANK is high, all outputs are forced off, but the data in the
latch do not change as long as LAT does not latch in new data.
When the device is powered on, all bits in the data latch are set to '0'.
The output on/off data latch configuration is shown in Figure 21 and the data bit assignment is shown in Table 3.
From
Common Shift
Register
16 Bits
Output On/Off Data Latch (16 Bits)
MSB
LSB
OUTON OUTON OUTON OUTON OUTON
OUTON OUTON OUTON OUTON OUTON
15
14
13
12
11
4
3
2
1
0
15
14
13
12
11
3
2
1
0
4
16 Bits
To
Output On/Off
Control Circuit
Figure 21. Output On/Off Data Latch Configuration
Table 3. On/Off Control Data Latch Bit Assignment
CONTROLLED
BIT NUMBER
BIT NAME
OUTON0
OUTON1
OUTON2
∙ ∙ ∙
CHANNEL
OUT0
OUT1
OUT2
∙ ∙ ∙
DESCRIPTION
0
1
'0' = Output off
2
∙ ∙ ∙
'1' = Output on with BLANK low. When
the device is powered on, all bits are set
to '0'.
13
OUTON13
OUT13
14
15
OUTON14
OUTON15
OUT14
OUT15
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Function Control Data Latch
The function control data latch is 16 bits long and contains the global brightness control (BC) data, status
information data (SID) load control data, LED short detection (LSD) voltage level data, the current value of the
invisible detection mode (IDM), IDM working time, and power-save mode enable control data.
When the device is powered up, the data in this data latch are set to the default values shown in Table 4. This
table contains the bit names, numbers and descriptions.
The function control data latch configuration is shown in Figure 22. Table 4 lists the bit descriptions.
From Common Shift Register
16 Bits
Control Data Latch (16 Bits)
MSB
LSB
Power-
IDM
IDM
IDM
IDM
LSD
LSD
SID
SID
Brightness
Control
Brightness
Control
Save Working Working Current Current Detect
Detect
Load
Load
Enable Time 1 Time 0 Select 1 Select 0 Voltage 1 Voltage 0 Control 1 Control 0 (BC) 6
(BC) 0
15
14
13
12
11
10
9
7
6
0
8
1 Bit
2 Bits
2 Bits
2 Bits
2 Bits
7 Bits
To
Power-Save
Mode
Control Circuit Control Circuit
To
IDM
Working Time
To
IDM
Current
Control Circuit
To
LSD
Circuit
To
SID
Data Load
Control Circuit
To
Output
Constant-Current
Control Circuit
Figure 22. Function Control Data Latch Configuration
Table 4. Function Control Data Latch Bit Description
DEFAULT
VALUE
BIT
BIT
NUMBER
NAME
(BINARY)
DESCRIPTION
Global brightness control. These seven bits control the current of all outputs
with 128 steps between 0% to 100% of the maximum current value set by the
external resistor. Table 2 shows the current value truth table.
[6:0]
[8:7]
BCALL
SIDLD
1111111
SID load control. These two bits select the SID loaded to the common register
when the LAT pulse is input for on/off data writing (MSB of the common shift
register must be '0'). Table 6 shows the selected data truth table.
00
11
LSD detection voltage select. These two bits select the detection threshold
voltage for the LED short detection (LSD). Table 7 shows the detect voltage
truth table.
[10:9]
LSDVLT
IDM current select. These two bits select the sink current at OUTn for the IDM
to detect the LED open detection (LOD) or the LED short detection (LSD)
without visible lighting. Table 8 shows the current value truth table. Figure 27
and Figure 28 show the IDM operation timing.
[12:11]
[14:13]
[15]
IDMCUR
IDMTIM
00
11
1
IDM working time select. These two bits select the time of the IDMCUR output
sink current at OUTn to detect the LED open detection (LOD) or LED short
detection (LSD) without visible light. Table 9 shows the work-time truth table.
Figure 27 and Figure 28 show the IDM operation timing.
Power save mode enable. This bit enables or disables the power-save mode.
When the mode is enabled (PSMODE = '1'), the device goes into power-save
mode if all data in the on/off data latch are '0'. Table 10 shows the power-save
mode truth table. Figure 25 shows the power-save mode operation timing.
PSMODE
Output On/Off Data Write Timing and Output Control
When the 17-bit shift register MSB is '0', the output on/off data latch can be updated with the lower 16 bits of
data in the shift register at the rising edge of the LAT signal, after the data are stored in the shift register using
the SIN and SCLK signals. When the output on/off data latch is updated, SID (selected by the SIDLD bit) is
loaded into the shift register, except when SIDLD = '00' (see Table 6). The output on/off data write timing is
shown in Figure 23.
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DATA DATA DATA DATA DATA DATA
0A 16B 15B 14B 13B 12B
Low
DATA DATA DATA DATA
3B 2B 1B 0B
DATA DATA DATA DATA DATA DATA
15C 14C 13C 12C 11C
SIN
16C
High
SCLK
LAT
1
2
3
4
5
1
2
3
4
5
6
14
15
16
17
Shift Register
LSB Data
SID
0A
SID
0B
DATA
0A
DATA DATA DATA DATA
16B
DATA DATA DATA DATA DATA
15C
DATA DATA DATA
1B
DATA
0B
15B
14B
13B
3B
2B
16C
14C 13C 12C
(Internal)
‘0’
‘1’
Shift Register
LSB + 1 Data
(Internal)
DATA
16B
SID
1A
SID
1B
DATA
1A
SID
0A
DATA DATA
15B
14B
DATA DATA DATA DATA
1B
SID DATA DATA DATA DATA
0B
16C
15C
14C 13C
4B
3B
2B
‘0’
‘1’
Shift Register
MSB - 1 Data
(Internal)
DATA
15A
SID
15A
SID
15B
SID
14A
DATA DATA
12A
SID
1A
SID DATA
0A
SID SID
14B 13B
SID
12B
SID SID
11B 10B
DATA
13A
DATA
15B
11A
16B
‘0’
Shift Register
MSB Data
(Internal)
DATA
16A
DATA
16B
SID SID
15A 14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
SID SID
15B 14B
SID
13B
SID SID
12B 11B
‘0’
‘0’
Output On/Off
Data Latch
(Internal)
DATA15B to DATA0B
DATA15A to DATA0A
Control
Data Latch
(Internal)
Control data do not change from previous data
DATA
16B
DATA
16A
SID
2A
SID
1A
SID
0A
SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
SID
15A
SID
14A
SID SID
13A 12A
SOUT
Low
Low
BLANK
OFF
ON
OFF
OFF
(1)
OUTn
ON
ON
OFF
ON
OFF
(2)
OUTn
ON
OFF
ON
OFF
OFF
OFF
ON
(3)
OUTn
ON
OFF
ON
OFF
(4)
OUTn
These dotted arrows point to the
output pulse timing for IDM.
(1) On/off latch data is '1'.
(2) On/off latch data change from '1' to '0' at second LAT signal.
(3) On/off latch data is change from '0' to '1' at second LAT signal.
(4) On/off latch data is '0'.
Figure 23. On/Off Data Write Timing
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Function Control Data Writing
When the MSB is 1' in the 17-bit shift register, the control data latch can be updated with the lower 16 bits of
data in the shift register at the rising edge of the LAT signal after the data are stored to the shift register using
the SIN and SCLK signals. When the control data latch is updated, SID is not loaded into the shift register. The
function control data write timing is shown in Figure 24.
DATA DATA DATA DATA DATA DATA
12B
DATA DATA DATA DATA
3B 2B 1B 0B
DATA DATA DATA DATA DATA DATA
15C 14C 13C 12C 11C
SIN
0A
16B
15B
14B
13B
16C
Low
High
SCLK
LAT
1
2
3
4
5
1
2
3
4
5
6
14
15
16
17
Shift Register
LSB Data
SID
0A
DATA
0B
DATA
0A
DATA DATA DATA DATA
16B
DATA DATA DATA
3B 2B 1B
DATA DATA DATA DATA DATA
16C
15B
14B
13B
15C
14C 13C 12C
(Internal)
‘1’
‘0’
Shift Register
LSB + 1 Data
(Internal)
SID
1A
DATA
1A
SID
0A
DATA DATA
15B
DATA DATA DATA DATA DATA
14C 13C
DATA
16B
DATA DATA DATA
2B
DATA
1B
14B
0B
16C
15C
4B
3B
‘1’
‘0’
Shift Register
MSB - 1 Data
(Internal)
DATA
15A
SID
15A
SID DATA DATA DATA
14A
SID
1A
SID DATA
0A
DATA
15B
DATA DATA DATA DATA DATA
14B 13B 12B 11B 10B
13A
12A
11A
16B
‘1’
Shift Register
MSB Data
(Internal)
DATA
16A
SID SID
15A 14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
DATA DATA DATA DATA DATA
15B 14B 13B 12B 11B
DATA
16B
‘0’
‘1’
Output On/Off
Data Latch
(Internal)
DATA15A to DATA0A
DATA15B to DATA0B
DATA15A to DATA0A
Function Control
Data Latch
Previous Function Control Data
(Internal)
DATA
16A
SID
2A
SID
1A
SID
0A
DATA DATA DATA DATA DATA
15B
SID
15A
SID
14A
SID SID
13A 12A
DATA
16B
SOUT
14B
13B
12B
11B
Low
High
Figure 24. Function Control Data Write Timing
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Function Control Data Bit Assignment
The function control data latch is 16 bits long and is used to adjust the output current values for LED brightness,
SID selection, LSD voltage level, output current for IDM, output on-time for IDM, and power-save mode
enable/disable. When the device powers on, the function control data latch is set to the default value (E67Fh).
The function control data latch truth tables are shown in Table 5 through Table 10.
Table 5. Global Brightness Control (BC) Truth Table
BCALL
BITS[6:0]
0000000
0000001
∙ ∙ ∙
DESCRIPTION
Output current of OUTn is set to IOLCMax × 0%
IOLCMax × 0.8%
∙ ∙ ∙
1111110
1111111
I
OLCMax × 99.2%
I
OLCMax × 100% (default value)
Table 6. SID Load Control Truth Table (see Table 11 for more details)
SIDLD
LSDVLT
IDMCUR
IDMTIM
BIT 8
BIT 7
STATUS INFORMATION DATA (SID) LOADED TO THE COMMON SHIFT REGISTER
No data is loaded (default value)
0
0
1
1
0
1
0
1
LED open detection (LOD) or thermal error flag (TEF) data are loaded
LED short detection (LSD) or pre-thermal flag (PTF) data are loaded
Output leakage detection (OLD) or IREF pin short flag (ISF) data are loaded
Table 7. LSD Threshold Voltage Truth Table
BIT 10
BIT 9
LED SHORT DETECTION (LSD) THRESHOLD VOLTAGE
VLSD0 (0.35 × VCC typ)
0
0
1
1
0
1
0
1
VLSD1 (0.45 × VCC typ)
VLSD2 (0.55 × VCC typ)
VLSD3 (0.65 × VCC typ, default value)
Table 8. Current Select for IDM
BIT 12
BIT 11
SINK CURRENT AT OUTn FOR INVISIBLE DETECTION MODE (IDM)
0
0
1
1
0
1
0
1
IDM is disabled (default value)
2 µA (typ)
10 µA (typ)
20 µA (typ)
Table 9. IDM Work-Time Truth Table
BIT 14
BIT 13
INVISIBLE DETECTION MODE (IDM) WORKING TIME
All outputs are turned on for 17 OSC clocks (0.85 µs typ)
All outputs are turned on for 33 OSC clocks (1.65 µs typ)
All outputs are turned on for 65 OSC clocks (3.25 µs typ)
All outputs are turned on for 129 OSC clocks (6.45 µs typ, default value)
0
0
1
1
0
1
0
1
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Table 10. Power-Save Mode Truth Table
PSMODE
BIT 15
POWER-SAVE MODE FUNCTION
Power-save mode is disabled. The device does not go into power-save mode even if the bits
in the output on/off data latch are all '0'.
0
1
Power save mode is enabled (default value). The device goes into power-save mode when
the bits in the output on/off data latch are all '0'.
Table 11. SID Load Assignment
BIT NUMBER
LOADED INTO
COMMON SHIFT
SIDLD BIT
(BINARY)
SELECTED
DETECTOR
CHECKED OUTn
REGISTER
DESCRIPTION
No detector
selected
00
—
No data loaded The data in the common shift register are not changed.
The data in the common shift register are updated with LOD or
TEF data.
OUT0
0
OUT1
1
All bits '1' = device junction temperature (TJ) is very high (TJ >
TTEF) and all outputs are forced off by the thermal shutdown
function.
LED open
detection (LOD)
01
∙ ∙ ∙
∙ ∙ ∙
'1' = OUTn shows lower voltage than the LED open detection
threshold (VLOD).
OUT14
OUT15
OUT0
14
15
0
'0' = normal operation.
The data in the common shift register are updated with LSD or
PTW data.
OUT1
1
All bits '1' = device junction temperature (TJ) is high (TJ > TPTW).
LED short
detection (LSD)
10
11
∙ ∙ ∙
∙ ∙ ∙
'1' = OUTn shows higher voltage than the LED short detection
threshold (VLSD) selected by LSDVLT.
OUT14
OUT15
OUT0
14
15
0
'0' = normal operation.
The data in the common shift register are updated with OLD or
ISF data.
OUT1
∙ ∙ ∙
1
All bits '1' = IREF pin is shorted to GND with low impedance.
'1' = OUTn is leaking to GND with greater than 3µA.
'0' = normal operation.
Output leakage
detection (OLD)
∙ ∙ ∙
14
15
OUT14
OUT15
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POWER-SAVE MODE
In power-save mode, the TLC5929 input current becomes 10 µA (typ). When the PSMODE bit in the control data
latch is '1', power-save mode is enabled. If the rising edge of LAT writes '0' into all bits of the output on/off data
latch or any data into the control data latch with all bits of the on/off data latch being '0', the TLC5929 goes into
power-save mode. The device stays in power-save mode until the next rising edge on SCLK is received. The
power-save mode timing is shown in Figure 25.
Low
SIN
SCLK
1
2
3
4
5
1
2
3
14
15
16
17
LAT
Don’t Care
BLANK
‘1’
PSMODE bit
in Control Data
Latch (Internal)
Output On/Off
Control Data
Previous On/Off Data
All Data are ‘0’
Latch (Internal)
OFF
OFF
OUT0
OUT1
ON
OFF
OFF
ON
OFF
ON
OFF
OUT15
Power-Save
Mode
Power-Save mode(2) (ICC = 10 mA,typ)
See (1)
Normal mode
Normal mode
Normal Mode
(1) Contents depend on output on/off data.
(2) When PSMODE bit is '0', the device does not go into power-save mode even if the output on/off data is all '0'.
(3) Because it takes 20 µs (max) to return to normal mode, the first SCLK rising edge should be input at least 20 µs before OUTn is enabled.
Figure 25. Power-Save Mode Timing
LED OPEN DETECTION (LOD)
LOD detects a fault caused by an open circuit in the nth LED string, or a short from OUTn to ground, by
comparing the OUTn voltage to the LOD detection threshold voltage level (VLOD = 0.3 V, typ). If the OUTn
voltage is lower than VLOD, that output LOD bit is set to '1' to indicate an open LED string. Otherwise, the LOD bit
is set to '0'. LOD data are only valid for outputs that are programmed to be enabled. LOD data for outputs that
are programmed to be disabled are always '0' (see Table 11), except when IDM is enabled.
The LOD data are stored in a 16-bit register called SID holder (see the Functional Block Diagram) at the rising
edge of BLANK when the SIDLD bits are set to '01' (see Table 6). However, when the IDM is enabled, the LOD
bits are stored in the SID holder at the end of the IDM working time selected by IDMTIM (see Table 9).
The stored LOD data can be read out through the common shift register as SID at the SOUT pin. LOD/LSD data
are not valid for 0.5 µs after the output is turned on.
When the device resumes operation from power-save mode, the LOD cannot be executed before the
propagation delay (tD4) has elapsed because LOD does not work during power-save mode.
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LED SHORT DETECTION (LSD)
The LSD data are stored into a 16-bit register called SID holder at the rising edge of BLANK when the SIDLD
bits are set to '10' (see Table 6) or when IDM is enabled. The LSD bits are stored in the SID holder at the end of
the IDM working time (IDMTIM). The stored LSD data can be read out through the common shift register as SID
at the SOUT pin. Note that the LOD/LSD bits are not stable during the first 0.5 µs after the falling edge of
BLANK.
LSD data detect a fault caused by a shorted LED by comparing the OUTn voltage to the LSD detection threshold
voltage level set by LSDVLT in the control data latch (see Table 4 and Table 7). If the OUTn voltage is higher
than the programmed voltage, the corresponding output LSD bit is set to '1' to indicate a shorted LED.
Otherwise, the LSD bit is set to '0'. LSD data are only valid for outputs that are programmed to be enabled. LSD
data for outputs that are programmed to be disabled are always '0' (see Table 11), except when IDM is enabled.
When the device resumes operation from the power-save mode, LSD cannot be executed before the propagation
delay (tD4) has elapsed because LSD does not work during power-save mode.
INVISIBLE DETECTION MODE (IDM)
Invisible detection mode (IDM) can detect LOD and LSD even when the output on/off data are set to the off
state. When the IDMCUR bits in the control data latch are set to any value except '00', all outputs start sinking
the current set by the IDMCUR bits at the falling edge of BLANK and stop sinking the current at the rising edge
of BLANK, or the time set by IDMTIM has elapsed. When OUTn stops, the selected SID data by SIDLD bits are
latched into the SID holder.
When the IDMCUR bits in the control data latch are set to '00', IDM is disabled.
Figure 26 shows the LOD/LSD/OLD/IDM circuits. Figure 27 and Figure 28 illustrate the IDM operation timing and
Table 12 shows a truth table for LOD/LSD/OLD.
VCC
VLED
OLD
Control
2 mA (typ)
LED Lamp
LSD/OLD Data
‘1’ = Error
OUTn
On/Off
Control
Up to
50 mA
VLSD
2 mA/10 mA/20 mA
IDM
Control
(typ)
LOD Data
‘1’ = Error
GND
VLOD
Figure 26. LOD/LSD/OLD/IDM Circuit
Table 12. LOD/LSD/OLD Truth Table
LOD
LSD
OLD
CORRESPONDING BIT IN SID
OUTn does not leak to GND
(VOUTn > VLSD when
constant-current output off and
OUTn source current on)
LED is not opened (VOUTn
>
LED is not shorted (VOUTn ≤
0
VLOD
)
VLSD
)
Current leaks from OUTn to
internal GND, or OUTn is shorted
to external GND with high
impedance (VOUTn ≤ VLSD when
constant-current output off and
OUTn source current on)
LED is shorted between anode
and cathode, or shorted to higher
LED is open or shorted to GND
(VOUTn ≤ VLOD
1
)
voltage side (VOUTn > VLSD
)
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SIDLD in
Control Data
‘01’
Latch (Internal)
High
BLANK
Low
Current set by external
resistor and BC data
When the BLANK signal is high, all outputs
Programmed Output Current
are forced off, even if the IDM on-time has
not yet elapsed.
OUTn Current
0mA
for LED Lighting
0mA
Output current selected by
IDMCUR in the function control latch.
2/10/20 mA
2/10/20 mA
0mA
OUTn current
0mA
for IDM
LOD data are held in SID holder when
BLANK is high or when the IDM working
time elapses.
On-time selected by IDMTIM
in the function control latch.
SID Holder
LOD
Previous Data
LOD
XXXXh
LOD
XXXXh
Data (Internal)
LOD data go to SID holder when BLANK is low or when the IDM working time has not yet elapsed.
16-Bit LOD
Detector Output
Data (Internal)
LOD
0000h
LOD
0000h
LOD
0000h
LOD
XXXXh
LOD
XXXXh
LOD data are unstable
immediately after
LOD detector output data are all '0' when IDM working time elapses .
BLANK goes low.
LAT
17-Bit Common
Shift Register
Data (internal)
Latched Output On/Off Data
LOD is Loaded into the Shift Register
Figure 27. IDM Operation Timing with LOD Selected and IDM Enabled
SIDLD in
Control Data
‘01’
Latch (Internal)
High
BLANK
Low
Current set by external
When the BLANK signal is high, all outputs
resistor and BC data
Programmed Output Current
are forced off, even if the IDM on-time has
not yet elapsed.
OUTn Current
The output for IDM
0mA
for LED Lighting
0mA
is not turned on because
IDM is disabled by
the IDMCUR bit setting.
OUTn current
0mA
0mA
0mA
for IDM
LOD data are held in SID holder
when BLANK is high.
SID Holder
LOD
Previous Data
LOD
XXXXh
LOD
XXXXh
Data (Internal)
LOD data go to SID holder when BLANK is low.
16-Bit LOD
Detector Output
Data (Internal)
LOD
0000h
LOD
0000h
LOD
0000h
LOD
XXXXh
LOD
XXXXh
LOD detector output data are
all '0' when BLANK is high.
LOD data are unstable
immediately after BLANK
goes low.
LAT
17-Bit Common
Shift Register
Data (internal)
LOD is Loaded into the Shift Register
Latched On/Off Control Data
Figure 28. IDM Operation Timing with LOD Selected and IDM Disabled
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OUTPUT LEAKAGE DETECTION (OLD)
When IDM mode is enabled, OLD is always disabled.
Output leakage detection (OLD) detects a fault caused by a short with high resistance from OUTn to GND by
comparing the OUTn voltage to the LSD detection threshold voltage when the output on/off data are set to the off
state. OLD can also detect a short between adjacent pins. A very small current is sourced from the turned-off
OUTn to detect leaking when the SIDLD bits are '11' and BLANK is low. OLD operation is disabled when the
SIDLD bits are set to any value except '11', and then the current source is stopped. If the OUTn voltage is lower
than the programmed LSD threshold voltage, the corresponding OLD bit is set to '1' to indicate a leaking LED.
Otherwise, the OLD bit is set to '0'. The OLD result is valid for disabled outputs only. The OLD data are latched
into the SID holder when BLANK goes high. The OLD bits of the enabled outputs are always '0'. When the
device resumes operation from power-save mode, OLD cannot be executed until after the propagation delay (tD4
has elapsed because OLD does not work during power-save mode.
)
STATUS INFORMATION DATA (SID)
The status information data (SID) contains the status of the LED open detection (LOD), LED short detection
(LSD), output leakage detection (OLD), pre-thermal warning (PTW), thermal error flag (TEF), and IREF short flag
(ISF), depending on the SIDLD bits in the control data latch. When the MSB of the common shift register is set to
'0', the selected SID overwrite the lower 16 bits in the common shift register at the rising edge of LAT after the
data in the common shift register are copied to the output on/off data latch. If the MSB of the common shift
register is '1', the data in the common shift register do not change.
After being copied into the common shift register, new SID data are not available until new data are written into
the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID without
changing the on/off control data, reprogram the common shift register with the same data currently programmed
into the on/off data latch. When LAT goes high, the output on/off data do not change, but new SID data are
loaded into the common shift register. LOD, LSD, OLD, PTW, TEF, and ISF are shifted out of SOUT with each
rising edge of SCLK.
The SID reading must be delayed for a duration of tD4 or more after the device resumes operation from the
power-save mode because SID does not indicate correct data during the power-save mode. The SID load
configuration and SID read timing are shown in Figure 29 and Figure 30, respectively.
Selected SID (16 bits) by SIDLD Data in the Control Data Latch
MSB
LSB
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT15 OUT14 OUT13 OUT12 OUT11
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT4
OUT3
OUT2
OUT1
OUT0
15
14
13
12
11
3
2
1
0
4
SID are loaded to the
common shift register
at the rising edge of
No data are loaded
into the MSB of the
common shift register
LAT when the common
shift register MSB is ‘0’.
MSB = ‘0’
LSB
Latch Common Common Common Common Common
Select Data Bit Data Bit Data Bit Data Bit Data Bit
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
SIN
SOUT
SLCK
Bit
15
14
13
12
11
4
3
2
1
0
16
15
14
13
12
11
3
2
1
0
4
Common Shift Register (17 Bits)
Figure 29. SID Load Configuration
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High
DATA DATA DATA DATA
16C 15C 14C 13C
DATA
1A
DATA
0A
DATA DATA DATA DATA DATA
16B
DATA DATA DATA
3B 2B 1B
DATA
0B
SIN
15B
14B
13B 12B
Low
SCLK
15
16
17
1
2
3
1
2
3
4
5
14
15
16
17
LAT
Shift Register
LSB Data
DATA DATA
1A
SID
0A
SID
0B
DATA
16B
DATA
0A
DATA DATA DATA
13B
DATA DATA DATA
3B 2B 1B
DATA
0B
DATA DATA
15C
2A
15B
14B
16C
(Internal)
‘0’
‘1’
Shift Register
LSB + 1 Data
(Internal)
SID
1A
DATA
16B
DATA DATA DATA DATA
1B
SID
1B
SID DATA
16C
DATA DATA
2A
DATA
1A
DATA DATA
15B
14B
SID
0A
3A
4B
3B
2B
0B
‘1’
‘0’
Shift Register
MSB - 1 Data
(Internal)
DATA
16A
DATA
15A
SID
15A
SID DATA DATA DATA
14A
13A 12A 11A
SID
1A
SID DATA
16B
SID
15B
DATA
0
DATA
15B
SID SID
14B 13B
0A
‘0’
SID data selected by SIDLD bit is loaded into the common
shift register at LAT rising edge, except when SIDLD is ‘00’.
Shift Register
MSB Data
(Internal)
DATA
16A
DATA DATA
1
SID SID
15A 14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
DATA
16B
SID SID
15B 14B
0
‘0’
‘0’
Output On/Off
Data Latch
(Internal)
DATA15A to DATA0A
Previous On/Off Data
DATA15B to DATA0B
SIDLD in Function
Control Data
Don’t Care
Latch (Internal)
LOD data are selected when SIDLD is ‘01’. LSD data are selected when SIDLD is set to ‘10’.
OLDdata are selected when the SID are set to ‘11’. No SID are loaded when SIDLD is ‘00’.
DATA
16A
SID
2A
SID
1A
SID
0A
SID
15B
SID
14B
DATA
16B
DATA DATA
1
SID
15A
SID
14A
SID SID
13A 12A
SOUT
0
Low
Low
16 bit Status Information Data (SID)
BLANK
Detector data selected by SIDLD are held in SID holder when BLANK is high, orwhen IDM working time has elapsed.
The held data are loaded into the common shift register except when SIDLD is ‘00’.
SID Holder
Data
Detector data
XXXXh
Detector data
XXXXh
(Internal)
LOD data go to SID holder when BLANK is low,
or when IDM working time has not elapsed.
16-Bit
LOD, LSD, or OLD
Detector Output
Data (Internal)
Detector data
0000h
Detector data
0000h
Detector
XXXXh
Detector data
XXXXh
The detector data are not stable immediately
after the BLANK signal goes low.
Figure 30. SID Read Timing
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THERMAL SHUTDOWN (TSD) AND THERMAL ERROR FLAG (TEF)
The thermal shutdown (TSD) function turns off all constant-current outputs when the junction temperature (TJ)
exceeds the threshold (TTEF = +165°C, typ) and sets all LOD data bits to '1'. When the junction temperature
drops below (TTEF – THYST), the output control starts normally. The TEF remains '1' until the next rising edge on
LAT even if the temperature drops below the low level. Figure 31 shows the timing diagram and Table 13 shows
the truth table for TEF.
SCLK
LAT
Common Shift
LOD/TEF Data
Register Bits[15:0]
(Internal)
These data are copied to the on/off data latch at LAT rising edge.
Common Shift
‘0’
Register Bit 16
(Internal)
Output On/Off
Previous On/Off Data
New Latched GS Data
Data (Internal)
SIDLD Data
(Internal)
‘01’ (LOD is selected)
High
Low
BLANK
Resumed with T
J
All outputs are forced off
going down.
by TSD function.
OFF
OFF
OFF
OFF
ON
ON
ON
OUTn
T
J
³ T
T ³ T
J TEF
TEF
T
< T
- T
T
³ T
T ³ T
J PTW
J
TEF HYST
J
PTW
Device Junction
Temperature (TJ)
T
< T
T < T
J PTW
J
PTW
PTW is not reset at LAT rising edge because SIDLD
does not select LOD. PTW is reset to ‘0’ when the
device junction temperature is less than T and
PTW
SIDLD selects LOD.
‘1’
‘1’
‘1’
‘1’
PTW in SID
‘0’
TEF is reset to ‘0’at LAT riging edge for
on/off data writing when the device junction
temperature is less than T and SIDLD
(Internal Data)
PTW is set to ‘1’ when device
junction temperature is greater
than T
TEF
selects LOD.
.
‘1’
PTW
TEF in SID
‘0’
‘0’
(Internal Data)
TEF is set to ‘1’ when device junction
temperture is grerater than T
TEF
.
Figure 31. TEF/PTW/ISF Timing (LOD selected)
Table 13. TEF/PTW/ISF Truth Table
CORRESPONDING DATA BITS
IN SID
TEF
PTW
ISF
Device temperature is lower than Device temperature is lower than
high-side detect temperature pre-thermal warning temperature
(temperature ≤ TTEF (temperature ≤ TPTW
IREF terminal is not shorted
Depends on LOD/LSD/OLD
)
)
Device temperature is higher
than high-side detect
temperature and all outputs are
Device temperature is higher
than pre-thermal warning
temperature
IREF terminal is shorted to GND SID is all 1s for TEF when SIDLD
with low impedance and all
outputs (OUT0 to OUT15) are
forced off
bit = '01'. SID is all 1s for PTW
when SIDLD = '10'. SID is all 1s
for ISF when SIDLD = '11'.
forced off (temperature >TTEF
)
(temperature > TPTW
)
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PRE-THERMAL WARNING (PTW)
The PTW function indicates that the device junction temperature is high. The PTW is set and all LSD data bits
are set to '1' while the device junction temperature exceeds the temperature threshold (TPTW = +138°C, typ);
however, the outputs are not forced off. When the PTW indicates a high temperature, the device temperature
should be reduced by lowering the power dissipated in the driver to avoid a forced shutdown by the thermal
shutdown circuit. This reduction can be accomplished by lowering the values of the BC data or the LED supply
voltage. The PTW remains '1' until the next rising edge on LAT, even if the temperature drops below TPTW
.
Figure 31 shows a timing diagram and Table 13 shows the truth table for PTW.
CURRENT REFERENCE (IREF PIN) SHORT FLAG (ISF)
The ISF function indicates that the IREF pin is shorted with low impedance to GND. When ISF is set, all OLD
data bits are set to '1'. Then all outputs (OUTn) are forced off and remain off until the short is removed. Table 13
shows the truth table for ISF.
NOISE REDUCTION
Large surge currents may flow through the device and the board on which the device is mounted if all 16 outputs
turn on simultaneously when BLANK goes low or on/off data change at the LAT rising edge with BLANK low.
These large current surges could introduce detrimental noise and electromagnetic interference (EMI) into other
circuits. The TLC5929 turns the outputs on with a 2-ns series delay for each output in order to provide a circuit
soft-start feature.
30
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLC5929
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLC5929DBQ
ACTIVE
ACTIVE
SSOP/QSOP
SSOP/QSOP
DBQ
DBQ
24
24
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TLC5929DBQR
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC5929DBQR
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP/QSOP DBQ 24
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TLC5929DBQR
2500
Pack Materials-Page 2
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