TLC59291RGER [TI]
具有低静态电流和完全自诊断功能的 8/16 通道恒流 LED 驱动器 | RGE | 24 | -40 to 85;
| 型号： | TLC59291RGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低静态电流和完全自诊断功能的 8/16 通道恒流 LED 驱动器 | RGE | 24 | -40 to 85 驱动 驱动器 |
| 文件： | 总48页 (文件大小：2110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC59291
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
TLC59291 用于 LED 灯且具有 7 位亮度控制、低静态电流和完全自诊断的
8/16 通道、恒流 LED 驱动器
1 特性
2 应用范围
1
•
•
8/16 个支持开关控制的恒定灌电流输出通道
电流能力：
•
•
•
工业用 LED 指示灯
照明
LED 视频显示
–
–
1mA - 40mA (VCC ≤ 3.6V)
1mA - 50mA (VCC > 3.6V)
3 说明
•
•
•
•
全局亮度控制：7 位（128 色阶）
电源电压范围：3V 至 5.5V
LED 电源电压：高达 10V
恒定电流精度：
TLC59291 是一款 8/16 通道恒定灌电流 LED 驱动
器。每个通道可通过向内部寄存器写入数据进行开关。
所有 16 个通道的恒定电流值均由单个外部电阻设置，
并且支持 128 色阶全局亮度控制 (BC)。
–
–
通道间 = ±3%（典型值）
器件间 = ±2%（典型值）
TLC59291 具有六类错误标志：LED 开路检测
(LOD)、LED 短路检测 (LSD)、输出漏电检测 (OLD)、
基准引脚短路检测 (ISF)、预热报警 (PTW) 以及热故
障标志 (TEF)。此外，LOD 和 LSD 功能还具有无形检
测模式 (IDM)，可在输出关闭时检测这些故障。故障检
测结果可通过串行接口端口读取。
•
•
•
低静态电流
SOUT 可配置为 8 通道或 16 通道输出
支持无形检测模式的 LED 开路检测 (LOD)/LED 短
路检测 (LSD)
•
•
•
•
•
•
•
•
输出漏电检测 (OLD) 可检测 3µA 漏电
预热报警 (PTW)
TLC59291 在正常工作模式下拥有低静态电流，并且还
可在所有输出关闭时进入省电模式，从而将总电流消耗
设为 10uA（典型值）。
热关断 (TSD
)
电流基准引脚短路标志 (ISF)
10µA 流耗的省电模式
器件信息(1)
欠压锁定可设置默认数据
通道间 2ns 延迟开关可最大限度减少浪涌电流
运行温度：-40°C 至 85°C
器件型号
TLC59291
封装
VQFN (24)
封装尺寸（标称值）
4.00mm x 4.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用电路（以菊花链方式连接的多个 TLC59291）
VLED
OUT0 - - - - - - - - - - OUT15
OUT0 - - - - - - - - - - OUT15
DATA
SIN
SOUT
SIN
SOUT
Controller
VCC
SCLK
LAT
VCC
SCLK
LAT
SCLK
LAT
TLC59291
IC1
TLC59291
ICn
VCC
VCC
BLANK
BLANK
IREF
BLANK
IREF
GND
GND
RIREF
RIREF
GND
GND
GND
GND
3
SID read
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSA96
TLC59291
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
www.ti.com.cn
目录
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 28
8.5 Register Maps......................................................... 31
Application and Implementation ........................ 37
9.1 Application Information............................................ 37
9.2 Typical Application ................................................. 37
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 8
6.7 Timing Diagrams....................................................... 9
6.8 Typical Characteristics............................................ 21
Parameter Measurement Information ................ 23
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 24
9
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 39
12 器件和文档支持 ..................................................... 40
12.1 文档支持 ............................................................... 40
12.2 社区资源................................................................ 40
12.3 商标....................................................................... 40
12.4 静电放电警告......................................................... 40
12.5 Glossary................................................................ 40
13 机械、封装和可订购信息....................................... 40
7
8
4 修订历史记录
Changes from Original (September 2015) to Revision A
Page
•
•
•
已特性从 “通道间 = ±1%（典型值）”更改为 “通道间 = ±3%（典型值）” ............................................................................... 1
Deleted device number TLC5929 From the Electrical Characteristics table.......................................................................... 6
Changed ΔIOL(C0) Test Condition in Electrical Characteristics From: BC = 7Fh, RIREF = 1.6 kΩ To: BC = 0Eh, RIREF
=
3.6 kΩ, ................................................................................................................................................................................... 7
•
Changed the ΔIOL(C1) values in Electrical Characteristics From: TYP = ±2%, MAX = ±4% To TYP = 1% , MAX =
÷3%: ....................................................................................................................................................................................... 7
•
•
Deleted device number TLC5929 From the Switching Characteristics table......................................................................... 8
Changed text From: "with the 1-bit data" To: "with the 16-bit data" in the Function Control Data Writing section ............. 34
2
Copyright © 2015–2016, Texas Instruments Incorporated
TLC59291
www.ti.com.cn
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
5 Pin Configuration and Functions
RGE Package
24-Pin VQFN
(Top View)
1
2
3
4
5
6
18 BLANK
17 OUT15
16 OUT14
15 OUT13
14 OUT12
13 OUT11
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
Thermal Pad
(Bottom Side)
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BLANK PIN, has two configures:
When FC9(BLANK Mode) = 0, Blank pin worked as SOUT select pin:
a. When BLANK = Low, SOUT is connected to the bit 7 of the 16-bit shift register, worked as 8ch
device;
b. When BLANK = High, SOUT is connected to the bit 15 of the 16-bit shift register, worked as
16ch device;
BLANK
18
I
When FC9(BLANK Mode) = 1, Blank pin worked as OUTPUT enable pin;
a. When BLANK = Low, all constant current outputs are controlled by the on/off control data in the
data latch.
b. When BLANK = High, all OUTx are forced off
Ground
GND
IREF
22
20
—
Maximum current programming terminal.
A resistor connected between IREF and GND sets the maximum current for every constant-current
output. When this terminal is directly connected to GND, all outputs are forced off. The external
resistor should be placed close to the device and must be in the range of 1.32 kΩ to 66 kΩ.
I/O
Data latch.
The rising edge of LAT latches the data from the common shift register into the output on/off data
latch. At the same time, the data in the common shift register are replaced with SID, which is
selected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID)
section for more details.
LAT
1
I
Copyright © 2015–2016, Texas Instruments Incorporated
3
TLC59291
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
www.ti.com.cn
Pin Functions (continued)
PIN
NAME
OUT0
NO.
2
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
3
4
5
6
7
8
Constant-current sink outputs.
9
Multiple outputs can be configured in parallel to increase the constant-current capability. Different
voltages can be applied to each output.
10
11
12
13
14
15
16
17
Serial data shift clock.
Data present on SIN are shifted to the LSB of the 16-bit shift register with the SCKI rising edge. Data
in the shift register are shifted toward the MSB at each SCLK rising edge. The MSB data of the
common shift register appear on SOUT.
SCLK
SIN
24
23
I
I
Serial data input for the 16-bit common shift register.
When SIN is high, a '1' is written to the LSB of the common shift register at the rising edge of SCLK.
Serial data output of the 16-bit common shift register.
When FC9(BLANK Mode) = 0 and BLANK = LOW;
SOUT is connected to the bit 7 of the 16-bit shift register. Data are clocked out at the SCLK rising
SOUT
VCC
19
21
O
edge.
In other case:
SOUT is connected to the bit 15 of the 16-bit shift register. Data are clocked out at the SCLK rising
edge.
—
Power-supply voltage
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
MIN
–0.3
MAX
UNIT
V
(2)
Supply voltage, VCC
6
Input voltage
SIN, SCLK, LAT, BLANK, IREF
SOUT
–0.3 VCC + 0.3
–0.3 VCC + 0.3
V
V
Output voltage
Output current (DC)
OUT0 to OUT15
OUT0 to OUT15
–0.3
11
65
V
mA
°C
°C
Operating junction temperature, TJ (max)
Storage temperature, TSTG
150
150
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to device ground terminal.
4
Copyright © 2015–2016, Texas Instruments Incorporated
TLC59291
www.ti.com.cn
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
At TA= –40°C to 85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
VO
Supply voltage
3
3.3
5.5
V
V
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
OUT0 to OUT15
10
VIH
VIL
IOH
IOL
SIN, SCLK, LAT, BLANK
SIN, SCLK, LAT, BLANK
SOUT
0.7 × VCC
GND
VCC
V
0.3 × VCC
V
–2
2
mA
mA
mA
mA
°C
°C
SOUT
OUT0 to OUT15
OUT0 to OUT15
3 V ≤ VCC ≤ 3.6 V
40
50
85
125
IOLC
Constant output sink current
3.6 V < VCC ≤ 5.5 V
TA
TJ
Operating free-air temperature range
–40
–40
Operating junction temperature range
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (SCLK)
tWH0
tWL0
tWH1
tWH2
tWL2
tSU0
tSU1
tSU2
tH0
Data shift clock frequency
SCLK
33
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
10
10
20
40
40
5
SCLK
Pulse duration
(see Figure 1 and Figure 3)
LAT
BLANK
BLANK
SIN to SCLK↑
LAT↑ to SCLK↑
SCLK ↓to LAT↑
SIN to SCLK↑
LAT↑ to SCLK↑
LAT↑ to SCLK ↓
Setup time
(see Figure 1, Figure 3 and
Figure 4)
200
10
3
Hold time
(see Figure 1, Figure 3, and
Figure 13)
tH1
10
40
tH2
6.4 Thermal Information
TLC59291
RGE (VQFN)
24 PINS
38.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
45.3
16.9
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
16.9
RθJC(bot)
6.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2015–2016, Texas Instruments Incorporated
5
TLC59291
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
www.ti.com.cn
6.5 Electrical Characteristics
At VCC = 3 V to 5.5 V and TA = –40°C to 85°C. Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VOH
High-level output voltage
Low-level output voltage
LED open detection threshold
IOH = –2 mA at SOUT
VCC – 0.4
VCC
VOL
IOL = 2 mA at SOUT
0.4
V
VLOD
VLSD0
VLSD1
VLSD2
VLSD3
VIREF
IIN
All OUTn = on
0.25
0.30
0.35
V
All OUTn = on, detection voltage code = 0h
All OUTn = on, detection voltage code = 1h
All OUTn = on, detection voltage code = 2h
All OUTn = on, detection voltage code = 3h
RIREF = 1.3 kΩ
0.32 × VCC 0.35 × VCC 0.38 × VCC
0.42 × VCC 0.45 × VCC 0.48 × VCC
0.52 × VCC 0.55 × VCC 0.58 × VCC
0.62 × VCC 0.65 × VCC 0.68 × VCC
V
V
LED short detection threshold
V
V
Reference voltage output
Input current
1.175
–1
1.205
1.235
1
V
VIN = VCC or GND at SIN, SCLK, LAT, and BLANK
μA
SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = open
ICC0
2
5
3
7
mA
mA
SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)
ICC1
SIN/SCLK/LAT/BLANK =Low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)
ICC2
ICC3
ICC4
ICC5
5
3
7
4
mA
mA
mA
mA
SIN/SCLK/LAT/BLANK =Low, All OUTn = on,
VOUTn = 0.8 V, BC = 0Eh, RIREF = 1.6 kΩ
(IOUT = 2 mA target)
Supply current (VCC
)
SIN/SCLK/LAT/BLANK = Low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.6 kΩ
(IOUT = 41.3 mA target)
9
11
14
VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,
All OUTn = on, VOUTn = 0.8 V, BC = 7Fh,
RIREF = 1.3 kΩ (IOUT = 50.8 mA target)
11
VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.3 kΩ
(IOUT = 50.8 mA target), all output data off with power-
save mode enabled
ICC6
10
40
µA
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ
IOL(C0)
IOL(C1)
38.5
47.3
41.3
50.8
44.1
54.3
mA
mA
Constant output sink current
(OUT0 to OUT15, see
Figure 28)
VCC = 5 V, All OUTn = on, VOUTn = VOUTfix = 1 V,
BC = 7Fh, RIREF = 1.3 kΩ
IOL(KG0)
IOL(KG1)
IOL(KG2)
TJ = 25°C
TJ = 85°C(1)
TJ = 125°C(1)
0.1
0.2
0.8
μA
μA
μA
Output leakage current
(OUT0 to OUT15, see
Figure 28)
BLANK = high, VOUTn = VOUTfix
10 V, RIREF = 1.6 kΩ
=
0.3
(1) Not tested; specified by design.
6
Copyright © 2015–2016, Texas Instruments Incorporated
TLC59291
www.ti.com.cn
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
Electrical Characteristics (continued)
At VCC = 3 V to 5.5 V and TA = –40°C to 85°C. Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Constant-current error
(channel-to-channel, OUT0 to
OUT15)(2)
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 0Eh,
RIREF = 3.6 kΩ, TA = 25°C
ΔIO(LC0)
±3%
±6%
Constant-current error
(device-to-device, OUT0 to
OUT15)(3)
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ, TA = 25°C
ΔIOL(C1)
±1%
±3%
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ
ΔIOL(C2)
ΔIOL(C3)
Line regulation(4)
Load regulation(5)
±0.1
±0.5
±1
±3
%/V
%/V
All OUTn = on, VOUTn = 0.8 V to 3 V, VOUTfix = 0.8 V,
BC = 7Fh, RIREF = 1.6 kΩ
TTEF
THYS
TPTW
Thermal error flag threshold
Thermal error flag hysteresis
Pre-thermal warning threshold
Junction temperature(1)
Junction temperature(1)
Junction temperature(1)
150
5
165
10
180
20
°C
°C
°C
125
138
150
(2) The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
é
ê
ê
ê
ê
ê
ê
ë
ù
ú
ú
ú
I
OLC(n)
D (%) = 100 x
-1
ú
ú
ú
û
é
ê
ù
I
+ I
OLC(0) OLC(1)
+...+ I
+ I
OLC(14) OLC(15)
(
)
ú
ê
16
ú
ë
û
.
(3) The deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value. Deviation is calculated by the
formula:
é
ê
ê
ê
ê
ê
ê
ë
ù
ú
ú
ú
ú
ú
ú
û
é
ù
I
+ I
OLC(0) OLC(1)
+...+ I
+ I
OLC(14) OLC(15)
(
)
ê
ú
ê
ë
16
ú
û
D (%) = 100 x
- (Ideal Output Current)
Ideal Output Current
æ
ç
è
ö
1.20
I
= 54 x
÷
O(LC _IDEAL)
R
IREF ø
Ideal current is calculated by the formula:
(4) Line regulation is calculated by the formula:
é
ê
ù
I
at V
= 5.5 V
-
I
at V
= 3 V
(
) (OLC(n)
)
OLC(n)
CC
CC
ú
D (%) = 100 x
ê
ú
û
2.5 x
I
(
at V = 3 V
CC
)
OLC(n)
ë
(5) Load regulation is calculated by the equation:
æ
ç
ç
è
ö
I
(
at V
= 3 V - I
at V
= 1 V
) (OLC(n)
)
OLC(n)
OUTn
OUTn
÷
D (%) = 100 x
÷
ø
2 x
I
(
at V = 1 V
OUTn
)
OLC(n)
Copyright © 2015–2016, Texas Instruments Incorporated
7
TLC59291
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
www.ti.com.cn
6.6 Switching Characteristics
At VCC = 3 V to 5.5 V, TA = –40°C to 85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1.3 kΩ, and VLED = 5 V.
Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
10
40
10
40
8
MAX
UNIT
ns
tR0
tR1
tF0
tF1
tD0
At SOUT
15
60
15
60
22
Rise time
At OUTn, BC = 7Fh
At SOUT
ns
ns
Fall time
At OUTn, BC = 7Fh
SCLK↑ to SOUT↑↓
ns
ns
LAT↑ or BLANK↑↓ to OUT0 sink current on/off,
BC = 7Fh
tD1
tD2
tD3
35
2
65
6
ns
ns
ns
Propagation delay
OUTn on/off to OUTn + 1 on/off, BC = 7Fh
LAT↑ to power-save mode by data writing for all output
off
400
tD4
tD5
SCLK↑ to normal mode operation
100
100
µs
ns
BLANK↑↓ to SOUT↑↓ when BLANK MODE=0
Output on/off data = all '1',
BLANK low pulse = 40 ns, BC = 7Fh
tON_ERR
fOSC
Output on-time error(1)
–30
12
20
28
ns
Internal oscillator
frequency
20
MHz
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – 40 ns. tOUT_ON is the actual on-time of OUTn.
8
Copyright © 2015–2016, Texas Instruments Incorporated
TLC59291
www.ti.com.cn
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
6.7 Timing Diagrams
tWH0, tWL0, tWH1, tWH2, tWL2
:
VIH
Input(1) 50%
VIL
tWH
tWL
tSU0, tSU1, tH0, tH1
:
VIH
SCLK Input(1)
50%
VIL
tSU
tH
VIH
SIN/LAT Input(1)
50%
VIL
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 1. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2
:
VIH
Input(1)
50%
VIL
tD
VOH or VOUTnH
90%
50%
10%
Output
VOL or VOUTnL
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 2. Output Timing
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Timing Diagrams (continued)
DATA
0A
DATA
15B
DATA DATA DATA DATA
14B 12B 11B
13B
DATA
3B
DATA DATA
2B 1B
DATA
0B
DATA
15C
DATA
14C
DATA DATA DATA
11C
DATA
10C
SIN
SCLK
LAT
13C
12C
tH1
tH0
tSU0
tWH0
tSU1
1
2
3
4
5
1
2
3
4
5
6
13
14
15
16
tWH1
tWL0
tSU2
Shift Register
LSB Data
(Internal)
DATA
0A
SID
0A
DATA DATA DATA
13B
DATA
12B
DATA DATA
3B
2B
DATA
1B
Selected SID
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
15B
14B
DATA
0B
Shift Register
LSB + 1 Data
(Internal)
DATA
1A
SID
1A
SID
0A
DATA
15B
DATA
14B
DATA
13B
DATA DATA
3B
DATA
2B
Selected SID
1B
SID
0B
DATA
15C
DATA DATA
14C
DATA
12C
4B
13C
DATA
1B
Shift Register
MSB - 1 Data
(Internal)
DATA
14A
SID
14A
SID
13A
SID
12A
SID
11A
SID
10A
SID
1A
SID
0A
DATA
15B
SID
13B
SID
12B
SID
11B
SID
10B
SID
9B
Selected SID
14B
DATA
14B
Shift Register
MSB Data
(Internal)
DATA
15A
SID
15A
SID
14A
SID
13A
SID
12A
SID
11A
SID
2A
SID
1A
DATA
0A
SID
14B
SID
13B
SID
12B
SID
11B
SID
10B
Selected SID
15B
DATA
15B
Output On/Off
Data Latch
(Internal)
DATA15A–0A
DATA15B–0B
Control
Data Latch
(Internal)
Latest Control Data
DATA
15A
SID
15A
SID
14A
SID
13A
SID
12A
SID
11A
SID
2A
SID
1A
SID
0A
SID
14B
SID
13B
SID
12B
SID
11B
SID
10B
Selected
SID
SOUT
DATA
15B
tD0
tR0/tF0
tWH2
BLANK
tWL2
tD1
tD1
OFF
OFF
(1)
OUTn
ON
OFF
ON
tOUTON
tD2
tD2
OFF
OFF
(1)
ON
OUTn+1
ON
tD1
OFF
OFF
ON
(2)
(3)
(4)
ON
OUTn
OUTn
OUTn
tF1
tD1
OFF
OFF
OFF
OFF
ON
ON
ON
tR1
OFF
OFF
OFF
ON
(1) On/off latched data is '1'.
(2) On/off latched data change from '1' to '0' at second LAT signal.
(3) On/off latched data change from '0' to '1' at second LAT signal.
(4) On/off latched data is '0'.
Figure 3. Write for ON/Off Data and Output Timing (BLANK Mode = 1)
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Timing Diagrams (continued)
DATA
0A
DATA
15B
DATA DATA
14B
13B
DATA DATA
2B 1B
DATA
0B
DATA
7C
DATA
6C
DATA DATA
0C
SIN
SCLK
LAT
1C
tH0
tWH0
tSU0
tH1
1
2
3
1
2
7
8
6
14
15
16
tWH1
tSU2
Shift Register
LSB Data
(Internal)
DATA
0A
DATA DATA
15B
14B
DATA DATA
2B
1B
DATA
0B
DATA
7C
DATA
1C
DATA
0C
Shift Register
LSB + 1 Data
(Internal)
DATA
1A
DATA DATA
0A
15B
DATA DATA
3B
2B
DATA
1B
DATA
0B
DATA
2C
DATA
1C
Shift Register
MSB - 1 Data
(Internal)
DATA
14A
DATA DATA
13A
12A
DATA DATA
0A
15B
DATA
14B
DATA
14B
DATA
14B
DATA
14B
Shift Register
MSB Data
(Internal)
DATA
15A
DATA DATA
14A
13A
DATA DATA
1A
0A
DATA
15B
DATA
15B
DATA
15B
DATA
15B
Output On/Off
Data Latch
(Internal)
DATA15A–0A
DATA15B–0B
Control
Data Latch
(Internal)
Latest Control Data
DATA
15A
DATA DATA
13A
DATA DATA
1A
0A
DATA
15B
DATA
7B
DATA
6B
DATA
0B
DATA
7C
SOUT
14A
tD0
tR0/tF0
tD5
BLANK
OFF
(1)
OUT
ON
tD1
tD1
OFF
OFF
ON
tD2
tD2
OFF
(1)
ON
OUTn+1
ON
tD1
OFF
ON
(2)
(3)
(4)
ON
OUTn
OUTn
OUTn
tD1
tD1
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
(1) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at second LAT signal.
(2) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at second LAT signal.
(3) If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at second LAT signal.
(4) if the on/off latched data is “0”.
Figure 4. Write for On/Off Data and Output Timing (BLANK Mode = 0)
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Timing Diagrams (continued)
Low
SIN
SCLK
LAT
1
2
3
14 15
16
1
2
3
4
5
6
BLANK
Don’t Care
1
PSMODE Bit in
Control Data Latch
(Internal)
On/Off Control
Data Latch
(Internal)
Previous On/Off Data
All Data are 0
OFF
OFF
OUT0
OUT1
ON
OFF
OFF
ON
OFF
ON
OFF
OUT15
Power-Save
Mode
Normal Mode
Normal Mode
Power-Save Mode
Normal Mode
tD3
tD4
More Than 100 µA
ICC
(The Current
of VCC)
Less Than 100 µA
Figure 5. Power-Save Mode
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Timing Diagrams (continued)
SCLK
LAT
Common Shift
Register Bits[15:0]
(Internal)
LOD/TEF Data
These data are copied to the on/off data latch at LAT rising edge.
Common Shift
Register Bit 16
(Internal)
0
Output On/Off
Data (Internal)
Previous On/Off Data
New Latched GS Data
SIDLD Data
(Internal)
01 (LOD is selected)
High
Low
BLANK
OUTn
Resumed with T
going down.
All outputs are forced off
by TSD function.
J
OFF
OFF
OFF
OFF
ON
ON
ON
T
J
³ T
T ³ T
J TEF
TEF
T
< T
- T
T
³ T
T ³ T
J PTW
J
TEF HYST
J
PTW
Device Junction
Temperature (TJ)
T
< T
T < T
J PTW
J
PTW
PTW is not reset at LAT rising edge because SIDLD
does not select LOD. PTW is reset to 0 when the
device junction temperature is less than T
SIDLD selects LOD.
and
PTW
1
1
1
1
PTW in SID
(Internal Data)
0
TEF is reset to 0at LAT riging edge for
on/off data writing when the device junction
PTW is set to 1 when device
junction temperature is greater
temperature is less than T
selects LOD.
and SIDLD
TEF
than T
.
1
PTW
TEF in SID
(Internal Data)
0
0
TEF is set to 1 when device junction
temperture is grerater than T
.
TEF
Figure 6. PTW/TEF/TSD Timing (LOD Selected)
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Timing Diagrams (continued)
Low
SIN
SCLK
LAT
1
2
3
4
5
1
2
3
13
14
15
16
Don’t Care
BLANK
1
PSMODE bit
in Control Data
Latch (Internal)
Output On/Off
Control Data
Latch (Internal)
Previous On/Off Data
All Data are 0
OFF
OFF
OUT0
OUT1
ON
OFF
OFF
ON
OFF
ON
OFF
OUT15
Power-Save
Mode
Normal mode (No power save mode)
Normal mode
Normal Mode
Power-Save mode (ICC = 30 µA,(typ))
Depend on output on-off data
Because it takes about 50 µs return to normal
mode, 1'st SCLK rising edge should be input
50 µs or more before OUTn is turned on.
When PSMODE bit is 0, the device does not into
the power save mode even if output on-off data is all "0".
Figure 7. Power-Save Mode Timing
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Timing Diagrams (continued)
SIDLD in FC
data latch
(Internal)
01b
High
BLANK
(working as enable pin)
Low
Set current by external
resistor and BC data
, all output is
When BLANK signal is High
forced off even if the IDM on time has not
been passed the selected time.
Programmed output current
OUTn current
for LED lighting
0mA
0 µA
0mA
Selected output current by “IDMCUR”
bit in the function control latch
2/10/20 µA
2/10/20 µA
OUTn current
for IDM
0uA
LOD data is held in SID holder while
BLANK is high level or the data is held in
SID holder when IDM working time has
passed.
Selected on time by IDMTIM bit
in the function control latch.
SID holder
data
LOD
LOD
XXXXh
LOD
XXXXh
Old data
(Internal)
LOD data goes through SID holder while BLANK is low level or IDM working time is not passed.
LOD
0000h
16 bit LOD
LOD
0000h
LOD
0000h
LOD
XXXXh
circuit output
data (Internal)
LOD
XXXXh
LOD data is not stable just after BLANK goes low.
LAT
17 bit common
shift register data
(Internal)
Latched output on-off data
SID is loaded into the shift register
Figure 8. IDM Operation Timing with LOD Selected and IDM Enabled
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Timing Diagrams (continued)
SIDLD in FC
data latch
(Internal)
01b
High
BLANK
Low
Set current by external
resistor and BC data
When BLANK signal is “H” , all output is
forced off even if the IDM on time has not
been passed the selected time.
Programmed output current
OUTn current
for LED lighting
0mA
0mA
0 µA
The output for IDM is not turned on because
IDM is disabled by “IDMCUR” setting.
OUTn current
for IDM
0 µA
0 µA
LOD data is held in SID holder while
BLANK is high level.
SID holder
data
(Internal)
LOD
Old data
LOD
XXXXh
LOD
XXXXh
LOD data goes through SID holder while BLANK is low level.
16 bit LOD
circuit output
data (Internal)
LOD
0000h
LOD
LOD
XXXXh
LOD
0000h
0000h
LOD
XXXXh
LOD data is not stable just after BLANK goes low.
LAT
17 bit common
shift register data
(Internal)
Latched on-off control data
SID is loaded into the shift register
Figure 9. IDM Operation Timing with LOD Selected and IDM Disabled
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Timing Diagrams (continued)
High
DATA
1A
DATA
0A
DATA DATA DATA DATA DATA
13B 12B
DATA DATA DATA DATA
3B 2B 1B 0B
DATA DATA DATA DATA
16C 15C 14C 13C
SIN
16B 15B
14B
Low
SCLK
LAT
14
15
16
1
2
3
---
1
2
3
4
5
13
14
15
16
Shift register
LSB Data
(Internal)
SID
0A
DATA DATA
2A 1A
DATA
16B
SID
0B
DATA
0A
DATA DATA DATA
13B
DATA DATA DATA
3B
DATA DATA
16C 15C
15B
14B
2B
1B
0
1
DATA
0B
Shift register
LSB +1 Data
(Internal)
SID
1A
DATA
16B
DATA
1A
SID
0A
DATA DATA
15B
14B
DATA DATA DATA
2B
SID
1B
DATA DATA
2A
SID DATA
0B
4B
3B
16C
3A
1
0
DATA
1B
Shift register
MSB -1 Data
(Internal)
DATA
16A
DATA
15A
SID
15B
SID
15A
SID DATA DATA DATA
14A 13A 12A 11A
SID
1A
SID DATA
16B
DATA
0
SID SID
14B 13B
0A
0
DATA
15B
SID data selected by SIDLD bit is loaded into the common
shift register at LAT rising edge except SIDLDis 00b.
Shift register
MSB Data
(Internal)
DATA
16A
DATA DATA
0
DATA
16B
SID SID
15A 14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
SID SID
15B 14B
1
0
0
Output on-off
data latch
(Internal)
DATA15A-0A
Old on-off data
SIDLDin FC
data latch
(Internal)
XXb
LOD data is selected when SIDLD is 01h. LSD data is selected when SIDLDis set to10b. OLD
data is selected when SID is set to 11b. No SID data is loaded whenSIDLDis 00h.
DATA DATA
0
DATA
16A
SID
2A
SID
1A
SID
0A
SID
15B
SID
14B
SID
15A
SID
14A
SID SID
13A 12A
DATA
16B
SOUT
1
Low
16 bit SID data
Low
BLANK
Selected detector data by SIDLD is held in SID holder while BLANK is high level. Or the data is held in SID holder when IDM
working time is passed. The held data is loaded into the common shift register as SID except the case SIDLD is 00h.
SID holder
data
(Internal)
Detector data Detector data
XXXXh XXXXh
LOD data goes through SID holder while BLANK is low level or IDM working time is not passed.
16 bit LOD or
LSD or OLD
data (Internal)
Detector data
0000h
Detector data
0000h
Detector
XXXXh
Detector data
XXXXh
The detectors data are not stable just after BLANK signal goes low.
Figure 10. SID Read Timing
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Timing Diagrams (continued)
DATA DATA DATA DATA DATA DATA
SIN
DATA DATA DATA DATA
3B 2B 1B 0B
DATA DATA DATA DATA DATA DATA
15C 14C 13C 12C 11C 10C
0A
15B 14B
13B
12B 11B
SCLK
LAT
1
2
3
4
5
1
2
3
4
5
6
13
14
15
16
Shift register
LSB Data
(Internal)
SID
0A
DATA
0A
SID
0B
DATA DATA DATA DATA
13B
DATA DATA DATA
3B
DATA DATA DATA DATA DATA
13C 12C
16B
15B
14B
2B
1B
16C 15C
14C
0
1
DATA
0B
Shift register
LSB +1Data
(Internal)
SID
1A
DATA
16B
DATA
1A
SID
0A
DATA DATA
15B
14B
DATA DATA DATA
2B
SID DATA DATA DATA DATA
0B
SID
1B
4B
3B
16C
15C
14C 13C
1
0
DATA
1B
Shift register
DATA
15A
SID
15A
SID DATA DATA DATA
11A
SID
1A
SID DATA
0A
SID
15B
SID SID
14B 13B
SID
12B
SID
11B
SID
10B
MSB -1Data
(Internal)
14A 13A
12A
16B
0
DATA
15B
Shift register
MSB Data
(Internal)
DATA
16A
DATA
16B
SID SID
15A 14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
SID SID
15B 14B
SID
13B
SID SID
12B 11B
0
0
Output on-off
data latch
(Internal)
DATA15B-0B
DATA15A-0A
Control data
Latch
(Internal)
Control data is not changed from previous data
DATA
16B
DATA
16A
SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
SID
15A
SID
14A
SID SID
13A 12A
SID
2A
SID
1A
SID
0A
SOUT
Low
Low
BLANK
OFF
OFF
OFF
ON
ON
ON
OUTn(1)
OUTn(2)
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
OUTn(3)
OUTn(4)
ON
OFF
OFF
ON
These dotted lines are output pulse timing for IDM
(1) On/off latch data is '1'.
(2) On/off latch data change from '1' to '0' at second LAT signal.
(3) On/off latch data is change from '0' to '1' at second LAT signal.
(4) On/off latch data is '0'.
Figure 11. On-Off Control Data Write Timing (BLANK Mode = 1)
18
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Timing Diagrams (continued)
DATA
0C
DATA DATA DATA DATA
SIN
DATA DATA DATA
2B 1B 0B
DATA DATA
7C 6C
DATA
1C
0A
15B 14B
13B
SCLK
LAT
1
2
3
14
15
16
1
2
7
8
Shift register
LSB Data
(Internal)
DATA
0A
DATA DATA
15B 14B
DATA DATA DATA
2B 1B 0B
DATA
7C
DATA DATA
0C
1C
Shift register
LSB +1Data
(Internal)
DATA DATA DATA
1A
0A 15B
DATA DATA DATA
3B 2B 1B
DATA
1C
DATA
0B
DATA
2C
Shift register
DATA DATA DATA
14A
13A 12A
DATA DATA DATA
0A 15B 14B
DATA
14B
DATA
14B
DATA
14B
MSB -1Data
(Internal)
Shift register
MSB Data
(Internal)
DATA DATA DATA
15
DATA DATA DATA
0A
DATA
15B
DATA
15B
DATA
15B
A
14A 13A
1A
15B
Output on-off
data latch
(Internal)
DATA15B-0B
DATA 7C-0C
DATA15A-0A
Control data
Latch
(Internal)
Latest control data
DATA
0B
DATA DATA
14A 13A
DATA
1A
DATA
7B
DATA
15A
DATA DATA
0A 15B
DATA
6B
DATA
7C
SOUT
BLANK
OFF
OFF
ON
OUTn(1)
OUTn+1(1)
OUTn(2)
ON
OFF
OFF
ON
ON
OFF
ON
ON
OFF
OFF
OFF
ON
OUTn(3)
OUTn(4)
ON
OFF
OFF
OFF
ON
(1) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at 2’nd LAT signal.
(2) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at 2’nd LAT signal.
(3) If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at 2’nd LAT signal.
(4) If the on/off latched data is “0”.
Figure 12. On-Off Control Data Write Timing (BLANK Mode = 0)
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Timing Diagrams (continued)
DATA
15C
DATA
0A
DATA DATA DATA DATA
14B
DATA DATA DATA DATA
2B
DATA DATA DATA DATA DATA
14C 13C 12C 11C 10C
DATA
15B
SIN
13B
12B 11B
3B
1B
0B
SCLK
LAT
1
2
3
4
5
1
2
3
4
5
6
13
14
15
16
tH2
Shift register
LSB Data
(Internal)
SID
0A
DATA
0A
DATA
0B
DATA DATA DATA DATA
13B
DATA DATA DATA
3B 2B 1B
DATA DATA DATA DATA DATA
13C 12C
16B 15B
14B
16C 15C
0
14C
1
Shift register
LSB +1 Data
(Internal)
SID
1A
DATA
1A
DATA
1B
SID DATA DATA DATA
14B
DATA DATA DATA
4B
DATA DATA DATA DATA DATA
15C
0A
16B
15B
3B
2B
0B
16C
14C 13C
1
0
Shift register
MSB -1 Data
(Internal)
DATA
15A
DATA
15B
SID
15A
SID DATA DATA DATA
11A
SID
1A
SID DATA
0A
DATA DATA DATA DATA DATA
14B 13B 12B 11B 10B
14A 13A
12A
16B
1
Shift register
MSB Data
(Internal)
DATA
16B
DATA
16A
SID SID
15A 14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
DATA DATA DATA DATA DATA
15B 14B 13B 12B 11B
0
1
Output Oo-off
data
(Internal)
DATA15A-0A
DATA15A-0A
Function control
Latch Data
(Internal)
Old function control data
DATA15B-0B
DATA
16A
SID
2A
SID
1A
SID
0A
DATA DATA DATA DATA DATA
15B 14B 13B 12B 11B
SID
15A
SID
14A
SID SID
13A 12A
DATA
16B
SOUT
Low
High
Figure 13. Function Control Data Write Timing
20
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6.8 Typical Characteristics
At TA = 25°C, unless otherwise noted.
100
60
50
40
30
20
10
0
66.0
33.0
13.2
IOLCMax = 40 mA
IOLCMax = 30 mA
IOLCMax = 20 mA
10
6.60
4.40
3.30
2.64
2.20
30
IOLCMax = 2 mA
IOLCMax = 10 mA
IOLCMax = 5 mA
1.89
1.65
40
IOLCMax = 1 mA
1.47
1.32
50
1
0
10
20
IOLCMax (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
VCC = 3.3 V
BC = 7Fh
VOUTn = 0.8 V
Figure 14. Reference Resistor vs Output Current
Figure 15. OUTn Current vs Output Voltage
46
45
44
43
42
41
40
39
38
60
50
40
30
20
10
0
IOLCMax = 50 mA
IOLCMax = 40 mA
IOLCMax = 30 mA
IOLCMax = 20 mA
TA = -40°C
TA = +25°C
TA = +85°C
IOLCMax = 2 mA
IOLCMax = 10 mA
IOLCMax = 5 mA
IOLCMax = 1 mA
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
VCC = 3.3 V
VOUTn = 0.8 V
BC = 7Fh
RIREF = 1.58 kΩ
VCC = 5 V
50 mA = 1 V
BC = 7Fh
VOUTn = 0.8 V
Figure 16. OUTn Current vs Output Voltage
Figure 17. OUTn Current vs Output Voltage
56
55
54
53
52
51
50
49
48
3
2
1
0
-1
-2
-3
TA = -40°C
TA = +25°C
TA = +85°C
VCC = 3.3 V
VCC = 5 V
0
0.5
1.0
1.5
2.0
2.5
3.0
0
10
20
30
40
50
Output Voltage (V)
Output Current (mA)
VCC = 5 V
VOUTn = 1 V
BC = 7Fh
RIREF = 1.28 kΩ
BC = 7Fh
VOUTn = 0.8 V
50 mA = 1 V
Figure 18. OUTn Current vs Output Voltage
Figure 19. Constant-Current Error
vs Output CurrenT set by RIREF or BC Data (Channel-to-
Channel)
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
3
60
50
40
30
20
10
0
VCC = 3.3 V
VCC = 5 V
IO = 2 mA
2
1
IO = 5 mA
IO = 10 mA
IO = 20 mA
IO = 40 mA
0
-1
-2
-3
IO = 50 mA
VCC = 3.3 V
VCC = 5 V
-40
-20
0
20
40
60
80
100
0
16
32
48
64
80
96
112
128
Temperature (°C)
BC Data (Decimal)
RIREF = 1.28 kΩ
VOUTn = 0.8 V
Figure 20. Constant-Current Error
vs Ambient Temperature (Channel-to-Channel)
Figure 21. Global Brightness
Control Linearity
16
14
12
10
8
14
12
10
8
6
6
4
4
2
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
2
0
0
0
10
20
30
40
50
-40
-20
0
20
40
60
80
100
Output Current (mA)
RIREF = 1.6 kΩ
All Outpts on
Ambient Temperature (°C)
RIREF = 1.6 kΩ
BC = 7Fh
SIN = 17.5 MHz
BC = 7Fh
SCLK = 35 MHz
SIN = 17.5 MHz
SCLK = 35 MHz
All Outpts on
Figure 22. Supply Current
vs Output Current Set by RIREF
Figure 23. Supply Current
vs Ambient Temperature
30
25
20
15
10
5
CH1 (5 V/div)
CH1-BLANK
CH2-OUT0
CH2 (2 V/div)
CH3 (2 V/div)
CH3-OUT1
CH4-OUT15
CH4 (2 V/div)
VCC = 3.3 V
VCC = 5 V
0
Time (20 ns/div)
BC = 7Fh
-40
-20
0
20
40
60
80 100
VCC = 3.3 V
VLED = 5 V
RIREF = 1.6 kΩ
CL = 15 pF
Ambient Temperature (°C)
RL = 100 Ω
BC = 7Fh
RIREF = 1.6 kΩ
SIN = SCLK = Low
Power-Save Mode
Figure 25. Constant-Current Output
Voltage Waveform
Figure 24. Supply Current in Power-Save Mode
vs Ambient Temperature
22
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ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
7 Parameter Measurement Information
RL
CL
VCC
GND
VCC
IREF
OUTn
VLED
(1)
RIREF
(1) CL includes measurement probe and jig capacitance.
Figure 26. Rise Time and Fall Time Test Circuit for OUTn
VCC
SOUT
VCC
(1)
CL
GND
(1) CL includes measurement probe and jig capacitance.
Figure 27. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
OUTn
VCC
IREF
RIREF
GND OUT15
VOUTn
VOUTfix
Figure 28. Constant-Current Test Circuit for OUTn
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8 Detailed Description
8.1 Overview
The TLC59291 is a 8/16-channel constant current sink LED driver. Each channel can be turned on-off by writing
data to an internal register. The constant current value of all 16 channels is set by a single external resistor and
128 steps for the global brightness control (BC).
The TLC59291 has six type error flags: LED open detection (LOD), LED short detection (LSD), output leak
detection (OLD), reference terminal short detection (ISF), Pre thermal warning (PTW) and thermal error flag
(TEF). In addition, the LOD and LSD functions have invisible detection mode (IDM) that can detect those errors
even when the output is off. The error detection results can be read via a serial interface port.
8.2 Functional Block Diagram
VCC
VCC
16 bit LOD or 16 bit LSD data or 16 bit OLD data
RESET
UVLO
LSB
MSB
Bit 7/15
Select
SIN
SOUT
LOAD
SELECT
Common shift register
0
15
SCLK
2
16
LSB
MSB
All off
Output On-Off data Latch
16
0
15
16
LSB
MSB
16
Control data latch
(Global brightness control, LSD voltage select,
loaded error select, other function control)
1
LAT
Blank
Mode
0
15
4
3
1
BLANK
SID
Selector
2
2
7
To all
analog
circuit
ERROR
SELECT
Power
save
control
2
IDM timing
control
OSC
Temp
Error
Status
ISF
BC
RESET
165C
138C
Thermal
Detector
16
2
SID
Holder
On-Off control with output delay
ISF
Reference
current
control
16
IREF
16channels constant current sink driver
with 7bit global brightness control
16
ERROR
SELECT
VLSD
SELECT
LED Open Detection (LOD) / LED Short Detection (LSD)
/Output Leak Detection (OLD)
Detection
Voltage
GND
GND
OUT0 OUT1
OUT2
OUT13 OUT14 OUT15
24
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8.3 Feature Description
8.3.1 Maximum Constant Sink Current
The maximum output current of each channel (IO(LCmax)) is programmed by a single resistor (RIREF) that is placed
between the IREF and GND pins. The current value can be calculated by Equation 1:
V
(V)
IREF
R
(KW) =
x 54.8
IREF
I
(mA)
O(CLmax)
Where:
VIREF = the internal reference voltage on IREF (typically 1.205 V when the global brightness control
data are at maximum.
IO(LCmax) = 1 mA to 40 mA ( VCC ≤ 3.6 V), or 1 mA to 50 mA (VCC > 3.6 V) at OUT0 to OUT15 (BC =
7Fh)
(1)
IO(LCmax) is the highest current for each output. Each output sinks IO(LCmax) current when it is turned on with the
maximum global brightness control (BC) data. Each output sink current can be reduced by lowering the global
brightness control value. RIREF must be between 1.32 kΩ and 66 kΩ to hold IO(LCmax) between 50 mA (typical) and
1 mA (typical). Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved by
setting IO(LCmax) to 1 mA or higher and then using the global brightness control to lower the output current.
Figure 14 and Table 1 show the characteristics of the constant-current sink versus the external resistor, RIREF
.
Table 1. Maximum Constant Current Output versus
External Resistor Value
IO(LCmax) (mA)
RIREF (kΩ, typ)
1.32
50 (VCC > 3.6 V only)
45 (VCC > 3.6 V only)
1.47
40
35
30
25
20
15
10
5
1.65
1.89
2.20
2.64
3.30
4.40
6.60
13.2
2
33
1
66
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8.3.2 Global Brightness Control (BC) Function
The TLC59291 has the ability to adjust the output current of all constant current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) can be set with
a 7-bit word. The global BC adjusts all output currents in 128 steps from 0% to 100%. where 100% corresponds
to the maximum output current set by RIREF. Equation 2 calculates the actual output current. BC data can be set
via the serial interface.
I
(mA) x BC
O(LCmax)
I
(mA) =
O(LCn)
127d
Where:
IO(LCmax) = the maximum constant-current value for each output determined by RIREF
.
BC = the global brightness control value in the control data latch (0h to 127d)
(2)
Table 2 shows the BC data versus the constant-current ratio against IO(LCmax)
.
Table 2. BC Data versus Constant-Current Ratio Against IO(LCmax)
BC DATA
RATIO OF OUTPUT
CURRENT TO IO(LCmax)
(%)
IO(LC)
(mA, IO(LCmax)= 40mA,
typ)
IO(LC)
BINARY
000 0000
000 0001
000 0010
∙ ∙ ∙
DECIMAL
HEX
00
(mA, IO(LCmax)= 1mA, typ)
0
0
0
0
1
01
0.8
0.31
0.63
∙ ∙ ∙
0.01
0.02
∙ ∙ ∙
2
02
1.6
∙ ∙ ∙
125
126
127
∙ ∙ ∙
7D
7E
7F
∙ ∙ ∙
111 1101
111 1110
111 1111
98.4
99.2
100.0
39.4
39.7
40.0
0.98
0.99
1.00
8.3.3 Thermal Shutdown (TSD) and Thermal Error Flag (TEF)
The thermal shutdown (TSD) function turns off all constant-current outputs when the junction temperature (TJ)
exceeds the threshold (TTEF = 165°C, typical) and sets all LOD data bit to ‘1’. When the junction temperature
drops below (TTEF – THYST), the output control starts. The TEF is remains ‘1’ until LAT is input even if low
temperature. Figure 6 shows a timing diagram and Table 3 shows a truth table for TEF.
8.3.4 Pre-Thermal Warning (PTW)
The PTW function indicates that the IC junction temperature is high. The PTW is set and all LSD data bit are set
to “1” while the IC junction temperature exceeds the temperature threshold (TPTW = 138 °C, typical). Then OUTn
are not forced off. When the PTW is set, the IC temperature should be reduced by lowering the power dissipated
in the driver to avoid a forced shutdown by the thermal shutdown circuit. This reduction can be accomplished by
lowering the values of the BC data. When the IC junction temperature decreases below the temperature of TPTW
,
PTW is reset. Figure 6 shows a timing diagram and Table 3 shows a truth table for PTW.
26
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8.3.5 Current Reference Terminal – IREF Terminal - Short Flag (ISF)
The ISF function indicates that IREF terminal is short to GND with low impedance. When IREF is set, all OLD
data bit is set to “1”. Then all outputs (OUTn) are forced off and remain off until the short is removed. Table 3
shows the truth table for ISF.
Table 3. TEF/PTW/ISF Truth Table
CORRESPONDING DATA BITS
TEF
Device temperature is lower than Device temperature is lower than
high-side detect temperature pre-thermal warning temperature
(temperature ≤ TTEF (temperature ≤ TPTW
PTW
ISF
IN SID
IREF terminal is not shorted
Depends on LOD/LSD/OLD
)
)
Device temperature is higher
than high-side detect
temperature and all outputs are
Device temperature is higher
than pre-thermal warning
temperature
IREF terminal is shorted to GND SID is all 1s for TEF when SIDLD
with low impedance and all
outputs (OUT0 to OUT15) are
forced off
bit = '01'. SID is all 1s for PTW
when SIDLD = '10'. SID is all 1s
for ISF when SIDLD = '11'.
forced off (temperature >TTEF
)
(temperature > TPTW)
8.3.6 Noise Reduction
Large surge currents may flow through the IC and the board on which the device is mounted if all 16 outputs turn
on simultaneously when BLANK goes low or on-off data changes at LAT rising edge with BLANK low. These
large current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits.
The TLC59291 turns the outputs on in 2ns series delay for each output to provide a circuit soft-start feature.
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8.4 Device Functional Modes
8.4.1 Blank Mode Selection (BLKMS)
The device has two configuration for BLANK pin, which is decided by BIT[9] in FC register. When BLANK mode
= 1, the device is in ENABLE mode, BLANK pin is worked as OUTPUT enable pin: when BLANK=Low, all
constant current outputs are controlled by the on/off control data in the data latch; when BLANK=High, all OUTx
are forced off.
When BLANK mode = 0, the device is in SOUT mode, BLANK pin is worked as SOUT select pin; when BLANK=
Low, SOUT is connected to the bit7 of the 16-bit shift register, worked as 8 channel device; when BLANK= High,
SOUT is connected to the bit15 of the 16-bit shift register, worked as 16ch device. If device is already in
ENABLE mode and we want to switch to SOUT mode, the new FC data with BIT[9]=0 must be input. Then it
enter SOUT mode.
If device is already in SOUT mode and the user wants to switch to ENABLE mode. First make sure BLANK pin is
high, SOUT is connected with bit15 of common shift register. Then input the new FC data with BIT[9] = 1. The
device enters ENABLE mode
When the IC is powered on, SOUT mode is selected as default value. Refer to table 7 for detail.
8.4.2 Power-Save Mode
In this mode, the device dissipation current becomes 30 µA (typical). When “PSMODE” bit is ‘1’, the power save
mode is enabled. Then if LAT rising edge is input to write all ‘0’ data into the output on-off data latch or to write
any data into the control data latch when the on-off data latch are all ‘0’, TLC5929 goes into the power save
mode. When SCLK rising edge is input, the device returns to normal operation. The power-save mode timing is
shown in Figure 7.
8.4.3 LED Open Detection (LOD)
LOD detects the fault caused by LED open circuit or a short from OUTn to ground by comparing the OUTn
voltage to the LOD detection threshold voltage level (VLOD = 0.3 V typical). If the OUTn voltage is lower than
VLOD, that output LOD bit is set to '1' to indicate an open LED. Otherwise, the LOD bit is set to '0'. LOD data are
only valid for outputs programmed to be on. LOD data for outputs programmed to be off are always '0' (Table
11).
The LOD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is set
to ‘01b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LOD data are stored to SID holder at
the end timing of IDM working time.
The stored LOD data can be read out through the common shift register as Status Information Data (SID) from
SOUT pin. LOD/LSD data are not valid until 0.5 µs after the falling edge of BLANK.
8.4.4 LED Short Detection (LSD)
LSD data detects the fault caused by a shorted LED by comparing the OUTn voltage to the LSD detection If the
OUTn voltage is higher than the programmed voltage, that output LSD bit is set to '1' to indicate a shorted LED.
Otherwise, the LSD bit is set to'0'. LSD data are only valid for outputs programmed to be on. LSD data for
outputs programmed to be off are always '0' (Table 4).
The LSD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is set to
‘10b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LSD data are stored to SID holder at the
end timing of IDM working time. The stored LSD data can be read out through the common shift register as
Status Information Data (SID) from SOUT pin. LOD/LSD data are not stabled until 0.5 µs after the falling edge of
BLANK. Therefore, BLANK must be low for at least that time.
The LSD need to be executed after propagation delay, “td4” or more from the device operation resumed from the
power save mode because LOD does not work during the power save mode.
28
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Device Functional Modes (continued)
8.4.5 Invisible Detection Mode (IDM)
Invisible Detection Mode (IDM) is the mode which can detect LOD and LSD when output on-off data is set to off
state. When “IDMCUR” bit in the control data latch are set any data except “00b”, OUTn start to sink the current
set by the “IDMCUR” bit at BLANK falling edge and OUTn stop to sink the current at BLANK rising signal or the
time set by “IDMTIM” has passed. When OUTn is stopped, the selected SID data by “SIDLD” bit are latched to
into SID holder.
When IDM mode is enabled, OLD is always set to disable. When “IDMCUR” bit in the control data latch is set
“00b”, OUTn doesn’t start to sink the current set. Figure 29 shows LOD/LSD/OLD/IDM circuit. Figure 8 shows
IDM operation timing and Table 5 shows a truth table for LOD/LSD/OLD.
IDM can only be working when FC[9] = 1.
8.4.6 Output Leakage Detection (OLD)
Output leak detection (OLD) detects a fault caused by OUTn is short to GND with high resistance by comparing
the OUTn voltage to the LSD detection threshold voltage when output on-off data is set to off state. Also OLD
can detect the short between adjacent pins. Small current is sourced from OUTn turned off to LED to detect LED
leaking when “SIDLD” bit are ‘11b’ and BLANK is low. OLD operation is disabled when SIDLD bit are set any
data except “11b” and then the sourced current is stopped. Also OLD is disabled when Invisible Detection Mode
(IDM) is enabled. If the OUTn voltage is lower than the programmed LSD threshold voltage, that output OLD bit
is set to '1' to indicate a leaking LED. Otherwise, the OLD bit is set to '0'. OLD result is valid for outputs
programmed to off only. The OLD data is latched into SID holder when BLANK goes high. OLD data for outputs
not programmed to off are always '0'. The OLD need to be executed after propagation delay, “td4” or more from
the device operation resumed from the power save mode because OLD does not work during the power save
mode.
VCC
VLED
OLD
Control
2 mA (typ)
LED Lamp
LSD/OLD Data
‘1’ = Error
OUTn
On/Off
Control
Up to
50 mA
VLSD
2 mA/10 mA/20 mA
IDM
Control
(typ)
LOD Data
‘1’ = Error
GND
VLOD
Figure 29. LOD/LSD/OLD/IDM Circuit
8.4.7 Status Information Data (SID)
The status information data (SID) contains the status of the LED Open Detection (LOD), LED Short Detection
(LSD), Output Leakage Detection (OLD), Pre-Thermal Warning (PTW), Thermal Shutdown (TSD) and Thermal
Error Flag (TEF) and Current Reference Terminal – IREF Terminal - Short Flag (ISF). The loaded SID data can
be selected by “SIDLD” bits in the control data latch. When the MSB of the common shift register is set to '0', the
selected SID overwrites lower 16-bit data in the common shift register data at the rising edge of LAT after the
data in the common shift register are copied to the output on-off data latch. If the common shift register MSB is
'1', the selected SID does not overwrite the 16-bit data in the common shift register
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Device Functional Modes (continued)
After being copied into the common shift register, new SID data are not available until new data are written into
the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID without
changing the on-off control data, reprogram the common shift register with the same data currently programmed
into the on-off data latch. When LAT goes high, the output on-off data is not changed, but new SID data are
loaded into the common shift register. LOD, LSD, OLD, PTW, TEF, ISF are shifted out of SOUT with each rising
edge of SCLK. The SID need to be read out after td4 or more from the device operation resumed from the power
save mode.
The SID reading must be delayed for a duration of tD4 or more after the device resumes operation from the
power-save mode because SID does not indicate correct data during the power-save mode. The SID load
configuration and SID read timing are shown in Figure 10 and Figure 30, respectively.
Selected SID (16 bits) by SIDLD Data in the Control Data Latch
MSB
LSB
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT15 OUT14 OUT13 OUT12 OUT11
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT4
OUT3
OUT2
OUT1
OUT0
15
14
13
12
11
3
2
1
0
4
SID are loaded to the
common shift register
at the rising edge of
LAT when the common
shift register MSB is 0.
No data are loaded
into the MSB of the
common shift register
MSB = ‘0’
LSB
Latch Common Common Common Common Common
Select Data Bit Data Bit Data Bit Data Bit Data Bit
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
SIN
SOUT
Bit
15
14
13
12
11
4
3
2
1
0
SLCK
16
15
14
13
12
11
3
2
1
0
4
Common Shift Register (17 Bits)
Figure 30. SID Load Configuration
Table 4. SID Load Assignment
BIT NUMBER
LOADED INTO
COMMON SHIFT
REGISTER
SIDLD
1/0 BIT
SELECTED
DETECTOR
CHECKED OUTn
DESCRIPTION
00b
01b
No detector selected
—
No data loaded
The data in the common shift register are not changed.
The data in the common shift register are updated with LOD or TEF data.
All bits '1' = device junction temperature (TJ) is high (TJ > TTEF) and all
outputs are forced off by the thermal shutdown function.'1 = OUTn shows
lower voltage than the LED open detection threshold (VLOD).
0 = normal operation.
OUT0
OUT1
∙ ∙ ∙
0
1
LED open detection
(LOD)
∙ ∙ ∙
14
15
0
OUT14
OUT15
OUT0
OUT1
∙ ∙ ∙
The data in the common shift register are updated with LSD or PTW data.
All bits '1' = device junction temperature (TJ) is high (TJ > TPTW).
1 = OUTn shows higher voltage than the LED short detection threshold
(VLSD) selected by LSDVLT.
1
LED short detection
(LSD)
10b
11b
∙ ∙ ∙
14
15
0
OUT14
OUT15
OUT0
OUT1
∙ ∙ ∙
0 = normal operation.
The data in the common shift register are updated with OLD or ISF data.
All bits '1' = IREF pin is shorted to GND with low impedance.
1 = OUTn is leaking to GND with greater than 3µA.
0 = normal operation.
1
Output leakage
detection (OLD)
∙ ∙ ∙
14
15
OUT14
OUT15
30
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Table 5. LOD/LSD/OLD Truth Table
LOD
LSD
OLD
CORRESPONDING BIT IN SID
OUTn does not leak to GND (VOUTn
VLSD when constant-current output off
>
LED is not opened
(VOUTn > VLOD
LED is not shorted (VOUTn ≤ VLSD
)
0
)
and OUTn source current on)
Current leaks from OUTn to internal
GND, or OUTn is shorted to external
LED is shorted between anode and
cathode, or shorted to higher voltage
LED is open or shorted to GND
(VOUTn ≤ VLOD
GND with high impedance (VOUTn
≤
1
)
side (VOUTn > VLSD
)
VLSD when constant-current output off
and OUTn source current on)
8.5 Register Maps
8.5.1 Register and Data Latch Configuration
The TLC59291 has one common shift register and two control data latch. The common shift register is 16-bits in
length and two control data latch is 16-bits length. When SCLK is '0' at LAT rising edge, the 16-bits common shift
register are copied into the output on-off data latch. Also when SCLK is '1' at LAT rising edge the 16-bits data are
copied into the control data latch. Figure 31 shows the common shift register and two control data latches
configuration.
SID 16 bit
Common shift register (16 bits)
LSB
MSB
Common Common Common Common
Data bit
15
Common Common Common Common
Data bit
4
Common
Data bit
11
Common
Data bit
0
SIN
Data bit Data bit
14
Data bit
12
Data bit
3
Data bit Data bit
2
SOUT
13
1
SCLK
15
14
13
12
11
---
3
2
1
0
4
16 bit
Output on - off data latch (16 bits)
LSB
0
MSB
15
---
13
12
2
1
14
11
4
3
The latch pulse
OUTON OUTON
14 13
OUTON
2
OUTON
15
OUTON
3
OUTON OUTON
0
OUTON OUTON
12 11
OUTON
4
comes from LAT
pin when SCLK
signal = 0.
1
0
16 bit
To output on-off control circuit
16 bit
Control data latch (16 bits)
LSB
0
MSB
15
10
9
8
13
IDM
12
7
---
6
14
11
The latch pulse
comes from LAT
pin when SCLK
signal = 1.
LSD LSD
detect detect
voltage1 voltage0
Power
save
enable
Brightness
control
(BC) 6
Brightness
control
(BC) 0
IDM
current
select 1
IDM
current
select 0
IDM
SID load
control
0
SID load
control
1
working working
time 0
time 1
2 bit
1 bit
2 bit
2 bit
2 bit
7 bit
To LSD
circuit
To output constant current
control circuit
To IDM
To SID
To power To IDM
save mode working time
current
control
circuit
data load
control
circuit
control
circuit
control
circuit
Figure 31. Common Shift Register and Control Data Latches Configuration
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Register Maps (continued)
8.5.1.1 Common Shift Register
The 16-bit common shift register is used to shift data from the SIN pin into the TLC59291. The data shifted into
the register are used for the data writing for output on-off control, global brightness control, and some functions
control. The register LSB is connected to SIN. On each SCLK rising edge, the data on SIN are shifted into the
register LSB and all bits are shifted towards the MSB.
SOUT can be connected to either bit 15 or bit 7 of common shift register depending on BLANK signal and control
data setting.
Also Status Information Data (SID) selected by the load select data in the control data latch are loaded to the
common shift register when LAT rising edge is input with SCLK is “0” of the shift register.
When the device powered up, the data in the 16-bit common shift register is set to all “0”.
8.5.1.2 Output On/Off Data Latch
The output on/off data latch is 16 bits long and sets the on or off status for each constant-current output.
When FC[9] = 1 and BLANK is high, all outputs are forced off. But then the data in the latch are not changed. In
other case, the corresponding output is turned on if the data in the output on-off data latch are '1' and remains off
if the data are '0'.
When the IC is initially powered on, the data in the data latch is set to all “0”.
The output on/off data latch configuration is shown in Figure 32 and the data bit assignment is shown in Table 6.
From common shift register
16 bit
Output on-off data latch (16 bits)
LSB
0
MSB
15
---
13
12
2
1
14
11
4
3
OUTON OUTON OUTON
14
13
OUTON OUTON
12 11
OUTON OUTON OUTON OUTON
1
OUTON
4
15
2
3
0
16 bit
To output on off control circuit
Figure 32. Output On/Off Data Latch Configuration
Table 6. On/Off Control Data Latch Bit Assignment
BIT NUMBER
BIT NAME
OUTON0
OUTON1
OUTON2
∙ ∙ ∙
CONTROLLED CHANNEL
0
1
OUT0
OUT1
OUT2
∙ ∙ ∙
2
∙ ∙ ∙
13
14
15
OUTON13
OUTON14
OUTON15
OUT13
OUT14
OUT15
32
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TLC59291
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ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
Figure 33. Output On/Off Data Latch
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Output On/Off Data Latch
Bit
[15]
[14]
[13]
[12]
[11]
[10]
[9]
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Description
OUTON15
OUTON14
OUTON13
OUTON12
OUTON11
OUTON10
OUTON9
OUTON8
OUTON7
OUTON6
OUTON5
OUTON4
OUTON3
OUTON2
OUTON1
OUTON0
When IC is powered up, these all data are set to “0”
0 = output OFF (default)
1 = output ON
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
8.5.1.3 Control Data Latch
The control data latch is 16-bit in length and contains the Global Brightness Control (BC) Function data, Status
Information Data (SID) load select data, Blank Mode Selection (BLKMS) data, the current value for Invisible
Detection Mode (IDM), IDM working time, and Power-Save Mode enable control data.
When the device is powered up, the data in this data latch are set to the default values shown in Table 8.
The function control data latch configuration is shown in Figure 34.
From common shift register
16 bit
Control data latch (16bits)
LSB
0
MSB
15
10
9
8
13
12
7
---
6
14
11
BLANK
Mode
Select1
BLANK
Mode
Select0
Power
save
enable
Brightness
control
(BC) 6
Brightness
control
(BC) 0
IDM
current
select 1
IDM
current
select 0
IDM
IDM
working working
SID load
control
0
SID load
control
1
time 1
time 0
2 bit
1 bit
2 bit
2 bit
2 bit
7 bit
To BLANK
To output constant current
control circuit
To IDM
To power
save mode
control
To IDM
working
time control
circuit
To SID
current
control
circuit
Mode
select
circuit
data load
control
circuit
circuit
Figure 34. Function Control Data Latch Configuration
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Figure 35. Control Data Latch
15
1
14
0
13
0
12
0
11
0
10
1
9
0
8
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
0
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Control Data Latch
Bit
Field
Type
Reset
Description
[15]
PSMODE
R/W
1b
Power save mode enable (Default value = ‘1b’)
The data selects power save mode enable or disable. When the
mode is enabled, the device goes into power save mode if all
data in the on/off data latch are “0”. Table 15 shows the power
save mode truth table. Figure 7 shows the power save mode
operation timing.
[14:13]
[12:11]
[10]
IDMTIM
IDMCUR
LSDVLT
R/W
R/W
R/W
00b
00b
1b
IDM working time select (Default value = ‘00b’)
The data selects the time of output current sink at OUTn for IDM
to detect LED open detection (LOD) or LSD without visible
lighting. Table 15 shows the work time truth table.Figure 9
shows the IDM operation timing.
IDM current select (Default value = ‘00b’)
The data selects the sink current at OUTn for IDM to detect LED
open detection (LOD) or LSD without visible lighting. Table 14
shows the current value truth table. Figure 9 shows the IDM
operation timing.
LSD detection voltage select. (Default value = ‘1b’)
These two bits select the detection threshold voltage for the LED
short detection (LSD). Table 12 shows the detect voltage truth
table.
[9]
BLKMS
SIDLD
R/W
R/W
0b
BLANK Mode Select (Default value = ‘0b’)
The data selects the working mode for BLANK pin. Table 11
shows the truth table.
[8:7]
00b
SID load control (Default value = ‘00b’)
The data selects the SID data loaded to the common register
when LAT pulse is input for on-off data writing. Table 10 shows
the selected data truth table.
[6:0]
BCALL
R/W
1111111b Global brightness control (Default value = ‘1111111b’)
The 7-bit data controls the current of all output with 128 steps
between 0~100% of the maximum current value set by a
external resistor. Table 13 shows the current value truth table.
8.5.1.4 Output On/Off Data Write Timing and Output Control
When SCLK = “0” at LAT rising edge, the output on-off data can be updated with the 16-bit data in the shift
register after the data are stored to the shift register using SIN and SCLK signals. When the on-off data latch is
updated, SID is loaded into the shift register except SID load control is “00b”. See Figure 11.
When BLANK = SOUT mode, the timing is show in Figure 12.
8.5.1.5 Function Control Data Writing
When SCLK = “1” at LAT rising edge, the control data latch can be updated with the 16-bit data in the shift
register after the data are stored to the shift register using SIN and SCLK signals. When the control data latch is
updated, SID is not loaded into the shift register.
If the device is in SOUT mode (FC[9] = 0) and BLANK = Low, SOUT is connected with BIT 7 of common shift
register. Then FC data can’t be input and not valid. See Figure 13
34
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ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
8.5.1.6 Function Control (FC) Data
The FC data latch is 16 bits long and is used to adjust output current values for LED brightness, select the SID,
BLANK mode select, the output current for IDM, the output on time for IDM, and power-save mode
enable/disable. When the IC is powered on, the control data latch is set to the default value (E67Fh).The control
data latch truth tables are shown in Table 9 through Table 14.
Table 9. Global Brightness Control (BC) Truth Table
BCALL (BIT 6:0)
0000000
0000001
∙ ∙ ∙
Brightness Control for all Output with Output Current
Output current of OUTn is set to IO(LCmax) × 0%
IO(LCmax) × 0.8%
∙ ∙ ∙
1111110
1111111
IO(LCmax) × 99.2%
IO(LCmax) × 100%
Table 10. SID Load Control Truth Table
SIDLD
SID LOADED TO THE COMMON SHIFT REGISTER
BIT 8
BIT 7
0
0
1
1
0
1
0
1
No data is loaded (default value)
LED open detection (LOD) or thermal error flag (TEF) data are loaded
LED short detection (LSD) or pre-thermal warning (PTW) data are loaded
Output leakage detection (OLD) or IREF pin short flag (ISF) data are loaded
Table 11. BLANK Mode Selection Table
BLKMS (BIT 9)
BLANK MODE SELECTION
0
1
SOUT mode, BLANK pin worked as SOUT 8/16 select signal (default)
Enable mode, BLANK pin worked as OUTPUT enable
Table 12. LSD Threshold Voltage Truth Table
LSDVLT (BIT 10)
LED SHORT DETECTION (LSD) THRESHOLD VOLTAGE
VLSD0 (0.35 × VCC typ)
0
1
VLSD3 (0.65 × VCC typ, default value)
Table 13. Current Select for IDM
IDMCUR
SINK CURRENT AT OUTn FOR INVISIBLE DETECTION MODE (IDM)
BIT 12
BIT 11
0
0
1
1
0
1
0
1
IDM is disabled (default value)
2 µA (typ)
10 µA (typ)
20 µA (typ)
Table 14. IDM Work-Time Truth Table
IDMTIM
INVISIBLE DETECTION MODE (IDM) WORKING TIME
BIT 14
BIT 13
0
0
1
1
0
1
0
1
All outputs are turned on for 17 OSC clocks (0.85 µs typ)
All outputs are turned on for 33 OSC clocks (1.65 µs typ)
All outputs are turned on for 65 OSC clocks (3.25 µs typ)
All outputs are turned on for 129 OSC clocks (6.45 µs tyicalp, default value)
Copyright © 2015–2016, Texas Instruments Incorporated
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www.ti.com.cn
Table 15. Power-Save Mode Truth Table
PSMODE (BIT 15)
POWER-SAVE MODE FUNCTION
Power-save mode is disabled.
0
The device does not go into power-save mode even if the bits in the output on/off data latch
are all '0'.
Power save mode is enabled (default value).
1
The device goes into power-save mode when the bits in the output on/off data latch are all
'0'.
36
Copyright © 2015–2016, Texas Instruments Incorporated
TLC59291
www.ti.com.cn
ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The device is a 8/16-channel, constant sink current, LED driver. This device is typically connected in series to
drive many LED lamps with only a few controller ports. On/Off control data and FC control data can be written
from the SIN input terminal. The device has six type error flags: LED open detection (LOD), LED short detection
(LSD), output leak detection (OLD), reference terminal short detection (ISF), Pre themal warning (PTW) and
thermal error flag (TEF).
9.2 Typical Application
In this application, the device VCC and LED lamp anode voltages are supplied from different power supplies.
VLED
OUT0 - - - - - - - - - - OUT15
OUT0 - - - - - - - - - - OUT15
DATA
SIN
SOUT
SIN
SOUT
Controller
VCC
SCLK
LAT
VCC
SCLK
LAT
SCLK
LAT
TLC59291
IC1
TLC59291
ICn
VCC
VCC
BLANK
BLANK
IREF
BLANK
IREF
GND
GND
RIREF
RIREF
GND
GND
GND
GND
3
SID read
Figure 36. Multiple Daisy-chained TLC59291 Devices
9.2.1 Design Requirements
The parameters for the design example are shown in Table 16.
Table 16. Design Parameters
PARAMETER
VALUE
VCC input voltage range
3 V to 5.5 V
LED lamp (VLED) input voltage range
SIN, SCLK, LAT, and GSCLK voltage range
Maximum LED forward voltage (VF) + 0.3 V (knee voltage)
Low level = GND, High level = VCC
9.2.2 Detailed Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
•
•
•
Maximum output constant-current value for each color LED lamp.
Maximum LED forward voltage (VF).
Which error flags are used.
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9.2.3 Application Curves
Time = 400 ns/div
Time = 400 ns/div
Figure 37. Output Waveform When BLANK_Mode = 0
Figure 38. Output Waveform When BLANK_Mode = 1
10 Power Supply Recommendations
The VCC power supply voltage should be decoupled by placing a 0.1-µF ceramic capacitor close to the VCC pin
and GND plane. Depending on the panel size, several electrolytic capacitors must be placed on the board
equally distributed to get a well regulated LED supply voltage (VLED). The VLED voltage ripple must be less than
5% of it nominal value. Futhremore, the VLED must be set to the voltage calculated by Equation 3.
VLED > VF + 0.4 V (10-mA constant-current example)
(3)
Where
•
VF = maximum forward voltage of all LEDs.
38
Copyright © 2015–2016, Texas Instruments Incorporated
TLC59291
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ZHCSE50A –SEPTEMBER 2015–REVISED MARCH 2016
11 Layout
11.1 Layout Guidelines
•
•
•
•
Place the decoupling capacitor near the VCC pin and GND plane
Place the current programming resistor RIREF close to the IREF pin an the IREFGND pin.
Route the GND pattern as widely as possible for large GND currents.
The routing wire between the LED cathode side and the device OUTXn pin must be as short and straight as
possible to reduce wire inductance.
•
When several ICs are chained, symmetric placements are recommended.
11.2 Layout Example
Figure 39. Layout
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12 器件和文档支持
12.1 文档支持
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
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Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC59291RGER
TLC59291RGET
ACTIVE
VQFN
VQFN
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TLC
59291
ACTIVE
RGE
NIPDAU
TLC
59291
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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