TLC5930 [TI]
12-CHANNEL LED DRIVER; 12通道LED驱动器
| 型号： | TLC5930 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-CHANNEL LED DRIVER |
| 文件： | 总39页 (文件大小：780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLLS528 – MARCH 2002
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FEATURES
DESCRIPTION
D
0.2-mA to 40-mA (Constant-Current Sink)
Drive Capability x 12 Bits Output Count into
24-Pin HTSSOP Package
The TLC5930 is a constant-current sink driver
with an adjustable current value, and 1024 gray
scale display that uses pulse width control. The
output current is 0.2 mA to 40 mA with 12 bits of
RGBx4. The maximum current value of the
constant-current output can be set by one external
resistor.
D
D
1024 Gray-Scale Display (PWM Control 1024
Steps) with Max 25-MHz Clock Frequency
3-Way Brightness Adjustment
– Plane Brightness Adjustment for 64 Steps
(40% to 100%)
– Frequency Division for 16 Steps
(6.3% to 100%)
The TLC5930 includes three kinds of brightness
adjustment functions: one adjusts the plane
brightness between devices, changing the current
values of all outputs uniformly. The second adjusts
the frequency division to controls overall panel
brightness, and the third adjusts the dot correction
per LED, changing the current values of
independent output.
– Dot Correction for 256 Steps (0% to 100%)
D
D
D
DS–Link Data Input/Output (Data Rate Max
20 Mbps) with Packet Operation
5 Error Information Types and 2 Gray–Scale
Clock Modes
3.3-V V
and LVTTL Interface
The TLC5930 also includes color–tone correction
function for correcting color per dot (pixel) and
OVM function for constant-current output
terminals used for LED failure detection.
CC
APPLICATION
D
Full- or Multi-Color LED Display
Other features include the thermal error flag
(TEF). The active wire-check (AWC) to check the
communication between the controller and the
device. The LED leakage-detect (LKD) to detect
the reverse leakage on the LED. The GCLK error
flag (GEF) and the HSYNC error flag (HEF) by
monitoring the gray-scale clock count, and the
dual source gray-scale clock (DSG) function to
switch the gray-scale clock to the external input
clock or to switch the internally-generated clock.
The TLC5930 requires three signals for standard
operation: data input and gray-scale clock. Only
three-signal line and 24-pin HTSSOP package
reduce board area and total cost.
PowerPAD is a trademark of Texas Instruments Incorporated.
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Copyright 2002, Texas Instruments Incorporated
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ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
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1
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SLLS528 – MARCH 2002
PWP PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
OUT0
OUT1
OUT2
GND
OUT3
OUT4
OUT5
GND
DTIN
STIN
GCLK
GND
OUT11
OUT10
OUT9
GND
OUT8
OUT7
OUT6
DTOUT
STOUT
XRST
IREF
2
AVAILABLE OPTIONS
PACKAGE
3
4
5
T
A
PowerPad TSSOP
(PWP)
6
7
–20°C to 85°C
TLC5930PWP
8
9
10
11
12
VCC
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage,
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V
Output current (dc),
Input voltage range,
Output voltage range,
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC
O(LC)
IN
V
V
V
V
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC – 0.2 V)
, (when off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 17 V
, (when on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 10 V
DTOUT STOUT
V
OUT0 – OUT11
V
OUT0 – OUT11
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Power dissipation rating at (or above) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 W
stg
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages values are with respsect to GND terminal.
2. At operating temperature range over 25°C, dependent on derating factor of 41 mW/°C.
2
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SLLS528 – MARCH 2002
electrical characteristics, MIN/MAX: V
A
= 3.0 V to 3.6 V, T = – 20°C to 85°C, TYP: V
CC
= 3.3 V,
CC
A
T = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
= – 1 mA
MIN
2.4
TYP
MAX
UNIT
V
V
High-level output voltage
Low-level output voltage
Input current
I
OH
OH
V
I
= 1 mA
0.4
OL
OL
I
I
V
= V
or GND
± 1
µA
IN
CC
Input signal is static, V
= 1 V,
OUT
LL output bits off
16
21
50
R
= 5.1 kΩ,
IREF
I
Supply current
mA
CC
Input signal is static, V = 1 V,
OUT
LL output bits on
40
40
R
= 5.1 kΩ,
IREF
V
= 1.0 V,
R
= 5.1 kΩ,
IREF
OUTn
I
I
Constant-current output current
Output leakage current
35
45
0.1
mA
O(LC)
LL output bits on
OUT0 to OUT11 (V
OUT0 to OUT11 (V
= 15 V)
= 1 V),
µA
LKG
(OUTn)
Constant-current outout error between
bits
(OUTn)
∆I
∆I
∆I
∆I
± 4%
OLC
R
= 5.1 kΩ
IREF
Changes in constant output current
depend on supply voltage
V
= 1.23 V
± 3
± 1
OLC1
OLC2
REF
Changes in constant output current
depend on output voltage
V
OUT
V
IREF
= 1 V to 3 V, R
= 1.23 V,
= 5.1 kΩ,
IREF
1 bit light on
%/V
Changes in constant output current
depend on brightness data
V
OUT
V
IREF
= 1.3 V,
= 1.23 V,
R
= 5.1 kΩ,
IREF
1 bit light on
± 2
OLC3
T
TEF detection temperature
Reference voltage
Junction temperature
= 5.1 kΩ
150
160
170
°C
TSD
V
R
1.23
V
IREF
IREF
switching characteristics, C = 15 pF
L
PARAMETER
TEST CONDITIONS
STOUT
MIN
TYP
12
MAX
15
UNIT
t
t
Rise time
Fall time
DTOUT,
DTOUT,
OUTn,
R
STOUT
10
13
F
See Figure 1
15
40
GCLK – OUT0 on
GCLK – OUT0 off
[(OUTn + 1) – OUTn]
90
110
60
35
25
40
ns
DTIN – OUT0,
STIN – OUT0
60
t
t
Propagation delay time
PD
DTIN – DTOUT,
STIN – DTOUT,
DTIN,
STIN,
STOUT
STOUT
18
60
25
90
10
(1)
Operation mode setting (all output force off)
– OUT0 off
Duty deviation between edge of DTIN and
STIN
DTOUT/STOUT,
STOUT/DTOUT
–10
± 1
EDGE
(1) This specification shows the delay of edge for DATA/STROBE, but data appears in the output with 2 bits delay. (Data propagation delay time
is 2 bits + t
)
D [D/STIN – D/STOUT]
3
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SLLS528 – MARCH 2002
recommended operating conditions
dc characteristics
PARAMETER
CONDITIONS
MIN
3.0
MAX
3.6
UNIT
Supply voltage, V
CC
OUT0 to OUT11 off
OUT0 to OUT11 on
15
10
Voltage applied to constant-current output, V
O
V
High-level input voltage, V
IH
2.0
VCC
0.8
Low-level input voltage, V
IL
GND
High-level output current, I
V
V
= 3.1 V @ DTOUT, STOUT
= 3.1 V @ DTOUT, STOUT
– 1.0
1.0
OH
CC
Low-level output current, I
mA
OL
CC
Constant output current, I
OUT0 to OUT11
40
O(LC)
Operating free-air temperature range, T
– 20
85
°C
A
ac characteristics, V
= 3.1 V to 3.5 V, T = –20°C to 85°C (unless otherwise noted)
A
CC
PARAMETER
GCLK clock frequency
Time between edges
GCLK pulse duration
CONDITIONS
MIN
MAX
UNIT
(1)
f
t
t
t
t
t
2 gray scale inputs
I
= 40 mA
25
MHz
(GCLK)
O(LC)
STIN – DTIN
DTIN – STIN,
30
20
1
(EDGE)
ns
/t
w(H) w(L)
XRST reset pulse duration
Data transfer rate
Setup time
ms
Mb/s
ns
w(L)
20
(DATA)
SU
HSYNC – GCLK
6.5
(1) This is the frequency when any output is obtailed at two or more than gray-scale entered.
4
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SLLS528 – MARCH 2002
functional block diagram
VCC
Communication Logic
DATA
CLK
DM
DTIN
DTOUT
D/S
Link
Decoder
D/S
Link
Decoder
STIN
STOUT
Packet
Shift
Register
Packet
Data
Latch
Packet
Interface
Packet
Interface
GCLK
330 kΩ
CLR
XRST
GSCLK
PWM
Controller
BLANK, FON, FOF, INHSW, INHCS
Analog Converter
Thermal
Error
Flag
ITEF
IOVM
Bandgap
Reference
Generator
Trimming
Circuit
BC
Digital to Analog Converter
Reference
Voltage
&
IDC,ICC
12-Bit Constant Current Driver
IREF
&
Bias Current
Generator
Output
Voltage
Monitor
&
LED Leak
Detector
GND
GND = DGND, AGND, LGND
5
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SLLS528 – MARCH 2002
Terminal Functions
TERMINAL
DESCRIPTION
I/O
NAME
DTIN
NO.
9
I
DS–link data input
DS–link data output
DTOUT
17
O
Clock input for gray scale. The gray scale display is accomplished by lighting the LED until the
number of the gray-scale clock counted is equal to the data latched.
GCLK
GND
11
I
4, 8, 12, 21
–
Ground
Constant-current value setting. LED current is set to the desired value by connecting an external
resistor between IREF and GND. The 168 times current compared to current across the external
resistor flows through the constant-current output terminals.
IREF
14
I/O
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
STIN
1
2
Constant-current output.
3
5
6
7
O
18
19
20
22
23
24
10
16
13
I
O
I
DS–link strobe input
DS–link strobe output
Power supply
STOUT
VCC
Reset signal. This signal is used to initialize the device reset is accomplished by pulling this pin low
(internally pulled up with a 330-kΩ resistor). If not used, this terminal should be left open or connect
XRST
15
I
to V
.
CC
6
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SLLS528 – MARCH 2002
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DTIN, STIN, GCLK
VCC
PAD
GND
DTOUT, STOUT
VCC
PAD
GND
OUTn
PAD
GND
XRST
VCC
330 k
PAD
GND
7
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SLLS528 – MARCH 2002
TIMING DIAGRAMS
VCC
56 Ω
VCC
IREF OUTn
15 pF
5.1 kΩ
GND
Figure 1. Rise Time and Fall Time Test Circuit for OUTn
VIH or VOH
VIH
90%
10%
50%
50%
VIL
VIL or VOL
txxxx
tR
tF
VIH or VOH
VIL or VOL
50%
50%
Figure 2. Timing Requirements
PRINCIPLES OF OPERATION
setting for constant output current value
On the constanct current output terminals (OUT0 to OUT11), approximately 168 times the current that flows
through the external resistor, R , (connected between IREF and GND) can flow. The external resistor value
IREF
is calculated using the following equation:
168 1.23 V
R
(W) +
(IREF)
I
(A)
O(LC)
(1)
where R
should be ≤ 4.88 kΩ
(IREF)
Note that more current flows if IREF is connected directly to GND.
8
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
command packet list
FUNCTION
ID
COMMAND
NO. OF
DATA
BITS
NO. OF
PACKET MODE
BITS
CONTROL
HEX
HEX
BIN
COMMON INDIVIDUAL
Internal reset
00
X
00
02
04
08
10
20
40
50
60
70
80
00000000
8(03h)
24
136
112
48
Write
Write
Write
Write
Write
Write
Write
Read
Read
Write
Wr/Rd
Gray scale data setting
00or01.FF
00or01.FF
00or01.FF
00or01.FF
00or01.FF
00or01.FF
00or01.FF
00or01.FF
00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
00000010 10x12 output
00000100 8x12 output
Dot correction data setting
Color tone correction data setting
Plane brightness adjustment data setting
Color tone correction control setting
Operation mode setting
00001000
00010000
00100000
01000000
01010000
01100000
01110000
10000000
8x4set
16
32
8
16
24
32
OVM information read
16
32
Failure monitor information read
Automatical ID setting
8
24
16(min)
16
32(min)
32
HSYNC synchronization
00
NOTE
Common control is applied to all the devices connected. Indidual control is applied to the device specified by ID.
basic packet configuration
MSB
LSB
DATA (0 to 120 bit)
ID (8 bit)
MSB
CMD (8 bit)
MSB LSB
LSB
MSB
LSB
data configuration
D
D
Q
Q
DATA
GCLK
DTIN
STIN
Q
Q
UDG–02058
Figure 3. DS LINK Configuration
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
packet operation
Data output is performed with delay of two bits from input. In other words, by using the edge of the input, data
before two bits appear in the output terminal. Figure 4 shows the concept for data transfer when some TLC5930s
are connected in a cascade, where data A–Z indicates valid data, and the asterisk (*) marks invalid data. Also,
data A is a first data input from controller, and there is assumed to be no data transition for DATA/STROBE
between [H and I] and [S and T] in the IC1 input data.
Invalid data is clocked out corresponding to the input edge to ensure that no data exists before data A. After
that, data A is clocked out with a time delay of two bits plus t
using the input edge for data C.
D(D/STIN–D/STOUT)
Once data output is started, data before two bits from current input is sequentially clocked out using the input
edge. It should be noted that data output stays during no transition of DATA/STROBE, since no input edge
makes the output edge. Figure 4 shows that the output of IC1 remains in data F and does not go to data G until
the edge of input data I is entered (after IC1 clocked out data F, although the input data of IC1 is continued from
A to H.)
If data A to H are included in one packet, the data output for each output of the device in data H, (which indicates
the completion of packet operation), is performed out at the edge establishing data J for IC1, data L for IC2, data
O for IC3, and data Q for IC4 from the view of controller. In other words, in order to complete the packet operation
for all the devices connected in cascades, additional bit data equivalent to two times the number of devices
cascaded is needed to be clocked in.
Additionally, since each device has the time delay, T
, from input to output, the controller views
D(D/STIN–D/STOUT)
that output having a time delay exceeding two bits against a virtual input to IC1. In this example, while, in
practice, the output data H for IC4 is established by the input edge of data Q, it appears to be synchronized with
data S for IC1.
A
B
C
D
E
F
G
H
I
J
K
L
M
O
P
Q
R
S
T
O
I
U
P
J
V
W
X
Y
Z
IC1 INPUT DATA
2 bit+t
D(D/STIN–D/STOUT)
t
D(D/STIN–D/STOUT)
IC2 INPUT DATA
IC1 OUTPUT DATA
A
B
C
D
E
F
G
H
I
J
K
L
M
O
P
Q
R
S
T
U
V
W X
*
*
IC3 INPUT DATA
IC2 OUTPUT DATA
A
B
C
D
E
F
G
H
I
J
K
L
M
Q
R
S
T
U
V
*
*
*
*
IC4 INPUT DATA
IC3 OUTPUT DATA
A
B
C
D
E
F
G
H
I
J
K
L
M
O
P
Q
R S
*
*
*
*
*
*
2-bit + t
D (D/STIN – D/STOUT)
IC4 OUTPUT DATA
A
B C
D
E
F
G
H
K
L
M
O
P
Q
*
*
*
*
*
*
*
*
UDG–02032
Figure 4. Data Transfer Concept in Cascade Connection
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
As shown in Figure 4, in order for all the cascade-connected devices to complete one packet operation,
additional bit data to input to the first stage equivalent to two times the number of devices cascaded is required
to be clocked in. But, in practice, sending just any data is not acceptable, and some packets with bits
corresponding to two times the number of devices connected are needed for synchronization to be successful.
For example, in the case that 16 ICs are connected in cascade, since 16 x 2 = 32 bits are needed to complete
the packet operation of sixteenth IC, OVM information reading packet as a dummy, which does not write any
data to the device, is desirable. Or, an alternative method to send any packet such as use of unused ID (e.g.
FFh) is available.
Figure 5 shows the concept for normal lighting-ON operation (based on pulse-width control method). Internal
BLANK goes high on the falling edge of the 21st bit in the HSYNC packet. If the constant-current output is ON
at that time, it is turned off (except for force on mode), and the data for which the latch flag is set in the HSYNC
packet is latched during internal BLANK high-level. Internal BLANK goes low on the rising edge of the gray-scale
clock (GCLK) after the edge of LSB (32nd bit) for HSYNC packet, and the TLC5930 goes into the status that
can be turned on by the constant-current output. The constant-current output is turned on by the next rising edge
of the gray-scale clock.
During power up, the initial value of BLANK is at a high level, therefore, operation for BLANK and
constant-current output when HSYNC packet is entered for the first time as a normal operation is different from
the example shown in Figure 5.
In addition, since BLANK and the gray-scale clock are ignored in the force-ON mode, the timing to be lighted
on is also different from the example shown in Figure 5.
11
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
HSYNC packet
DATA INPUT
ID
CMD
Next Packet
DATA
1
20
10
30
INTERNAL CLOCK
LSB of HSYNC Packet
When Gray Scale Clock is Not Sequential
INTERNAL BLANK
GCLK
CONSTANT
Light ON
CURRENT OUTPUT
When Gray Scale Clock Is Sequential
INTERNAL BLANK
GCLK
CONSTANT
Light ON
CURRENT OUTPUT
When Internal Gray Scale Clock Is Used
INTERNAL BLANK
CONSTANT
Light ON
CURRENT OUTPUT
Figure 5. Normal Lighting-ON Operation
12
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
There are two different methods available as shown in Figure 6 for entering the gray-scale clock when in
light-ON mode. When the gray-scale clock is sequential, lighting-ON by the device is initiated after the HSYNC
packet operation for each device has been completed. When the external clock is used as gray-scale clock, all
the devices can be lighted-ON simultaneously by entering the gray scale clock after the HSYNC packet is
entered for the last device (in this example, just after OVM information reading packet has entered to IC1).
When Light-ON in a 4 Gray Scale With 16 ICs
When Gray Scale Clock Is Sequential (Including Use of Internally Generated Gray-Scale Clock)
GRAY SCALE
CLOCK
IC1 D/STIN
HSYNC Packet 32 bits
OVM Information Reading Packet 32bits
ON
IC1 Constant Current Output
IC2 D/STIN
HSYNC Packet 32 bits
OVM Information Reading Packet 32bits
ON
IC2 Constant Current Output
IC15 D/STIN
IC16 D/STIN
HSYNC Packet 32 bits
HSYNC Packet 32 bits
Other Packet
IC15 Constant Current Output
ON
Other Packet
IC16 Constant Current Output
ON
When Gray Scale Clock Is Not Sequential (External Input Only)
GRAY SCALE
CLOCK
IC1 D/STIN
HSYNC Packet 32 bits
OVM Information Reading Packet 32bits
IC1 Constant Current Output
ON
IC2 D/STIN
HSYNC Packet 32 bits
OVM Information Reading Packet 32bits
IC2 Constant Current Output
ON
IC15 D/STIN
IC16 D/STIN
HSYNC Packet 32 bits
HSYNC Packet 32 bits
Other Packet
IC15 Constant Current Output
ON
ON
Other Packet
IC16 Constant Current Output
Figure 6. Lighting-ON Operation With 16 Devices
13
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
command packet and operation
internal reset
By sending this packet once, the internal register within all the devices connected is set to the default value and
synchronized with the controller. Note that individual reset for the device is not available.
packet configuration
ID (bin)
CMD (bin) CMD (bin)
00000000 00000011
00000000
default value
REGISTER
DEFAULT VALUE
COMMENTS
ID
xxxxxxxx
Indeterminate (no write)
Automatic ID setting
Plane brightness adjustment
data setting
Plane brightness
111111 (bin)
0000 (bin)
100%
Plane brightness correction
data setting
Frequency division ratio
1/1 (no frequency division)
Dot correction
Color tone correction
Gray scale
11111111 (bin) × 12 (output)
00000000 (bin) × 4
100%
0%
0
Dot correction data setting
Color tone correction setting
Gray scale data setting
0000000000 (bin) × 12 (output)
CCEN–2
(color tone correction ON/OFF)
000 (bin)
Color tone correction disable
Color tone correction control
FORCE OFF
FORCE ON
DCEN
0
Normal operation
Normal operation
Dot correction disable
Brightness control disable
LKD disable
Operation mode setting
Operation mode setting
Operation mode setting
Operation mode setting
Operation mode setting
Operation mode setting
Operation mode setting
0
0
BCEN
0
LKDEN
0
DSGSL
0
Use GCLK terminal
0.3 V
OVM comparator voltage
0000 (bin)
OVMF, OVMFA, GEF, HEF,
TEF
HSYNC, fault information
reading
1
initialization
During power up, the device is in an indeterminate condition. To fully reset the device after power up, it is
necessary to send an internal reset packet after entering the reset pulse to the XRST terminal or after sending
a 0 to each device 256 times as a dummy and then 03h.
Table 1. Input Configuration After Power-Up When Using XRST (reset pulse + 24 bit)
XRST
RESET (NEGATIVE PULSE)
(03000003h)
INTERNAL RESET PACKET
00000000 00000000 00000011
Note: Both DTIN and STIN should be 0 during XRST 0.
Table 2. Input Configuration After Power-Up When Not Using XRST (256 bit × devices + 24 bit)
DATA (bin)
INTERNAL RESET PACKET
00000000 00000000
DUMMY (bin)
00000011
00000011
0 (256 × devices)
(00h [256 bits × n] + 03000003h)
14
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
gray scale data
Using this packet, the same gray-scale data can be written to all the connected devices simultaneously or
different gray-scale data can be written to each device.
The constant-current output is turned on (constant-current flows), except that gray-scale data entered to
gray-scale data latch is 0, synchronizing with the next rising edge of the gray-scale clock after the rising edge
of the gray-scale clock with the time delay of t from the edge of DTIN/STIN of HSYNC packet LSB. Thereafter,
su
the 10-bit gray-scale counter counts the number of rising edge of the gray-scale clock and outputs is matched
to gray-scale data is turned off (constant-current flow stops).
The user can select either the gray scale clock using GCLK terminal input or the internally generated clock using
DTIN/STIN terminal input. (See DSG function section for more detail)
Table 3. Packet Configuration (136-bit)
DATA
ID
CMD
(bin)
(bin)
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10 OUT11
10 bit 10 bit
xxxxxxxx 00000010 10 bit
10 bit
10 bit
10 bit
10 bit
10 bit
10 bit
10 bit
10 bit
10 bit
OUTn
GRAY SCALE
DATA
dt [9]
dt [8]
dt [7]
dt [6]
dt [5]
dt [4]
dt [3]
dt [2]
dt [1]
dt [0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1023
1024
(xx02xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxh) After ID and CMD, 10 bit data continues 12 output
15
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
dot correction data
Using this packet, the same dot correction data can be written to all connected devices simultaneously, or
different dot correction data can be written to each device.
The dot correction register latch is configured with 12 output x 8 bit; the current value on each constant output
current can be adjusted in 256 steps as 1 step of 0.4% of current ratio between 100% and 0% when output
current is set to 100% by adjusting external resistor and brightness adjustment data. By using this function,
brightness deviation due to brightness variation of LED can be reduced.
Table 4. Packet Configuration (112-bit)
DATA
ID
CMD
(bin)
(bin)
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10 OUT11
xxxxxxxx 00000100 8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
OUTn
RELATIVE
CURRENT
RATIO (%)
I
= 40 mA
OLC
dt [7]
dt [6]
dt [5]
dt [4]
dt [3]
dt [2]
dt [1]
dt [0]
(mA)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0.0
0.4
0.0
0.16
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
99.6
100
39.84
40.00
(xx04xxxxxxxxxxxxxxxxxxxxxxx xh) After ID and CMD, 8 bit data continues 12 output.
color tone correction data
Using this packet, the same color-tone correction data can be written to all the connected devices
simultanoeously or different color tone correction data can be written to each device.
Color tone correction makes correction for color deviation by lighting-ON a little the color of the other LED
simultaneously when wavelength of LED for each RGB is out of alignment from the color required essentially.
The color tone correction function with TLC5930 is configured with color tone correction data packet setting fro
current value corrected per pixel assuming OUT0–OUT2, OUT3–OUT5, OUT6–OUT8 and OUT9–OUT11 as
four pixels, and with color tone correction control packet which controls ON/OFF by OUT0, OUT3, OUT6, OUT9,
and OUT1, OUT4, OUT7, OUT10, and OUT2, OUT5, OUT8, and OUT11 assuming that same color is assigned
for OUT0, OUT3, OUT6, OUT9 and OUT1, OUT4, OUT7, OUT10 and OUT2, OUT5, OUT8, and OUT11
respectively.
The current value for color tone correction set by this packet is set per pixel for OUT0–OUT2, OUT3–OUT5,
OUT6–OUT8, and OUT9–OUT11. In other words, the current value for color tone correction is same in
OUT0–OUT2, OUT3–OUT5, OUT6–OUT8, and OUT9–OUT11.
16
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
The color tone correction register latch is configured with a 4 pixel × 8 bit, and the current value for color tone
correction by pixel can be adjusted between 50% and 0% when output current is set to 100% by adjusting
external resistor and brightness adjustment data. The color tone correction is divided into the coarse adjustment
with 2 bit / 4 steps and the fine adjustment with 6 bit / 64 steps. The current value for the coarse adjustment can
be set to 6.25%, 12.5%, 25% or 50% when current is set to 100% by adjusting external resistor and brightness
adjustment data. The current value for the fine adjustment can be adjusted in 64 steps as 1 step of 1.6% of
current ratio between 100% and 0% when current set at the coarse adjustment is 100%. By using this function,
color tone deviation for RGB can be individually corrected.
This packet sets the current value for color tone correction only, thus setting color tone correction control packet
to ON/OFF is required for effective color tone correction.
Table 5. Packet Configuration (48-bit)
DATA
CMD
(bin)
ID
(bin)
PIXEL3
(OUT6, OUT7, OUT8)
PIXEL1
(OUT0, OUT1, OUT2)
PIXEL2
(OUT3, OUT4, OUT5)
PIXEL4
(OUT9, OUT10, OUT11)
xxxxxxxx 00001000
8 bit
8 bit
8 bit
8 bit
Pixel n
MSB
LSB
COARSE ADJ
(2 bit)
FINE ADJUSTMENT (6 bit)
CURRENT VALUE SET BY COARSE TO 0%
I
= 40 mA
RELATIVE
CURRENT
RATIO (%)
OLC
COARSE
dt [7]
dt [6]
dt [5]
dt [4]
dt [3]
dt [2]
dt [1]
dt [0]
ADJUSTMENT
(3h) (mA)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0.0
1.6
0.0
0.3
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
98.4
19.7
20.0
100.0
CURRENT VALUE AFTER PLANE BRIGHTNESS
ADJUSTMENT (%)
0
1
1
1
0
1
0
1
6.25%
12.5%
25.0%
50.0%
(xx08xxxxxxxxh) After ID and CMD 8 bit data continues 4 set.
17
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
plane brightness adjustment data
Using this packet, the same brightness adjustment data and frequency division data can be written to all
connected devices simultaneously, or different brightness adjustment data and frequency division data can be
written to each device.
The brightness adjustment data latch is configured with 1 x 16 bit, and the current value on each constant output
current can be adjusted in 64 steps as 1 step of 0.94% of current ratio between 100% and 40% when output
current is set to 100% by adjusting external resistor. By using this function, brightness adjustment between
devices can be accomplished by sending required the data from external even though these are mounted on
printed circuit board.
The frequency division ratio register latch is configured with 1 x 4 bit, and the frequency division ratio can be
adjusted in 16 steps between 1:1 and 1:16. This function means that brightness can be adjusted in 16 steps
only by selecting the frequency division ratio, if gray scale clock is set to 16 times the clock (1024x16=16384)
during horizontal scanning time. By using this function, the total panel brightness can be adjusted
simultaneously, and applied to the brightness of day or night.
Table 6. Packet Configuration (32 bit)
DATA
CMD
(Bin)
ID (Bin)
MSB
LSB
MSB
LSB
FREQUENCY
DIVISION DATA
xxxxxxxx 00010000
(xx100xxxh)
RESERVED
RESERVED BRIGHTNESS CONTROL DATA
FREQUENCY
DIVISION
RATIO
RELATIVE
BRIGHTNESS
RATIO %( )
dt [3] dt [2] dt [1] dt [0]
1:1
1:2
6.3
0
0
0
0
0
0
0
1
12.6
.
.
.
.
.
.
.
.
.
1:15
1:16
93.8
1
1
1
1
1
1
0
1
100.0
RELATIVE CURRENT
RATIO (%)
20 (mA)
40 (mA) dt [5] dt [4] dt [3] dt [2] dt [1] dt [0]
40.00
8.00
8.18
16.00
16.38
0
0
0
0
0
0
0
0
0
0
0
1
40.94
.
.
.
.
.
.
.
.
.
.
.
.
99.06
19.82
20.00
39.62
40.00
1
1
1
1
1
1
1
1
1
1
0
1
100.00
UDG–02036
18
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
color tone correction control
Using this packet, the same color tone correction control data can be written to all the connected devices
simultaneously or different color tone correction control data can be written to each device.
The current value set to OUT0–OUT2, OUT3–OUT5, OUT6–OUT8, and OUT9–OUT11 respectively by color
tone correction data packet can be turned on and off per OUT0, OUT3, OUT6, OUT9 and OUT1, OUT4, OUT7,
OUT10 and OUT2, OUT5, OUT8, OUT11 by this color tone correction control packet.
The color tone correction control register latch is configured with 1 × 3 bit, and can be selected from the following
status.
1. To correct the LED color connected to OUT0, OUT3, OUT6, OUT9 (ROUT0, ROUT1, ROUT2, ROUT3)
using small lighting-ON of LED connected to OUT1, OUT4, OUT7, OUT10 (GOUT0, GOUT1, GOUT2,
GOUT3).
2. To correct the LED color connected to OUT0, OUT3, OUT6, OUT9 (ROUT0, ROUT1, ROUT2, ROUT3)
using small lighting-ON of LED connected to OUT2, OUT5, OUT8, OUT11 (BOUT0, BOUT1, BOUT2,
BOUT3).
3. To correct the LED color connected to OUT1, OUT4, OUT7, OUT10 (GOUT0, GOUT1, GOUT2, GOUT3)
using small lighting-ON of LED connected to OUT0, OUT3, OUT6, OUT9 (ROUT0, ROUT1, ROUT2,
ROUT3).
4. To correct the LED color connected to OUT1, OUT4, OUT7, OUT10 (GOUT0, GOUT1, GOUT2, GOUT3)
using small lighting–ON of LED connected to OUT2, OUT5, OUT8, OUT11 (BOUT0, BOUT1, BOUT2,
BOUT3).
5. To correct the LED color connected to OUT2, OUT5, OUT8, OUT11 (BOUT0, BOUT1, BOUT2, BOUT3)
using small lighting-ON of LED connected to OUT0, OUT3, OUT6, OUT9 (ROUT0, ROUT1, ROUT2,
ROUT3).
6. To correct the LED color connected to OUT2, OUT5, OUT8, OUT11 (BOUT0, BOUT1, BOUT2, BOUT3)
using small lighting-ON of LED connected to OUT1, OUT4, OUT7, OUT10 GOUT0, GOUT1, GOUT2,
GOUT3).
7. Does not perform color tone correction.
The constant-current output selected by this packet is lighted-ON with the current value set by the color tone
data packet as many as gray-scale data set to constant-current output for target corrected in addition to gray
scale data and current value set by itself. The current value in this status for lighing-ON equals the sum of the
original display and the color tone correction value.
19
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
Table 7. Packet Configuration (24 bit)
DATA
ID (Bin) CMD (Bin)
MSB
LSB
xxxxxxxx 00100000
RESERVED
CCEN2 CCEN1 CCEN0
CONSTANT CURRENT OUTPUT
FOR COLOR TONE CORRECTION
TURN ON
TARGETED
COLOR TONE CORRECTION OFF
0
0
0
0
0
1
OUT1 (GOUT0)
OUT4 (GOUT1)
OUT7 (GOUT2)
OUT10 (GOUT3)
OUT2 (BOUT0)
OUT5 (BOUT1)
OUT8 (BOUT2)
OUT11 (BOUT3)
OUT0 (ROUT0)
OUT3 (ROUT1)
OUT6 (ROUT2)
OUT9 (ROUT3)
OUT2 (BOUT0)
OUT5 (BOUT1)
OUT8 (BOUT2)
OUT11 (BOUT3)
OUT0 (ROUT0)
OUT3 (ROUT1)
OUT6 (ROUT2)
OUT9 (ROUT3)
OUT1 (GOUT0)
OUT4 (GOUT1)
OUT7 (GOUT2)
OUT10 (GOUT3)
OUT0 (ROUT0)
OUT3 (ROUT1)
OUT6 (ROUT2)
OUT9 (ROUT3)
OUT0 (ROUT0)
OUT3 (ROUT1)
OUT6 (ROUT2)
OUT9 (ROUT3)
OUT1 (GOUT0)
OUT4 (GOUT1)
OUT7 (GOUT2)
OUT10 (GOUT3)
OUT1 (GOUT0)
OUT4 (GOUT1)
OUT7 (GOUT2)
OUT10 (GOUT3)
OUT2 (BOUT0)
OUT5 (BOUT1)
OUT8 (BOUT2)
OUT11 (BOUT3)
OUT2 (BOUT0)
OUT5 (BOUT1)
OUT8 (BOUT2)
OUT11 (BOUT3)
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
0
1
COLOR TONE CORRECTION OFF
UDG–02035
Only one combination is allowed to turn the color tone correction on or off in 1 HSYNC cycle. In other words,
when multiple combinations of correction is required, repeated color tone correction with required number of
gray scale display at one time is necessary. The following is example when all combinations for color tone
correction are needed. Since the current value of the constant-current output for basic display is determined
by the brightness adjustment data plus the dot correction data, the current value for color tone correction is
determined per pixel by the color tone correction data packet based on the current value excluding the dot
correction data after brightness adjustment, although it is different by the constant-current output depending
on dot correction data. Accordingly, the current value for color tone correction is shown as follows.
OUT0 (ROUT0) = OUT1 (GOUT0) = OUT2 (BOUT0), OUT3 (ROUT1) = OUT4 (GOUT1) = OUT5 (BOUT1)
OUT6 (ROUT2) = OUT7 (GOUT2) = OUT8 (BOUT2), OUT9 (ROUT3) = OUT10 (GOUT3) = OUT11 (BOUT3)
20
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
The following example shows all the combinations of color tone correction control with 8 gray scale.
Figure 7. Color Tone Correction Control Combinations With 8–Bit Gray Scale
The timing of lighting-ON for the basic display to be turned on is delayed by t
The lighting-ON for color tone correction is turned on based on ON/OFF timing of output for color tone corrected.
until OUT1–OUT11.
D(OUTn+1–OUTn)
21
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
operation mode setting
Using this packet, the same operation mode can be set to all the connected devices simultanoeously or different
operation modes can be set to each device.
Table 8. Packet Configuration (32-bit)
DATA
ID (Bin) CMD (Bin)
MSB
LSB
F
O
R
C
E
R
E
S
E
R
V
E
D
F
O
R
C
E
D
S
G
S
L
L
K
D
E
N
D
C
E
N
B
C
E
N
OVM
DETECTION
VOLTAGE
SETTING
xxxxxxxx 01000000
RESERVED
O
F
F
O
N
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.3 V
0.1 V
0.2 V
0.3 V
0.4 V
0.5 V
0.6 V
0.7 V
0.8 V
0.9 V
1.0 V
1.1 V
1.2 V
1/2 VCC
2/3 VCC
NO UPDATE
0
0
1
1
0
1
0
1
NORMAL OPERATION
FORCE ALL OUTPUT ON
FORCE ALL OUTPUT OFF
INHIBIT
0
1
SET BRIGHTNESS ADJUSTMENT TO 111111 (100%)
COMPLY WITH VALUE SET BY LATCH
0
1
SET DOT CORRECTION TO 11111111 (100%)
COMPLY WITH VALUE SET BY LATCH
0
1
LKD FUNCTION OFF
LKD FUNCTION ON
0
1
USE INPUT CLOCK TO GCLK AS GRAY SCALE
USE INTERNAL CLOCK WITH INPUT CLOCK TO DTIN/STIN
UDG–02037
22
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
This packet allows DSG function, LKD function, dot correction function, brightness adjustment function, flag
setting for enable/disable to turn all the output on/off, and data setting for detection voltage set in the OVM
function.
DSG function (dual source gray scale clock)
The DSG function selects gray-scale clock from the input clock to GCLK terminal or internally-generated clock
using input to the DTIN/STIN terminals. By using the DSGSL flag in this packet, the signal used for the gray scale
clock is switched as below from next HSYNC packet. By using this function, the number of signal lines for gray
scale clock can be reduced, and display can be continued if DATA/STROBE lines are alive, even though the
gray scale clock has stopped due to any failures such as disconnection when using GCLK terminal.
The GEF/HEF function informs of any failures that may occur on the gray scale clock.
DSGSL=0: input clock to GCLK terminal (maximum operating frequency: 20 MHz)
DSGSL=1: internally generated clock using data input to DTIN/STIN terminals (maximum operating
frequency: 10 MHz)
LKD function
The LKD function supplies a constant-current of approximately 0.6 µA to the output terminal. When the power
supply voltage for the LED is 0 V (GND), writing a 1 to the LKDEN flag allows current flow through LED
subtracted leakage current of the device output transistor (below 0.1 µA) from 0.6µA, and at this time the voltage
on output terminal decreases if the reverse leakage current occurs on LED. In this function, since maximum
applied voltage is 2.7 V, occurrence of reverse leakage current across LED can be found by reading the OVM
detection result through OVM information reading packet by setting the OVM detection voltage to 2/3 VCC. This
function should be used in combination with the FORCE OFF function to turn off all the constant-current outputs
off. The example for this function is shown in Table 9 below.
Table 9. LKD Function Sequence Example
1
2
Set LED power supply to 0 V (GND)
Set operation mode setting packet to force ON=0, force
OFF = 1 and LKDEN = 1
Set OVM detection voltage and force all outputs OFF and
LKD functions ON
3
4
5
Wait at least 1 µs
Read OVM result through OVM information reading packet
Demand detection result
Set operation mode setting paclet to force ON = 0, force
OFF = 0 and LKDEN = 0
LKD function OFF and return to normal operation
DCEN/BCEN
By writing 0 to the flag, the corresponding data (plane brightness data or dot correction data) is set to 100%
default value. By writing 1 to the flag, corresponding data is complied with the value set by data setting packet.
When both DCEN and BCEN are 0, the current value will be 100% of the value set by R
.
IREF
The function by flag setting becomes effective from next HSYNC packet after this packet, and in addition, when
both BCEN and DCEN flags are 1, the value set by respective data setting packets does not become effective
unless BCL and DCL flags in HSYNC packet are set to 1.
Setting both BCEN and DCEN flags to 0, doesn’t affect the latch flags in the HSYNC packet. This function writes
the default 1 to internal latch and the shift register is not updated. Therefore, unless the value for shift register
is updated in respective data setting packet, when plane brightness and dot correction functions are used next,
the previous status can be returned by latching the value of shift register into internal latch by setting BCL/DCL
flag in HSYNC packet after setting this packet.
23
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
all output force off
By writing 0 to force-ON flag and 1 to force-OFF flag in this packet, all the outputs can be turned off
simultaneaously. Also, in this mode, by writing 0 to force-ON flag and 0 to force-OFF flag, it returns to the normal
operation.
all output force on
By writing 1 to force-ON flag and 0 to force-OFF flag in this packet, all the output are turned on independent
of the gray scale data from next HSYNC packet after this packet. At this time, the current value depends on the
plane brightness adjustment data and dot correction data. However, when both DCEN and BCEN are 0, it is
100% of the current value set by R
it returns to the normal operation after sending the HSYNC packet.
. Also, in this mode, by writing 0 to force-ON flag and 0 to force-OFF flag,
IREF
Table 10. All Outputs Forced ON Sequence Example
1
2
3
4
5
Plane brightness, dot corection data setting packet
Operation mode setting packet: force ON = 1 and force OFF = 0
HSYNC synchronization packet
Set desired value for output current.
Demand all output force ON.
Al outputs force ON.
Operation mode setting packet: force ON = 0 and force OFF = 0
HSYNC synchronization packet
Demand return to normal operation
Return to normal operation
Figure 8 shows the operation concept for this mode. All the constant-current outputs are turned on with the
current value set independent of the gray-scale data by HSYNC packet after writing 1 to force-ON flag and 0
to force-OFF flag in operation mode setting packet (these are not turned on if the dot correction value is 0). It
remains in that state independent of gray scale clock until all output force off mode in the packet is sent or
HSYNC packet is sent after writing 0 to force-ON flag and 0 to force-OFF flag in the packet.
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
ALL OUTPUT FORCE ON OPERATION
OPERATION
MODE SETTING
PACKET
FORCE ON = 1
FORCE OFF = 0
OPERATION
MODE SETTING
PACKET
FORCE ON = 0
FORCE OFF = 0
HSYNC
PACKET
OTHER
PACKET
HSYNC
PACKET
OTHER
PACKET
HSYNC
OTHER
PACKET
PACKET
GRAY
SCALE
CLOCK
DON’T CARE
CONSTANT
CURRENT
OUTPUT
NORMAL
LIGHT ON
FORCE ON
NORMAL
LIGHT ON
IF DIFFERENT CURRENT VALUE IS SET
RELATION TO ALL OUTPUT FORCE OFF
OPERATION
OPERATION
MODE SETTING
PACKET
FORCE ON = 0
FORCE OFF = 1
OPERATION
MODE SETTING
PACKET
FORCE ON = 0
FORCE OFF = 0
MODE SETTING
PACKET
FORCE ON = 1
OTHER
PACKET
A
OTHER
PACKET
A
HSYNC
PACKET
OTHER
PACKET
HSYNC
PACKET
FORCE OFF = 0
GRAY
SCALE
CLOCK
DON’T CARE
LIGHT OFF BY RELEASE OF ALL OUTPUT
FORCE ON (LATCHED BY HSYNC)
CONSTANT
CURRENT
OUTPUT
FORCE ON
FORCE ON
NORMAL
LIGHT ON
LIGHT ON BY ALL
OUTPUT FORCE OFF
RE–LIGHT ON BY RELEASE OF
ALL OUTPUT FORCE OFF
UDG–0203
Figure 8. All Output Force ON Operation
Note that, in relation to all output force off shown in Figure 8, when the HSYNC packet is between the other
packet and operation mode setting packet with force-ON = 0 / force-OFF = 0, no re-light-ON happens by release
of all the output force-OFF.
OVM function
The OVM function is to compare the voltage across the constant-current output terminals (OUT0 to OUT11) with
the detection voltage set by this packet, and to output 0 as a comparison result if voltage across terminal is higher
than detection voltage and 1 if lower. The TLC5930 has one comparator per output as shown in Figure 9.
The comparison result input ORed with all the output appears in OVMFA of failure monitor information reading,
and result per output appears in OVM information reading data OVMF[0:11]. By using this function, where LED
disconnection (the voltage across output falls below 0.3 V) or LED short (the voltage across output goes
extremely high) has occurred can be detected. Also, the voltage across the constant-current output terminals
can be known when it is being turned on by changing the setting value of detection voltage, and heat-up from
the device can be minimized by controlling the voltage applied to the anode of the LED to minimize the voltage
across constant-current output (approximately 0.4 V at I = 40 mA) based on the resulting voltage.
O
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
OUT0
+
+
INTERNAL OUT0
LIGHT ON SIGNAL
OVMFA
INTERNAL OUT1
LIGHT ON SIGNAL
OVMF[0]
OUT1
OVMF[1]
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
OUT10
+
+
INTERNAL OUT10
LIGHT ON SIGNAL
OVMF[10]
OVMF[11]
INTERNAL OUT11
LIGHT ON SIGNAL
OUT11
+
COMPARISON
VOLTAGE
UDG–02039
Figure 9. OVM Function
The comparator works so that if a flag is set when read in its operation, voltage across the constant-current
output terminals is lower than the comparison voltage. However, the constant-current output is needed to be
turned on approximately 1 µs continuously until the comparator starts working. For this reason, the following
sequence is recommended to ensure the proper result.
Table 11. OVM Function Sequence Example
1
2
Gray-scale data, dot correction data setting packet
Set the desired value for output current.
Operation mode setting packet: force ON = 1 and force
OFF = 0
Set OVM detection voltage and demand all output force ON.
3
4
5
HSYNC synchronization packet
Al outputs force ON.
Wait at least 1 µs
OVM information reading packet or failure monitor information Read OVM comparison result.
reading packet
6
7
Operation mode setting packet; force ON = 0 and force
OFF = 0
Demand return to normal operation.
HSYNC synchronization packet
Return to normal operation
26
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
OVM information read
Using this packet, the comparison results between OVM detection voltage set by operation mode setting packet
and the each voltage across constant-current output terminal can be read by the individual constant-current
output terminals.
For individual IDs, each flag is information for each constant-current output for each specified device ID.
However for common ID devices, the ORed information for constant-current output terminals of devices is
connected in series. Data sent from the controller should be 0 as a dummy data except for ID and CMD. If the
flag is 1, it is passed through.
Table 12. Packet Configuration (32-bit)
DATA
ID (Bin) CMD (Bin)
LSB
MSB
OVMF OVMF OVMF OVMF OVMF OVMF OVMF OVMF OVMF OVMF OVMF OVMF
xxxxxxxx 01010000
RESERVED
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
OUT11 RESULT
OUT10 RESULT
OUT9 RESULT
OUT8 RESULT
OUT7 RESULT
OUT6 RESULT
OUT5 RESULT
OUT4 RESULT
OUT3 RESULT
OUT2 RESULT
OUT1 RESULT
OUT0 RESULT
(xx500000h. PACKET SENT FROM CONTROLLER)
UDG–02040
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
failure monitor information read
Using this packet, information is ORed when all outputs for OVM detection results, error flags for HEF, GEF,
TEF, and AWC flag can be read out. For individual IDs, each flag is information for each device, and for common
IDs, the information is ORed for devices connected in series. Although defective devices cannot be detected,
problems can be detected only by sending this packet periodically. Data other than AWC sent from controller
should be 0 as a dummy except ID and CMD. When the failure monitor information is 0, the input data (except
AWC) passes through. OVMFA and TEF are sent when this packet is sent. However, HEF and GEF are sent
when the HSYNC packet before this packet has been sent.
Table 13. Packet Configuration (24-bit)
DATA
ID (Bin) CMD (Bin)
MSB
LSB
xxxxxxxx 01100000
RESERVED
OVMFA
HEF
GEF
TEF
AWC
(xx6000h.PACKET SENT FROM CONTROLLER)
UDG–02041
The default value for all the information is 1, so, note that 1 may be read out until normal lighting-ON starts after
the reset packet is sent.
OVMFA
The information ORed with detection results for all constant-current output in OVM function appears in this flag.
Although defective constant-current output cannot be identified by reading this flag, the OVM function detects
output errors.
HEF function (HSYNC Error Flag)
This function is to set 0 to HEF flag if the input number of gray-scale clock per 1 HSYNC cycle is more than 1024,
and 1 if less than 1025, at the time when the next HSYNC packet is sent. For example, when, despite the normal
gray-scale clock, the sending period of the HSYNC packet is shortened for any reason and the number of
gray-scale clock in 1 HSYNC cycle is less than 1025, that is, when the HSYNC packet is entered with the number
of gray-scale clock than 1025, HEF is set to 1. In other words, by using this function, one can know failure in
the HSYNC cycle. This function is assumed to use the TLC5930 for 1024 gray scale, and if use it less than 1025
such as 256 gray scale, this flag should be neglected even though it is always set to 1.
Regarding the number of the gray-scale clock needed for lighting-ON, a gray-scale clock total of 1025,
equivalent to 1024 plus 1, is needed to complete lighting on with 1024 gray-scale clock, since lighting on starts
with second rising edge of gray-scale clock after LSB input of the HSYNC packet.
GEF function (GCLK Error Flag)
This function is to set 0 to GEF flag if the number of gray-scale clock meet the requied number of gray-scale
per 1 HSYNC cycle, and 1 if not, at the time when the next HSYNC packet is sent. For example, when the
gray-scale data for given constant-current output is 100, and the gray-scale clock is entered between 2 and 100
for each HSYNC cycle, the correcponding constant-current output remains in an on–state until the next HSYNC
packet is sent. When the clock is less than 2, the output is not turned on. In this case, if lighting-ON for the number
of gray-scale clock is not done, GEF is set to 1 assumed as failure. In other words, by using this function, one
can know whether the gray scale clock is normally sent or 1 HSYNC cycle meet the lighting-ON time desired.
Notes that this flag is set to 1 independent of the status of the gray-scale clock during one HSYNC cycle after
all outputs are forced on.
28
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
failure monitor information read (continued)
TEF function (thermal error flag)
This function, is used to determine when the junction temperature of the device exceeds its limit. This function
sets 0 to the TEF flag if the junction temperature is less than 160_C, and set it to 1 if the temperature is greater
than 160_C.
AWC function (active wire check)
This function is used to check that the communication between controller and driver is performing normally. The
TLC5930 clocks out the inverted data from written data into bits when this packet is entered. For individual IDs,
the inverted data from the controller output returns to the controller. For common IDs, the same data as the
controller output returns to the controller if the number of devices connected in series is even, but returns to the
inverted data if it is odd.
read information output
For failure monitor information reading (including OVM information reading, failure monitor information flags in
the HSYNC packet), for individual IDs or common IDs, it is set to 1 if an error is indicated. Input data is passed
through if there is no error detected. For AWC, for both individual and common IDs, the inverted data from input
data is clocked out. When the ID is neither common nor matched, the data including AWC is passed through.
Table 16 shows four connected device. Bold bits indicates the reading information output from the device.
Table 14. Read Information Output
ID
NO.
DATA BIT 111111111122222222223333
.123456789012345678901234567890123
DEVICE NUMBER
CONDITION
IC1 INPUT (CONTROLLER OUTPUT)
IC1 OUTPUT (IC2 INPUT)
x000000000110000000000000xxxxxxxxx
IC1: OVM fail
xxx000000000110000000010001xxxxxxx
xxxxx000000000110000000010000xxxxx
xxxxxxx000000000110000000011101xxx
COMM
ON
IC2OUTPUT (IC3 INPUT)
IC2: ALL PASS
IC3: HEF, GEF fail
IC4: ALL PASS
IC3 OUTPUT (IC4 INPUT)
IC4 OUTPUT (CONTROLLER INPUT)
xxxxxxxxx000000000110000000011100x
DEVICE
NUMBER
ID
NO.
DATA BIT 111111111122222222223333
.123456789012345678901234567890123
ID
NO.
DATA BIT 111111111122222222223333
.123456789012345678901234567890123
IC1 INPUT
x000000010110000000000000xxxxxxxxx
xxx000000010110000000010001xxxxxxx
xxxxx000000010110000000010001xxxxx
xxxxxxx000000010110000000010001xxx
xxxxxxxxx000000010110000000010001x
x000000100110000000000000xxxxxxxxx
xxx000000100110000000000000xxxxxxx
IC1 OUTPUT
IC2 OUTPUT
IC3 OUTPUT
IC4 OUTPUT
1
2
xxxxx000000100110000000000001xxxxx
xxxxxxx000000100110000000000001xxx
xxxxxxxxx000000100110000000000001x
DEVICE
NUMBER
ID
NO.
DATA BIT 111111111122222222223333
.123456789012345678901234567890123
ID
NO.
DATA BIT 111111111122222222223333
.123456789012345678901234567890123
IC1 INPUT
x000000110110000000000000xxxxxxxxx
xxx000000110110000000000000xxxxxxx
xxxxx000000110110000000000000xxxxx
xxxxxxx000000110110000000001101xxx
xxxxxxxxx000000110110000000001101x
x000001000110000000000000xxxxxxxxx
xxx000001000110000000000000xxxxxxx
xxxxx000001000110000000000000xxxxx
xxxxxxx000001000110000000000000xxx
xxxxxxxxx000001000110000000000001x
IC1 OUTPUT
IC2 OUTPUT
IC3 OUTPUT
IC4 OUTPUT
3
4
29
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
automatic ID setting
The device that receives this packet stops DTOUT and STOUT for 8 bits (ID portion in below packet
configuration) after CMD, and recognizes the 8 bits as its own ID. Next, 8 bits data with recognized ID plus 1
bit is clocked out, and dummy data sent is passed through until 03h data is entered. When the device receives
03h data, it recognizes the ID setting completion and is ready to receive the next command. During reception
of the next 8 bits each device receives, DATA/STROBE output is inhibited, so the controller must send dummy
data (0) with bit counts of at least minimum device number times 8 bit after ID/CMD/DATA(ID) until this packet
operation is completed including DTOUT/STOUT output.
Table 15. Packet Configuration (32-bit + 8-bit (IC–1))
DATA (BIN)
ID (Bin) CMD (Bin)
ID
DUMMY
END
00000000 01110000
xxxxxxxx
00000000 × IC NUMBER
00000011
(0070xxh + 00h × IC NUMBER + 03h)
UDG–02043
The following is a sequence example for automatic ID setting (in the case of one device and four devices). In
this example, IC1 input indicates output from the controller, while the last device output indicates the input for
the controller. Since the blank portion in the example does not recognize the input in DS-LINK, input to controller
is continuous ID/CMD/DATA(DATA=number of devices + 1). There are two different methods to send
DATA(END) 03h;
D
D
Calculate and send the number of dummy data as the number of devices times 8 bits.
Stop the dummy data output synchronizing with receiving the ID/CMD/DATA(DATA=number of devices +
1) at the controller input and send DATA 03h.
The latter case is useful when the number of connected devices is unknown (for automatic recognition). The
number of devices connected that can be known from that DATA(ID) received by the controller shows the
number of devices plus 1. In any case, dummy data should be an 8-bit base.
Table 16. One IC (No Dummy Data)
IC NUMBER
DATA BIT ..............1111111111222222222233333333334444
.....1234567890123456789012345678901234567890123.....
IC1 INPUT
IC1 OUTPUT
xxxxx0000000001110000000000010000001100000011xxxxx
xxxxxxx0000000001110000........0000001000000011xxx
Table 17. Four ICs (24-bit Dummy Data)
IC NUMBER
DATA BIT ..............11111111112222222222333333333344444444445555555555666666666677
.....12345678901234567890123456789012345678901234567890123456789012345678901..
IC1 INPUT
xxxxx0000000001110000000000010000000000000000000000000000000000000011xxxxxxxxx
IC1 OUTPUT (IC2 INPUT) xxxxxxx0000000001110000........0000001000000000000000000000000000000011xxxxxxx
IC2 OUTPUT (IC3 INPUT) xxxxxxxxx00000000011100........00........00000011000000000000000000000011xxxxx
IC3 OUTPUT (IC4 INPUT) xxxxxxxxxxx000000000111........00........00........000001000000000000000011xxx
IC4 OUTPUT
xxxxxxxxxxxxx0000000001........11........00........00........0000010100000011x
30
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
HSYNC synchronization
The constant-current output is turned on, synchronizing with this packet. In addition, for common IDs, the failure
monitor information flag is read out through the 5 LSB of DATA within the packet (see failure monitor information
read section), and data written in the internal register within gray scale data setting packet, plane brightness
adjustment data setting packet, dot correction data setting packet, color tone correction setting packet, and color
tone correction control setting packet are latched, depending on the status of the register latch flag of 5 MSB
of DATA. Since each flag in the register latch flag is independent, writing a 1 allows the respective packet data
to be latched. Writing a 0 to the flag allows no latch. By using this function, gray scale data, plane brightness
adjustemnt data , dot correction data, color–tone correction, and correction control setting packets can be sent
asynchronously with the HSYNC cycle.
Note that no lighting-ON occurs when the gray-scale clock is entered before this HSYNC packet of normal
lighting-ON operation (including use of internally generated clock) during the first normal lighting-ON operation
(PWM operation) after power up. Normal operation occurs after the second operation.
Table 18. Packet Configuration (32-bit)
REGISTER LATCH FLAG
MSB
DATA
FAILURE MONITOR FLAG
ID (Bin)
CMD (Bin)
LSB
TEF AWC
00000000 10000000 GSL
BCL
DCL CCL
CSL
RESERVED
OVMFA HEF GEF
REFER FAILURE MONITOR READ
LATCH COLOR TONE
1
CORRECTION CONTROL DATA
LATCH COLOR TONE CORRECTION DATA
LATCH DOT CORRECTION DATA
1
1
1
0
LATCH PLANE BRIGHTNESS ADJUSTMENT DATA
LATCH GRAY SCALE DATA
1
0
0
0
0
NO LATCH
(0080xxh.PACKET SENT FORM CONTROLLER)
UDG–02044
Table 21 shows the relationship between failure monitor information reading packet, HSYNC packet, and other
various error flags.
Table 19. Error Flag Relationships
TIME
HSYNC
PACKET
FAILURE
PACKET
FAILURE
PACKET
FAILURE
PACKET
HSYNC
PACKET
HSYNC
PACKET
FAILURE
PACKET
HSYNC
PACKET
FAIL
FAIL
FAIL
FAIL
OVMFA
HEF
1
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
OCCUR
RELEASE
OCCUR
RELEASE
GEF
TEF
31
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
calculating constant-current output
The current value of constant-current output can be calculated using the following expression.
+ 42 ǒI
Ǔ
I
) I
OLC (n)
DC (n)
CC (n)
(2)
Where I
is main current (except color tone correction), I
is color tone correction current. Both currents are
is established by dot correction data and gray scale data.
DC
CC
referenced with reference current, I
, and I
(IREF)
(DC)
I
from color tone correction data and color tone correction control data. n is output terminal number, 0 to 11.
CC
reference current
The reference current I
can be calculated with external resistor, R
, voltage reference, V
, and plane
IREF
IREF
IREF
brightness data, r , using the following expression.
BC
VȀ
IREF
+ 4 ǒ Ǔ
I
IREF
R
IREF
(3)
0.6 ǒr ) 1Ǔ
+ȱ0.4 )
ȳ
BC
VȀ
V
ǒ Ǔȧ
ȧ
IREF
IREF
64
Ȳ
ȴ
(4)
main current
The main current, I , can be calculated with dot correction data, r , logic signal, S , established by gray
DC
DC
MAIN
scale data, and reference current, I
, using the following expression.
IREF
ǒr
Ǔ
DC (n)
I
+
S
I
DC (n)
MAIN (n)
IREF
256
(5)
Where S
, is set to following value depending on gray scale data, r
.
MAIN
GC
1: r
0: r
> 0
= 0
GC (n)
S
MAIN (n) =
{
GC (n)
32
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
color tone correction current
The color tone correction current, I , can be calculated with I′
established by color tone correction data, and
CC
CC
logic signal, S , for color tone correction current switch established by the combination of color tone correction
CC
control data with logic signal for main current switch, using the following expression.
I′
is expressed depending on color tone correction data r
r
through r
as follows.
CC
CC1
CC4
CC1[5:0]
1
IȀ
IȀ
IȀ
+ IȀ
+ IȀ
+ IȀ
+ IȀ
+ IȀ
+ IȀ
+ IȀ
+
+
+
I
CC(0)
CC(3)
CC(6)
CC(1)
CC(4)
CC(7)
CC(2)
CC(5)
CC(8)
IREF
64
2 ǒ4 * r
Ǔ
Ǔ
Ǔ
CC1[7:6]
(6)
(7)
(8)
(9)
r
r
CC2[5:0]
1
I
IREF
64
2 ǒ4 * r
CC2[7:6]
CC3[5:0]
1
I
IREF
64
2 ǒ4 * r
CC3[7:6]
r
CC4[5:0]
1
IȀ
+ IȀ
+
I
CC(9)
CC(10)
CC(11)
IREF
64
2 ǒ4 * r
Ǔ
CC4[7:6]
S
is set up by color tone correction control switch, S
, established by color tone correction control data
CC
CCEN
r
and S
. S
is expressed as follows:
CCEN
MAIN CCEN
1: r
=0 0 1 (bin)
CCEN
S
S
S
S
S
S
CCEN1 =
CCEN2 =
CCEN3 =
CCEN4 =
CCEN5 =
CCEN6 =
{
{
{
{
{
{
0: except the above
1: r =0 1 0 (bin)
CCEN
0: except the above
1: r =0 1 1 (bin)
CCEN
0: except the above
1: r =1 0 0 (bin)
CCEN
0: except the above
1: r =1 0 1 (bin)
CCEN
0: except the above
1: r =1 1 0 (bin)
CCEN
0: except the above
33
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
1: (S
and S
) or (S
) or (S
) or (S
) or (S
) or (S
) or (S
) or (S
) or (S
) or (S
and S
and S
and S
and S
and S
and S
and S
and S
and S
) = TRUE
) = TRUE
) = TRUE
) = TRUE
) = TRUE
) = TRUE
) = TRUE
) = TRUE
) = TRUE
CCEN3
MAIN[1]
CCEN5
CCEN6
CCEN4
CCEN5
CCEN6
CCEN4
CCEN5
CCEN6
CCEN4
MAIN[2]
MAIN[2]
MAIN[1]
MAIN[5]
MAIN[5]
MAIN[4]
MAIN[8]
MAIN[8]
MAIN[7]
S
S
S
S
S
S
S
S
S
S
CC[0] =
CC[1] =
CC[2] =
CC[3] =
CC[4] =
CC[5] =
CC[6] =
CC[7] =
CC[8] =
CC[9] =
{
{
{
{
{
{
{
{
{
{
{
{
0: except the above
1: (S and S
CCEN1
MAIN[0]
0: except the above
1: (S and S
CCEN2
MAIN[0]
0: except the above
1: (S and S
CCEN3
MAIN[4]
0: except the above
1: (S and S
CCEN1
MAIN[3]
0: except the above
1: (S and S
CCEN2
MAIN[3]
0: except the above
1: (S and S
CCEN3
MAIN[7]
0: except the above
1: (S and S
CCEN1
MAIN[6]
0: except the above
1: (S and S
CCEN2
MAIN[6]
0: except the above
1: (S and S
) or (S
and S
) = TRUE
CCEN3
MAIN[10]
CCEN5
MAIN[11]
0: except the above
1: (S and S
) or (S
and S
) = TRUE
) = TRUE
CCEN1
MAIN[9]
CCEN6
CCEN4
MAIN[11]
MAIN[10]
S
CC[10] =
0: except the above
1: (S and S
) or (S
and S
CCEN2
MAIN[9]
S
CC[11] =
0: except the above
34
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SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
Table 20. Register Term Summary
DATA
FUNCTION
r
Plane brightness adjustment data set by plane brightness adjustment data setting packet
Dot correction data set by dot correction data setting packet
BC
DC
GC
r
r
Gray scale data set by gray scale data setting packet
r
r
r
r
Color tone correction data for pixel 1 set by color tone correction data setting packet
Color tone correction data for pixel 2 set by color tone correction data setting packet
Color tone correction data for pixel 3 set by color tone correction data setting packet
Color tone correction data for pixel 4 set by color tone correction data setting packet
Color tone correction control flag set by color tone correction control setting packet
CC1
CC2
CC3
CC4
r
CCEN
35
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Timing chart 1
(when external gray scale clock is used)
GSL BCL DCL CCL CSL
OVMFA
HSYNC PACKET
Next packet
Input data
HEF GEF TEF AWC
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
DTIN
STIN
1/tDATA
tEDGE
Hsync packet
Next packet
TEF AWC
Output data
GSL BCL DCL CCL CSL
HEF GEF
OVMFA
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
DTOUT
STOUT
By AWC function, inverted data from
input is clocked out
tD(D/SIN–D/SOUT)
1/fGCLK
tSU(HSYNC–GCLK)
tWL(GCLK)
GCLK
OUT0
tWH(GCLK)
2nd rising edge
tD(D/SIN–OUT0)
tD(GCLK–OUT0)
Driver ON
tD(GCLK–OUT0)
Driver OFF
(OUT0:G/S data9)
Driver OFF
tD(OUTn+1–OUTn)
tD(OUTn+1–OUTn)
Driver OFF
OUT1
Driver ON
OUT11
Driver OFF
Driver ON
When in all output force on or number of gray scale clock is less than data count
T iming chart 2 (when internal gray scale clock is used)
HSYNC packet
Next packet
HEF GEF TEF AWC
Input data
GSL BCL DCL CCL CSL
OVMFA
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
DTIN
STIN
1/tDATA
tEDGE
HSYNC packet
Next packet
Output data
GSL BCL DCL CCL CSL
HEF GEF TEF AWC
OVMFA
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
DTOUT
STOUT
By AWC function, inverted data from input is clocked out
tD(D/SIN–D/SOUT)
tD(D/SIN–OUT0)
tD(D/SIN–OUT0)
4th edge from edge of D/SIN HSYNC packet LSB
tD(D/SIN–OUT0)
OUT0
Driver OFF
Driver ON
(OUT0:G/S data3)
Driver OFF
tD(OUTn+1–OUTn)
tD(OUTn+1–OUTn)
OUT1
Driver OFF
Driver ON
OUT11
Driver OFF
Driver ON
When in all output force on or number of gray-scale closk is less than data count
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ
MHTS001D – JANUARY 1995 – REVISED MAY 1999
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
M
0,10
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/F 10/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
38
www.ti.com
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