TLC5940 [TI]
16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL; 16通道LED驱动器，具有点校正和灰度PWM控制
| 型号： | TLC5940 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL |
| 文件： | 总29页 (文件大小：1385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5940
PWP
RHB
NT
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
FEATURES
APPLICATIONS
•
•
•
•
Monocolor, Multicolor, Fullcolor LED Displays
LED Signboards
Display Backlighting
General, High-Current LED Drive
•
•
•
16 Channels
12 bit (4096 Steps) Grayscale PWM Control
Dot Correction
– 6 bit (64 Steps)
– Storable in Integrated EEPROM
Drive Capability (Constant Current Sink)
– 0 mA to 60 mA (VCC < 3.6 V)
– 0 mA to 120 mA (VCC > 3.6 V)
LED Power Supply Voltage up to 17 V
VCC = 3 V to 5.5 V
DESCRIPTION
•
The TLC5940 is a 16-channel constant-current sink
LED driver. Each channel has an individually adjust-
able 4096-step grayscale PWM brightness control
and a 64-step constant-current sink (dot correction).
The dot correction adjusts the brightness variations
between LED channels and other LED drivers. The
dot correction data is stored in an integrated
EEPROM. Both grayscale control and dot correction
are accessible via a serial interface. A single external
resistor sets the maximum current value of all 16
channels.
•
•
•
•
•
•
•
Serial Data Interface, SPI comp.
Controlled In-Rush Current
30-MHz Data Transfer Rate
CMOS Level I/O
Error Information
The TLC5940 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature con-
dition.
– LOD: LED Open Detection
– TEF: Thermal Error Flag
VCC
GND
SCLK
SIN
XLAT
DCPRG
CNT
VPRG
Constant Current
1
0
12−Bit Grayscale
PWM Control
Driver
OUT0
GS Register
DC Register
V
=1.24 V
REF
IREF
VPRG
0
0
11
5
Max. OUTn
Current
Delay
x0
0
DCPRG
1
1
6−Bit Dot
Correction
0
0
GSCLK
BLANK
GS Counter
CNT
DC EEPROM
VPRG
0
5
LED Open Detection
Input
Shift
Register
CNT
0
96
Status
Information:
Constant Current
Driver
192
192
12−Bit Grayscale
PWM Control
GS Register
OUT1
LOD,
12
6
23
TED,
DCPRG
1
Delay
x1
96
DC DATA
191
95
96
6−Bit Dot
Correction
DC Register
1
0
11
0
VPRG
DC EEPROM
6
11
LED Open Detection
96
LED Open
Detection
(LOD)
VPRG
CNT
Temperature
Error Flag
(TEF)
Blank
1
0
Input
Constant Current
Driver
12−Bit Grayscale
PWM Control
Shift
GS Register
OUT15
Register
180
191
Delay
x15
DCPRG
1
XERR
6−Bit Dot
DC Register
Correction
90
95
0
191
DC EEPROM
LED Open Detection
90
95
SOUT
VPRG
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE(1)
28-pin HTSSOP PowerPAD™
32-pin 5 mm x 5 mm QFN
28-pin PDIP
PART NUMBER
TLC5940PWP
TLC5940RHB
TLC5940NT
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS.
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
–0.3 V to 6 V
130 mA
VI
IO
VI
Input voltage range(2)
Output current (dc)
Input voltage range
VCC
V(BLANK), V(DCPRG), V(SCLK), V(XLAT)
V(SOUT), V(XERR)
V(OUT0) to V(OUT15)
V(PRG)
–0.3 V to VCC +0.3 V
–0.3 V to VCC +0.3 V
–0.3 V to 18 V
–0.3 V to 24 V
50
VO
Output voltage range
EEPROM program range
EEPROM write cycles
HBM (JEDEC JESD22-A114, Human Body Model)
CBM (JEDEC JESD22-C101, Charged Device Model)
2 kV
ESD rating
500 V
Tstg
TA
Storage temperature range
–55°C to 150°C
–40°C to 85°C
31.58°C/W
35.9°C/W
Operating ambient temperature range
HTSSOP (PWP)(4)
Package thermal impedance(3)
QFN (RHB)
PDIP (NP)
48°C/W
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) With PowerPAD soldered on PCB with 2 oz. trace of copper. See SLMA002 for further information.
2
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX UNIT
DC CHARACTERISTICS
VCC
VO
Supply Voltage
3
5.5
17
V
V
Voltage applied to output (OUT0–OUT15)
High-level input voltage
VIH
VIL
IOH
IOL
0.8 VCC
GND
VCC
0.2 VCC
–1
V
Low-level input voltage
V
High-level output current
Low-level output current
VCC = 5 V at SOUT
mA
mA
mA
mA
V
VCC = 5 V at SOUT, XERR
OUT0 to OUT15, VCC < 3.6 V
OUT0 to OUT15, VCC > 3.6 V
1
60
IOLC
Constant output current
120
23
V(PRG)
TA
AC CHARACTERISTICS VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
EEPROM program voltage
20
22
Operating free-air temperature range
-40
85
°C
f(SCLK)
f(GSCLK)
twh0/twl0
twh1/twl1
twh2
twh3
tsu0
Data shift clock frequency
Grayscale clock frequency
SCLK pulse duration
SCLK
30
30
MHz
MHz
ns
GSCLK
SCLK = H/L (see Figure 8)
GSCLK = H/L (see Figure 13)
XLAT = H (see Figure 11)
BLANK = H (see Figure 13)
SIN–SCLK (see Figure 11)
SCLK–XLAT (see Figure 11)
VPRG–SCLK (see Figure 6)
VPRG–XLAT (see Figure 6)
BLANK–GSCLK (see Figure 13)
VPRG–DCPRG
16
16
20
20
10
10
10
10
10
1
GSCLK pulse duration
XLAT pulse duration
ns
ns
BLANK pulse duration
ns
ns
tsu1
ns
tsu2
ns
Setup time
tsu3
ns
tsu4
ns
tsu5
ms
ns
th0
SCLK–SIN (see Figure 11)
XLA–SCLK (see Figure 11)
SCLK–VPRG (see Figure 6)
XLAT–VPRG (see Figure 6)
BLANK–GSCLK (see Figure 13)
DCPRG–VPRG
10
10
10
10
10
1
th1
ns
th2
ns
Hold Time
th3
ns
th4
ns
th5
ms
ms
tprog
Programming time for EEPROM
20
DISSIPATION RATINGS
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
POWER RATING
PACKAGE
TA < 25°C
TA = 70°C
TA = 85°C
28-pin HTSSOP with
3958 mW
2026 mW
31.67 mW/°C
2533 mW
1296 mW
2058 mW
1053 mW
PowerPAD™(1)soldered
28-pin HTSSOP with PowerPAD™ un-
soldered
16.21 mW/°C
32-pin QFN(1)
3482 mW
2456 mW
27.86 mW/°C
19.65 mW/°C
2228 mW
1572 mW
1811 mW
1277 mW
28-pin PDIP
(1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information.
3
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = -1 mA, SOUT
IOL = 1 mA, SOUT
VCC– 0.5
V
0.5
1
V
VI = VCC or GND; BLANK, DCPRG, GSCLK, SCLK, SIN,
XLAT
–1
–1
µA
mA
VI = GND; VPRG
1
50
10
II
Input current
VI = VCC; VPRG
VI = 22 V; VPRG; DCPRG = VCC
4
No data transfer, all output OFF,
VO = 1 V, R(IREF) = 10 kΩ
0.9
6
12
25
No data transfer, all output OFF,
VO = 1 V, R(IREF) = 1.3 kΩ
5.2
16
ICC
Supply current
mA
Data transfer 30 MHz, all output ON,
VO = 1 V, R(IREF) = 1.3 kΩ
Data transfer 30 MHz, all output ON,
VO = 1 V, R(IREF) = 640 Ω
30
61
60
69
IO(LC)
Ilkg
Constant output current
Leakage output current
All output ON, VO = 1 V, R(IREF) = 640 Ω
54
mA
All output OFF, VO = 15 V, R(IREF) = 640 Ω,
OUT0 to OUT15
0.1
µA
All output ON, VO = 1 V, R(IREF) = 640 Ω,
OUT0 to OUT15, –20°C to 85°C
±1
±1
±1
±1
±4
±8
±6
±8
±4
±4
±4
±6
±6
±8
All output ON, VO = 1 V, R(IREF) = 640 Ω,
OUT0 to OUT15
∆IO(LC0) Constant current error
%
All output ON, VO = 1 V, R(IREF) = 320 Ω,
OUT0 to OUT15, –20°C to 85°C
All output ON, VO = 1 V, R(IREF) = 320 Ω,
VCC = 4.5 V to 5.5 V, OUT0 to OUT15
Device to device, Averaged current from OUT0 to
OUT15, R(IREF) = 1920 Ω (20 mA)
–2
+0.4
∆IO(LC1) Constant current error
∆IO(LC2) Constant current error
%
Device to device, Averaged current from OUT0 to
OUT15, R(IREF) = 480 Ω (80 mA)
–2.7
+2
%
All output ON, VO = 1 V, R(IREF) = 640 Ω
OUT0 to OUT15
±1
±1
±2
±2
%/V
%/V
%/V
%/V
Power supply rejection ratio,
PSRR
∆IO(LC3)
All output ON, VO = 1 V, R(IREF) = 320 Ω ,
OUT0 to OUT15
All output ON, VO = 1 V to 3 V, R(IREF) = 640 Ω,
OUT0 to OUT15
∆IO(LC4) Load regulation
All output ON, VO = 1 V to 3 V, R(IREF) = 320 Ω,
OUT0 to OUT15
T(TEF)
V(LED)
Thermal error flag threshold
LED open detection threshold
Junction temperature(1)
150
170
0.4
°C
0.3
V
Reference voltage
output
V(IREF)
RI(REF) = 640 Ω
1.20
1.24
1.28
V
(1) Not tested. Specified by design
4
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
SWITCHING CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = -40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX UNIT
tr0
SOUT
16
ns
30
Rise time
tr1
OUTn, VCC = 5 V, TA = 60°C, DCx = 3F
SOUT
tf0
16
ns
30
Fall time
tf1
OUTn, VCC = 5 V, TA = 60°C, DCx = 3F
SCLK–SOUT (see Figure 11)
DCPRG–OUT0
10
tpd0
tpd1
tpd2
tpd3
tpd4
tpd5
td
30
30
ns
ns
ns
ns
ns
ns
ns
BLANK–OUT0 (see Figure 13 )
OUTn - XERR (see Figure 13 )
GSCLK–OUT0 (see Figure 13 )
XLAT–IOUT (dot correction)
OUTn–OUT(n+1) (see Figure 13 )
60
Propagation delay time
Output delay time
1000
60
1000
30
20
5
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
NT PACKAGE
(TOP VIEW)
OUT1
OUT0
VPRG
SIN
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
28
GND
BLANK
XLAT
SCLK
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
2
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
27
26
25
24
23
22
21
20
19
18
17
16
15
3
DCPRG
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
3
4
SCLK
XLAT
4
5
5
6
Thermal
PAD
BLANK
GND
7
6
8
7
9
VCC
8
10
11
12
13
14
IREF
9
DCPRG
GSCLK
SOUT
XERR
OUT15
10
11
12
13
14
OUT8
RHB PACKAGE
(TOP VIEW)
DCPRG 25
IREF 26
VCC 27
NC 28
16 OUT10
15 OUT9
14 OUT8
13 NC
THERMAL
PAD
NC 29
12 NC
GND 30
BLANK 31
XLAT 32
11 OUT7
10 OUT6
9
OUT5
NC − No internal connection
6
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTION
TERMINAL
NO.
I/O
DESCRIPTION
NAME
DIP PWP
RHB
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also
reset. When BLANK = L, OUTn are controlled by grayscale PWM control.
BLANK
23
2
31
I
I
Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H,
DC is connected to the DC register.
DCPRG
19
26
25
DCPRG is also controls EEPROM writing, when VPRG = V(PRG)
GND
22
18
20
1
30
24
26
G
I
Ground
GSCLK
IREF
25
27
Reference clock for grayscale PWM control
Reference current terminal
I
12, 13,
28, 29
NC
–
–
No connection
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
SCLK
SIN
28
1
7
4
5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Serial data shift clock
Serial data input
8
2
9
6
3
10
11
12
13
14
15
16
17
18
19
20
21
22
4
7
4
8
5
9
6
10
11
14
15
16
17
18
19
20
21
1
7
8
9
10
11
12
13
14
15
25
26
17
21
5
2
I
SOUT
VCC
24
28
23
27
O
I
Serial data output
Power supply voltage
Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the
device is in DC mode. When VPRG = V(PRG), DC register data can programmed into DC
EEPROM with DCPRG=HIGH.
VPRG
27
6
3
I
XERR
XLAT
16
24
23
3
22
32
O
I
Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.
Data latch. Note that the internal connections are switched by VPRG. At XLAT↑ (VPRG =
GND), GS register gets new data. At XLAT↑ (VPRG = VCC), DC register gets new data.
7
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Resistor values are equivalent resistances, and they are not tested.
INPUT EQUIVALENT CIRCUIT
OUTPUT EQUIVALENT CIRCUIT (SOUT)
(BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG)
VCC
23 W
400 W
INPUT
SOUT
23 W
GND
GND
INPUT EQUIVALENT CIRCUIT (IREF)
OUTPUT EQUIVALENT CIRCUIT (XERR)
VCC
23 W
Amp
XERR
_
400 W
+
INPUT
100 W
GND
GND
INPUT EQUIVALENT CIRCUIT (VCC)
OUTPUT EQUIVALENT CIRCUIT (OUT)
INPUT
OUT
GND
INPUT EQUIVALENT CIRCUIT (VPRG)
INPUT
GND
GND
Figure 1. Input and Output Equivalent Circuits
8
TLC5940
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SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION (continued)
t
, t , t
, t , t
t
t
who wIO wh1 wl1 su0
su4, h4
V
(LED)
= 4 V
SOUT
Testpoint
C = 15 pF
R = 51 W
L
L
OUTn
Testpoint
C = 15 pF
L
IOLC, IOLC3, IOLC4, IOUT/IREF
=
V
(LED)
1 V
OUT0
OUTn
V
= 0 V ~ 7 V
_
CC
+
OUT15
IREF
Testpoint
= 640 W
R
IREF
Figure 2. Parameter Measurement Circuits
9
TLC5940
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SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS
REFERENCE RESISTOR
vs
OUTPUT CURRENT
POWER DISSIPATION RATE
vs
FREE-AIR TEMPERATURE
100 k
4 k
TLC5940PWP
PowerPAD Soldered
TLC5940RHB
3 k
10 k
TLC5940NT
2 k
TLC5940PWP
PowerPAD Unsoldered
1 k
1 k
100
0
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
o
I
− Output Current − mA
T
− Free-Air Temperature − C
O
A
Figure 3.
Figure 4.
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
I
= 60 mA
max
I
= 30 mA
max
I
= 5 mA
max
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
V
− Output Voltage − V
O
Figure 5.
10
TLC5940
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SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5940 includes a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal
shifts the data from the SIN pin to the internal register. After all data is clocked in, a rising edge of XLAT latches
the serial data to the internal registers. All data are clocked in with the MSB first. Multiple TLC5940 devices can
be cascaded by connecting the SOUT pin of one device with the SIN pin of the following device. The SOUT pin
can also be connected to the controller to receive status information from TLC5940. The serial data format is
96-bit or 192-bit wide, depending on programming mode of the device.
DC Mode Data
Input Cycle
GS Mode Data
Input Cycle
DC Mode Data
Input Cycle
Vcc
VPRG
t
h3
t
t
h3
su3
XLAT
SIN
DC n
MSB
DC n
LSB
GS
MSB
GS
LSB
DC n+1
MSB
DC n+1
MSB−1
t
h2
t
t
h2
t
su2
su2
1
96
1
192
193
1
2
SCLK
SOUT
DC n
MSB
DC n
LSB
DC
MSB
GS
MSB
SID
MSB
X
X
X
Figure 6. Serial Data Input Timing Chart
ERROR INFORMATION OUTPUT
The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned
on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and
pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error
(see Figure 14).
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 1. XERR Truth Table
ERROR CONDITION
TEMPERATURE
ERROR INFORMATION
SIGNALS
OUTn VOLTAGE
Don't Care
TEF
L
LOD
X
BLANK
XERR
TJ < T(TEF)
TJ > T(TEF)
H
H
L
H
L
L
L
Don't Care
H
X
OUTn > V(LED)
OUTn < V(LED)
OUTn > V(LED)
OUTn < V(LED)
L
L
TJ < T(TEF)
L
H
L
H
L
TJ > T(TEF)
H
H
11
TLC5940
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SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
TEF: THERMAL ERROR FLAG
The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If
the junction temperature exceeds the threshold temperature (160°C typical), the TEF circuit trips and pulls XERR
to ground. TEF status can also be read out from the TLC5940 status register.
LOD: LED OPEN DETECTION
The TLC5940 provides an LED open-detection circuit (LOD). This circuit reports an error if any one of the 16
LEDs is open or disconnected from the circuit. The LOD circuit trips when the following two conditions are met
simultaneously:
1. BLANK is set to LOW
2. When the voltage at OUTn is less than V(LED) of 0.3 V (typical) (Note: the voltage at each OUTn is sampled
1 µs after being turned on).
The LOD circuit also pulls XERR to GND when tripped. The LOD status of each channel can also be read out
from the TLC5940 status information data (SID) in GS data input cycle.
DELAY BETWEEN OUTPUTS
The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current
driver block of the device (see the functional block diagram). The fixed-delay time is 20 ns (typical), OUT0 has no
delay, OUT1 has 20 ns delay, and OUT2 has 40 ns delay, etc. The maximum delay is 300 ns from OUT0 to
OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large
inrush currents which reduces the bypass capacitors when the outputs turn on.
OUTPUT ENABLE
All OUTn channels of TLC5940 can switched off with one signal. When BLANK is set to high, all OUTn are
disabled, regardless of logic operations of the device. The grayscale counter is also reset. When BLANK is set to
low, all OUTn work under normal conditions.
Table 2. BLANK Signal Truth Table
BLANK
LOW
OUT0 - OUT15
Normal condition
Disabled
HIGH
SETTING MAXIMUM CHANNEL CURRENT
The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between
IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of
1.24 V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of
31.5. The maximum output current can be calculated by Equation 1:
V
(IREF)
I
+
31.5
max
R
(IREF)
(1)
where:
V(IREF) = 1.24 V
R(IREF) = User selected external resistor.
Figure 3 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF
terminal to GND, and IO is the constant output current of OUT0 to OUT15.
12
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
POWER DISSIPATION CALCULATION
The device power dissipation needs to be below the power dissipation rate of the device package to ensure
correct operation. Equation 2 calculates the power dissipation of device:
DC
n
x d
PWM
x N)
P
= V
(
x I
CC
+
( V x I
OUT MAX
x
)
D
CC
63
(2)
where:
VCC: device supply voltage
ICC: device supply current
VOUT: TLC5940 OUTn voltage when driving LED current
IMAX: LED current adjusted by R(IREF) Resistor
DCn: maximum dot correction value for OUTn
N: number of OUTn driving LED at the same time
dPWM: duty cycle defined by BLANK pin or GS PWM value
OPERATING MODES
The TLC5940 has different operating modes depending on the signals VPRG and DCPRG. Table 3 shows the
available operating modes. The TLC5940 GS operating mode (see Figure 11) and shift register values are not
defined after power up. One solution to solve this is to set dot correction data after TLC5940 power up and
switch back to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy
data and latch it while TLC5940 is in GS PWM mode.
Table 3. TLC5940 Operating Modes Truth Table
SIGNAL
INPUT SHIFT REGISTER
MODE
DC VALUE
DCPRG
VCPRG
L
H
L
EEPROM
DC Register
GND
192 bit
96 bit
X
Grayscale PWM Mode
EEPROM
VCC
Dot Correction Data Input Mode
EEPROM Programming Mode
H
L
DC Register
EEPROM
V(PRG)
H
Write dc register value to EEPROM
SETTING DOT CORRECTION
The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently.
This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to
the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The
channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. Equation 3
determines the output current for each output n:
DCn
63
I
+ I
max
OUTn
(3)
where:
Imax = the maximum programmable output current for each output.
DCn = the programmed dot correction value for output n (DCn = 0 to 63).
n = 0 to 15
Dot correction data are entered for all channels at the same time. The complete dot correction data format
consists of 16 x 6-bit words, which forms a 96-bit wide serial data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 7 shows the DC data format.
13
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
LSB
MSB
95
0
5
6
79
90
DC 0.0
DC 0.5
DC 1.0
DC 14.5 DC 15.0
DC 15.5
DC OUT0
DC OUT15
DC OUT2 − DC OUT14
Figure 7. Dot Correction Data Packet Format
To input data into the dot correction register, VPRG must be set to VCC. The internal input shift register is then
set to 96-bit width. After all serial data are clocked in, a rising edge of XLAT is used to latch the data into the dot
correction register. Figure 8 shows the dc data input timing chart.
DC Mode Data
Input Cycle n
DC Mode Data
Input Cycle n+1
V
CC
MODE
DC n
DC n
DC n
DC n
DC n
LSB
DC n+1
DC n+1
SIN
MSB−1
MSB−2
LSB+1
MSB
MSB−1
MSB
t
wh0
SCLK
1
2
3
95
96
1
2
t
wl0
DC n−1
MSB
DC n−1
MSB−1
DC n−1
MSB−2
DC n−1
LSB+1
DC n−1
DC n
DC n
MSB−1
DC n
MSB−2
SOUT
LSB
MSB
t
wh2
t
t
su1
h1
XLAT
Figure 8. Dot Correction Data Input Timing Chart
The TLC5940 has also an EEPROM to store dot correction data. To store data from the dot correction register to
EEPROM, DCPRG is set to high after applying VPRG to VPRG pin. Figure 9 shows the EEPROM programming
timings.
DC EEPROM Write Timing
V
(PRG)
VPRG
0 V or V
CC
t
h5
t
t
prog
su5
DCPRG
Figure 9. EEPROM Programming Timing Chart
14
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
SETTING GRAYSCALE
The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12-bit
per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 4 determines
the brightness level for each output n:
GSn
4095
Brightness in % +
100
(4)
where:
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
n = 0 to 15
Grayscale data for all OUTn
The input shift register enters grayscale data into grayscale register for all channels simultaneously. The
complete grayscale data format consists of 16 x 12 bit words, which forms a 192-bit wide data packet (see
Figure 10). The data packet must be clocked in with the MSB first.
LSB
0
MSB
191
11
12
178
180
GS 0.0
GS 0.11 GS 0.0
GS 14.11 GS15.0
GS 15.11
GS OUT0
GS OUT2 − GS OUT14
GS OUT15
Figure 10. Grayscale Data Packet Format
When VPRG is set to GND, TLC5940 enters the grayscale data input mode. The device switches the input shift
register to 192-bit width. After all data is clocked in, a rising edge of XLAT signal latches the data into the
grayscale register (see Figure 11). The first GS data input cycle after dot correction requires an additional SCLK
pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register is
replaced with status information data (SID) after latching into grayscale register.
DC Mode Data
First GS Mode Data
Following GS Mode Data
Input Cycle
Input Cycle
Input CycleAfter DC Data Input Cycle
MODE
t
su3
t
h3
t
h3
XLAT
t
wh2
GS
GS + 1
GS + 1
LSB
GS
DC
SIN
LSB
MSB
LSB
MSB
t
t
t
h1
su2
h2
t
su1
96
1
192
193
1
192
SCLK
t
pd0
SID n + 1
MSB
SID
MSB−1
SID
MSB
SID
LSB
DC
MSB
DC n
GS
MSB
SOUT
X
X
LSB
Figure 11. Grayscale Data Input Timing Chart
15
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
STATUS INFORMATION OUTPUT
The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG =
GND). After the XLAT signal latches the data into GS register the input shift register data will be replaced with
status information data (SID) of the device (see Figure 11). LOD, TEF and dot correction EEPROM data
(DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at the SOUT pin. The status
information data packet is 192-bit wide. Bit 176 - bit 191 contains the LOD status of each channel. Bit 175
contains the TEF status. If DCPRG is low, bit 72 - bit 167 contains the value of the dot correction EEPROM. If
DCPRG is high, bit 72 - bit 167 contains the data of the dot correction register. The remaining bits are reserved.
The complete status information data packet is shown in Figure 12.
LSB
0
MSB
191
71
X
72
167
168
X
175
176
X
DC 0.0
DC15.5
X
TEF
LOD 0
LOD 15
Reserved
DC Values
TEF
LOD Data
Figure 12. Status Information Data Packet Format
GRAYSCALE PWM OPERATION
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK increases
the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following rising edge
of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of each output
OUTn with the grayscale counter value. All OUTn with grayscale values equal to counter values are switched off.
A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and completes the grayscale
PWM cycle (see Figure 13).
GS PWM
Cycle n
GS PWM
Cycle n+1
BLANK
GSCLK
t
wl1
t
t
su4
t
wh1
t
h4
wh3
4096
1
2
3
1
t
wl1
t
t
t
pd4
pd2
pd4
OUT0
(Current)
n x t
d
t + n x t
pd4 d
t
+ t
d
pd2
OUT1
(Current)
t
+ 14 x t
d
pd2
OUT15
(Current)
t
pd3
XERR
Figure 13. Grayscale PWM Cycle Timing Chart
16
TLC5940
www.ti.com
SLVS515A–DECEMBER 2004–REVISED AUGUST 2005
SERIAL DATA TRANSFER RATE
Figure 14 shows a cascading connection of n TLC5940 devices connected to a controller, building a basic
module of an LED display system. The maximum number of cascading TLC5940 devices depends on the
application system and is in the range of 40 devices. Equation 5 calculates the minimum frequency needed:
f
4096
f
(GSCLK)
(update)
f
+ 193 f
n
(SCLK)
(update)
(5)
where:
f(GSCLK): minimum frequency needed for GSCLK
f(SCLK): minimum frequency needed for SCLK and SIN
f(update): update rate of whole cascading system
n: number cascaded of TLC5940 device
APPLICATION EXAMPLE
V
V
V
V
V
(LED)
CC
(LED)
(LED)
(LED)
100 k
OUT0
OUT15
SOUT
OUT0
OUT15
SOUT
SIN
SIN
XERR
SCLK
SIN
XERR
SCLK
XERR
SCLK
XLAT
V
V
CC
CC
100 nF
100 nF
XLAT
XLAT
TLC5940
IC 0
TLC5940
IC n
GSCLK
DCPRG
BLANK
SOUT
GSCLK
DCPRG
BLANK
VPRG
GSCLK
DCPRG
BLANK
VPRG
IREF
IREF
Controller
W_EEPROM
VPRG_D
7
VPRG_OE
V
V
(22V)
(22V)
50 k
50 k
50 k
50 k
50 k
50 k
VPRG
Figure 14. Cascading Devices
17
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLC5940NT
ACTIVE
ACTIVE
PDIP
NT
28
28
13
TBD
Call TI
Level-NA-NA-NA
TLC5940PWP
HTSSOP
PWP
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLC5940PWPG4
TLC5940PWPR
TLC5940PWPRG4
TLC5940RHB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
QFN
PWP
PWP
PWP
RHB
RHB
RHB
28
28
28
32
32
32
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLC5940RHBR
TLC5940RHBRG4
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2006
PACKAGING INFORMATION
Orderable Device
TLC5940NT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
NT
28
28
28
28
28
28
32
32
32
32
13 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
TLC5940NTG4
TLC5940PWP
PDIP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
QFN
NT
13 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
PWP
PWP
PWP
PWP
RHB
RHB
RHB
RHB
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLC5940PWPG4
TLC5940PWPR
TLC5940PWPRG4
TLC5940RHB
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLC5940RHBG4
TLC5940RHBR
TLC5940RHBRG4
QFN
73 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
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