TLC5944PWP [TI]
16-Channel, 12-Bit PWM LED Driver with 6-Bit Dot Correction and Pre-Charge FET; 16通道， 12位PWM LED驱动器， 6位点校正和预充电FET
| 型号： | TLC5944PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Channel, 12-Bit PWM LED Driver with 6-Bit Dot Correction and Pre-Charge FET |
| 文件： | 总36页 (文件大小：1219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5944
www.ti.com ...................................................................................................................................................................................................... SBVS112–JUNE 2008
16-Channel, 12-Bit PWM LED Driver with
6-Bit Dot Correction and Pre-Charge FET
1
FEATURES
23
•
16 Channels, Constant Current Sink Output
•
Thermal Shutdown (TSD):
•
60-mA Capability (Constant Current Sink)
–
Automatic shutdown at over-temperature
conditions
•
•
•
12-Bit (4096 Steps) Grayscale Control with
PWM
–
Restart under normal temperature
6-Bit (64 Steps) Dot Correction with Sink
Current
•
•
Pre-Thermal Warning (PTW):
High temperature operation alert
Readable Error Information:
–
Internal Pre-Charge FET to Prevent LED
Ghosting Phenomenon on Multiplexed LED
Systems
–
–
–
LED Open Detection (LOD)
Thermal Error Flag (TEF)
Pre-Thermal Warning (PTW)
•
•
•
LED Power-Supply Voltage up to 15 V
VCC = 3.0 V to 5.5 V
•
•
Noise Reduction:
Constant Current Accuracy:
–
4-channel grouped delay to prevent inrush
current
–
–
Channel-to-Channel = ±1%
Device-to-Device = ±3%
Operating Temperature: –40°C to +85°C
•
•
•
•
CMOS Logic Level I/O
30-MHz Data Transfer Rate
APPLICATIONS
•
Monochrome, Multicolor, Full-Color LED
Displays Using Multiplexing System
LED Signboards Using Multiplexing System
33-MHz Grayscale Control Clock
Continuous Base LED Open Detection (LOD):
•
–
Detect LED opening and LED short to GND
during display with auto output off function
VLED
LINEn
VLED
LINE0
¼
¼
¼
OUT0
OUT15
SOUT
XERR
OUT0
SIN
OUT15
SOUT
XERR
DATA
SIN
SCLK
SCLK
SCLK
DCSEL
VLED
VLED
VCC
DCSEL
DCSEL
XLAT
XLAT
XLAT
VUP
VUP
BLANK
Controller
VCC
BLANK
BLANK
GSCLK
IREF
VCC
GSCLK
GSCLK
FLAGS
VCC
GND
VCC
GND
IREF
READ
TLC5944
TLC5944
XERR
READ
RIREF
RIREF
IC1
ICn
5
Typical Application Circuit (Multiple Daisy-Chained TLC5944s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLC5944
SBVS112–JUNE 2008...................................................................................................................................................................................................... www.ti.com
DESCRIPTION
The TLC5944 is a 16-channel, constant current sink driver. Each channel is individually adjustable with 4096
pulse-width modulated (PWM) steps and 64 constant sink current (dot correction) steps. The dot correction (DC)
adjusts for brightness variations between LEDs. Both grayscale (GS) control and DC are accessible via a
common serial interface port. The maximum current value of all 16 channels can be set by a single external
resistor.
The TLC5944 has an internal pre-charge FET to prevent the ghost-lighting phenomenon that occurs on
multiplexed LED systems. The TLC5944 has three error detection circuits for LED open detection (LOD), a
thermal error flag (TEF), and a pre-thermal warning (PTW). The LOD detects a broken or disconnected LED, and
a shorted LED to GND during the display period. The TEF indicates a too-high temperature condition; when the
TEF is set, all output drivers are turned off by the thermal shutdown (TSD) protection. Additionally, when the TEF
is cleared, all output drivers are restarted. The PTW indicates that the IC is operating in a high temperature
condition. The output drivers remain on when PTW is set.
blank
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
TRANSPORT MEDIA,
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
TLC5944PWPR
TLC5944PWP
QUANTITY
Tape and Reel, 2000
Tube, 50
TLC5944
HTSSOP-28 PowerPAD™
TLC5944RHBR
TLC5944RHBT
Tape and Reel, 3000
Tape and Reel, 250
TLC5944
5 mm × 5 mm QFN-32
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
TLC5944
–0.3 to +6.0
–0.3 to +16
6
UNIT
V
VCC
VUP
Supply voltage, VCC
Pre-charge voltage
V
XERR
mA
mA
IOUT
VIN
Output current (dc)
Input voltage range:
OUT0 to OUT15
70
–0.3 to VCC + 0.3
V
SIN, SCLK, XLAT, BLANK, GSCLK, DCSEL, IREF
SOUT, XERR
Output voltage range
–0.3 to VCC + 0.3
V
V
VOUT
OUT0 to OUT15
–0.3 to VUP + 0.3
TJ(max)
TSTG
Operating junction temperature
Storage temperature range
+150
°C
°C
kV
V
–55 to +150
Human body model (HBM)
Charged device model (CDM)
2
ESD rating
500
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
2
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TLC5944
www.ti.com ...................................................................................................................................................................................................... SBVS112–JUNE 2008
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC5944
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
VUP
VO
Supply voltage
3.0
3.0
5.5
V
V
Pre-charge voltage
15
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
OUT0 to OUT15
VUP
V
VIH
VIL
0.7 × VCC
GND
VCC
V
0.3 × VCC
V
IOH
SOUT
SOUT
–1
1
mA
mA
mA
mA
°C
IOL
Low-level output current
XERR
5
IOLC
TA
Constant output sink current
Operating free-air temperature
OUT0 to OUT15
60
+85
–40
–40
Operating junction
temperature
TJ
+125
°C
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (sclk)
Data shift clock frequency
SCLK
30
33
MHz
MHz
Grayscale control clock
frequency
fCLK (gsclk)
GSCLK
TWH0/TWL0
TWH1
SCLK, GSCLK
XLAT, BLANK
SIN–SCLK↑
10
15
5
ns
ns
ns
ns
ns
Pulse duration
Setup time
TSU0
TSU1
BLANK↓–GSCLK↑
XLAT↑–SCLK↑
15
100
TSU2
XLAT↓–SCLK↑
(for SID reading only)
TSU3
20
ns
TSU4
TSU5
TH0
DCSEL–SCLK↑
DCSEL–XLAT↑
SIN–SCLK↑
10
10
3
ns
ns
ns
ns
ns
ns
TH1
XLAT↑–SCLK↑
DCSEL–SCLK↓
DCSEL–XLAT↑
10
10
100
Hold time
TH2
TH3
DISSIPATION RATINGS
OPERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
PACKAGE
HTSSOP-28 with
31.67 mW/°C
3958 mW
2533 mW
2058 mW
PowerPAD soldered(1)
HTSSOP-28 with
16.21 mW/°C
27.86 mW/°C
2026 mW
3482 mW
1296 mW
2228 mW
1053 mW
1811 mW
PowerPAD not soldered(2)
QFN-32(3)
(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2-oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
(2) With PowerPAD not soldered onto copper area on PCB.
(3) The package thermal impedance is calculated in accordance with JESD51-5.
Copyright © 2008, Texas Instruments Incorporated
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TLC5944
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ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5944
PARAMETER
TEST CONDITIONS
IOH = –1 mA at SOUT
MIN
TYP
MAX
VCC
0.4
UNIT
VOH
VOL
High-level output voltage
VCC – 0.4
V
V
V
IOL = 1 mA at SOUT
IOL = 5 mA at XERR
0
0
Low-level output voltage
Input current
0.4
VIN = VCC or GND at SIN, SCLK, XLAT, GSCLK,
BLANK, DCSEL
IIN
–1
1
2
µA
mA
mA
SIN/SCLK/GSCLK/XLAT/DCSEL = low, BLANK = high,
DCn = 3Fh, VOUTn = 1 V, RIREF = 24 kΩ
ICC1
ICC2
1
5
SIN/SCLK/GSCLK/XLAT/DCSEL = low, BLANK = high,
DCn = 3Fh, VOUTn = 1 V, RIREF = 1.6 kΩ
10
SCLK = 30 MHz, GSCLK = 33 MHz, SIN = 15 MHz,
XLAT/DCSEL = low,
BLANK = low during 4095 GSCLK period and high
during 1 GSCLK period,
GSn = FFFh, DCn = 3Fh, VOUTn = 1 V,
RIREF = 1.6 kΩ
ICC3
17
35
60
mA
mA
Supply current (VCC
)
SCLK = 30 MHz, GSCLK = 33 MHz, SIN = 15 MHz,
XLAT/DCSEL = low,
BLANK = low during 4095 GSCLK period and high
during 1 GSCLK period,
GSn = FFFh, DCn = 3Fh, VOUTn = 1 V,
RIREF = 820 Ω
ICC4
30
60
All OUTn = ON, DCn = 3Fh, VOUTn = VOUTfix = 1 V,
RIREF = 1 kΩ (see Figure 9), at OUT0 to OUT15
IO(LC)
Constant output current
Leakage output current
54
66
mA
All OUTn for constant current driver, all output off,
BLANK = high, VOUTn = VOUTfix = 15 V, VUP = 15 V,
RIREF = 820 Ω (see Figure 10), at OUT0 to OUT15
IO(LKG)
0.1
µA
All OUTn for pre-charge FET, all output off,
BLANK = low, VOUTn = VOUTfix = 0 V, VUP = 15 V,
RIREF = 820 Ω (see Figure 10), at OUT0 to OUT15
IO(LKG1)
–10
µA
IO(LKG2)
XERR, no error status, VOUTn = 5.5 V
1
µA
Constant current error
(channel-to-channel)(1)
All OUTn = ON, DCn = 3Fh, VOUTn = 1 V,
RIREF = 820 Ω, at OUT0 to OUT15
ΔIO(LC)
±1
±3
±3
%
Constant current error
(device-to-device)(2)
All OUTn = ON, DCn = 3Fh, VOUTn = 1 V,
RIREF = 820 Ω, at OUT0 to OUT15
ΔIO(LC1)
ΔIO(LC2)
±6
±1
%
All OUTn = ON, DCn = 3Fh, VOUTn = 1 V,
RIREF = 820 Ω, at OUT0 to OUT15
Line regulation(3)
±0.5
%/V
(1) The deviation of each output from the average of OUT0–OUT15 constant current. Deviation is calculated by the formula:
IOUTn
D (%) =
- 1 ´ 100
(IOUT0 + IOUT1 + ... + IOUT14 + IOUT15
)
16
.
(2) The deviation of the OUT0–OUT15 constant current average from the ideal constant current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15
)
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
1.20
IOUT(IDEAL) = 40.5 ´
RIREF
(3) Line regulation is calculated by this equation:
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
D (%/V) =
100
´
(IOUTn at VCC = 3.0 V)
5.5 V - 3 V
4
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www.ti.com ...................................................................................................................................................................................................... SBVS112–JUNE 2008
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 3.0 V to 5.5 V and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5944
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All OUTn = ON, DCn = 3Fh, VOUTn = 1 V to 3 V,
RIREF = 820 Ω, at OUT0 to OUT15
ΔIO(LC3)
Load regulation(4)
±1
±3
%/V
VUP = 3 V, VOUTn = 1 V, BLANK = high,
OUT0 to OUT15
RPCHG
Pre-charge FET on-resistance
1
3
kΩ
T(TEF)
T(HYST)
T(PTW)
T(HYSP)
VLOD
Thermal error flag threshold
Thermal error flag hysteresis
Pre-thermal warning threshold
Pre-thermal warning hysteresis
LED open detection threshold
Reference voltage output
Junction temperature(5)
Junction temperature(5)
Junction temperature(5)
Junction temperature(5)
All OUTn = ON
+150
+5
+162
+10
+175
+20
°C
°C
°C
°C
V
+105
+5
+120
+10
+135
+20
0.2
0.3
0.4
VIREF
RIREF = 820 Ω
1.16
1.20
1.24
V
(4) Load regulation is calculated by the equation:
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
100
D (%/V) =
´
3 V - 1 V
(IOUTn at VOUTn = 1 V)
(5) Not tested. Specified by design.
SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 68 Ω, RIREF = 820 Ω, VLED = 5.0 V, and VUP = 5.0 V. Typical
values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5944
PARAMETER
Rise time
TEST CONDITIONS
SOUT (see Figure 6)
MIN
TYP
MAX UNIT
tR0
tR1
tF0
tF1
16
ns
30
OUTn, DCn = 3Fh (see Figure 5)
SOUT (see Figure 6)
10
16
ns
30
OUTn, DCn = 3Fh (see Figure 5)
10
Fall time
XERR, CL XERR = 100 pF, RL XERR = 1 kΩ,
VXERR = 5 V (see Figure 7)
tF2
50
ns
tD0
tD1
tD2
tD3
tD4
tD5
tD6
tD7
SCLK↑ to SOUT
25
25
ns
ns
ns
ns
ns
ns
ns
ns
DCSEL to SOUT
BLANK↑ to OUT0 sink current off
GSCLK↑ to OUT0/4/8/12
GSCLK↑ to OUT1/5/9/13
GSCLK↑ to OUT2/6/10/14
GSCLK↑ to OUT3/7/11/15
XLAT↑ to IOUT (dot correction)
20
18
42
66
90
40
5
20
35
50
40
73
Propagation delay time
106
140
50
BLANK↑ to pre-charge FET on, RL PRE = 10 kΩ,
constant current driver off (see Figure 8)
tD8
10
35
130
10
ns
ns
tON_ERR Output on-time error(1)
GSn = 001h, GSCLK = 33 MHz
–20
(1) Output on-time error is calculated by the following formula: TON_ERR (ns) = tOUTON – TGSCLK. tOUTON is the actual on-time of the constant
current driver. TGSCLK is the period of GSCLK.
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TLC5944
SBVS112–JUNE 2008...................................................................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM
XERR
VUP
XERR
VCC
33rd GSCLK Signal
Control
16
VUP
VCC
After BLANK Goes Low
LED Open Detection Data Latch
(16 LOD)
16
LSB
MSB
SIN
Grayscale Shift Register
(12 Bits x 16 Channels)
SOUT
0
191
192
SCLK
XLAT
LSB
MSB
Grayscale Data Latch
(12 Bits x 16 Channels)
0
191
LSB
MSB
Dot Correction Shift Register
(6 Bits x 16 Channels)
0
95
192
96
LSB
MSB
Dot Correction Data Latch
(6 Bits x 16 Channels)
DCSEL
0
95
Grayscale
Counter
GSCLK
BLANK
12
12-Bit PWM Timing Control
16
Thermal
Detection
96
Output Switching Delay
(4-Channel Unit)
and
Flag Control
(+162°C/+120°C)
16
Reference
Current
Control
Constant Current Sink Driver With Dot Correction
(16 Channels)
IREF
GND
16
LED Open Detection
(LOD, 16 Channels)
VUP
GND
Pre-Charge FET
(16 Channels)
¼
OUT0
OUT1
OUT14 OUT15
6
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TLC5944
www.ti.com ...................................................................................................................................................................................................... SBVS112–JUNE 2008
DEVICE INFORMATION
PWP PACKAGE
RHB PACKAGE
HTSSOP-28 PowerPAD
5mm × 5mm QFN-32
(TOP VIEW)
(TOP VIEW)
GND
BLANK
XLAT
1
2
3
4
5
6
7
8
9
28 VCC
27 IREF
26 VUP
OUT10
15 OUT9
OUT8
14
VUP
25
GSCLK
25
26
16
SCLK
SIN
24 SOUT
23 XERR
22 OUT15
21 OUT14
20 OUT13
19 OUT12
18 OUT11
17 OUT10
16 OUT9
15 OUT8
IREF
VCC 27
DCSEL
OUT0
OUT1
OUT2
28
29
30
13 NC
12 NC
11 OUT7
NC
NC
Thermal
PAD
Thermal
Pad
GND
OUT6
10
BLANK 31
OUT3 10
OUT4 11
OUT5 12
OUT6 13
OUT7 14
32
OUT5
XLAT
9
NC = No internal connection.
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TLC5944
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TERMINAL FUNCTIONS
TERMINAL
NAME
SIN
PWP
RHB
I/O
DESCRIPTION
Serial data input for grayscale and dot correction.
5
2
I
Serial data shift clock for GS shift register and DC shift register. Schmitt buffer input. The shift
register is selected by the DCSEL pin. Data present on the SIN pin are shifted into the shift
register selected by DCSEL with the rising edge of the SCLK pin. Data in the selected shift
register are shifted to the MSB side by 1-bit synchronizing to the rising edge of SCLK. The MSB
data of the selected register appears on SOUT.
SCLK
4
1
I
Data in the GS and DC shift register are moved to the respective data latch with a low-to-high
transition of this pin.
XLAT
3
6
32
3
I
I
I
Shift register and data latch select. When DCSEL is low, SCLK/XLAT/SOUT are connected to the
GS shift register and data latch. When DCSEL is high, SCLK/XLAT/SOUT are connected to the
DC shift register and data latch. DCSEL should not be changed while SCLK is high.
DCSEL
GSCLK
Reference clock for grayscale PWM control. If BLANK is low, then each rising edge of GSCLK
increments the grayscale counter for PWM control.
25
24
Blank (all constant current outputs off). When BLANK is high, all constant current outputs (OUT0
through OUT15) are forced off, the grayscale counter is reset to '0', and the grayscale PWM
timing controller is initialized. When BLANK is low, all constant current outputs are controlled by
the grayscale PWM timing controller.
BLANK
2
31
I
Constant current value setting. OUT0 through OUT15 sink constant current is set to the desired
value by connecting an external resistor between IREF and GND.
IREF
27
24
23
7
26
23
22
4
I/O
O
Serial data output for GS, DC, and status information data (SID). This output is connected to the
MSB of the shift register selected by DCSEL.
SOUT
XERR
OUT0
Error output. Open-drain output. XERR goes low when LOD or TEF are set. XERR is in high
impedance when error free.
O
Constant current output. Each output can be tied to other outputs to increase the constant
current.
O
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
VCC
8
5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Power-supply voltage
Pre-charge FET power supply
Power ground
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
28
26
1
7
8
9
10
11
14
15
16
17
18
19
20
21
27
25
30
VUP
GND
12, 13,
28, 29
NC
—
—
No internal connection
8
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
SOUT
GND
GND
Figure 1. SIN, SCLK, XLAT, DCSEL, BLANK, GSCLK
Figure 2. SOUT
OUTn
XERR
GND
GND
Figure 3. XERR
Figure 4. OUT0 Through OUT15
TEST CIRCUITS
RL
CL
VCC
GND
VCC
VCC
IREF
OUTn
SOUT
VLED
VCC
(1)
(1)
CL
RIREF
GND
(1) CL includes measurement probe and jig
capacitance.
Figure 5. Rise Time and Fall Time Test Circuit for OUTn
(1) CL includes measurement probe and jig
capacitance.
Figure 6. Rise Time and Fall Time Test Circuit for SOUT
VCC
RL XERR
VUP VCC
VCC
VCC
VUP
XERR
VXERR
OUTn
(1)
CL XERR
GND
RL PRE
CL
GND
Figure 8. Delay Time Test Circuit for Pre-Charge FET
(1) CL XERR includes measurement probe and jig capacitance.
Figure 7. Fall Time Test Circuit for XERR
VCC
OUT0
OUTn
VCC VUP
IREF
OUT0
OUTn
VCC
VUP
VCC
IREF
RIREF
GND OUT15
VOUTn
RIREF
GND OUT15
VOUTn
VOUTFIX
VOUTFIX
Figure 9. Constant Current Test Circuit for OUTn
Figure 10. Leakage Current of Pre-Charge FET Test
Circuit for OUTn
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TIMING DIAGRAMS
TWH0, TWL0, TWH1
:
VCC
INPUT(1) 50%
GND
TWH
TWL
TSU0, TSU1, TSU2, TSU3, TSU4, TSU5, TH0, TH1, TH2, TH3
:
VCC
CLOCK
50%
INPUT(1)
GND
VCC
TSU
TH
DATA/CONTROL
50%
INPUT(1)
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 11. Input Timing
tR0, tR1, tF0, tF1, tF2, tD0, tD1, tD2, tD3, tD4, tD5, tD6
:
VCC
INPUT(1)
50%
GND
tD
VOH or VOUTn
H
90%
50%
10%
OUTPUT
VOL or VOUTn
L
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 12. Output Timing
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tD8 only:
VCC
BLANK(1)
50%
GND
tD8
V
OUTnH
OUTn
50% ´ VUP
V
OUTnL
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 13. Output Timing (Pre-Charge FET)
DC0
0A
GS15 GS15 GS15 GS15 GS15
8B
GS0
3B
GS0
2B
GS0
1B
GS0
0B
GS15 GS15 GS15 GS15 GS15 GS15 GS15 GS15 GS15
11C 10C 9C 8C 7C 6C 5C 4C 3C
SIN
11B
10B
9B
7B
TH0
TSU0
fCLK (SCLK)
TWH0
TSU2
SCLK
1
2
3
4
5
189
190
191
192
1
2
3
4
5
6
7
TH1
TWH1 TSU3
TH2
TWL0
XLAT
TSU4
Keep L Level
TSU5
SID Data are Transferred to GS Shift Register
TSU1
TWH1
DCSEL
BLANK
GSCLK
Shift Register Data are Transferred to GS Data Latch
fCLK (GSCLK)
TD1
Latched Data
for Gray Scale
(Internal)
Previous Data
Latest Data
TD0
GS15 GS15 GS15 GS15 GS15 GS0
3A
GS0
2A
GS0
1A
GS0
0A
GS15
11B
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
10
LOD
9
LOD
8
SOUT
10A
9A
8A
7A
6A
DC
GS15
11A
MSB
tR0/tF0
tD2
(VOUTnH)
OFF
OUT
ON
(VOUTnL)
0/4/8/12
ON
tD3
tF1
OFF
ON
OUT
ON
1/5/9/13
tD4
tR1
OFF
ON
OUT
ON
2/6/10/14
tD5
OFF
ON
OUT
ON
3/7/11/15
tD6
ON
ON
Pre-Charge
MOS
OFF
OFF
OFF
tD8
Figure 14. Grayscale Data Write Timing
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DC0
0A
DC15 DC15 DC15 DC15 DC15
2B
DC0
3B
DC0
2B
DC0
1B
DC0
0B
DC15 DC15 DC15 DC15 DC15 DC15 DC14
5C 4C 3C 2C 1C 0C 5C
SIN
5B
4B
3B
1B
TSU0
TH0
fCLK (SCLK)
TWH0
TSU2
SCLK
93
94
95
96
1
2
3
4
5
1
2
3
4
5
6
7
TH1 TWH1
TH2
TWL0
XLAT
TSU4
Keep H Level
DCSEL
Latched Data
for Dot Correction
(Internal)
Previous Data
Latest Data
tD0
DC15 DC15 DC15 DC15 DC15
4A 3A 2A 1A 0A
DC0
3A
DC0
2A
DC0
1A
DC0
0A
DC15
5B
DC15 DC15 DC15 DC15 DC15 DC14 DC14
0B
SOUT
4B
3B
2B
1B
5B
4B
GS
MSB
DC15
5A
tR0/tF0
(IOUTnH)
(IOUTnL)
(IOUTnH)
OUTn
(IOUTnL
)
(Current)
tD7
Figure 15. Dot Correction Data Write Timing
The SCLK falling edge must be prior to the XLAT rising edge in case SID is read.
GS0
1
GS0
0
GS15 GS15 GS15 GS15 GS15
11A 10A 9A 8A 7A
GS14 GS14 GS14 GS14 GS14 GS14 GS14
9A 8A 7A 6A 5A 4A 3A
GS0
1A
GS0
0A
SIN
TSU2
191 192
1
2
3
4
5
13
14
15
16
17
18
19
20 190 191 192
SCLK
TH1 TWH1 TSU3
XLAT
Keep L Level
DCSEL
SOUT
tD0
GS15
11
LOD
15
LOD
14
LOD
13
LOD
12
LOD
3
LOD
2
LOD
1
LOD
0
GS14
5
GS0
1
GS0 GS15
11A
TEF
TEF1
0
SID are entered in GS shift register at the first rising edge of SCLK with low level
of DCSEL after XLAT. The SID readout consists of the saved LOD result at the
33rd GSCLK rising edge in the previous display period and the saved TEF data
and TEF1 at the rising edge of the first of SCLK after XLAT goes low.
Figure 16. Status Information Data Read Timing
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TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
POWER DISSIPATION RATE
vs FREE-AIR TEMPERATURE
REFERENCE RESISTOR vs OUTPUT CURRENT
100000
10000
1000
4000
3000
2000
1000
0
TLC5944PWP
PowerPAD Soldered
24300
9750
TLC5944RHB
3240
4860
1944
TLC5944PWP
PowerPAD Not Soldered
1389
2430
1080
1620
884
810
1215
972
100
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
60
Free-Air Temperature (°C)
Output Current (mA)
Figure 17.
Figure 18.
OUTPUT CURRENT vs OUTPUT VOLTAGE(1)
OUTPUT CURRENT vs OUTPUT VOLTAGE
70
60
50
40
30
20
10
0
65
64
63
62
61
60
59
58
57
56
55
TA = +25°C
IO = 60 mA
DC = 3Fh
IO = 60 mA
IO = 50 mA
IO = 40 mA
IO = 30 mA
IO = 20 mA
TA = -40°C
TA = +25°C
TA = +85°C
IO = 10 mA
IO = 2 mA
IO = 5 mA
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
Figure 20.
(1) When the output voltage is less than the maximum voltage of the
LED open detection threshold (VLOD = 0.4 VMAX) while the LED is on,
the LED is forced off by the auto output off function.
Figure 19.
ΔIOLC vs AMBIENT TEMPERATURE
ΔIOLC vs OUTPUT CURRENT
4
4
3
IO = 60 mA
TA = +25°C
3
2
2
1
1
0
0
-1
-1
-2
-3
-4
-2
VCC = 3.3 V
VCC = 3.3 V
VCC = 5 V
-3
VCC = 5 V
-4
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
60
Ambient Temperature (°C)
Output Current (mA)
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
DOT CORRECTION LINEARITY
ΔIOLC vs OUTPUT CURRENT
(ABS Value)
4
3
70
60
50
40
30
20
10
0
VCC = 3.3 V
TA = +25°C
TA = +25°C
2
IO = 60 mA
1
0
-1
-2
-3
-4
IO = 30 mA
RIREF Control
Dot Correction Control at RIREF (60 mA)
IO = 2 mA
60
0
10
20
30
40
50
60
0
20
30
40
50
70
10
Output Current (mA)
Dot Correction Data (dec)
Figure 23.
Figure 24.
DOT CORRECTION LINEARITY
(ABS Value)
CONSTANT CURRENT OUTPUT
VOLTAGE WAVEFORM
70
60
50
40
30
20
10
0
IO = 60 mA
CH1-GSCLK
(33 MHz)
CH1 (2 V/div)
CH2 (2 V/div)
CH2-OUT0
(GSData = 0x001h)
CH3-OUT15
(GSData = 0x001h)
IOLCMax = 60 mA
CH3 (2 V/div)
TA = -40°C
TA = +25°C
TA = +85°C
DC = 3Fh, TA = +25°C
RL = 68 W, CL = 15 pF
VLED = VUP = 5 V
Time (25 ns/div)
0
10
20
30
40
50
60
70
Dot Correction Data (dec)
Figure 25.
Figure 26.
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DETAILED DESCRIPTION
Setting for the Maximum Constant Sink Current Value
On the TLC5944, the maximum constant current sink value for each channel, IOLCMax, is determined by an
external resistor, RIREF, and GND pins. The RIREF resistor value is calculated with Equation 1:
VIREF (V)
RIREF (kW) =
´ 40.5
IOLCMax (mA)
(1)
Where:
•
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V)
IOLCMax is the largest current for all outputs. Each output sinks the IOLCMax current when it is turned on and the dot
correction is set to the maximum value of 3Fh (63d). The sink current for each output can be reduced by
lowering the respective output dot correction data.
RIREF must be between 810 Ω (typ) and 24.3 kΩ (typ) in order to keep IOLCMax between 2 mA and 60 mA. The
output may become unstable when IOLCMax is set lower than 2 mA. However, output currents lower than 2 mA
can be achieved by setting IOLCMax to 2 mA or higher, and then using dot correction to lower the output current.
Figure 17 in the Typical Characteristics and Table 1 show the characteristics of the constant sink current versus
the external resistor, RIREF
.
Table 1. Maximum Constant Current Output versus
External Resistor Value
IOLCMax (mA, Typical)
RIREF (Ω)
810
60
55
50
45
40
35
30
25
20
15
10
5
884
972
1080
1215
1389
1620
1944
2430
3240
4860
9720
24300
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Dot Correction (DC) Function
The TLC5944 is able to individually adjust the output current of each channel (OUT0 to OUT15). This function is
called dot correction (DC). The DC function allows users to individually adjust the brightness and color deviations
of LEDs connected to the outputs OUT0 to OUT15. Each respective channel output current can be adjusted in
64 steps from 0% to 100% of the maximum output current, IOLCMax. Dot correction data are entered into the
TLC5944 via the serial interface.
Equation 2 determines the sink current for each output (OUTn):
DCn
IOUTn (mA) = IOLCMax (mA) ´
63d
(2)
Where:
•
•
IOLCMax = the maximum channel current for each channel determined by RIREF
DCn = the programmed dot correction value for OUTn (DCn = 0 to 63d)
When the IC is powered on, the data in the dot correction shift register and data latch are not set to any default
values. Therefore, DC data must be written to the DC latch before turning on the constant current output.
Table 2 summarizes the DC data versus current ratio and set current value.
Table 2. DC Data versus Current Ratio and Set Current Value
SET CURRENT
RATIO TO
MAX CURRENT (%)
OUTPUT CURRENT
(mA, Typical)
AT IOLCMax = 60 mA
OUTPUT CURRENT
(mA, Typical)
AT IOLCMax = 2 mA
DC DATA
(Binary)
DC DATA
(Decimal)
DC DATA
(Hex)
00 0000
00 0001
00 0010
... ...
0
1
00
01
0.0
1.6
0.0
0.4
0.000
0.032
0.064
... ...
2
02
3.2
0.8
... ...
61
62
63
... ...
3D
3E
3F
... ...
96.8
98.4
100.0
... ...
58.1
59.0
60.0
11 1101
11 1110
11 1111
1.937
1.968
2.000
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Grayscale (GS) Function (PWM Operation)
The pulse width modulation (PWM) operation is controlled by a 12-bit grayscale counter that is clocked on each
rising edge of the grayscale reference clock (GSCLK). The counter is reset to zero when BLANK is high. The
counter value is held at zero while BLANK is high, even if the GSCLK input is toggled high and low. After the
falling edge of BLANK, the counter increments with each rising edge of GSCLK. Any constant current sink output
(OUT0 through OUT15) with a nonzero value in the corresponding grayscale latch starts to sink current after the
first rising edge of GSCLK following a high-to-low transition of BLANK. The internal counter keeps track of the
number of GSCLK pulses. Each output channel stays on as long as the internal counter is equal to or less than
the respective output GSCLK. Each channel turns off at the rising edge of GSCLK when the grayscale counter
value is larger than the grayscale latch value.
For example, an output that has a grayscale latch value of '1' turns on at the first rising edge of GSCLK after
BLANK goes low. It turns off at the second rising edge of GSCLK. Figure 27 shows the PWM timing diagram.
BLANK
2048
2049
2050
4094
4095
4096
1
2 3 4
¼
¼
GSCLK
GSCLK counter starts to count GSCLK after BLANK goes low.
No driver turns on when Gray Scale data is zero
(VOUTnH)
OUTn
OFF
ON
(GSDATA = 000h)
(VOUTnH)
(VOUTnL)
T = GSCLK ´ 1
OUTn
OFF
ON
(GSDATA = 001h)
T = GSCLK ´ 2
(VOUTnH)
(VOUTnL)
OUTn
OFF
ON
(GSDATA = 002h)
T = GSCLK ´ 3
(VOUTnH)
OUTn
OFF
(GSDATA = 003h)
ON (VOUTnL)
(VOUTnH)
T = GSCLK ´ 2047
T = GSCLK ´ 2048
T = GSCLK ´ 2049
OUTn
OFF
(GSDATA = 7FFh)
ON (VOUTnL)
(VOUTnH)
OUTn
OFF
(GSDATA = 800h)
ON
(VOUTnL)
(VOUTnH)
(VOUTnL)
OUTn
OFF
ON
(GSDATA = 801h)
(VOUTnH)
T = GSCLK ´ 4093
OUTn
OFF
(GSDATA = FFDh)
ON (VOUTnL)
(VOUTnH)
T = GSCLK ´ 4094
OUTn
OFF
ON (VOUTnL)
(GSDATA = FFEh)
(VOUTnH)
(VOUTnL)
T = GSCLK ´ 4095
OUTn
OFF
ON
(GSDATA = FFFh)
OUTn does not turn on again until BLANK goes high to reset the
grayscale clock and then goes low to enable all OUTn.
OUTn turns on at first rising edge of GSCLK
after BLANK goes low except when Grayscale data are zero.
Figure 27. PWM Operation Timing
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When the IC powers on, the data in the grayscale shift register and latch are not set to any default value.
Therefore, grayscale data must be written to the grayscale latch before turning on the constant current output.
Additionally, BLANK should be held high when the device turns on, to prevent the outputs from turning on before
the proper grayscale and dot correction values can be written. All constant current outputs are forced off when
BLANK is high. Equation 3 determines the on time (tOUTON) for each output (OUTn).
tOUTON (ns) = tGSCLK (ns) ´ GSn
(3)
Where:
•
•
TGSCLK = the period of GSCLK
GSn = the programmed grayscale value for OUTn (GSn = 0 to 4095d)
If GS data change during a display period because XLAT goes high, and latches new GS data, the internal data
latch registers are immediately updated. This action can cause the outputs to turn on or off unexpectedly. For
proper operation, GS data should only be latched into the IC at the end of a display period when BLANK is high.
Table 3 summarizes the GS data versus OUTn on duty and on time.
Table 3. GS Data versus OUTn On Duty and OUTn On Time
OUTn ON-TIME
OUTn ON DUTY RATIO
TO MAXIMUM CODE (%)
(ns, Typical)
AT 33-MHz GSCLK
GS DATA (Binary)
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
—
GS DATA (Decimal)
GS DATA (Hex)
0
000
001
002
003
---
0.00
0.02
0
30
1
2
0.05
61
3
0.07
91
---
---
---
0111 1111 1111
1000 0000 0000
1000 0000 0001
—
2047
2048
2049
---
7FF
800
801
---
49.99
50.01
50.04
---
62030
62061
62091
---
1111 1111 1101
1111 1111 1110
1111 1111 1111
4093
4094
4095
FFD
FFE
FFF
99.95
99.98
100.00
124030
124061
124091
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Grayscale (GS) Shift Register and Data Latch
The grayscale (GS) shift registers and data latches are each 192 bits in length, and set the PWM timing for each
constant current driver. See Table 3 for the ON time duty of each GS data bit. Figure 28 shows the shift register
and latch configuration. Refer to Figure 14 for the timing diagram for writing data into the GS shift register and
latch.
The driver on time is controlled by the data in the GS data latch. GS data present on the SIN pin are clocked into
the GS shift register with each rising edge of the GSCLK pin when DCSEL is low. Data are shifted in MSB first.
Data are latched from the shift register into the GS data latch with a rising edge on the XLAT pin. A DCSEL level
change is allowed when SCLK is low and 100 ns after the rising edge of XLAT.
When the device powers up, the data in the GS shift register and latches are not set to any default value.
Therefore, GS data must be written to the GS latch before turning on the constant current output. Also, BLANK
should be at a high level when powering on the device, because the constant current may be turned on as well.
All constant current output is off when BLANK is at a high level. The status information data (SID) byte is
overwritten on the most significant 18 bits of the grayscale shift register at the first rising edge of GSCLK after
XLAT goes low.
Grayscale Shift Register (12 Bits ´ 16 Channels)
GS Data for OUT15
MSB
GS Data for OUT14
175
¼
GS Data for OUT1
174
GS Data for OUT0
LSB
191
0
180
179
12
11
SIN
SOUT
(DCSEL = L)
OUT15-Bit11
(LOD-OUT15)
OUT15-Bit0 OUT14-Bit11
(LOD-OUT4) (LOD-OUT3)
OUT14-Bit7
OUT14-Bit6
(PTW)
¼
¼
¼
¼
OUT1-Bit0
OUT0-Bit11
OUT0-Bit0
(TEF)
SCLK
(DCSEL = L)
SID Data are Overwritten Between Bits 191 and 174
¼
¼
¼
¼
GS Data for OUT15
MSB
GS Data for OUT14
¼
GS Data for OUT1
GS Data for OUT0
LSB
191
0
180
179
12
11
XLAT
¼
¼
¼
¼
OUT15-Bit11
OUT15-Bit0 OUT14-Bit11
OUT14-Bit7
OUT14-Bit6
OUT1-Bit0
OUT0-Bit11
OUT0-Bit0
(DCSEL = L)
Grayscale Data Latch (12 Bits ´ 16 Channels)
192 Bits
To PWM Timing Control Block
Figure 28. Grayscale Shift Register and Data Latch Configuration
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Dot Correction (DC) Shift Register and Data Latch
The dot correction (DC) shift register and latches are each 96 bits long and are used to individually adjust the
constant current value for each constant current driver. Each channel can be adjusted from 0% to 100% of the
maximum LED current with 6-bit resolution. Table 2 describes the percentage of maximum current for each dot
correction data. Figure 29 shows the shift register and latch configuration for DC data. Figure 15 illustrates the
timing for writing data into the DC shift registers and latches. Each LED channel current is dot-corrected by the
percentage value that corresponds to the data in the respective DC data latch. DC data present on the SIN pin
are clocked, MSB first, into the DC shift register at each rising edge of the SCLK pin when DCSEL is high. Data
are latched from the shift register into the DC data latch with a rising edge on the XLAT pin when DCSEL is high.
A DCSEL level change is allowed when SCLK is low and 100 ns after the rising edge of XLAT.
When the IC is powered on, the data in the DC shift register and data latch are not set to any default value.
Therefore, dot correction data must be written to the DC latch before turning on the constant current output.
Dot Correction Shift Register (6 Bits ´ 16 Channels)
DC Data for OUT15
MSB
DC Data for OUT14
¼
DC Data for OUT1
DC Data for OUT0
LSB
95
90
89
6
5
0
SIN
SOUT
(DCSEL = H)
¼
¼
¼
OUT15-Bit5
OUT15-Bit0 OUT14-Bit5
OUT1-Bit0
OUT0-Bit5
OUT0-Bit0
SCLK
(DCSEL = H)
¼
¼
¼
DC Data for OUT15
MSB
DC Data for OUT14
¼
DC Data for OUT1
DC Data for OUT0
LSB
95
90
89
6
5
0
XLAT
¼
¼
¼
OUT15-Bit5
OUT15-Bit0 OUT14-Bit5
OUT1-Bit0
OUT0-Bit5
OUT0-Bit0
(DCSEL = H)
Dot Correction Data Latch (6 Bits ´ 16 Channels)
96 Bits
To Constant Current Driver Block
Figure 29. Dot Correction Shift Register and Latch Configuration
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Status Information Data (SID)
Status information data (SID) are 18-bit, read-only data. The 16-bit LED open detection (LOD) error, the thermal
error flag (TEF), and the pre-thermal warning (PTW) are shifted out onto the SOUT pin with each rising edge of
the serial data shift clock, SCLK. The 16 LOD bits for each channel and the two TEF bits are written into the 18
most significant bits of the grayscale shift register at the rising edge of the first SCLK after XLAT goes low. As a
result, the previous data in the 18 most significant bits of the grayscale information are lost at the same time. No
data are loaded into the other 174 bits. Figure 30 shows the bit assignments. Figure 16 illustrates the read timing
for the status information data.
Status Information Data (SID) Configuration
LOD Data of OUT15 to OUT0 (16 Bits)
MSB
17
LSB
0
¼
¼
16
2
1
OUT15
OUT14
OUT0
TEF Data
PTW Data
LOD Data
LOD Data
LOD Data
The 16 LOD bits for each channel and the TEF and PTW bits
overwrite the most significant 18 bits of the grayscale shift register
at the rising edge of the first SCLK after XLAT goes low.
¼
GS Data for OUT15
MSB
GS Data for OUT14
¼
GS Data for OUT1
GS Data for OUT0
LSB
191
180
179
175
174
12
11
0
SIN
SOUT
(DCSEL = L)
OUT15-Bit11
(LOD-OUT15)
OUT15-Bit0 OUT14-Bit11
(LOD-OUT4) (LOD-OUT3)
OUT14-Bit7
(TEF)
OUT14-Bit6
(PTW)
¼
¼
¼
¼
OUT1-Bit0 OUT0-Bit11
OUT0-Bit0
SCLK
(DCSEL = L)
Grayscale Shift Register (12 Bits ´ 16 Channels)
Figure 30. Status Information Data Configuration
The LOD data update at the rising edge of the next 33rd GSCLK of the subsequent PWM cycle; the LOD data
are retained until the next 33rd GSCLK. LOD data are only checked for outputs that are turned on during the
rising edge of the 33rd GSCLK pulse. A '1' in an LOD bit indicates an open LED condition for the corresponding
channel. A '0' indicates normal operation. It is possible for LOD data to show a '0' even if the LED is open when
the grayscale data are less than 20h (32d).
The PTW and TEF bits indicate that the IC temperature is high and too high, respectively. The TEF flag also
indicates that the IC has turned off all drivers to avoid damage by overheating the device. A '1' in the TEF bit
means that the IC temperature has exceeded the detect temperature threshold of high side (T(TEF)) and the driver
is forced off. A '0' in the TEF bit indicates the driver has not exceeded the high temperature. The PTW flag
indicates that the IC temperature has exceeded the detect temperature threshold, but does not force the driver
off. A '1' in the PTW bit indicates that the IC temperature has exceeded the pre-thermal warning threshold
(T(PTW)) but does not force the driver off. A '0' in the PTW bit indicates normal operation with low-side
temperature conditions. When the PTW is set, the IC temperature should be reduced by lowering the power
dissipated in the driver to avoid a forced shutdown by the thermal shutdown circuit. This reduction can be
accomplished by lowering the values of the GS or DC data.
When the IC powers on, LOD data do not show correct values. Therefore, LOD data must be read from the 33rd
GSCLK pulse input after BLANK goes low. Table 4 shows a truth table for both LOD and TEF.
Table 4. LOD and TEF Truth Table
CONDITION
SID DATA
LED OPEN DETECTION (LODn)
THERMAL ERROR FLAG (TEF)
PRE-THERMAL WARNING (PTW)
Device temperature is lower than the
high-side detect temperature
Device temperature is lower than the
low-side detect temperature
LED is connected
0
(VOUTn > VLOD
)
(temp ≤ T(TEF) –T(HYST)
)
(temp < T(PTW) – T(HYSP))
Device temperature is higher than the
high-side detect temperature and the
driver is forced off
Device temperature is higher than the
low-side detect temperature
LED is open or shorted to GND
(VOUTn ≤ VLOD
1
)
(temp ≥ T(PTW)
)
(temp > T(TEF)
)
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Continuous Base LED Open Detection
At the rising edge of the 33rd GSCLK after the falling edge of BLANK, the LED open detection (LOD) circuit
checks the voltage of each constant current output (OUT0 through OUT15 = OUTn) that is turned on to detect
open LEDs and short LEDs to GND. The channels corresponding to the LOD bit in the status information data
(SID) register are set to '1' if the voltage of the OUTn pin (VOUTn) is less than the LED open detection threshold
(VLOD = 0.3 VTYP). This status information can be read from the SOUT pin when DCSEL is low. No special test
sequence is required for LED open detection.
The LOD function automatically checks for open LEDs and short LEDs to GND during each grayscale PWM
cycle. The SID information of LOD is latched into the LED open detection data latch and does not change until
the rising edge of the 33rd GSCLK pulse following the next falling edge of BLANK. To eliminate false detection of
open LEDs, the LED driver design must ensure that the TLC5944 output voltage is greater than VLOD when the
outputs are on. The GS data must be 21h (33d) or more to get the LOD result. Figure 31 shows the LED open
detection timing.
BLANK
4094 4096
4093 4095
1
2
3
4
30 31 32 33 34 35
1
2
3
30 31 32 33 34 35
GSCLK
1st GSCLK Period
If LOD error is detected
OFF
OUTn
ON
(Data = FFFh)
VOUTn
If no LOD error is detected
GND
If the OUTn voltage (VOUTn) is less than VLOD (0.3 V, typ) at the rising edge of the 33rd
GSCLK after the falling edge of BLANK, the LOD sets the SID bit corresponding
to the output channel in which LED is open or shorted to GND equal to ‘1’.
OUTn is turned off at the 33rd falling edge of GSCLK if the LOD error flag is set.
SID Value
(Internal)
Old LED open detection data
New LED open detection data
If no LOD error is detected
Hi-Z
Depends on LOD data
Depends on previous
XERR
Low
('L')
If LOD error is detected
LOD data
If XERR goes low because of an LOD error,
XERR is forced high when BLANK goes high.
Figure 31. LED Open Detection (LOD) Timing
22
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TLC5944
www.ti.com ...................................................................................................................................................................................................... SBVS112–JUNE 2008
Thermal Shutdown and Thermal Error Flag
The thermal shutdown (TSD) function turns off all of the constant current outputs on the IC immediately when the
junction temperature (TJ) exceeds the threshold (T(TEF) = +162°C, typ) and sets the thermal error flag (TEF) to '1'.
All outputs are latched off when TEF is set to '1'; TEF and PTW remain off until the next grayscale cycle after TJ
drops below (T(TEF) – T(HYST)). TEF is set to '0' once TJ drops below (T(TEF) – T(HYST)), but the output does not turn
on until the first GSCLK after BLANK goes low while TEF is set to '0'. Figure 32 illustrates the TEF/TSD/XERR
timing sequence.
XLAT
SCLK
BLANK
4094 4096
1
2
3
4
4093 4095
1 3
2
GSCLK
TJ ³ T(TEF)
TJ ³ T(TEF)
TJ ³ T(PTW)
TJ < T(TEF) - T(HYST)
TJ ³ T(PTW)
IC Junction
TJ < T(PTW)
TJ < T(PTW) - T(HYSP)
Temperature (TJ)
‘1’
‘1’
‘1’
‘1’
PTW in SID
‘0’
‘0’
(Internal Data)
TEF in SID
‘0’
‘0’
(Internal Data)
Hi-Z
Hi-Z
‘L’
XERR
OUTn
‘L’
OFF
OFF
OFF
ON
ON
Figure 32. TEF/TSD/XERR Timing
Internal Pre-Charge FET
The internal pre-charge FET can prevent ghosting of multiplexed LED modules. One cause of this phenomenon
is the charging current for parastic capacitance of the constant current output line and driver through the LED.
One of the mechanisms is shown in Figure 33.
In Figure 33, the constant current driver turns LED0-0 on at (1) and off at (2). After LED0-0 is turned off, OUT0
voltage is pulled up to VCHG by LED0-0. This OUT0 node has some parasitic capacitance (such as the constant
current driver output capacitance, and the board layout capacitance shown as C0-2). After LED0-0 turns off,
SWPMOS0 is turned off and SWNMOS0 is turned on for LINE0, then LINE0 is pulled down to GND. Because
there is a parastic capacitance between LINE0 and OUT0, OUT0 voltage is also pulled down to GND. After that,
SWPMOS1 is turned on for next line (LINE1). When SWPMOS1 turns on, OUT0 voltage is pulled up from the
ground voltage to VLED – VF. The charge current (ICHRG) flows to the parasitic capacitor (C0) through LED1-0,
causing the LED to briefly turn on and creating the ghosting effect of LED1-0.
The TLC5944 has an internal pre-charge FET to prevent ghosting. The power supply of the pre-charge FET must
be connected to VLED (LED anode voltage). After a small delay after BLANK goes high, this FET pulls OUTn
(OUT0 to OUT15) up to VLED. The charge current does not flow to C0 through LED1-0 when SWMOS1 is turned
on and the ghosting is eliminated at (3). The pre-charge FET turns off as soon as BLANK goes low to avoid
current flowing from VLED through the pre-charge FET.
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SBVS112–JUNE 2008...................................................................................................................................................................................................... www.ti.com
VLED
Line 0 is VLED level.
(Power-Supply for LED)
ON
OFF
ON
SW
PMOS0
Line 0 is GND level.
SW
SW
PMOS1
LED1-1
LED1-2
NMOS0
OFF
ON
Line 1
Line 1 is VLED level.
SW
¼
PMOS1
OFF
ON
Parasitic Capacitor
C2
SW
Line 1 is GND level.
LED1-0
NMOS1
SW
NMOS1
C0
C1
OFF
High
Low
ON
VLED
ICHRG
BLANK
OUT0
SW
PMOS0
Line 0
OFF
VLED
SW
OUT0
Voltage
VCHG
GND
LED0-0
LED0-1
LED0-2
NMOS0
¼
VLED - VF
OUT0
OUT1
OUT2
50 mA
LED0-0
Ordinal
LED Driver
OUT0
OUT1
ON
OUT2
ON
Current
0 mA
50 mA
0 mA
¼
ON
LED1-0
Current
Constant Current
IOUT = 50 mA
(1) (2)
(3)
Ghost phenomenon is observed
when Line 1 goes up to VLED.
(4)
OUT0 voltage is pulled down to GND side
by the coupling with LED lamp capacitor
between Line 0 and OUT0.
Figure 33. LED Ghost-Lighting Phenomenon Mechanism
VLED
(Power-Supply for LED)
SW
Line 0 is VLED level.
PMOS1
LED1-1
LED1-2
ON
SW
Line 1
PMOS0
OFF
Line 0 is GND level.
¼
ON
SW
Parasitic Capacitor
C2
SW
NMOS1
NMOS0
OFF
LED1-0
Line 1 is VLED level.
ON
SW
C0
C1
VLED
PMOS1
OFF
Line 1 is GND level.
Disappearing ICHRG
ON
SW
PMOS0
SW
NMOS1
OFF
Line 0
High
Low
ON
BLANK
OUT0
SW
NMOS0
LED0-0
LED0-1
LED0-2
OFF
ON
¼
VUP
OUT0
OUT1
OUT2
PCHGON
Signal
OFF
Pre-Charge MOS
VLED
OUT0
VCHG
GND
Voltage
VLED - VF
PCHGON
Timing
Control
BLANK
50 mA
0 mA
LED0-0
Current
OUT0
ON
OUT0
ON
OUT0
ON
¼
50 mA
0 mA
LED1-0
Current
Constant Current
IOUT = 50 mA
TLC5944
(1) (2)
(3)
(4)
LED Driver
Ghost phenomenon not seen
Figure 34. LED Ghost-Lighting Mechanism by Pre-Charge FET
24
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Product Folder Link(s): TLC5944
TLC5944
www.ti.com ...................................................................................................................................................................................................... SBVS112–JUNE 2008
Auto Output Off
The TLC5944 current consumption increases if any output (OUTn) is turned on and no LED is connected, the
LED is an open circuit, or the output is shorted to GND. The TLC5944 has the auto output off function to reduce
consumption current in these cases. This function turns off any OUTn where LED open has been detected to
reduce the current into the VCC pin during error conditions. Figure 35 illustrates the auto output off function.
Therefore, the LED anode voltage must be held over the LED forward voltage (VF) plus the maximum voltage of
the LED open detection threshold (VLOD = 0.4 VMAX) while the LED is on, in any case. Otherwise, the LED is
forced off by the auto output off function.
VCC
Higher
Dissipation
Current
Lower
BLANK
4094 4096
4093 4096
1
2
3
4
30 31 32 33 34 35
1
2
3
30 31 32 33 34 35
GSCLK
OFF
If LOD error is detected
Voltage of
OUTn
ON
VOUTn
If no LOD error is detected
GND
SID Register Value
(Internal)
Old LED open detection data
New LED open detection data
ON (if no LOD error detected)
ON (if no LOD error detected)
ON
ON
ON Signal of OUTn
(Internal)
OFF
OFF
(GS data = FFFh)
OFF (if LOD error is detected)
OFF (if LOD error is detected)
Figure 35. Auto Output Off Function
Noise Reduction
Large surge currents may flow through the IC and the printed circuit board (PCB) on which the device is mounted
if all 16 LED channels turn on simultaneously at the start of each grayscale cycle. This large current surge could
introduce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5944 turns on the
LED channels in a series delay to provide a circuit soft-start feature. The output current sinks are grouped into
four groups of four channels each. The first group is OUT0/4/8/12; the second group is OUT1/5/9/13; the third
group is OUT2/6/10/14; and the fourth group is OUT3/7/11/15. Each group is turned on sequentially with a small
delay between groups; Figure 14 shows this delay. Both turn-on and turn-off are delayed.
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TLC5944
SBVS112–JUNE 2008...................................................................................................................................................................................................... www.ti.com
POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rate of the device package (illustrated in
Figure 18) to ensure correct operation. Equation 4 calculates the power dissipation of the device:
DCn
PD = (VCC ´ ICC) + VOUT ´ IOLCMax ´ N ´
´ dPWM
63d
(4)
Where:
•
•
•
•
•
•
•
VCC = device supply voltage
ICC = device supply current
VOUT = OUTn voltage when driving LED current
IMAX = LED current adjusted by RIREF resistor
DCn = maximum DC value for OUTn
N = number of OUTn driving LED at the same time
dPWM = duty ratio defined by BLANK pin or GS PWM value
26
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Product Folder Link(s): TLC5944
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jun-2008
PACKAGING INFORMATION
Orderable Device
TLC5944PWP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
28
28
32
32
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLC5944PWPR
TLC5944RHBR
TLC5944RHBT
HTSSOP
QFN
PWP
RHB
RHB
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLC5944PWPR
TLC5944RHBR
TLC5944RHBT
HTSSOP PWP
28
32
32
2000
3000
250
330.0
330.0
180.0
16.4
12.4
12.4
7.1
5.3
5.3
10.4
5.3
1.6
1.5
1.5
12.0
8.0
16.0
12.0
12.0
Q1
Q2
Q2
QFN
QFN
RHB
RHB
5.3
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC5944PWPR
TLC5944RHBR
TLC5944RHBT
HTSSOP
QFN
PWP
RHB
RHB
28
32
32
2000
3000
250
346.0
346.0
190.5
346.0
346.0
212.7
33.0
29.0
31.8
QFN
Pack Materials-Page 2
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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