TLC5957 [TI]

具有预充电 FET、LED 开路检测和 Caterpillar 消除功能的 48 通道、16 位 ES-PWM LED 驱动器;
TLC5957
型号: TLC5957
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

具有预充电 FET、LED 开路检测和 Caterpillar 消除功能的 48 通道、16 位 ES-PWM LED 驱动器

驱动 驱动器
文件: 总26页 (文件大小:1284K)
中文:  中文翻译
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TLC5957  
ZHCSCX6 OCTOBER 2014  
TLC5957 具有预充电 FETLED 开路检测和 Caterpillar 消除功能  
48 通道、16 ES-PWM LED 驱动器  
1 特性  
3 说明  
1
48 个恒定灌电流输出通道  
TLC5957 是一款 48 通道恒流灌电流驱动器。 每个通  
道都具有单独可调的 65536 步长脉宽调制 (PWM) 灰  
(GS) 亮度控制。  
具有最大亮度控制 (BC)/最大颜色亮度控制 (CC) 数  
据的灌电流  
1~20mA (VCC = 3.3V)  
1~25mA (VCC = 5V)  
输出通道分为三组,每组均含 512 步长的颜色亮度控  
(CC) 功能,CC 可调节颜色之间的亮度。 全部 48  
通道的最大电流值可通过 8 步长全局亮度控制 (BC) 功  
能设置。 BC 调节 LED 驱动器之间的亮度偏差。 可通  
过一个串行接口端口访问 GSCC BC 数据。  
全局亮度控制 (BC)3 位(8 步长)  
每个颜色组的全局亮度控制 (CC)9 位(512 步  
长),三组  
LED 电源电压高达 10V  
VCC = 3.0V 5.5V  
10mA 时拐点电压 Vout = 0.24V  
恒流精度  
TLC5957 有一个错误标志:LED 开路检测 (LOD),可  
通过串行接口端口读取。 每个恒流输出都有一个预充  
电的场效应晶体管 (FET),能够消除复用 LED 显示时  
的重影并提升显示性能。 此外,TLC5957 具有增强电  
路,可消除 LED 开路所引起的 caterpillar 效应。  
通道之间 = ±1%(典型值),±3%(最大值)  
器件之间 = ±1%(典型值),±2%(最大值)  
数据传输速率:33MHz  
TLC5957 具有扑克数据传输模式;GS 数据长度可配  
置为 9 位至 16 位,具体取决于各子段中的 PWM 位。  
扑克模式可显著提升复用应用的视觉刷新率。  
灰度控制时钟:33MHz  
预充电 FET 可消除重影  
增强电路可消除 Caterpillar 效应  
器件信息(1)  
可选数据传输位和脉宽调制 (PWM) 位(9 位至 16  
位)  
部件号  
TLC5957  
封装  
QFN (56)  
封装尺寸(标称值)  
8.0mm x 8.0mm  
可选传统 PWM ES-PWM  
LED 开路检测 (LOD)  
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。  
热关断 (TSD)  
自动显示重复/自动数据刷新  
延迟开关可防止浪涌电流  
工作温度范围:-40°C +85°C  
2 应用范围  
采用多路复用系统的 LED  
LED 信号板  
4 典型应用电路(多个菊花链 TLC5957)  
V
LED  
OUTR0 - - - - - - - - - - - OUTB15  
OUTR0 - - - - - - - - - - - OUTB15  
DATA  
SCLK  
LAT  
SIN  
SOUT  
SIN  
SOUT  
V
V
CC  
CC  
SCLK  
LAT  
SCLK  
LAT  
Device 1  
VCC  
Device n  
VCC  
GSCLK  
GSCLK  
GSCLK  
IREF  
GND  
GND  
IREF  
Controller  
RIREF  
RIREF  
3
Data Read  
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.  
English Data Sheet: SLVSCQ4  
 
 
 
 
TLC5957  
ZHCSCX6 OCTOBER 2014  
www.ti.com.cn  
目录  
8.2 Test Circuit.............................................................. 10  
Detailed Description ............................................ 11  
9.1 Overview ................................................................. 11  
9.2 Functional Block Diagram ....................................... 12  
9.3 Device Functional Modes........................................ 13  
1
2
3
4
5
6
7
特性.......................................................................... 1  
9
应用范围................................................................... 1  
说明.......................................................................... 1  
典型应用电路(多个菊花链 TLC5957.................. 1  
修订历史记录 ........................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
7.1 Absolute Maximum Ratings ...................................... 4  
7.2 Handling Ratings ...................................................... 4  
7.3 Recommended Operating Conditions....................... 5  
7.4 Thermal Information ................................................. 5  
7.5 Electrical Characteristics........................................... 5  
7.6 Timing Requirements ............................................... 7  
7.7 Typical Characteristics.............................................. 8  
Parameter Measurement Information ................ 10  
10 Application and Implementation........................ 17  
10.1 Application Information.......................................... 17  
11 Power Supply Recommendations ..................... 17  
12 Layout................................................................... 17  
12.1 Layout Guidelines ................................................. 17  
12.2 Layout Example .................................................... 18  
13 器件和文档支持 ..................................................... 18  
13.1 相关链接................................................................ 18  
13.2 ....................................................................... 18  
13.3 静电放电警告......................................................... 18  
13.4 术语表 ................................................................... 18  
14 机械封装和可订购信息 .......................................... 18  
8
8.1 Pin Equivalent Input and Output Schematic  
Diagrams.................................................................. 10  
5 修订历史记录  
日期  
修订版本  
注释  
2014 10 月  
*
最初发布。  
2
Copyright © 2014, Texas Instruments Incorporated  
 
TLC5957  
www.ti.com.cn  
ZHCSCX6 OCTOBER 2014  
6 Pin Configuration and Functions  
RTQ  
56 PINS  
Top View  
56 55 54 53 52 51 50 49 48 47 46 45 44 43  
IREF  
OUTR14  
OUTG14  
OUTB14  
OUTR15  
OUTG15  
OUTB15  
OUTR0  
OUTG0  
OUTB0  
1
SOUT  
42  
41  
40  
39  
38  
2
3
4
5
6
7
OUTB9  
OUTG9  
OUTR9  
OUTB8  
OUTG8  
OUTR8  
OUTB7  
OUTG7  
OUTR7  
OUTB6  
OUTG6  
OUTR6  
GCLK  
37  
36  
Thermal  
PAD  
(Solder side)  
(GND terminal)  
35  
34  
33  
32  
31  
30  
29  
8
9
10  
11  
12  
13  
14  
OUTR1  
OUTG1  
OUTB1  
OUTR2  
15 16 17 18 19 20 21 22 23 24 25 26 27 28  
Pin Functions  
PIN  
NO.  
29  
I/O  
DESCRIPTION  
NAME  
GCLK  
I
Grayscale(GS) pulse width modulation (PWM) reference clock control for OUTXn.  
Each GCLK rising edge increase the GS counter by1 for PWM control.  
Power ground. The thermal pad must be soldered to GND on PCB.  
GND  
IREF  
ThermalPad  
1
Maximum constant-current value setting. The OUTR0 to OUTB15 maximum constant output  
current are set to the desired values by connecting an external resistor between IREF and  
IREFGND. See Equation 1 for more detail. The external resistor should be placed close to the  
device.  
IREFGND 56  
I
Analog ground. Dedicated ground pin for the external IREF resistor. This pin should be connected  
to analog ground trace which is connected to power ground near the common GND point of board.  
LAT  
27  
The LAT falling edge latches the data from the common shift register into the GS data latch or FC  
data latch.  
OUTR0-  
R15  
8, 11, 14, 17, 20,  
23, 30, 33, 36,  
39, 44, 47, 50,  
53, 2, 5  
O
Constant current output for RED LED. Multiple outputs can be tied together to increase the  
constant current capability. Different voltages can be applied to each output. These outputs are  
turned on-off by GCLK signal and the data in GS data memory.  
OUTG0-  
G15  
9, 12, 15, 18, 21,  
24, 31, 34, 37,  
40, 45, 48, 51,  
54, 3, 6  
O
O
Constant current output for GREEN LED. Multiple outputs can be tied together to increase the  
constant current capability. Different voltages can be applied to each output. These outputs are  
turned on-off by GCLK signal and the data in GS data memory.  
OUTB0-  
B15  
10, 13, 16, 19,  
22, 25, 32, 35,  
38, 41, 46, 49,  
52, 55, 4, 7  
Constant current output for BLUE LED. Multiple outputs can be tied together to increase the  
constant current capability. Different voltages can be applied to each output. These outputs are  
turned on-off by GCLK signal and the data in GS data memory.  
Copyright © 2014, Texas Instruments Incorporated  
3
TLC5957  
ZHCSCX6 OCTOBER 2014  
www.ti.com.cn  
Pin Functions (continued)  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
SCLK  
28  
I
Serial data shift clock. Data present on SIN are shifted to the 48-bit common shift register LSB  
with the SCLK rising edge. Data in the shift register are shifted towards the MSB at each SCLK  
rising edge.  
The common shift register MSB appears on SOUT.  
SIN  
26  
I
Serial data input of the 48-bit common shift register.  
When SIN is high level, the LSB is set to '1' for only one SCLK input rising edge. If two SCLK  
rising edges are input while SIN is high, then the 48-bit shift register LSB and LSB+1 are set to '1'.  
When SIN is low, the LSB is set to '0' at the SCLK input rising edge.  
SOUT  
VCC  
42  
43  
O
Serial data output of the 48-bit common shift register. SOUT is connected to the MSB of the  
register.  
Power-supply voltage.  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)  
(1)  
MIN  
–0.3  
30  
MAX  
6.0  
UNIT  
V
(2)  
VCC  
IOUT  
Supply voltage  
VCC  
Output current (dc)  
Input voltage range  
OUTx0 to OUTx15, x = R, G, B  
SIN, SCLK, LAT, GCLK, IREF  
SOUT  
30  
mA  
V
(2)  
VIN  
–0.3  
–0.3  
–0.3  
–40  
VCC + 0.3  
VCC + 0.3  
11  
V
(2)  
VOUT  
Output voltage range  
OUTx0 to OUTx15, x = R, G, B  
V
TJ(MAX)  
Operation junction temperature  
150  
°C  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to device ground terminal.  
7.2 Handling Ratings  
MIN  
–55  
–3  
MAX  
150  
3
UNIT  
Tstg  
Storage temperature range  
Electrostatic discharge  
°C  
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)  
V(ESD)  
kV  
Charged device model (CDM), per JEDEC specification JESD22-C101, all  
pins(2)  
–1  
1
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
4
Copyright © 2014, Texas Instruments Incorporated  
TLC5957  
www.ti.com.cn  
ZHCSCX6 OCTOBER 2014  
7.3 Recommended Operating Conditions  
At TA = –40°C to 85°C, unless otherwise noted.  
MIN  
NOM  
MAX  
UNIT  
DC CHARACTERISTICS VCC = 3 V to 5.5 V  
VCC  
VO  
Supply voltage  
3
5.5  
10  
V
V
Voltage applied to output  
High level input voltage  
Low level input voltage  
High level output current  
Low level output current  
OUTx0 to OUTx15, x = R, G, B  
SIN, SCLK, LAT, GCLK  
VIH  
VIL  
IOH  
IOL  
0.7×VCC  
GND  
VCC  
0.3×VCC  
–2  
V
SIN, SCLK, LAT, GCLK  
V
SOUT  
mA  
mA  
SOUT  
2
OUTx0 to OUTx15, x = R, G, B, 3V VCC 4V  
OUTx0 to OUTx15, x = R, G, B, 4V < VCC 5.5V  
20  
IOLC  
Constant output sink current  
mA  
25  
TA  
TJ  
Operating free air temperature  
Operation junction temperature  
–40  
–40  
85  
°C  
°C  
125  
AC CHARACTERISTICS, VCC = 3 V to 5.5 V  
FCLK(SCLK) Data shift clock frequency  
FCLK(GCLK)  
SCLK  
33  
33  
MHz  
MHz  
Grayscale control clock frequency GCLK  
7.4 Thermal Information  
TLC5957  
THERMAL METRIC(1)  
UNIT  
RTQ (56 PINS)  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
27.4  
13.6  
5.5  
RθJC(top)  
RθJB  
Junction-to-board thermal resistance  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
0.2  
ψJB  
5.5  
RθJC(bot)  
0.8  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
7.5 Electrical Characteristics  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
Output voltage  
TEST CONDITIONS  
MIN  
TYP  
MAX  
VCC  
0.4  
UNIT  
V
VOH  
High  
Low  
IOH = –2mA at SOUT  
IOL = 2mA at SOUT  
LODVTH = 00b  
LODVTH = 01b  
LODVTH = 10b  
LODVTH = 11b  
VCC-0.4  
VOL  
V
VLOD0  
VLOD1  
VLOD2  
VLOD3  
VIREF  
IIN  
0.05  
0.15  
0.3  
0.09  
0.19  
0.15  
0.25  
0.4  
V
V
LED open detection threshold  
0.35  
V
0.45  
1.184  
–1  
0.49  
0.55  
1.234  
1
V
Reference voltage output  
RIREF = 5.97kΩ(1mA target), BC = 0h, CCR/G/B = 80h  
1.209  
V
Input current (SIN, SCLK, LAT, GCLK)  
VIN = VCC or GND  
µA  
SIN/SCLK/LAT/GSCLK = GND, GSn = 0000h, BC = 4h, CCR/G/B = 120h,  
VOUTn = 0.6V, RIREF = OPEN, VCC = 4V  
ICC0  
8
10  
13  
SIN/SCLK/LAT/GSCK = GND, GSn = 0000h, BC = 4h, CCR/G/B = 120h,  
VOUTn = 0.6V, RIREF = 7.5kΩ (Io = 10mA target) , VCC = 4V  
ICC1  
11  
SIN/SCLK/LAT = GND, GCLK = 33MHz, TSU3 = 200ns, XREFRESH = 0,  
GSn = FFFFh, BC = 4h, CCR/G/B = 120h, VOUTn = 0.6V,  
RIREF = 7.5kΩ (Io = 10mA target) , VCC = 4V  
ICC2  
Supply current (VCC  
)
20  
26  
mA  
SIN/SCLK/LAT = GND, GCLK = 33MHz, TSU3 = 200ns, XREFRESH = 0,  
GSn = FFFFh, BC = 7h, CCR/G/B = 1D2h, VOUTn = 0.6V,  
RIREF = 7.5kΩ (Io = 25mA target) , VCC = 4V  
ICC3  
22  
28  
ICC4  
In power save mode  
0.9  
1.5  
Copyright © 2014, Texas Instruments Incorporated  
5
TLC5957  
ZHCSCX6 OCTOBER 2014  
www.ti.com.cn  
Electrical Characteristics (continued)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
All OUTn = on, BC = 0h, CCR/G/B = 08Fh, VOUTn = VOUTfix = 0.6V,  
RIREF = 7.5kΩ(1mA target), TA = +25C, at same color grouped output of  
OUTR0-15, OUTG0-15 and OUTB0-15  
Constant current error  
(OUTx0-15, x = R/G/B)  
Channel-to-  
channel(1)  
Δ IOLC0  
±1%  
±3%  
All OUTn = on, BC = 0h, CCR/G/B = 08Fh, VOUTn = VOUTfix = 0.6V,  
RIREF = 7.5kΩ(1mA target), TA = +25C, at same color grouped output of  
OUTR0-15, OUTG0-15 and OUTB0-15  
Constant current error  
(OUTx0-15, x = R/G/B)  
Device-to-  
device(2)  
ΔIOLC1  
±1%  
±2%  
VCC = 3.0 to 5.5V, All OUTn = on, BC = 0h, CCR/G/B = 08Fh,  
VOUTn = VOUTfix = 0.6V, RIREF = 7.5kΩ(1mA target)  
Δ IOLC2  
Line regulation(3)  
Load regulation(4)  
±1  
±1  
±3  
±3  
%/V  
%/V  
VCC = 4V, All OUTn = on, BC = 0h, CCR/G/B = 08Fh, VOUTn = 0.6 to 3V,  
VOUTfix = 1V, RIREF = 7.5kΩ(1mA target)  
ΔIOLC3  
All OUTn = on, BC = 7h, CCR/G/B - 1CCh, VOUTn = VOUTfix = 0.6V,  
RIREF = 7.5kΩ(25mA target), TA = +25C, at same color grouped output of  
OUTR0-15, OUTG0-15 and OUTB0-15  
Constant current error  
(OUTx0-15, x = R/G/B)  
Channel-to-  
channel(1)  
ΔIOLC4  
±1%  
±1%  
±3%  
All OUTn = on, BC = 7h, CCR/G/B - 1CCh, VOUTn = VOUTfix = 0.6V,  
RIREF = 7.5kΩ(25mA target), TA = +25C, at same color grouped output of  
OUTR0-15, OUTG0-15 and OUTB0-15  
Constant current error  
(OUTx0-15, x = R/G/B)  
Device-to-  
device(2)  
ΔIOLC5  
±3%  
±3  
VCC = 3.0 to 5.5V, All OUTn = on, BC = 7h, CCR/G/B - 1CCh,  
VOUTn = VOUTfix = 0.6V, RIREF = 7.5kΩ(25mA target)  
ΔIOLC6  
Line regulation(3)  
Load regulation(4)  
±1  
±1  
%/V  
%/V  
All OUTn = on, BC = 7h, CCR/G/B - 1CCh, VOUTn = 0.6 to 3V,  
VOUTfix = 0.6V, RIREF = 7.5kΩ(25mA target)  
Δ IOLC7  
±3  
TTSD  
Thermal shutdown threshold  
160  
170  
10  
180  
°C  
°C  
V
THYS  
Thermal shutdown hysterisis  
VISP(in)  
IREF resistor short protection threshold  
0.190  
IREF resistor short-protection release  
threshold  
VISP(out)  
0.330  
V
(1) The deviation of each outputs in same color group (OUTR0~15 or OUTG0~15 or OUTB0~15) from the average of same color group  
constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0~15  
æ
ç
ö
÷
IOUTXn  
- 1 ´ 100  
D(%) = ç  
÷
(IOUTX0 + IOUTX1 + ... + IOUTX14 + IOUTX15)  
ç
÷
è
ø
16  
(2) The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B) :  
(IOUTX0 + IOUTX1 + ... + IOUTX15)  
16  
æ
ç
ç
ö
÷
÷
- (Ideal Output Current)  
D(%) =  
´ 100  
Ideal Output Current  
ç
÷
ç
÷
è
ø
Ideal current is calculated by the following equation:  
V
æ
ö
IREF  
Ideal Output (mA) = Gain ´  
´ CCR(or CCG, CCB) / 511d, VIREF = 1.209V(Typ), refer to Table 1 for the Gain at chosen BC.  
ç
÷
ç
÷
è R  
(W) ø  
IREF  
(3) Line regulation is calculated by the following equation. (X = R or G or B, n = 0~15):  
(IOUTXn at VCC = 5.5V)  
-
(IOUTXn at VCC = 3.0V)  
100  
æ
ö
´
D(% / V) = ç  
÷
(IOUTXn at VCC = 3.0V  
5.5V - 3V  
è
ø
(4) Load regulation is calculated by the following equation. (X = R or G or B, n = 0~15):  
(IOUTXn at VOUTXn  
=
3V)  
-
(IOUTXn at VOUTXn  
=
1V)  
100  
æ
ö
÷
ø
´
D(% / V) = ç  
(IOUTXn at VOUTXn  
=
1V  
3V - 1V  
è
6
Copyright © 2014, Texas Instruments Incorporated  
TLC5957  
www.ti.com.cn  
ZHCSCX6 OCTOBER 2014  
7.6 Timing Requirements  
At TA = –40°C to 85°C, unless otherwise noted.  
MIN  
TYP  
MAX UNIT  
AC CHARACTERISTICS, VCC = 3 V to 5.5 V  
tWH0  
tWL0  
tWH1  
tWL1  
tWH2  
tSU0  
tSU1  
SCLK  
10  
10  
10  
10  
10  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCLK  
Pulse duration  
GCLK  
GCLK  
LAT  
SIN – SCLK  
LAT– SCLK↑  
3
Setup time  
LAT– SCLK, for WRTGS, WRTFC, and TMGST Command  
LAT– SCLK, for LATGS, READFC, and LINERESET Command  
LAT– GCLK, for LATGS AND LINERESET Command  
SCLK– SIN  
20  
80  
30  
2
tSU2  
tSU3  
tH0  
tH1  
SCLK– LAT↑  
2
tH2  
SCLK– LAT↓  
2
tWHO ,tWL0 , tWH1, tWL1, tWH2  
VCC  
INPUT  
50%  
GND  
twl  
twh  
tSU0 , tSU1 , tSU2 , tSU3 , tH0 , t1  
VCC  
CLOCK  
50%  
(1)  
INPUT  
GND  
tSU  
tH  
VCC  
DATA/CONTROL  
50%  
(1)  
INPUT  
GND  
tH2  
LAT  
SCLK  
1
2
3
1022 1023 1024  
1
2
3
4
5
tH2  
LAT Signal needsto include falling edge of SCLK  
Figure 1. Input Timing  
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7.7 Typical Characteristics  
At VCC= 4V and TA = 25°C, unless otherwise noted.  
50  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
1 mA  
5 mA  
10 mA  
20 mA  
1 mA  
5 mA  
10 mA  
20 mA  
25 mA  
45  
40  
35  
30  
25  
20  
15  
10  
5
0
0
0
0.2  
0.4  
0.6  
0.8  
1
0
0.2  
0.4  
0.6  
0.8  
1
Output Voltage (V)  
Output Voltage (V)  
D001  
D003  
VCC = 4 V  
VCC = 5 V  
Figure 2. Output Current vs Output Voltage  
Figure 3. Output Current vs Output Voltage  
3
2
3
2
1 mA  
5 mA  
10 mA  
20 mA  
1 mA  
5 mA  
10 mA  
20 mA  
1
1
0
0
-1  
-2  
-3  
-1  
-2  
-3  
Output Current (Ch)  
Output Current (Ch)  
D005  
D006  
VCC = 4 V  
VCC = 4 V  
Figure 4. Constant-Current Error vs Output Current  
(Channel-to-Channel in RED color group)  
Figure 5. Constant-Current Error vs Output Current  
(Channel-to-Channel in GREEN color group)  
3
2
1.4  
1.3  
1.2  
1.1  
1
1 mA  
5 mA  
10 mA  
20 mA  
1 mA  
25 mA  
1
0
0.9  
0.8  
0.7  
0.6  
0.5  
-1  
-2  
-3  
-40  
-20  
0
20  
40  
60  
80  
100 120 140  
Ambient Temperature (qC)  
D014  
VCC=4V  
VOUTXn=0.6V  
Output Current (Ch)  
D007  
VCC = 4 V  
Figure 7. Maximum Constant-Current Error vs Ambient  
Temperature  
Figure 6. Constant-Current Error vs Output Current  
(Channel-to-Channel in BLUE color group)  
(Channel-to-Channel in RED color group)  
8
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Typical Characteristics (continued)  
At VCC= 4V and TA = 25°C, unless otherwise noted.  
1.6  
1.4  
1.2  
1
1 mA  
25 mA  
1 mA  
25 mA  
1.4  
1.2  
1
0.8  
0.6  
0.4  
0.2  
0.8  
0.6  
0.4  
0.2  
-40  
-20  
0
20  
40  
60  
80  
100 120 140  
-40  
-20  
0
20  
40  
60  
80  
100 120 140  
Ambient Temperature (qC)  
Ambient Temperature (qC)  
D015  
D016  
VCC=4V  
VOUTXn=0.6V  
VCC=4V  
VOUTXn=0.6V  
Figure 8. Maximum Constant-Current Error vs Ambient  
Temperature  
Figure 9. Maximum Constant-Current Error vs Ambient  
Temperature  
(Channel-to-Channel in GREEN color group)  
(Channel-to-Channel in BLUE color group)  
30  
25  
1 mA  
5 mA  
10 mA  
20 mA  
25 mA  
VCC = 3 V  
VCC = 4 V  
VCC = 5.5 V  
24  
23  
22  
21  
20  
19  
18  
17  
25  
20  
15  
10  
5
0
0
1
2
3
4
5
6
7
8
0
5
10  
15  
20  
25  
Step [dec]  
Output Current (mA)  
D012  
D017  
VOUTXn=0.6V,  
GCLK=33MHz,  
GSXn=FFFFh,  
Figure 10. Global Brightness Control Linearity  
Figure 11. Supply Current (ICC) vs Output Current  
21.5  
21.25  
21  
20.75  
20.5  
20.25  
20  
VCC = 3 V  
VCC = 4 V  
VCC = 5.5 V  
19.75  
19.5  
-50  
0
50  
100  
150  
Ambient Temperature (qC)  
D013  
GCLK=33MHz  
GSXn=FFFFh,  
VOUTXn=0.6V,  
Output Current=10mA,  
Figure 12. Supply Current vs Ambient Temperature  
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8 Parameter Measurement Information  
8.1 Pin Equivalent Input and Output Schematic Diagrams  
VCC  
VCC  
OUTPUT  
INPUT  
GND  
GND  
Figure 13. SIN, SCLK  
Figure 14. SOUT  
(1)  
VCC  
OUTXn  
(1) X=R or G or B, n=0~15  
INPUT  
GND  
GND  
Figure 16. OUTR0/G0/B0 through OUTR15/G15/B15  
Figure 15. LAT, GCLK  
8.2 Test Circuit  
RL  
CL  
VCC  
VCC  
VLED  
VCC  
VCC  
(2)  
OUTXn  
SOUT  
(1)  
(1)  
CL  
GND  
GND  
(1) CL includes measurement probe and jig capacitance.  
(1) CL includes measurement probe and jig capacitance.  
(2) X=R or G or B, n=0~15  
Figure 17. Rise Time and Fall Time Test Circuit for OUTXn  
Figure 18. Rise Time and Fall Time Test Circuit for SOUT  
OUTR0  
VCC  
GND  
VCC  
(1)  
OUTXn  
(1)  
VOUTXn  
OUTB15  
VOUTfix  
(1) X=R or G or B, n=0~15  
Figure 19. Constant Current Test Circuit for OUTXn  
10  
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9 Detailed Description  
9.1 Overview  
The TLC5957 is a 48-channel constant-current sink driver for multiplexing an LED display system. Each channel  
has an individually-adjustable, 65536-step, pulse width modulation (PWM) grayscale control.  
The TLC5957 supports output current range from 1 mA to 25 mA. Channel-to-channel accuracy is 3% max,  
device-to-device accuracy is 2% max in all current ranges. Also, the TLC5957 implements Low Grayscale  
Enhancement (LGSE) technology to improve the display quality at low grayscale conditions. These features  
improve the performance of the TLC5957-multiplexed display system.  
The output channels are grouped in three groups, each group has 16 channels for one color. Each group has a  
512-step color brightness control (CC) function. The maximum current value of all 48 channels can be set by 8-  
step global brightness control (BC) function. GS, CC and BC data are accessible via a serial interface port.  
The TLC5957 has one error flag: LED open detection (LOD), that can be read via a serial interface port. The  
TLC5957 also has an enhanced circuit to solve the caterpillar issue caused by open LEDs. Thermal shutdown  
(TSD) and Iref resistor short protection (ISP) assure TLC5957 of a higher system reliability.  
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9.2 Functional Block Diagram  
VCC  
SIN  
48 bit LOD  
DATA LATCH  
LSB  
MSB  
SOUT  
48 bit Common Shift Register  
SEL_TD0  
SCLKB  
767  
SCLK  
0
47  
48  
ADR<767:0>  
Grayscale (GS)  
48  
LSB  
48  
48  
48  
48  
48  
48  
48  
MSB  
XRST  
data latch  
Address Counter  
GS first data GS first data  
latch for latch for  
OUTR/G/B0 OUTR/G/B1  
GS first data GS first data  
latch for latch for  
OUTR/G/B14 OUTR/G/B15  
ADR Select  
0
47 48  
95 97  
671 672 719 720 767  
LAT16B LOAD  
48  
48  
48  
48  
LAT768B  
LSB  
MSB  
767  
LAT  
Command  
Decoder  
LATFC  
2nd 48ch GS Data Latch for Display  
0
48  
48  
48  
48  
XRST  
SCLK  
XRFESH  
Poker Trans  
Mode  
ES-PWN Timing Control  
SCLKB  
LAT  
2
1
PWM Mode  
48  
48  
LSB  
MSB  
XRST  
Power On  
Reset  
Function Control (FC) Data latch  
48  
0
47  
48  
42  
Internal circuit  
1st line and  
Quick pulse  
5
3
PRIODEND  
XRFRESH  
GCLK EDGE  
2
LSB  
MSB  
16 bit  
GS Counter  
3rd GS Data Latch for ES-PWN Synch  
GSCLK  
34  
0
48  
47  
GDLY  
32  
12-grouped Switching Delay  
48  
BC & CC & PCHG  
2
48CH Constant driver with 3 bit BC, 27 bit CC  
and Pre-charge FET  
Reference  
Current Control  
IREF  
GND  
48  
Detection  
Voltage  
LOD Detection  
OUTR  
OUTG0  
OUTB0  
OUTR15  
OUTR1  
OUTG15  
OUTB15  
12  
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9.3 Device Functional Modes  
After power on, all OUTXn of TLC5957 are turned off. All the internal counters and function control registers are  
initialized. Below is a brief summary of the sequence to operate TLC5957, just give users a general idea how this  
part works. After that, the function block related to each step will be detailed in following sections.  
1. According to required LED current, choose BC and CC code, select the current programming resistor RIREF  
.
2. Send WRTFC command to set FC register value if the default value need be changed.  
3. Write GS data of line 1 into GS data latch. Using LATGS command for the last group of 48bit GS data  
loading, the GS data written just now will be displayed.  
4. Input GCLK continuously, 2N GCLK (N>=9) as a segment. Between the interval of two segments, supply  
voltage should be switched from one line to next line accordingly.  
5. During the same period of step4, GS data for next line should be written into GS data latch. Using LATGS  
command for the last group of 48bit GS data loading.  
6. Repeat step 4-5 until it comes to the last line for a multiplexing panel. Input 2N GCLK (N>=9) as a segment,  
at the same time, GS data for 1st line should be written into GS data latch. Using LINERESET command for  
the last group of 48bit GS data loading.  
Repeat step 4 through 6.  
9.3.1 Brightness Control (BC) Function  
The TLC5957 is able to adjust the output current of all constant-current outputs simultaneously. This function is  
called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit word, thus all  
output currents can be adjusted in 8 steps from 12.9% to 100% (See Table 2) for a given current programming  
resistor(RIREF  
)
BC data can be set via the serial interface. When the BC data change, the output current also changes  
immediately. When the device is powered on, the BC data in the function control (FC) register is set to 4h as the  
initial value.  
9.3.2 Color Control (CC) Function  
The TLC5957 is able to adjust the output current of each of the three color groups OUTR0-OUTR15, OUTG0-  
OUTG15, and OUTB0-OUTB15 separately. This function is called color brightness control (CC). For each color,  
it has 9-bit data latch CCR, CCG, or CCB in FC register. Thus, all color group output currents can be adjusted in  
512 steps from 0% to 100% of the maximum output current, IOLCMax. (See next section for more details about  
IOLCMax). The CC data are entered via the serial interface. When the CC data change, the output current also  
changes immediately.  
When the IC is powered on, the CC data are set to ‘100h’.  
Equation 1 calculates the actual output current.  
Iout(mA) = IOLCMax(mA) × ( CCR/511d or CCB/511d)  
(1)  
Where:  
IOLCMax = the maximum channel current for each channel, determined by BC data and RIREF (See Equation 2)  
CCR/G/B = the color brightness control value for each color group in the FC1 register (000h to 1FFh)  
Table 1 shows the CC data versus the constant-current against IOLCMax  
.
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Device Functional Modes (continued)  
Table 1. CC Data vs Current Ratio and Set Current Value  
RATIO OF OUTPUT  
CURRENT  
CC DATA (CCR or CCG or CCB)  
OUTPUT CURRENT (mA, RIREF = 7.41 k)  
TO IolcMax(%, typical)  
BC = 7h  
(IolcMax =25mA)  
BC = 0h  
(IolcMax=3.2mA)  
BINARY  
DECIMAL  
HEX  
0 0000 0000  
0 0000 0001  
0 0000 0010  
0
1
00  
01  
02  
0
0
0
0.2  
0.4  
0.05  
0.10  
0.006  
0.013  
2
1 0000 0000  
(Default)  
256  
(Default)  
100  
(Default)  
50.1  
12.52  
1.621  
1 1111 1101  
1 1111 1110  
1 1111 1111  
509  
510  
511  
1FD  
1FE  
1FF  
99.6  
99.8  
100.0  
24.90  
24.95  
25  
3.222  
3.229  
3.235  
9.3.3 Select RIREF For a Given BC  
The maximum output current per channel, IOLCMax is determined by resistor RIREF placed between the IREF and  
IREFGND pins, and the BC code in FC register. The voltage on IREF is typically 1.209V. RIREF can be calculated  
by Equation 2.  
Riref(k) = Viref(V) / IOLCMax(mA) × Gain  
(2)  
Where:  
VIREF = the internal reference voltage on IREF (1.209V, typical)  
IOLCMax is the largest current for each output at CCR/G/B=1FFh.  
Gain = the current gain at a selected BC code (See Table 2 )  
Table 2. Current Gain Versus BC Code  
BC DATA  
RATIO OF  
GAIN / GAIN_MAX (AT MAX BC)  
GAIN  
BINARY  
HEX  
000 (recommend)  
0 (recommend)  
20.0  
39.5  
12.9%  
25.6%  
37.9%  
52.4%  
64.7%  
73.3%  
91.7%  
100%  
001  
010  
1
2
58.6  
011  
3
80.9  
100 (default)  
101  
4 (default)  
100.0  
113.3  
141.6  
154.5  
5
6
7
110  
111  
NOTE: Recommend to use smaller BC code for better performance. For noise immunity purposes, suggest RIREF < 60 kΩ.  
9.3.4 Choosing BC/CC For a Different Application  
BC is mainly used for global brightness adjustment between day and night. Suggested BC is 4h, which is in the  
middle of the range; thus, one can change brightness up and down flexibly.  
CC can be used to fine tune the brightness in 512 steps, this is suitable for white balance adjustment between  
RGB color groups. To get a pure white color, the general requirement for the luminous intensity ratio of R, G, B  
LED is 3:6:1. Depending on LED’s characteristics (Electro-Optical conversion efficiency), the current ratio of R,  
G, B LED will be much different from this ratio. Usually, the Red LED will need the largest current. One can  
choose 511d(the max value) CC code for the color group which needs the largest current at first, then choose  
proper CC code for the other two color groups according to the current ratio requirement of the LED used.  
14  
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9.3.4.1 Example 1: Red LED Current is 20mA, Green LED Needs 12mA, Blue LED needs 8mA  
1. Red LED needs the largest current, so choose 511d for CCR  
2. 511 x 12mA / 20mA = 306.6, thus choose 307d for CCG. With same method, choose 204d for CCB.  
3. According to the required red LED current, choose 7h for BC.  
4. According to Equation 2, RIREF = 1.2V/20mA x 154.5 = 9.27 kΩ  
In this example, we choose 7h for BC, instead of using the default 4h. This is because the Red LED current is  
20mA, approaching the upper limit of current range. To prevent the constant output current from exceeding the  
upper limit in case a larger BC code is input accidently, we choose the maximum BC code here.  
9.3.4.2 Example 2: Red LED Current is 5mA, Green LED Needs 2mA, Blue LED Needs 1mA.  
1. Red LED needs the largest current, so choose 511d for CCR.  
2. 511 x 2mA / 5mA = 204.4, thus choose 204d for CCG. With same method, choose 102d for CCB.  
3. According to the required blue LED current, choose 0h for BC.  
4. According to Equation 2, RIREF = 1.2V / 5mA x 20 = 4.8 kΩ  
In this example, we choose 0h for BC, instead of using the default 4h. This is because the Blue LED current is  
1mA, which is approaching the lower limit of current range. To prevent the constant output current from  
exceeding the lower limit in case a lower BC code is input accidently, we choose the min BC code here.  
In general, if LED current is in the middle of range(i.e, 10mA), one can just use the default 4h as BC code.  
9.3.5 LED Open Detection (LOD)  
LOD function detects a fault caused by an open circuit in any LED string, or a short from OUTXn to ground with  
low impedance, by comparing the OUTXn voltage to the LOD detection threshold voltage level set by LODVLT in  
the FC register. If the OUTXn voltage is lower than the programmed voltage, the corresponding output LOD bit  
will be set to '1' to indicate a opened LED. Otherwise, the output of that LOD bit is '0'. LOD data output by the  
detect circuit are valid only during the ‘on’ period of that OUTXn output channel. LOD data are always ‘0’ for  
outputs that are turned off.  
9.3.6 Poker Mode  
Poker Mode provides the TLC5957 with a flexible PWM bit, from 9 bit to 16 bit. Therefore, data length can be  
reduced. In high multiplexing applications, Poker Mode can significantly increase visual refresh rate.  
9.3.7 Internal Circuit for Caterpillar Removal  
Caterpillar effect is a very common issue on LED panels. It is usually caused by an LED lamp open, LED lamp  
leakage or LED lamp short. The TLC5957 implements an internal circuit that can eliminate the caterpillar issue  
caused by LED open. This function can be enabled and disabled by LINERESET command. If the function is  
enabled, the IC automatically detects the broken LED lamp, and the lamp will not light until IC reset.  
9.3.8 Internal Pre-charge FET for Ghost Removal  
The internal pre-charge FET can prevent ghosting of multiplexed LED modules. One cause of this phenomenon  
is the charging current for parasitic capacitance of the OUTXn through the LED when the supply voltage switches  
from one common line to the next common line.  
To prevent this unwanted charging current, the TLC5957 uses an internal FET to pull OUTXn up to VCC-1.4V  
during the common line switching period. Thus, no charging current flows through LED and the ghosting is  
eliminated.  
9.3.9 Thermal Shutdown (TSD)  
The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)  
exceeds 170°C (typ). It resumes normal operation when TJ falls below 160°C (typ).  
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9.3.10 IREF Resistor Short Protection (ISP)  
The Iref resistor short protection (ISP) function prevents unwanted large currents from flowing though the  
constant-current output when the Iref resistor is shorted accidently. The TLC5957 turns off all output channels  
when the Iref pin voltage is lower than 0.19V (typ). When the Iref pin voltage goes higher than 0.33V (typ), the  
TLC5957 resumes normal operation.  
9.3.11 Noise Reduction  
Large surge currents may flow through the IC and the board on which the device is mounted if all 48 LED  
channels turn on simultaneously at the 1st GCLK rising edge. This large surge current could induce detrimental  
noise and electromagnetic interference (EMI) into other circuits.  
The TLC5957 separate the LED channels into 12 groups. Each group turns on sequentially with some delay  
between one group and the next group. By this means, a soft-start feature is provided and the inrush current is  
minimized.  
16  
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10 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
10.1 Application Information  
Send request via email for Application Note: Build High Density, High Refresh Rate, Multiplexing LED Panel with  
TLC5957  
11 Power Supply Recommendations  
The VCC power supply voltage should be decoupled by placing a 0.1 µF ceramic capacitor close to VCC pin and  
GND plane. Depending on panel size, several electrolytic capacitors must be placed on board equally distributed  
to get a well regulated LED supply voltage (VLED). VLED voltage ripple should be less than 5% of its nominal  
value. Furthermore, the VLED should be set to the voltage calculated by equation:  
VLED > Vf + 0.4V (10mA constant current example)  
(3)  
Where: Vf = maximum forward voltage of LED  
12 Layout  
12.1 Layout Guidelines  
1. Place the decoupling capacitor near the VCC pin and GND plane.  
2. Place the current programming resistor Riref close to IREF pin and IREFGND pin.  
3. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is  
approximately 1.2A  
4. Routing between the LED cathode side and the device OUTXn pin should be as short and straight as  
possible to reduce wire inductance.  
5. The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally,  
there will be large current flow through this pad when all channels turn on. Furthermore, this pad should be  
connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via  
pattern is shown as below. For more information about suggested thermal via pattern and via size, see "  
PowerPAD Thermally Enhanced Package", SLMA002G.  
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12.2 Layout Example  
13 器件和文档支持  
13.1 相关链接  
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件,并且可以快速访问样片或购买  
链接。  
3. 相关链接  
部件  
产品文件夹  
请单击此处  
样片与购买  
请单击此处  
技术文档  
工具与软件  
请单击此处  
支持与社区  
请单击此处  
TLC5957  
请单击此处  
13.2 商标  
PowerPAD is a trademark of Texas Instruments.  
13.3 静电放电警告  
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损  
伤。  
13.4 术语表  
SLYZ022 TI 术语表。  
这份术语表列出并解释术语、首字母缩略词和定义。  
14 机械封装和可订购信息  
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对  
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。  
18  
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重要声明  
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IMPORTANT NOTICE  
邮寄地址: 上海市浦东新区世纪大道1568 号,中建大厦32 楼邮政编码: 200122  
Copyright © 2014, 德州仪器半导体技术(上海)有限公司  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TLC5957RTQR  
TLC5957RTQT  
ACTIVE  
ACTIVE  
QFN  
QFN  
RTQ  
RTQ  
56  
56  
2000 RoHS & Green  
250 RoHS & Green  
NIPDAU  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
-40 to 85  
-40 to 85  
5957AB  
5957AB  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
GENERIC PACKAGE VIEW  
RTQ 56  
8 x 8, 0.5 mm pitch  
VQFN - 1 mm max height  
PLASTIC QUAD FLATPACK - NO LEAD  
Images above are just a representation of the package family, actual package may vary.  
Refer to the product data sheet for package details.  
4224653/A  
www.ti.com  
PACKAGE OUTLINE  
VQFN - 1 mm max height  
RTQ0056G  
PLASTIC QUAD FLATPACK-NO LEAD  
8.15  
7.85  
A
B
8.15  
7.85  
PIN 1 INDEX AREA  
C
1 MAX  
SEATING PLANE  
0.08 C  
0.05  
0.00  
5.6±0.1  
(0.2) TYP  
15  
28  
52X 0.5  
14  
29  
57  
4X  
6.5  
SYMM  
5.6±0.1  
1
42  
0.30  
0.18  
56X  
PIN 1 ID  
(OPTIONAL)  
43  
56  
0.1  
C A B  
C
0.5  
0.3  
56X  
SYMM  
0.05  
4225369 / A 10/2019  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
VQFN - 1 mm max height  
RTQ0056G  
PLASTIC QUAD FLATPACK-NO LEAD  
(0.78)  
(5.6)  
8X (1.33)  
6X (1.22)  
43  
56X (0.6)  
56  
1
42  
56X (0.24)  
6X (1.22)  
8X (1.33)  
52X (0.5)  
SYMM  
(7.8)  
(5.6)  
57  
(R0.05)  
TYP  
14  
29  
(Ø0.2) TYP  
VIA  
15  
28  
SYMM  
LAND PATTERN EXAMPLE  
SCALE: 10X  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
SOLDER MASK  
OPENING  
METAL  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
NON SOLDER MASK  
SOLDER MASK  
DEFINED  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4225369 / A 10/2019  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments  
literature number SLUA271 (www.ti.com/lit/slua271).  
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their  
locations shown on this view. it is recommended thar vias under paste be filled, plugged or tented.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
VQFN - 1 mm max height  
RTQ0056G  
PLASTIC QUAD FLATPACK-NO LEAD  
(7.8)  
8X (0.665)  
8X (1.33)  
43  
56X (0.6)  
56  
56X (0.24)  
1
42  
57  
8X (1.33)  
52X (0.5)  
SYMM  
(7.8)  
8X (0.665)  
(R0.05) TYP  
16X  
(
1.13)  
14  
29  
METAL  
TYP  
15  
28  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
EXPOSED PAD  
66% PRINTED COVERAGE BY AREA  
SCALE: 10X  
4225369 / A 10/2019  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations..  
www.ti.com  
重要声明和免责声明  
TI 均以原样提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资  
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示  
担保。  
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、  
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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE  
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122  
Copyright © 2020 德州仪器半导体技术(上海)有限公司  

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