TLC6C5912PWR [TI]
TLC6C5912 12 位移位寄存器 LED 驱动器 | PW | 20 | -40 to 105;
| 型号： | TLC6C5912PWR |
| 厂家： | 
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| 描述： | TLC6C5912 12 位移位寄存器 LED 驱动器 | PW | 20 | -40 to 105 驱动 驱动器 移位寄存器 |
| 文件： | 总22页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC6C5912
ZHCSF22 –MAY 2016
TLC6C5912 12 通道移位寄存器 LED 驱动器
1 特性
此器件包含一个 12 位串入、并出移位寄存器，此寄存
器为一个 12 位 D 类存储寄存器提供数据。移位和存
储寄存器之间的数据传输分别在移位寄存器时钟
(SRCK) 和寄存器时钟 (RCK) 的上升边沿上发生。当
移位寄存器清零(CLR) 为高电平时，存储寄存器将数据
传输到输出缓冲器 。一个CLR上的低电平将器件中的
所有寄存器清零。将输出使能 (G) 保持为高电平将把
输出缓冲器中的所有数据保存为低电平，并且所有漏极
输出关闭。保持G为低电平将使得来自存储寄存器中的
数据对于输出缓冲器不可见。
1
•
•
•
3V 至 5.5V 宽 VCC 范围
40V 最大额定输出
12 路功率双扩散金属氧化物半导体 (DMOS) 晶体
管输出：
50mA 持续电流 (VCC = 5V) 或者
200mA 脉宽调制 (PWM) 电流（单脉冲持续时间短
于 1ms 且平均电流低于 50mAr）
•
•
•
•
•
热关断保护
针对多级的增强型级联
所有寄存器由单一输入清零
低功耗
该器件包含一个 12 位串入并出移位寄存器。该寄存器
为一个 12 位 D 类存储寄存器提供数据。移位寄存器
和存储寄存器各自具备独立时钟。
缓慢开关时间（t 和 tf），非常有助于减少电磁干扰
(EMI)
•
20 引脚薄型小外形尺寸 (TSSOP)-PW 封装
输出为低侧、漏极开路 DMOS 晶体管输出：额定输出
为 40V 及 50mA 持续灌电流或者 200mA PWM 电流
（VCC = 5V 时，单脉冲持续时间短于 1ms 且平均电流
低于 50mA）。该器件内置热关断保护，在人体模型和
200V 机器模型测试中可提供高达 2000V 的静电放电
(ESD) 保护。
2 应用
•
•
•
•
电器显示面板
电梯显示面板
PLC 功能指示器
七段显示器
TLC6C5912 的额定工作环境温度范围为 -40°C 至
105°C。
3 说明
TLC6C5912 是一款单片、中等电压、低电流功率 12
位移位寄存器，专为负载功率要求相对适中的系统（例
如 LED）而设计。
器件信息(1)
器件型号
TLC6C5912
封装
封装尺寸（标称值）
薄型小外形尺寸封
装 (TSSOP) (20)
6.50mm x 4.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用电路原理图
Power Supply
4/3
4/3
MCU Serial
Interface
12-Bit Shift Register
LED Driver
12-Bit Shift Register
LED Driver
Typical Cascade Topology
Power Supply
I/Os
12-Bit Shift-
Register
4/3
MCU Serial
Interface
3 ´ 12 LED Matrix
LED Driver
Typical Scan Topology
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS180
TLC6C5912
ZHCSF22 –MAY 2016
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
9
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 器件和文档支持 ..................................................... 16
12.1 社区资源................................................................ 16
12.2 商标....................................................................... 16
12.3 静电放电警告......................................................... 16
12.4 Glossary................................................................ 16
13 机械、封装和可订购信息....................................... 16
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注
2016 年 5 月
*
最初发布版本
2
Copyright © 2016, Texas Instruments Incorporated
TLC6C5912
www.ti.com.cn
ZHCSF22 –MAY 2016
5 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
V
1
2
3
4
20
19
18
17
GND
CC
SER_IN
SRCK
DRAIN0
DRAIN1
DRAIN11
DRAIN10
DRAIN2
DRAIN3
DRAIN4
DRAIN5
CLR
5
16
15
14
13
12
11
DRAIN9
DRAIN8
DRAIN7
DRAIN6
RCK
6
7
8
9
SER_OUT
10
G
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Shift register clear, active-low: CLR is the signal used to clear all the registers. The
storage register transfers data to the output buffer when shift register clear CLR is high.
Driving CLR is low clears all the registers in the device.
CLR
9
I
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
DRAIN8
DRAIN9
DRAIN10
DRAIN11
3
4
O
O
O
O
O
O
O
O
O
O
O
O
5
6
7
8
Open-drain output: DRAIN0 to DRAIN11 are the LED current-sink channels. These pins
connect to the LED cathodes, and they can survive up to 40-V LED supply voltage.
13
14
15
16
17
18
Output enable, active-low: G is the LED channel enable and disable input pin. Having G
low enables all drain channels according to the output-latch register content. When high, all
channels are off.
G
10
20
I
Power ground: GND is the ground reference pin for the device. This pin must connect to the
ground plane on the PCB.
GND
—
Register clock: RCK is the storage register clock. The data in each shift register stage
RCK
12
2
I
I
transfers to the storage register at the rising edge of RCK. Data in the storage register
appears at the output whenever the output enable G̅ input signal is high.
Serial-data input: SER IN is the serial data input. Data on SER IN loads into the internal
register on each rising edge of SRCK.
SER IN
Copyright © 2016, Texas Instruments Incorporated
3
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ZHCSF22 –MAY 2016
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Serial-data output: SER OUT is the serial data output of the 12−bit serial shift register. The
purpose of this pin is to cascade several devices on the serial bus. By connecting the SER
OUT pin to the SER IN input of the next device on the serial bus to cascade, the data
transfers to the next device on the falling edge of SRCK. This can improve the cascade
application reliability, as it can avoid the issue that the second device receives SRCK and
data input at the same rising edge of SRCK.
SER OUT
11
O
Shift-register clock: SRCK is the serial clock input. On each rising SRCK edge, data
transfers from SER IN to the internal serial shift registers.
SRCK
VCC
19
1
I
I
Power supply: VCC is the power supply pin voltage for the device. TI recommends adding a
0.1 μF ceramic capacitor close to the pin.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
8
UNIT
VCC Logic supply voltage
V
V
V
VI
Logic input-voltage
–0.3
8
VDS Power DMOS drain-to-source voltage
Continuous total dissipation
42
See Thermal Information
Operating ambient temperature (Top)
105
°C
°C
°C
TJ
Operating junction temperature
–40
–55
125
165
Tstg Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX UNIT
VCC
VIH
VIL
tsu
th
Supply voltage
3
5.5
V
V
High-level input voltage
2.4
Low-level input voltage
0.7
V
Setup time, SER IN high before SRCK↑
Hold time, SER IN high after SRCK↑
Pulse duration
15
15
ns
ns
ns
°C
tw
40
TA
Operating ambient temperature
–40
105
4
Copyright © 2016, Texas Instruments Incorporated
TLC6C5912
www.ti.com.cn
ZHCSF22 –MAY 2016
6.4 Thermal Information
TLC6C5912
PW (TSSOP)
20 PINS
114.8
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.1
61.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.7
ψJB
60.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
DRAIN0 to DRAIN11,
drain-to-source voltage
40
V
V
IOH = –20 μA
IOH = –4 mA
4.9
4.5
4.99
4.69
High-level output voltage,
SER OUT
VOH
VCC = 5 V
VCC = 5 V
IOH = 20 μA
0.001 0.01
Low-level output voltage,
SER OUT
VOL
V
IOH = 4 mA
0.25
0.2
0.4
IIH
IIL
High-level input current
Low-level input current
VCC = 5 V, VI = VCC
VCC = 5 V, VI = 0
μA
μA
–0.2
0.1
All outputs off
All outputs on
1
VCC = 5 V,
No clock signal
ICC
Logic supply current
μA
µA
μA
130 170
Logic supply current at
frequency
ICC(FRQ)
IDSX
fSRCK = 5 MHz, CL = 30 pF, all outputs on
300
VDS = 30 V, VCC = 5 V
0.1
Off-state drain current
VDS = 30 V, TC = 125°C, VCC = 5 V
0.15
7.4
0.3
8.6
9.6
ID = 20 mA, VCC = 5 V, TA = 25°C, single channel ON
ID = 20 mA, VCC = 5 V, TA = 25°C, all channels ON
ID = 20 mA, VCC = 3.3 V, TA = 25°C, single channel ON
ID = 20 mA, VCC = 3.3 V, TA = 25°C, all channels ON
ID = 20 mA, VCC = 5 V, TA = 105°C, single channel ON
ID = 20 mA, VCC = 5 V, TA = 105°C, all channels ON
ID = 20 mA, VCC = 3.3 V, TA = 105°C, single channel ON
ID = 20 mA, VCC = 3.3 V, TA = 105°C, all channels ON
6
6.7
8.9
7.9
9.3 11.2
10.6 12.3
11.2 12.9
13 14.5
13.7 16.4
15.6 18.2
175 200
15
8.7
Static drain-source on-state
resistance
rDS(on)
Ω
9.1
10.3
11.6
12.8
150
TSHUTDOWN Thermal shutdown trip point
tHYS Hysteresis
°C
°C
6.6 Switching Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Propagation delay time, low-to-high-level output from G
TEST CONDITIONS
MIN TYP MAX UNIT
tPLH
tPHL
tr
210
75
ns
ns
ns
ns
ns
ns
ns
Propagation delay time, high-to-low-level output from G
Rise time, drain output
CL = 30 pF, ID = 48 mA
250
200
35
tf
Fall time, drain output
tpd
tor
Propagation delay time, SRCK↓ to SEROUT
SEROUT rise time (10% to 90%)
SEROUT fall time (90% to 10%)
CL = 30 pF, ID = 48 mA
CL = 30 pF
20
tof
CL = 30 pF
20
Copyright © 2016, Texas Instruments Incorporated
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Switching Characteristics (continued)
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
f(SRCK)
Serial clock frequency
CL = 30 pF, ID = 20 mA
10
MHz
ns
tSRCK_WH
tSRCK_WL
SRCK pulse duration, high
SRCK pulse duration, low
30
30
ns
12
11
8
3
10
9
7
6
5
4
2
1
SRCK
SER IN
1
0
CLR
SER OUT
Figure 1. SER IN to SER OUT Waveform
Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift
register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 2). As a result, it takes seven
and a half periods of SRCK for data to transfer from SER IN to SER OUT.
5 V
50%
tPHL
G
Output
SRCK
50%
0 V
tPLH
10 V
90%
tr
90%
10%
10%
tf
0.5 V
5 V
50%
0 V
5 V
0 V
tsu
th
SER IN
50%
50%
tw
Switching Times, Input Setup and Hold Waveforms
50%
SRCK
50%
tpd
tpd
SER OUT
50%
50%
SER OUT Propagation Delay Waveform
Figure 2. Switching Times and Voltage Waveforms
Figure 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the
test circuit shown in Figure 12.
6
Copyright © 2016, Texas Instruments Incorporated
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6.7 Typical Characteristics
Conditions for Figure 5 and Figure 6: Single channel on; conditions for Figure 7, Figure 8, and Figure 9: All channels on.
700
600
500
400
300
200
100
0
500
450
400
350
300
250
200
150
100
50
All Channels Off
All Channels On
TA = -40èC
TA = 25èC
TA = 105èC
0
0.1
1
10
100
3
3.5
4
4.5
5
5.5
6
Frequency (MHz)
Supply Voltage (V)
D001
D002
VCC = 5 V
VCC
Figure 3. Supply Current vs Frequency
Figure 4. Supply Current vs Supply Voltage
16
14
12
10
8
14
12
10
8
6
6
4
4
TA = -40èC
TA = 25èC
TA = 105èC
TA = -40èC
TA = 25èC
TA = 105èC
2
2
0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Drain Current (mA)
Drain Current (mA)
D003
D004
VCC = 5 V
VCC = 3.3 V
Figure 5. Drain-to-Source On-State Resistance
vs Drain Current (Single Channel On)
Figure 6. Drain-to-Source On-State Resistance
vs Drain Current (Single Channel On)
16
14
12
10
8
20
18
16
14
12
10
8
6
6
4
4
TA = -40èC
TA = 25èC
TA = 105èC
TA = -40èC
TA = 25èC
TA = 105èC
2
2
0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Drain Current (mA)
Drain Current (mA)
D005
D006
VCC = 5 V
VCC = 3.3 V
Figure 7. Drain-to-Source On-State Resistance
vs Drain Current (All Channels On)
Figure 8. Drain-to-Source On-State Resistance
vs Drain Current (All Channels On)
Copyright © 2016, Texas Instruments Incorporated
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Typical Characteristics (continued)
Conditions for Figure 5 and Figure 6: Single channel on; conditions for Figure 7, Figure 8, and Figure 9: All channels on.
18
16
14
12
10
8
400
350
300
250
200
150
100
50
tPLH
tPHL
tr
tf
6
4
TA = 105èC
TA = 25èC
TA = -40èC
2
0
0
2.5
3
3.5
4
4.5
5
5.5
6
6.5
-40
-20
0
20
40
60
80
100
120
Supply Voltage (V)
Ambient Temperature (èC)
D007
D008
I(ds) = 20 mA
Figure 9. Drain-to-Source On-State Resistance
vs Supply Voltage
Figure 10. Switching Time vs Ambient Temperature
8
Copyright © 2016, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSF22 –MAY 2016
7 Parameter Measurement Information
5 V
10 V
VCC
CLR
ID
RL = 200 W
SRCK
Output
MCU
DRAIN
SER IN
CL = 30 pF
RCK
(see Note A)
G
GND
Copyright © 2016, Texas Instruments Incorporated
A. CL includes probe and jig capacitance.
Figure 11. Resistive-Load Test Circuit
12
11
8
7
6
5
4
3
10
9
2
1
SRCK
SER IN
G
RCK
0
1
0
0
CLR
DRAIN0
DRAIN1
DRAIN10
DRAIN11
0
0
Figure 12. Voltage Waveforms
Figure 11 and Figure 12 show the resistive-load test circuit and voltage waveforms. One can see from Figure 12
that with G held low and CLR held high, the status of each drain changes on the rising edge of the register clock,
indicating the transfer of data to the output buffers at that time.
Copyright © 2016, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
The TLC6C5912 device is a monolithic, medium-voltage, low current 12-bit shift register designed to drive
relatively moderate load power such LEDs. The device contains a 12-bit serial-in, parallel-out shift register that
feeds a 12-bit D-type storage register. Thermal shutdown protection is also built-into the device.
8.2 Functional Block Diagram
G
RCK
DRAIN0
CLR
D
D
SRCK
C1
C1
CLR
D
CLR
D
DRAIN1
DRAIN2
DRAIN3
DRAIN4
SER IN
C1
C1
CLR
D
CLR
D
C1
C1
CLR
D
CLR
D
C1
C1
CLR
CLR
D
D
C1
CLR
C1
CLR
DRAIN10
DRAIN11
GND
D
D
C1
C1
CLR
D
CLR
D
C1
C1
CLR
CLR
D
C1
CLR
SER OUT
8.3 Feature Description
8.3.1 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C
(typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds
the thermal trip threshold. Once the junction temperature decreases to less than 160°C (typical), the device
begins to operate again.
10
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ZHCSF22 –MAY 2016
Feature Description (continued)
8.3.2 Serial-In Interface
The TLC6C598 device contains an 8-bit serial-in, parallel out shift register that feeds an 8-bit D-type storage
register. Data transfer through both the shift and storage registers on the rising edge of the shift register clock
(SRCK) and the register clock (RCK), respectively. The storage transfers data to the output buffer when shift
register clear (CLR) is high.
8.3.3 Clear Register
A logic low on CLR clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.4 Cascade Through SER OUT
By connecting the SER OUT pin to the SER IN input of the next device on the serial bus to cascade, the data
transfers to the next device on the falling edge of SRCK. This can improve the cascade application reliability, as
it can avoid that the second device receives SRCK and data input at the same rising edge of SRCK.
8.3.5 Output Control
Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding
G low makes data from the storage register transparent to the output buffers. When data in the output buffers is
low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable of sink-
current. This pin also be used for global PWM dimming.
8.4 Device Functional Modes
8.4.1 Operation With VCC < 3 V
This device works normally during 3 V ≤ VCC ≤ 5.5 V, when operation voltage is lower than 3 V. The behavior of
device cannot be ensured, including communication interface and current capability.
8.4.2 Operation With 5.5 V ≤ VCC ≤ 8 V
The device works normally during this voltage range, but reliability issues may occurs while the device works for
a long time in this voltage range.
Copyright © 2016, Texas Instruments Incorporated
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLC6C5912 device is a serial-in, parallel-out, power logic 8-bit shift register with low-side open-drain DMOS
output rating of 40 V and 50-mA continuous sink-current capabilities when VCC= 5 V. The device is designed to
drive resistive loads and is particularly well-suited as an interface between a microcontroller and LEDs or lamps.
The device also provides up to 2000 V of ESD protection when tested using the human body model and 200 V
when using the machine model.
9.2 Typical Application
Figure 13 shows a typical cascade application circuit with two TLC6C5912 chips configured to cascade topology.
The MCU generates all the input signals.
12
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Typical Application (continued)
Battery 9 V–40 V
3 V–5.5 V
DRAIN0 DRAIN1
VCC
DRAIN10 DRAIN11
SER IN
SRCK
GND
MCU
G
SER OUT
CLR
RCK
DRAIN0 DRAIN1
VCC
DRAIN10 DRAIN11
SER IN
SRCK
GND
G
SER OUT
CLR
RCK
Figure 13. Typical Application Circuit
9.2.1 Design Requirements
Table 1 lists the parameters for this design example.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
9 V to 40 V
3.3 V
Vbattery
VCC _ 1
I(D0), I(D1), I(D2), I(D3) , I(D4), I(D5), I(D6), I(D7), I(D8), I(D9), I(D10), I(D11)
VCC _ 2
30 mA
5 V
I(D12), I(D13), I(D14), I(D15) , I(D16), I(D17), I(D18), I(D19), I(D20), I(D21), I(D122),
I(D23)
50 mA
Copyright © 2016, Texas Instruments Incorporated
13
TLC6C5912
ZHCSF22 –MAY 2016
www.ti.com.cn
9.2.2 Detailed Design Procedure
To begin the design process, the designer must decide on a few parameters:
•
•
•
Vsupply: LED supply voltage
VDx: LED forward voltage
I: LED current
After determining the parameters, calculate the resistor in series with LED using Equation 1.
Rx = (Vsupply – VDx) / I
(1)
9.2.3 Application Curve
Figure 14. TLC6C5912 Application Waveform
14
Copyright © 2016, Texas Instruments Incorporated
TLC6C5912
www.ti.com.cn
ZHCSF22 –MAY 2016
10 Power Supply Recommendations
The TLC6C5912 device is designed to operate from an input voltage supply range from 3 V to 5.5 V. This input
supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
11 Layout
11.1 Layout Guidelines
There are no special layout requirement for the digital signal pins. The only requirement is placing the ceramic
bypass capacitors near the corresponding pin.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-flow
path from the package to the ambient is through the cooper on the PCB. Maximizing the copper coverage is
extremely important when the design does not include heat sinks attached to the PCB on the other side of the
package.
•
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
•
All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Example
Vcc
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
1
2
3
4
5
6
7
20
19
18
17
16
15
14
GND
SRCK
DRAIN11
DRAIN10
DRAIN9
DRAIN8
DRAIN7
DRAIN5
CLR
G
8
9
13
12
11
DRAIN6
RCK
10
SER OUT
Figure 15. Layout Recommendation
版权 © 2016, Texas Instruments Incorporated
15
TLC6C5912
ZHCSF22 –MAY 2016
www.ti.com.cn
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件提供的最新数据。本数据随时可能发生变更并且
不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。
16
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC6C5912PWR
ACTIVE
TSSOP
PW
20
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
6C5912I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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