TLC7524E [TI]
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS; 8位乘法数字 - 模拟转换器型号: | TLC7524E |
厂家: | TEXAS INSTRUMENTS |
描述: | 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS |
文件: | 总10页 (文件大小:148K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
D, N, OR PW PACKAGE
Easily Interfaced to Microprocessors
(TOP VIEW)
On-Chip Data Latches
Monotonic Over the Entire A/D Conversion
Range
R
REF
OUT1
OUT2
GND
DB7
DB6
DB5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB
V
Segmented High-Order Bits Ensure
Low-Glitch Output
DD
WR
CS
DB0
DB1
DB2
Interchangeable With Analog Devices
AD7524, PMI PM-7524, and Micro Power
Systems MP7524
DB4
DB3
Fast Control Signaling for Digital
Signal-Processor Applications Including
Interface With TMS320
FN PACKAGE
(TOP VIEW)
CMOS Technology
KEY PERFORMANCE SPECIFICATIONS
Resolution
8 Bits
3
2
1
20 19
18
Linearity error
Power dissipation at V
Setting time
1/2 LSB Max
5 mW Max
100 ns Max
80 ns Max
V
GND
4
5
6
7
8
DD
= 5 V
DD
WR
NC
DB7
NC
17
16
15
14
Propagation delay time
CS
DB6
DB5
description
DB0
9 10 11 12 13
The TLC7524C, TLC7524E, and TLC7524I are
CMOS, 8-bit, digital-to-analog converters (DACs)
designed for easy interface to most popular
microprocessors.
NC–No internal connection
The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random
access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
which produce the highest glitch impulse. The devices provide accuracy to 1/2 LSB without the need for thin-film
resistors or laser trimming, while dissipating less than 5 mW typically.
Featuring operation from a 5-V to 15-V single supply, these devices interface easily to most microprocessor
buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation
from –25°C to 85°C. The TLC7524E is characterized for operation from – 40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
PLASTIC DIP
(D)
T
A
PLASTIC CHIP CARRIER
(FN)
PLASTIC DIP
(N)
SMALL OUTLINE
(PW)
0°C to 70°C
–25°C to 85°C
–40°C to 85°C
TLC7524CD
TLC7524ID
TLC7524ED
TLC7524CFN
TLC7524IFN
TLC7524EFN
TLC7524CN
TLC7524IN
TLC7524EN
TLC7524CPW
TLC7524IPW
–
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
functional block diagram
R
R
R
15
REF
2R
2R
2R
2R
2R
16
R
FB
S-1
S-2
S-3
S-8
R
1
2
OUT1
OUT2
12
13
CS
3
Data Latches
GND
WR
4
5
6
11
DB0
(LSB)
DB7
(MSB)
DB6
DB5
Data Inputs
Terminal numbers shown are for the D or N package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V
DD
Digital input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
I
DD
Reference voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
ref
Peak digital input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA
Operating free-air temperature range, T : TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I
A
TLC7524I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Case temperature for 10 seconds, T : FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
recommended operating conditions
V
= 5 V
V
= 15 V
DD
MIN NOM
DD
MIN NOM
UNIT
MAX
MAX
Supply voltage, V
4.75
2.4
5
5.25
14.5
13.5
15
15.5
V
V
DD
Reference voltage, V
ref
High-level input voltage, V
±10
±10
V
IH
Low-level input voltage, V
0.8
1.5
V
IL
CS setup time, t
40
0
40
0
ns
ns
ns
ns
ns
su(CS)
CS hold time, t
h(CS)
Data bus input setup time, t
25
25
su(D)
Data bus input hold time, t
10
10
h(D)
Pulse duration, WR low, t
w(WR)
40
40
TLC7524C
TLC7524I
TLC7524E
0
70
85
85
0
70
85
85
Operating free-air temperature, T
–25
–40
–25
–40
°C
A
electrical characteristics over recommended operating free-air temperature range, V = ±10 V,
ref
OUT1 and OUT2 at GND (unless otherwise noted)
V
= 5 V
V
= 15 V
DD
DD
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
I
I
High-level input current
Low-level input current
V = V
DD
10
10
µA
µA
IH
I
V = 0
I
–10
–10
IL
DB0–DB7 at 0 V,
= ±10 V
WR, CS at 0 V,
WR, CS at 0 V,
OUT1
OUT2
±400
±400
±200
±200
V
Output leakage
current
ref
DB0–DB7 at V
I
nA
Ikg
DD
,
DD
V
ref
= ±10 V
Quiescent DB0–DB7 at V min or V max
1
2
mA
IH
IL
I
Supply current
Standby
DB0–DB7 at 0 V or V
500
500
µA
DD
Supply voltage sensitivity,
∆gain/∆V
k
∆V
DD
= ±10%
0.01
0.16
5
0.005
0.04 %FSR/%
SVS
DD
Input capacitance,
DB0–DB7, WR, CS
C
V = 0
I
5
pF
pF
kΩ
i
OUT1
OUT2
OUT1
OUT2
30
120
120
30
30
120
120
30
DB0–DB7 at 0 V,
WR, CS at 0 V
WR, CS at 0 V
C
Output capacitance
o
DB0–DB7 at V
,
DD
Reference input impedance
(REF to GND)
5
20
5
20
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
operating characteristics over recommended operating free-air temperature range, V = ±10 V,
ref
OUT1 and OUT2 at GND (unless otherwise noted)
V
= 5 V
DD
TYP
V = 15 V
DD
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX MIN
±0.5
MAX
±0.5
±2.5
100
Linearity error
LSB
LSB
ns
Gain error
See Note 1
±2.5
Settling time (to 1/2 LSB)
See Note 2
100
Propagation delay from digital input
to 90% of final analog output current
See Note 2
80
80
ns
Vref = ±10 V (100-kHz sinewave)
WR and CS at 0 V, DB0–DB7 at 0 V
Feedthrough at OUT1 or OUT2
Temperature coefficient of gain
0.5
0.5
%FSR
T
A
= 25°C to MAX
±0.004
±0.001
%FSR/°C
NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = V – 1 LSB.
ref
2. OUT1 load = 100 Ω, C
= 13 pF, WR at 0 V, CS at 0 V, DB0 – DB7 at 0 V to V
or V
to 0 V.
ext
DD
DD
operating sequence
t
su(CS)
t
h(CS)
CS
t
w(WR)
WR
t
su(D)
t
h(D)
DB0–DB7
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
PRINCIPLES OF OPERATION
voltage-mode operation
It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the
reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage
mode.
R
R
R
REF (Analog Output Voltage)
2R
2R
2R
2R
0
1
R
OUT1 (Fixed Input Voltage)
OUT2
Figure 1. Voltage Mode Operation
The relationship between the fixed-input voltage and the analog-output voltage is given by the following
equation:
V
= V (D/256)
I
O
where
V
V
= analog output voltage
= fixed input voltage
O
I
D = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:
PARAMETER
Linearity error at REF
TEST CONDITIONS
MIN
MAX
UNIT
V
DD
= 5 V, OUT1 = 2.5 V, OUT2 at GND,
T
A
= 25°C
1
LSB
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
PRINCIPLES OF OPERATION
The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference
current, I , is switched to OUT2. The current source I/256 represents the constant current flowing through the
ref
termination resistor of the R-2R ladder, while the current source I
represents leakage currents to the
Ikg
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch
capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, I would
ref
be switched to OUT1.
The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control
signals. When CS and WR are both low, analog output on these devices responds to the data activity on the
DB0–DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the
analog output. When either the CS signal or WR signal goes high, the data on the DB0–DB7 inputs are latched
until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state
of the WR signal.
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrantor4-quadrantmultiplicationareshowninFigure3andFigure4. Table1andTable2summarizeinput
coding for unipolar and bipolar operation respectively.
R
FB
R
OUT1
30 pF
I
Ikg
I
ref
REF
OUT2
120 pF
I/256
I
Ikg
Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
PRINCIPLES OF OPERATION
V
ref
V
DD
R
= 2 kΩ
A
R
B
(see Note A)
C (see Note B)
R
FB
DB0–DB7
OUT1
OUT2
–
+
Output
CS
WR
GND
NOTES: A.
R and R used only if gain adjustment is required.
A B
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent
ringing or oscillation.
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
V
DD
V
ref
20 kΩ
R
= 2 kΩ
A
R
B
20 kΩ
(see Note A)
–
+
C (see Note B)
R
FB
OUT1
Output
DB0–DB7
10 kΩ
–
+
CS
5 kΩ
OUT2
WR
GND
NOTES: A.
R and R used only if gain adjustment is required.
A B
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
DIGITAL INPUT
(see Note 3)
(see Note 4)
ANALOG OUTPUT
ANALOG OUTPUT
MSB LSB
MSB LSB
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
–V (255/256)
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V
(127/128)
(1/128)
ref
ref
–V (129/256)
ref
–V (128/256) = –V /2
ref ref
–V (127/256)
ref
–V (1/256)
ref
V
ref
0
–V (1/128)
ref
–V (127/128)
ref
–V
ref
0
NOTE 3: LSB = 1/256 (V
)
ref
NOTE 4: LSB = 1/128 (V
)
ref
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
PRINCIPLES OF OPERATION
microprocessor interfaces
D0–D7
Z–80A
Data Bus
DB0–DB7
TLC7524
WR
OUT1
OUT2
WR
CS
Decode
Logic
IORQ
Address Bus
A0–A15
Figure 5. TLC7524 – Z-80A Interface
Data Bus
D0–D7
6800
DB0–DB7
TLC7524
φ2
OUT1
OUT2
WR
CS
Decode
Logic
VMA
Address Bus
A0–A15
Figure 6. TLC7524 – 6800 Interface
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7524C, TLC7524E, TLC7524I
8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998
PRINCIPLES OF OPERATION
microprocessor interfaces (continued)
A8–A15
8051
Address Bus
Decode
Logic
8-Bit
Latch
CS
TLC7524
OUT1
OUT2
WR
ALE
WR
DB0–DB7
Adress/Data Bus
AD0–AD7
Figure 7. TLC7524 – 8051 Interface
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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