TLC7528EDW [TI]
DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS; 双8位乘法数字 - 模拟转换器
| 型号： | TLC7528EDW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS |
| 文件： | 总17页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
DW OR N PACKAGE
(TOP VIEW)
Easily Interfaced to Microprocessors
On-Chip Data Latches
Monotonic Over the Entire A/D Conversion
Range
AGND
OUTA
RFBA
REFA
DGND
OUTB
RFBB
REFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Interchangeable With Analog Devices
AD7528 and PMI PM-7528
V
DD
WR
CS
DB0 (LSB)
DB1
DB2
Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320
DACA/DACB
(MSB) DB7
DB6
Voltage-Mode Operation
CMOS Technology
DB5
DB4
DB3
KEY PERFORMANCE SPECIFICATIONS
FN PACKAGE
(TOP VIEW)
Resolution
Linearity Error
Power Dissipation at V
Settling Time at V
8 bits
1/2 LSB
20 mW
100 ns
80 ns
= 5 V
DD
= 5 V
DD
Propagation Delay Time at V
= 5 V
DD
3
2 1 20 19
REFB
description
REFA
4
DGND
5
18
17
16
15
14
V
DD
The TLC7528C, TLC7528E, and TLC7528I are
dual, 8-bit, digital-to-analog converters designed
with separate on-chip data latches and feature
exceptionally close DAC-to-DAC matching. Data
is transferred to either of the two DAC data latches
through a common, 8-bit, input port. Control input
DACA/DACB determines which DAC is to be
loaded. The load cycle of these devices is similar
WR
DACA/DACB
6
7
8
CS
(MSB) DB7
DB6
DB0 (LSB)
9 10 11 12 13
to the write cycle of a random-access memory, allowing easy interface to most popular microprocessor buses
and output ports. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
where glitch impulse is typically the strongest.
These devices operate from a 5-V to 15-V power supply and dissipates less than 15 mW (typical). The 2- or
4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting
and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than
a current output. Refer to the typical application information in this data sheet.
The TLC7528C is characterized for operation from 0°C to 70°C. The TLC7528I is characterized for operation
from –25°C to 85°C. The TLC7528E is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(DW)
CHIP CARRIER
(FN)
PLASTIC DIP
(N)
0°C to 70°C
–25°C to 85°C
–40°C to 85°C
TLC7528CDW
TLC7528IDW
TLC7528EDW
TLC7528CFN
TLC7528IFN
TLC7528EFN
TLC7528CN
TLC7528IN
TLC7528EN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
functional block diagram
14
DB0
REFA
4
3
2
13
12
11
RFBA
OUTA
8
8
Input
Data
DACA
Latch A
10
Buffer
Inputs
9
8
1
AGND
7
DB7
19
20
RFBB
OUTB
6
8
DACA/DACB
8
16
15
DACB
18
Latch B
Logic
Control
WR
CS
REFB
operating sequence
t
t
t
su(CS)
h(CS)
CS
t
)
su(DAC
h(DAC)
DACA/DACB
WR
t
w(WR)
t
t
h(D)
su(D)
Data In Stable
DB0–DB7
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V
DD
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
DD
Input voltage range, V (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3
I
DD
Reference voltage, V
Feedback voltage V
or V
or V
(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
RFBB
refA
RFBA
refB
Input voltage (voltage mode out A, out B to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3
DD
Output voltage, V
or V
(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
OA
OB
Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA
Operating free-air temperature range, T : TLC7528C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC7528I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
TLC7528E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Case temperature for 10 seconds, T : FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
V
= 4.75 V to 5.25 V
V
= 14.5 V to 15.5 V
DD
DD
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
Reference voltage, V
refA
or V
refB
±10
±10
V
High-level input voltage, V
IH
2.4
13.5
V
Low-level input voltage, V
0.8
1.5
V
IL
CS setup time, t
50
0
50
0
ns
ns
ns
ns
ns
ns
ns
su(CS)
CS hold time, t
h(CS)
DAC select setup time, t
50
10
25
10
50
0
50
10
25
10
50
0
su(DAC)
DAC select hold time, t
h(DAC)
Data bus input setup time t
su(D)
Data bus input hold time t
h(D)
Pulse duration, WR low, t
w(WR)
TLC7628C
TLC7628I
TLC7628E
70
85
85
70
85
85
Operating free-air temperature, T
–25
–40
–25
–40
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range,
V
= V
= 10 V, V
and V
at 0 V (unless otherwise noted)
refA
refB
OA
OB
V
= 5 V
V
= 15 V
DD
DD
MIN TYP
PARAMETER
TEST CONDITIONS
V = V
UNIT
†
†
MIN TYP
MAX
10
MAX
10
I
I
High-level input current
Low-level input current
µA
µA
IH
I
DD
V = 0
I
5
12
–10
5
12
–10
IL
Reference input impedance
REFA or REFB to AGND
20
±400
±400
20
±200
±200
kΩ
DAC data latch loaded with
00000000, V = ±10 V
OUTA
OUTB
refA
DAC data latch loaded with
00000000, V = ±10 V
I
Output leakage current
nA
Ikg
refB
Input resistance match
(REFA to REFB)
±1%
0.04
2
±1%
0.02
2
DC supply sensitivity, ∆gain/∆V
Supply current (quiescent)
Supply current (standby)
∆V
DD
= ±10%
%/%
mA
DD
All digital inputs at V min or
IH
I
I
DD
V max
IL
All digital inputs at 0 V or V
0.5
10
0.5
10
mA
pF
DD
DD
DB0–DB7
C
C
Input capacitance
WR, CS,
DACA/DACB
i
15
50
15
50
pF
DAC data latches loaded with
00000000
Output capacitance (OUTA, OUTB)
pF
o
DAC data latches loaded with
11111111
120
120
†
All typical values are at T = 25°C.
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
operating characteristics over recommended operating free-air temperature range,
V
= V
= 10 V, V
and V
at 0 V (unless otherwise noted)
refA
refB
OA
OB
V
= 5 V
DD
TYP
V
= 15 V
DD
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
±1/2
100
MIN
TYP
MAX
±1/2
100
2.5
Linearity error
LSB
ns
Settling time (to 1/2 LSB)
Gain error
See Note 1
See Note 2
2.5
LSB
REFA to OUTA
REFB to OUTB
–65
–65
0.007
–65
–65
AC feedthrough
See Note 3
dB
Temperature coefficient of gain
See Note 4
See Note 5
0.0035 %FSR/°C
Propagation delay (from digital input to
90% of final analog output current)
80
80
ns
REFA to OUTB See Note 6
REFB to OUTA See Note 7
77
77
77
77
Channel-to-channel
isolation
dB
Measured for code transition
from 00000000 to 11111111,
= 25°C
Digital-to-analog glitch impulse area
Digital crosstalk
160
440
nV•s
T
A
Measured for code transition
from 00000000 to 11111111,
30
60
nV•s
T
A
= 25°C
Harmonic distortion
V = 6 V, f = 1 kHz,
i
T
A
= 25°C
–85
–85
dB
NOTES: 1. OUTA, OUTB load = 100 Ω, C
= 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to V
or V
to 0 V.
DD
ref
ext
DD
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = V – 1 LSB.
3.
4. Temperature coefficient of gain measured from 0°C to 25°C or from 25°C to 70°C.
5. = V = 10 V; OUTA/OUTB load = 100 Ω, C = 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to V
V
ref
= 20 V peak-to-peak, 100-kHz sine wave; DAC data latches loaded with 00000000.
V
refA
or V to 0 V.
DD
refB ext
DD
= 0; T = 25°C.
6. Both DAC latches loaded with 11111111; V
7. Both DAC latches loaded with 11111111; V
= 20 V peak-to-peak, 100-kHz sine wave; V
= 20 V peak-to-peak, 100-kHz sine wave; V
refA
refB
refB
refA
A
= 0; T = 25°C.
A
PRINCIPLES OF OPERATION
These devices contain two identical, 8-bit-multiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the
switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs
share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to
OUTA. A small leakage current (I ) flows across internal junctions, and as with most semiconductor devices,
Ikg
doubles every 10°C. C is due to the parallel combination of the NMOS switches and has a value that depends
o
onthenumberofswitchesconnectedtotheoutput. TherangeofC is50pFto120pFmaximum. Theequivalent
o
output resistance (r ) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder
o
resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line,
responds to the activity on the DB0–DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DB0–DB7 inputs is latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled regardless of the state of the WR signal.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
PRINCIPLES OF OPERATION
The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5 V. These
devices can operate with any supply voltage in the range from 5 V to 15 V; however, input logic levels are not
TTL compatible above 5 V.
R
R
R
REFA
2R
2R
2R
2R
2R
R
FB
RFBA
S1
S2
S3
S8
OUTA
AGND
DACA Data Latches and Drivers
Figure 1. Simplified Functional Circuit for DACA
RFBA
R
FB
R
OUTA
REFA
I
C
I
OUT
Ikg
256
AGND
Figure 2. TLC7528 Equivalent Circuit, DACA Latch Loaded With 11111111
MODE SELECTION TABLE
DACA/DACB CS WR DACA
DACB
L
H
X
X
L
L
H
X
L
L
X
H
Write
Hold
Hold
Hold
Hold
Write
Hold
Hold
L = low level, H = high level, X = don’t care
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. Tables 1 and 2 summarize input coding
for unipolar and bipolar operation.
V
I(A)
±10 V
R1 (see Note A)
R2 (see Note A)
C1
RFBA
OUTA
AGND
17
14
(see Note B)
V
DD
REFA
DB0
–
+
8
Input
Buffer
8
V
OA
DACA
Latch
DB7
7
R4 (see Note A)
C2
RFBB
OUTB
(see Note B)
8
6
15
16
5
–
DACA/DACB
8
Control
Logic
DACB
Latch
V
OB
CS
+
WR
AGND
REFB
AGND
DGND
RECOMMENDED TRIM
RESISTOR VALUES
R3 (see Note A)
V
I(B)
±10 V
R1, R3 500 Ω
R2, R4 150 Ω
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
V
R6
20 kΩ
I(A)
±10 V
(see Note B)
R1
R2 (see Note A)
(see Note A)
RFBA
OUTA
C1
R5
20 kΩ
17
14
(see Note C)
V
DD
R7
10 kΩ
DB0
–
Input
Buffer
8
8
DACA
Latch
A1
+
–
A2
+
AGND
(see Note B)
DB7
V
OA
7
6
R11
5 kΩ
R4 (see Note A)
C2
RFBB
DACA/
DACB
R8
20 kΩ
Control
Logic
15
CS
(see Note C)
16
5
–
OUTB
AGND
WR
8
8
–
DACB
REFB
Latch
A3
+
A4
+
V
OB
R9
10 kΩ
(see Note B)
DGND
AGND
R11
5 kΩ
R3
AGND
(see Note A)
R10
V
20 kΩ
(see Note B)
I(B)
±10 V
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for
= 0 V with code 10000000 in DACA latch. Adjust R3 for V = 0 V with 10000000 in DACB latch.
V
OA
OB
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
Table 2. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
DAC LATCH CONTENTS
ANALOG OUTPUT
ANALOG OUTPUT
†
LSB
‡
LSB
MSB
MSB
1 1 1 1 1 1 1 1
–V (255/256)
1 1 1 1 1 1 1 1
V (127/128)
I
I
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
–V (129/256)
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V (1/128)
I
I
–V (128/256) = –V /2
0 V
I
i
–V (127/256)
–V (1/128)
I
I
–V (1/256)
–V (127/128)
I
I
–V (0/256) = 0
–V (128/128)
I
I
†
–8
1 LSB = (2 )V
‡
–7
1 LSB = (2 )V
I
I
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
microprocessor interface information
8
Address Bus
A8–A15
DACA/DACB
CS
A
Address
Decode
Logic
A + 1
TLC7528
WR
CPU
8051
DB0
WR
DB7
ALE
Latch
8
Data Bus
AD0–AD7
NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB
Figure 5. TLC7528 – Intel 8051 Interface
8
Address Bus
A8–A15
VMA
DACA/DACB
CS
A
Address
Decode
Logic
A + 1
TLC7528
WR
CPU
6800
DB0
DB7
φ2
8
Data Bus
AD0–AD7
NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB
Figure 6. TLC7528 – 6800 Interface
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
8
Address Bus
A8–A15
DACA/DACB
A
Address
Decode
Logic
IORQ
CS
TLC7528
WR
A + 1
CPU
Z80-A
DB0
DB7
WR
8
Data Bus
D0–D7
NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB
Figure 7. TLC7528 To Z-80A Interface
programmable window detector
The programmable window comparator shown in Figure 8 determines if voltage applied to the DAC feedback
resistors are within the limits programmed into the data latches of these devices. Input signal range depends
on the reference and polarity, that is, the test input range is 0 to –V . The DACA and DACB data latches are
ref
programmed with the upper and lower test limits. A signal within the programmed limits drives the output high.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
V
DD
V
CC
Test Input
0 to –V
3
17
ref
RFBA
1 kΩ
OUTA
2
–
+
4
14–7
15
DACA
REFA
8
Data Inputs
DB0–DB7
TLC7528
1
PASS/FAIL Output
CS
AGND
16
6
WR
DACA/DACB
OUTB
20
–
+
18
5
REFB
V
ref
DACB
DGND
RFBB
19
Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester)
digitally controlled signal attenuator
Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo
audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB range.
Attenuation dB = –20 log D/256, D = digital input code
10
RFBA
OUTA
3
2
17
4
V
DD
REFA
V A
I
DACA
A1
8
Output
14–7
DB0–DB7
Data Bus
TLC7528
15
16
6
CS
WR
DACA/DACB
OUTB
RFBB
20
19
REFB 18
DACB
A2
V
O
B
1
AGND
5
DGND
Figure 9. Digitally Controlled Dual Telephone Attenuator
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
Table 3. Attenuation vs DACA, DACB Code
CODE IN
CODE IN
DECIMAL
ATTN (dB)
DAC INPUT CODE
ATTN (dB)
DAC INPUT CODE
DECIMAL
255
242
228
215
203
192
181
171
162
152
144
136
128
121
114
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
1 1 1 1 1 1 1 1
1 1 1 1 0 0 1 0
1 1 1 0 0 1 0 0
1 1 0 1 0 1 1 1
1 1 0 0 1 0 1 1
1 1 0 0 0 0 0 0
1 0 1 1 0 1 0 1
1 0 1 0 1 0 1 1
1 0 1 0 0 0 1 0
1 0 0 1 1 0 0 0
1 0 0 1 1 1 1 1
1 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0
0 1 1 1 1 0 0 1
0 1 1 1 0 0 1 0
0 1 1 0 1 1 0 0
8.0
8.5
0 1 1 0 0 1 1 0
0 1 1 0 0 0 0 0
0 1 0 1 1 0 1 1
0 1 0 1 0 1 1 0
0 1 0 1 0 0 0 1
0 1 0 0 1 1 0 0
0 1 0 0 1 0 0 0
0 1 0 0 0 1 0 0
0 1 0 0 0 0 0 0
0 0 1 1 1 1 0 1
0 0 1 1 1 0 0 1
0 0 1 1 0 1 1 0
0 0 1 1 0 0 1 1
0 0 1 1 0 0 0 0
0 0 1 0 1 1 1 0
0 0 1 0 1 0 1 1
102
96
91
86
81
76
72
68
64
61
57
54
51
48
46
43
9.0
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
108
programmable state-variable filter
This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass
outputs, and is suitable for applications requiring microprocessor control of filter parameters.
As shown in Figure 10, DACA1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2 control
the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the
cutoff-frequency equation to be true. With the TLC7528, this is easy to achieve.
1
f
c
2
R1C1
The programmable range for the cutoff or center frequency is 0 to 15 kHz with a Q ranging from 0.3 to 4.5. This
defines the limits of the component values.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
C3
47 pF
R5
4
2
REFA
OUTA
–
V
I
DACA
(R )
S
17
30 kΩ
V
DD
3
1
A1
+
RFBA
AGND
R4
8
14–7
Data In
DB0–DB7
30 kΩ
TLC7528
DACB
R3
–
15
16
5
High Pass
Out
CS
20
19
OUTB
A2
10 kΩ
+
WR
(R )
F
RFBB
REFB
DGND
18
6
DACA/DACB
Bandpass Out
DACA1 AND DACB1
C1
1000 pF
–
2
REFA
OUTA
4
DACA
(R )
1
17
A3
+
V
3
1
DD
C2
RFBA
AGND
8
14–7
Data In
DB0–DB7
TLC7528
DACB
1000 pF
–
15
16
5
CS
20
19
OUTB
WR
(R )
2
Low Pass Out
A4
+
RFBB
REFB
DGND
18
6
DACA/DACB
DACA2 and DACB2
Circuit Equations:
C
= C , R = R , R = R
1
2
1
2
4
5
R
R
R
3
4
F
Q
·
R
fb(DACB1)
Where:
R
is the internal resistor connected between OUTB and RFBB
fb
R
F
G
–
R
S
NOTES: A. Op-amps A1, A2, A3, and A4 are TL287.
B. CS compensates for the op-amp gain-bandwidth limitations.
256 (DAC ladder resistance)
C. DAC equivalent resistance equals
DAC digital code
Figure 10. Digitally Controlled State-Variable Filter
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
APPLICATION INFORMATION
voltage-mode operation
It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage
mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at
the reference voltage terminal. Figure 11 is an example of a current multiplying D/A, that operates in the voltage
mode.
R
R
R
REF
(Analog Output Voltage)
2R
2R
2R
2R
R
“0”
“1”
Out (Fixed Input Voltage)
AGND
Figure 11. Voltage-Mode Operation
The following equation shows the relationship between the fixed input voltage and the analog output voltage:
V
= V (D/256)
I
O
Where:
V
= analog output voltage
O
V = fixed input voltage (must not be forced below 0 V.)
I
D = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:
PARAMETER
Linearity error at REFA or REFB
TEST CONDITIONS
MIN
MAX
UNIT
V
DD
= 5 V, OUTA or OUTB at 2.5 V,
T
A
= 25°C
1
LSB
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/D 01/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062B – JANUARY 1987 – REVISED MARCH 2000
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.035 (0,89) MAX
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
M
14/18 PIN ONLY
4040049/D 02/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2000, Texas Instruments Incorporated
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