TLK1102ERGER [TI]
11.3-Gbps Dual-Channel Cable and PC Board Equalizer; 11.3 - Gbps的双通道电缆和PC主板均衡器
| 型号： | TLK1102ERGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 11.3-Gbps Dual-Channel Cable and PC Board Equalizer |
| 文件： | 总31页 (文件大小：1773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLK1102E
www.ti.com ................................................................................................................................................................................................... SLLS958–MARCH 2009
11.3-Gbps Dual-Channel Cable and PC Board Equalizer
1
FEATURES
•
Surface Mount Small Footprint 4-mm × 4-mm
24-Pin QFN Package
23
•
Dual-Channel Multi-Rate Operation up to
11.3Gbps
•
•
Single 3.3V Supply
•
•
Two-Wire Serial Interface (with 8 Selectable
Device Addresses) or Device Pin Control
-40°C to 100°C Operation (Lead Temperature)
APPLICATIONS
•
Compensates for up to 30dB Loss on the
Receive Side and up to 7dB Loss on the
Transmit Side at 5.65GHz
High-Speed Links In Communication and Data
Systems
•
Backplane, Daughtercard, and Cable
Interconnects for 10GE, 8GFC, 10GFC, 10G
SONET, SAS, SATA, and InfiniBand
QSFP, SFP+, XFP, SAS, SATA, and InfiniBand
Active Cable Assemblies
•
•
•
•
Adjustable Input Equalization Level
Adjustable Output De-Emphasis: 0 - 7dB
Adjustable Input Bandwidth: 4.5 - 11GHz
•
Adjustable CML Output Swing: 225 -
1200mVp-p
•
•
Loss of Signal (LOS) Detection
Output Disable with Selectable Auto-Squelch
Function
•
•
Output Polarity Switch
Excellent High Frequency Input and Output
Return Loss
Up to 20-meter 100 W
Cable or Equivalent
Backplane Link
100W Differential
PCB Interconnect
100 W Differential
PCB Interconnect
AC -
Coupling
Up to 11.3 Gbps
AC -
TLK1102E
TLK1102E
Differential Input Signal
Coupling
Up to 20-meter 100 W
Cable or Equivalent
Backplane Link
100W Differential
PCB Interconnect
W
100 Differential
PCB Interconnect
DESCRIPTION
The TLK1102E is a versatile and flexible high-speed dual-channel equalizer for applications in digital high-speed
links with data rates up to 11.3Gbps.
The TLK1102E can be configured in many ways through its two-wire serial interface, available through the SDA
and the SCL pins, to optimize its performance. The configurable parameters include the output de-emphasis
settable from 0 to 7dB, the output differential voltage swing settable from 225 to 1200mVp-p, the input
equalization level settable for 0 to 20 meters of 24-AWG twinaxial cable, 0 to 40 inches of FR-4 PCB
interconnect, or equivalent interconnect (see Table 1), the input filter bandwidth settable from 4.5 to 11GHz, and
the LOS (loss of signal) assert voltage level.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Spectra-Strip, SKEWCLEAR, XCede are registered trademarks of Amphenol Corporation.
SI is a trademark of Park Electrochemical Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TLK1102E
SLLS958–MARCH 2009................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Alternatively, the TLK1102E can be configured using its configuration pins in two modes selectable using the
MODE pin. In Pin Control Mode 1 (see Figure 2b), a common setting can be set for the two channels for the
output de-emphasis level and the interconnect length using the DE pin and LN0, LN1 pins respectively. In Pin
Control Mode 2 (see Figure 2c), those parameters can be set individually for the two channels using DEA, DEB,
LNA, and LNB pins. In both modes only a common setting is available for the output voltage swing using the
SWG pin. For Pin Control Mode 2 the typical LOS assert and de-assert voltage levels are fixed at 90mVp-p and
150mVp-p respectively with 4.0dB hysteresis.
The outputs can be disabled using the DISA and DISB pins. The DISA/DISB pins and the LOSA/LOSB pins can
be connected together to implement an external output squelch function. The TLK1102E implements an internal
output squelch function that can be enabled using the two-wire serial interface. In addition, a special fast
auto-squelch function can be selected through the two-wire serial interface when needed to support SAS and
SATA out-of-band (OOB) signals.
The POLA and POLB pins can be used to reverse the polarity of the OUTA+/OUTA- and OUTB+/OUTB– pins
respectively.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1600mVp-p differential. The low-frequency cut-off is low enough to support low-frequency
control signals such as SAS and SATA OOB signals. The loss-of-signal detection and output disable functions
are carefully designed to meet SAS/SATA OOB signal timing constraints.
Table 1. Equalization Level Settings
TWO-WIRE SERIAL I/F MODE
PIN MODE 1
PIN MODE 2
CABLE LENGTH (meters)
(1.8dB/m loss at 5 GHz)
(registers 3 and 6)
LN1
GND
GND
VCC
VCC
LN0
GND
VCC
GND
VCC
LNA / LNB
GND
EQ3
EQ2
EQ1
EQ0
0 – 2
2 – 6
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
GND
6 – 11
11 – 15
1.8 MΩ to GND
VCC
2
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TLK1102E
www.ti.com ................................................................................................................................................................................................... SLLS958–MARCH 2009
BLOCK DIAGRAM
A simplified block diagram of the TLK1102E is shown in Figure 1 for the two-wire serial interface control mode.
This compact, low power, 11.3-Gbps dual-channel equalizer consists of a high-speed data path with an offset
cancellation block combined with an analog input threshold selection circuitry, a loss of signal detection block, a
two-wire interface with a control-logic block, a bandgap voltage reference, and a bias current generation block.
VCC
GND
Offset
Cancellation
VCC
VCC
Input Buffer
with
Output
Buffer
Output
Driver
50 W
50 W
50 W
50 W
Selectable
Bandwidth
Equalizer
Stage
OUT[B:A]+
OUT[B:A]–
LOS[B:A]
IN[B:A]+
IN[B:A]–
Loss of Signal
Detection
General Settings
SDA
4-Bit
2 ´ 7-Bit
2 ´ 4-Bit
2 ´ 4-Bit
2 ´ 4-Bit
2 ´ 4-Bit
SDA
SCL
Control Settings
De-emphasis
SCL
Output Swing
DISA
DISA
Input Bandwidth
Equalization Level
DISB
DISB
2 ´ 7-Bit
2 ´ 1-Bit
2 ´ 1-Bit
LOS Assert Level
Fast LOS Control
LOS Status
Bandgap Voltage
Reference and
Bias Current
Generation
MODE
MODE
CS
CS
RST
RST
Power-On
Reset
ADD0
ADD1
ADD2
ADD0
ADD1
ADD2
2-Wire Interface and
Control Logic
Figure 1. Simplified Block Diagram of the TLK1102E
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TLK1102E
SLLS958–MARCH 2009................................................................................................................................................................................................... www.ti.com
PACKAGE
For the TLK1102E a small footprint 4-mm × 4-mm 24-pin QFN package is used, with a lead pitch of 0.5mm.
Three pin-outs are available for this device as shown in Figure 2. The pin-out in Figure 2a is applicable for the
case where the device is setup to be controlled through the two-wire serial interface. The pin-outs in Figure 2b
and Figure 2c are applicable for the cases where the device is setup to be controlled through the device
configuration pins. The MODE pin controls the pinout as described in the TERMINAL FUNCTIONS tables.
24
19
24
19
1
18
18
1
INA+
INA+
OUTA+
OUTA-
VCC
OUTA+
OUTA-
VCC
Top View
Top View
INA-
GND
GND
INB+
INB-
INA-
GND
GND
INB+
INB-
Exposed Thermal Pad
must be soldered
to GND
Exposed Thermal Pad
must be soldered
to GND
VCC
VCC
OUTB+
OUTB+
EP
EP
OUTB-
OUTB-
13
13
6
6
12
12
7
7
(a) Two-Wire Serial Interface Control Mode
(b) Pin Control Mode 1
24
1
19
18
INA+
OUTA+
OUTA-
VCC
Top View
INA-
GND
GND
INB+
Exposed Thermal Pad
must be soldered
to GND
VCC
OUTB+
EP
INB-
OUTB-
13
6
7
12
(c) Pin Control Mode 2
Figure 2. Pin-Out of the TLK1102E in a 4-mm × 4-mm 24-Pin QFN Package
4
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TLK1102E
www.ti.com ................................................................................................................................................................................................... SLLS958–MARCH 2009
TERMINAL FUNCTIONS - TWO-WIRE SERIAL INTERFACE CONTROL MODE
Pin descriptions for the TLK1102E in a 4-mm x 4-mm 24-pin QFN package when the device is set to be
controlled using the two-wire serial interface. This mode is selected through setting the MODE pin (pin 10) to
high level.
PIN
1, 2
3, 4
5, 6
7
SYMBOL
INA+, INA-
GND
TYPE
analog-in
supply
DESCRIPTION
First pair of differential data inputs. Each pin is on-chip 50Ω terminated to VCC.
Circuit ground.
INB+, INB-
CS
analog-in
digital-in
Second pair of differential data inputs. Each pin is on-chip 50Ω terminated to VCC.
Chip Select pin. Disables the two-wire serial interface when set to low level. Internally pulled up.
8
SDA
digital-in/out Bidirectional serial data pin for the two-wire serial interface. Open drain. Connect to a 10kΩ
pull-up resistor if used. Leave open if unused.
9
SCL
digital-in
Serial clock pin for the two-wire serial interface. Connect to a 10kΩ pull-up resistor if used. Leave
open if unused. Internally pulled up to VCC with a 500kΩ resistor.
10
11
12
MODE
DISB
three-state
digital-in
Device control mode select. Pull up to VCC for the two-wire serial interface control mode.
Disables CML output stage for OUTB+ and OUTB- when set to high level. Internally pulled down.
LOSB
digital-out
High level indicates that the input signal amplitude on INB+/INB- is below the programmed
threshold level. Open drain. Requires an external 10kΩ pull-up resistor to VCC for proper
operation.
13, 14 OUTB-, OUTB+ analog-out
15, 16 VCC supply
17, 18 OUTA-, OUTA+ analog-out
Second pair of differential data outputs. Each pin is on-chip 50Ω terminated to VCC.
3.3V ± 10% supply voltage.
First pair of differential data outputs. Each pin is on-chip 50Ω terminated to VCC.
19
LOSA
digital-out
High level indicates that the input signal amplitude on INA+/INA- is below the programmed
threshold level. Open drain. Requires an external 10kΩ pull-up resistor to VCC for proper
operation.
20
DISA
digital-in
digital-in
Disables CML output stage for OUTA+ and OUTA- when set to high level. Internally pulled down.
21, 22, ADD2, ADD1,
23
Configurable least significant bits (ADD[2:0]) of the two-wire serial interface device address. The
fixed most significant bits (ADD[6:3]) of the 7-bit device address are 0101. The default address is
0101100. These pins are internally pulled up. Pull down externally to invert the associated bits.
ADD0
24
RST
EP
digital-in
Reset pin. Resets all the device digital circuits when set to high level. Internally pulled down.
Exposed die pad (EP) must be grounded.
EP
TERMINAL FUNCTIONS - PIN CONTROL MODE 1
Pin descriptions for the TLK1102E in a 4-mm x 4-mm 24-pin QFN package when the device is set for Pin Control
Mode 1. This mode is selected through setting the MODE pin (pin 10) to low level.
PIN
1, 2
3, 4
5, 6
7
SYMBOL
INA+, INA-
GND
TYPE
analog-in
supply
DESCRIPTION
First pair of differential data inputs. Each pin is on-chip 50Ω terminated to VCC.
Circuit ground.
INB+, INB-
DE
analog-in
analog-in
Second pair of differential data inputs. Each pin is on-chip 50Ω terminated to VCC.
Output signal de-emphasis control. A 0 to 1.2-V controlling voltage on this pin adjusts output
de-emphasis on OUTA and OUTB pins from 0 to 7dB.
8
9
LOSL
POLB
analog-in
digital-in
LOS threshold control. A 0 to 0.7-V controlling voltage on this pin adjusts the LOS assert and
de-assert levels on INA and INB pins.
Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high level
or leave open for normal polarity. Set to low level for inverted polarity.
10
11
MODE
DISB
three-state Device control mode select. Tie to GND for pin control mode 1.
digital-in
Disables CML output stage for OUTB+ and OUTB- when set to high level. Internally pulled
down.
12
LOSB
digital-out
High level indicates that the input signal amplitude on INB+/INB- is below the programmed
threshold level. Open drain. Requires an external 10kΩ pull-up resistor to VCC for proper
operation.
13, 14 OUTB-, OUTB+ analog-out
15, 16 VCC supply
Second pair of differential data outputs. Each pin is on-chip 50Ω terminated to VCC.
3.3V ± 10% supply voltage.
17, 18 OUTA-, OUTA+ analog-out
First pair of differential data outputs. Each pin is on-chip 50Ω terminated to VCC.
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PIN
SYMBOL
LOSA
TYPE
DESCRIPTION
19
digital-out
High level indicates that the input signal amplitude on INA+/INA- is below the programmed
threshold level. Open drain. Requires an external 10kΩ pull-up resistor to VCC for proper
operation.
20
21
22
DISA
SWG
POLA
digital-in
Disables CML output stage for OUTA+ and OUTA- when set to high level. Internally pulled
down.
three-state OUTA, OUTB swing control. Tie to VCC for 1200mVp-p swing, tie to GND for 225mVp-p swing, or
pull down with a 1.8MΩ resistor for 600mVp-p swing.
digital-in
digital-in
Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high level
or leave open for normal polarity. Set to low level for inverted polarity.
23, 24 LN1, LN0
Equalization level setting. Internally pulled up. Each pin supports two logic levels: high and low –
four settings in the following low to high equalization order: LN1=LN0=0; LN1=0 LN0=1; LN1=1
LN0=0; LN1=LN0=1
EP
EP
Exposed die pad (EP) must be grounded.
TERMINAL FUNCTIONS - PIN CONTROL MODE 2
Pin descriptions for the TLK1102E in a 4-mm x 4-mm 24-pin QFN package when the device is set for Pin Control
Mode 2. This mode is selected through pulling down the MODE pin (pin 10) with a 1.8-MΩ resistor.
PIN
1, 2
3, 4
5, 6
7
SYMBOL
INA+, INA-
GND
TYPE
analog-in
supply
DESCRIPTION
First pair of differential data inputs. Each pin is on-chip 50Ω terminated to VCC.
Circuit ground.
INB+, INB-
DEA
analog-in
analog-in
Second pair of differential data inputs. Each pin is on-chip 50Ω terminated to VCC.
Output signal de-emphasis control for OUTA. A 0 to 1.2-V controlling voltage on this pin adjusts
output de-emphasis on OUTA+/OUTA- pins from 0 to 7dB.
8
9
DEB
analog-in
digital-in
Output signal de-emphasis control for OUTB. A 0 to 1.2-V controlling voltage on this pin adjusts
output de-emphasis on OUTB+/OUTB- pins from 0 to 7dB.
POLB
Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high level
or leave open for normal polarity. Set to low level for inverted polarity.
10
11
MODE
DISB
three-state
digital-in
Device control mode select. Pull down with a 1.8MΩ resistor for pin control mode 2.
Disables CML output stage for OUTB+ and OUTB- when set to high level. Internally pulled
down.
12
LOSB
digital-out
High level indicates that the input signal amplitude on INB+/INB- is below the programmed
threshold level. Open drain. Requires an external 10kΩ pull-up resistor to VCC for proper
operation.
13, 14 OUTB-, OUTB+ analog-out
15, 16 VCC supply
17, 18 OUTA-, OUTA+ analog-out
Second pair of differential data outputs. Each pin is on-chip 50Ω terminated to VCC.
3.3V ± 10% supply voltage.
First pair of differential data outputs. Each pin is on-chip 50Ω terminated to VCC.
19
LOSA
digital-out
High level indicates that the input signal amplitude on INA+/INA- is below the programmed
threshold level. Open drain. Requires an external 10kΩ pull-up resistor to VCC for proper
operation.
20
21
22
23
DISA
SWG
POLA
LNA
digital-in
Disables CML output stage for OUTA+ and OUTA- when set to high level. Internally pulled
down.
three-state
digital-in
OUTA, OUTB swing control. Tie to VCC for 1200mVp-p swing, tie to GND for 225mVp-p swing,
or pull down with a 1.8MΩ resistor for 600mVp-p swing.
Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high level
or leave open for normal polarity. Set to low level for inverted polarity.
three-state
Equalization level setting. Supports three equalization settings. Tie to VCC for high setting, tie
to GND for low setting, or pull down with 1.8MΩ resistor for medium setting. Internally tied to
VCC/2.
24
LNB
EP
three-state
Equalization level setting. Supports three equalization settings. Tie to VCC for high setting, tie
to GND for low setting, or pull down with 1.8MΩ resistor for medium setting. Internally tied to
VCC/2.
EP
Exposed die pad (EP) must be grounded.
6
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www.ti.com ................................................................................................................................................................................................... SLLS958–MARCH 2009
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
-0.3 to 4.0
0.5 to 4.0
-0.3 to 4.0
±2.5
UNIT
VCC
Supply voltage(2)
V
VIN+, VIN-
VIO
Voltage at INA+, INA-, INB+, INB-(2)
Voltage at pin 7 to 11 and pin 20 to 24(2)
Differential voltage between INA+ and INA-, and between INB+ and INB-
Continuous current at data inputs
Continuous current at data outputs
Sink current at LOSA and LOSB outputs
ESD rating at all pins
V
V
V
VIN,DIFF
IIN+, IIN-
IOUT+, IOUT-
ILOS
-25 to 25
-35 to 35
25
mA
mA
mA
ESD
2.5
kV (HBM)
°C
TJ,max
Maximum junction temperature
125
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
2.95
-40
NOM
MAX
3.6
UNIT
V
VCC
TA
Supply voltage
3.3
Operating lead temperature
CMOS input high voltage
CMOS input low voltage
100
°C
V
VIH
VIL
2.1
0.7
V
DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.3
MAX
3.6
UNIT
VCC
ICC
Supply voltage
2.95
V
600mVp-p SWG setting (CML output current included)
1200mVp-p SWG setting (CML output current included)
170
225
230
290
Supply current
mA
V
LOS high voltage
ISOURCE = 50µA; 10kΩ Pull-up to VCC on LOSA or
2.4
LOSB pin
LOS low voltage
ISINK = 10mA; 10kΩ Pull-up to VCC on LOSA or LOSB
0.4
V
pin
AC ELECTRICAL CHARACTERISTICS
Typical operating condition is at VCC = 3.3V and TA = 25°C. Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low frequency -3dB bandwidth
With 0.1µF input AC-coupling capacitors
30
50
kHz
BER < 10-12 , K28.5 pattern at 11.3Gbps over a 10m
28AWG cable including two SMA connectors (27dB loss
at 5.65GHz),
SWG = 600mVp-p setting, no de-emphasis, maximum
interconnect length setting. Voltage measured at the
input of the cable.
VIN,MIN
Data input sensitivity
Data input overload
250
mVp-p
BER < 10–12 , K28.5 pattern at 11.3Gbps, K28.5 pattern
at 11.3Gbps over a 15m 24AWG cable including two
SMA connectors (29dB loss at 5.65GHz), SWG =
600mVp-p setting, no de-emphasis, maximum
interconnect length setting. Voltage measured at the
input of the cable.
VIN,MAX
1600
mVp-p
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AC ELECTRICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3V and TA = 25°C. Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIS = Low, SWG = Low, VIN = 400mVp-p
no de-emphasis, no interconnect loss.
,
150
225
350
Differential data output voltage
swing
DIS = Low, SWG = 600mVp-p setting, VIN = 400mVp-p
no de-emphasis, no interconnect loss.
,
VOD
400
800
600
800
mVp-p
DIS = Low, SWG = High, VIN = 400mVp-p
,
1200
1600
no de-emphasis, no interconnect loss.
DIS = Low, SWG = Low, VIN = 400mVp-p
,
no de-emphasis, no interconnect loss, 50Ω to VCC
output termination.
VCC-0.12
VCC-0.08
VCC-0.04
VCC-0.12
VCC-0.25
DIS = Low, SWG = 600mVp-p setting, VIN = 400mVp-p
Data output common-mode voltage no de-emphasis, no interconnect loss, 50Ω to VCC
,
VCM,OUT
VCC-0.29 VCC-0.205
V
output termination.
DIS = Low, SWG = High, VIN = 400mVp-p
,
no de-emphasis, no interconnect loss, 50Ω to VCC
VCC-0.65
VCC-0.45
output termination.
DIS = Low, SWG = 600mVp-p setting, K28.5 pattern at
11.3Gbps, no interconnect loss, 600mV on DE pin, VIN
VCM,RIP
Common-mode output ripple
Differential output ripple
=
2
5
mVRMS
mVp-p
1600mVp-p
.
DIS = High, K28.5 pattern at 11.3Gbps, no interconnect
VOD,RIP
15
20
loss, VIN = 1600mVp-p
.
K28.5 pattern at 11.3Gbps on both channels, no
interconnect loss,
VIN = 400mVp-p, SWG = 600mVp-p setting, no
de-emphasis.
0
7
DE
DJ
RJ
Output de-emphasis
Deterministic jitter
Random jitter
dB
K28.5 pattern at 11.3Gbps on both channels, no
interconnect loss,
VIN = 400mVp-p, SWG = 600mVp-p setting, maximum
de-emphasis level.
K28.5 pattern at 11.3Gbps on both channels, 10m
28AWG cable (27dB loss at 5.65GHz),
VIN = 400mVp-p, SWG = 600mVp-p setting, 600mV on DE
pin, maximum interconnect length setting.
8
psp-p
K28.5 pattern at 11.3Gbps on both channels, 15m
24AWG cable (29dB loss at 5.65GHz),
VIN = 400mVp-p, SWG = 600mVp-p setting, 600mV on DE
pin, maximum interconnect length setting.
12
1.2
1.4
K28.5 pattern at 11.3Gbps on both channels, 10m
28AWG cable (27dB loss at 5.65GHz),
VIN = 400mVp-p, SWG = 600mVp-p setting, 600mV on DE
pin, maximum interconnect length setting.
psRMS
K28.5 pattern at 11.3Gbps on both channels, 15m
24AWG cable (29dB loss at 5.65GHz),
VIN = 400mVp-p, SWG = 600mVp-p setting, 600mV on DE
pin, maximum interconnect length setting.
Channel A: K28.5 pattern at 11.3Gbps, 15m 24AWG
cable (29dB loss at 5.65GHz), VIN = 600mVp-p, Register
2 = 10h (offset cancellation OFF), Register 3 = 01h
(equalizer filter 1 OFF), Register 4 = 66h (680mVpp
output swing, 3.3dB output de-emphasis);
Channel B: Repeated 1010 pattern at 11.3Gbps, no
interconnect line loss, VIN = 600mVp-p, Register 6 = 10h
(offset cancellation OFF), Register 7 = 0Fh (all equalizer
filters OFF), Register 8 = F6h (680mVpp output swing,
7dB output de-emphasis);
JPXT
Crosstalk jitter penalty
3
psp-p
20% to 80%, No interconnect line,
VIN = 400mVp-p, SWG = 600mVp-p setting, no
de-emphasis
tR
Output rise time
Output fall time
28
28
ps
20% to 80%, no interconnect loss,
VIN = 400mVp-p, SWG = 600mVp-p setting, no
de-emphasis
tF
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AC ELECTRICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3V and TA = 25°C. Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
0.01GHz < f < 4.1GHz
MIN
TYP
MAX
UNIT
(1)
See
SDD11
SDD22
SCC22
Differential input return loss
dB
(2)
(1)
(2)
(3)
(4)
4.1GHz < f < 12.1GHz
0.01GHz < f < 4.1GHz
4.1GHz < f < 12.1GHz
0.01GHz < f < 7.5GHz
7.5GHz < f < 12.1GHz
See
See
See
See
See
Differential output return loss
dB
dB
Common-mode output return loss
K28.5 Pattern at 11.3Gbps, no interconnect loss,
LOSL = Open (also applies to Pin Control Mode 2)
45
70
90
VAS
LOS assert threshold voltage
mVp-p
K28.5 Pattern at 11.3Gbps, no interconnect loss,
V(LOSL) = 0.7V
140
150
235
K28.5 Pattern at 11.3Gbps, no interconnect loss,
LOSL = Open (also applies to Pin Control Mode 2)
300
500
VDAS
LOS de-assert threshold voltage
mVp-p
K28.5 Pattern at 11.3Gbps, no interconnect,
V(LOSL) = 0.7V
LOS hysteresis
20log(VDAS / VAS
)
2.5
4.0
dB
TAS/DAS
VFAS
LOS assert/De-assert time
1/10
2/20
4/30
µs
K28.5 Pattern at 11.3Gbps, no interconnect loss,
Reg 5/9 = 10111111b
Fast LOS assert threshold voltage
150
mVp-p
Fast LOS de-assert threshold
voltage
K28.5 Pattern at 11.3Gbps, no interconnect loss,
Reg 5/9 = 10111111b
VFDAS
220
3.3
mVp-p
dB
Fast LOS hysteresis
20log(VFDAS / VFAS)
Fast auto-squelch mode, no interconnect loss, 600mVp-p
input swing, K28.5 pattern, 1.5Gbps, SWG = 600mVp-p
setting. Time from input off to output voltage < 120mVp-p
TSQUELCH Squelch time
5
ns
TDIS
Disable response time
2
2
ns
ps
ps
TSKEW
Channel-to-channel skew
Latency
OUTB+/ OUTB– relative to OUTA+/OUTA–
from IN[B:A]+/ IN[B:A]– to OUT[B:A]+/OUT[B:A]–
165
(1) Differential return loss given by SDD11, SDD22 = 12.3 - 13 log10(f/5.5), f in GHz
(2) Differential return loss given by SDD11, SDD22 = 18 - 2 √f, f in GHz
(3) Common-mode output return loss given by SCC22 = 12 - 2.8f, f in GHz
(4) Common-mode output return loss given by SCC22 = 5.2 - 0.08f, f in GHz
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TWO-WIRE SERIAL INTERFACE AND CONTROL LOGIC
FUNCTIONAL DESCRIPTION
The TLK1102E uses a two-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are
driven respectively by the serial data and serial clock from a microcontroller, for example. Both inputs require
10kΩ pull-up resistors to VCC when used. For driving these inputs, an open-drain output is recommended.
The two-wire interface allows write access to the internal memory map to modify control registers and read
access to read out control and status signals. The TLK1102E is a slave device only which means that it cannot
initiate a transmission itself; it always relies on the availability of the clock (SCL) signal for the duration of the
transmission. The master device provides the clock signal as well as the START and STOP commands. The
protocol for a data transmission is as follows:
1. START command
2. 7-bit slave address (0101A2A1A0) followed by an eighth bit which is the data direction bit (R/W). A zero
indicates a WRITE and a 1 indicates a READ. The default slave address is 0101100. The A2,A1, and A0
address bits change with the status of the ADD2, ADD1, and ADD0 device pins, respectively. Those pins are
internally pulled up. Pulling down the ADD[2:0] pins changes the address to 0101011. Table 2 summarizes
the slave address settings:
3. 8-bit register address
4. 8-bit register data word
5. STOP command
Table 2. Slave Address Settings
ADD2
ADDR1
ADDR0
SLAVE ADDRESS
0101011
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0101010
0101001
0101000
0101111
0101110
0101101
0101100
Regarding timing, the TLK1102E is I2C-compatible. The typical timing is shown in Figure 3 and a complete data
transfer is shown in Figure 4. Parameters for Figure 3 are defined in Table 3.
Bus Idle: Both SDA and SCL lines remain HIGH
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,
defines a START condition (S). Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH
defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still
wishes to communicate on the bus, it can generate a repeated START condition and address another slave
without first generating a STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
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Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The
transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver does not
acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time
later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by
the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the
master generates the STOP condition.
SDA
t
t
t
t
BUF
t
HDSTA
f
r
HIGH
t
LOW
SCL
P
S
S
P
t
t
t
t
SUSTA
t
SUSTO
HDDAT
HDSTA
SUDAT
Figure 3. Two-Wire Serial Interface Timing Diagram.
Table 3. Two-Wire Serial Interface Timing Diagram Definitions
SYMBOL
PARAMETER
MIN
MAX
UNIT
fSCL
SCL Clock frequency
400
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
tBUF
Bus free time between START and STOP conditions
Hold time after repeated START condition. After this period, the first clock pulse is generated
Low period of the SCL clock
1.3
0.6
1.3
0.6
0.6
0
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
High period of the SCL clock
Setup time for a repeated START condition
Data HOLD time
Data setup time
100
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
300
300
tF
tSUSTO
0.6
SDA
SCL
1-7
8
9
8
9
8
9
1-7
1-7
S
P
SLAVE
R/W
ACK
ACK
ACK
REGISTER
ADDRESS
REGISTER
FUNCTION
ADDRESS
Figure 4. Two-Wire Serial Interface Data Transfer
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REGISTER MAPPING
The register mapping for read/write register addresses 0 (0x00) through 15 (0x0F) are shown in Table 4 to
Table 19. Table 20 describes the circuit functionality based on the register settings.
Table 4. Register 0x00 - General Device Settings
REGISTER ADDRESS 0x00
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET
PWRDOWN
Reserved
Reserved
Reserved
Reserved
LOSRNG
CHA_TRACK
Table 5. Register 0x01 – Reserved
REGISTER ADDRESS 0x01
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 6. Register 0x02 – Control A Control Settings
REGISTER ADDRESS 0x02
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INOFF
OUTOFF
LOSOFF
OCOFF
Reserved
SQUELCH
POL
DISABLE
Table 7. Register 0x03 – Control A Input Settings
REGISTER ADDRESS 0x03
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BW3
BW2
BW1
BW0
EQ3
EQ2
EQ1
EQ0
Table 8. Register 0x04 – Channel A Output Settings
REGISTER ADDRESS 0x04
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEEM3
DEEM2
DEEM1
DEEM0
AMP3
AMP2
AMP1
AMP0
Table 9. Register 0x05 – Channel A LOS Settings
REGISTER ADDRESS 0x05
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FAST
LOSLVL6
LOSLVL5
LOSLVL4
LOSLVL3
LOSLVL2
LOSLVL1
LOSLVL0
Table 10. Register 0x06 – Channel B Control Settings
REGISTER ADDRESS 0x06
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INOFF
OUTOFF
LOSOFF
OCOFF
Reserved
SQUELCH
POL
DISABLE
Table 11. Register 0x07 – Channel B Input Settings
REGISTER ADDRESS 0x07
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BW3
BW2
BW1
BW0
EQ3
EQ2
EQ1
EQ0
Table 12. Register 0x08 – Channel B Output Settings
REGISTER ADDRESS 0x08
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEEM3
DEEM2
DEEM1
DEEM0
AMP3
AMP2
AMP1
AMP0
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Table 13. Register 0x09 – Channel B LOS Settings
REGISTER ADDRESS 0x09
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FAST
LOSLVL6
LOSLVL5
LOSLVL4
LOSLVL3
LOSLVL2
LOSLVL1
LOSLVL0
Table 14. Register 0x0A – Reserved
REGISTER ADDRESS 0x0A
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 15. Register 0x0B – Reserved
REGISTER ADDRESS 0x0B
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 16. Register 0x0C – Reserved
REGISTER ADDRESS 0x0C
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 17. Register 0x0D – Reserved
REGISTER ADDRESS 0x0D
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 18. Register 0x0E – Device Status
REGISTER ADDRESS 0x0E
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LOS_CHB
LOS_CHA
Table 19. Register 0x0F – Reserved
REGISTER ADDRESS 0x0F
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 20. Register Functionality
REGISTER BIT(s)
NAME
RESET
DESCRIPTION
Software Reset
FUNCTION
DEFAULT
0
7
6
Resets all registers
00000000
PWRDOWN
Powerdown
Set high to power down the device. In powerdown
mode the the current consumption about 2.5mA
5 - 2
Reserved
1
0
LOSRNG
LOS Range Select
Set to high to increase LOS detection sensitivity
CHA_TRACK
Channel A Tracking
Mode
All settings from channel A will be used for both
channels, A and B
1
7
6
5
4
3
2
1
0
7
6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INOFF
00000000
2
Channel A Input Off
Channel A Output Off
Set high to power down channel A input stages
00000000
OUTOFF
Set high to power down channel A output driver and
buffer
5
4
LOSOFF
OCOFF
Channel A LOS
Detector Off
Set high to power down channel A input signal
detector
Channel A Offset
Cancellation Off
Disables channel A offset cancellation circuit
3
2
Reserved
SQUELCH
Channel A Squelch
Mode
High activates channel A internal output squelch
function
1
0
7
6
5
4
3
2
1
0
POL
Channel A Polarity
Switch
Set to high to change polarity of channel A output
signal
DISABLE
BW3
BW2
BW1
BW0
EQ3
Channel A Output
Disable
Set to high to disable channel A output data and
keep common mode level
3
Channel A Bandwidth
Select 3 (MSB)
0000 -> highest bandwidth
1111 -> lowest bandwidth
00000000
Channel A Bandwidth
Select 2
Channel A Bandwidth
Select 1
Channel A Bandwidth
Select 0 (LSB)
Channel A EQ Filter
Stage 3 Control (MSB)
Set to high to switch off channel A EQ filter 3
Set to high to switch off channel A EQ filter 2
Set to high to switch off channel A EQ filter 1
Set to high to switch off channel A EQ filter 0
EQ2
Channel A EQ Filter
Stage 2 Control
EQ1
Channel A EQ Filter
Stage 1 Control
EQ0
Channel A EQ Filter
Stage 0 Control (LSB)
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Table 20. Register Functionality (continued)
REGISTER BIT(s)
4
NAME
DEEM3
DESCRIPTION
FUNCTION
DEFAULT
7
6
5
4
3
2
1
0
7
6
Channel A Output
0000 -> no peaking
00000000
De-emphasis 3 (MSB) 1111 -> highest peaking
DEEM2
DEEM1
DEEM0
AMP3
Channel A Output
De-emphasis 2
Channel A Output
De-emphasis 1
Channel A Output
De-emphasis 0 (LSB)
Channel A Output
Amplitude 3 (MSB)
0000 -> 225mVp-p
1111-> 1200mVp-p
approximately 60mVp-p per step
AMP2
Channel A Output
Amplitude
AMP1
Channel A Output
Amplitude 1
AMP0
Channel A Output
Amplitude 0 (LSB)
5
FAST
Channel A Fast Signal Set to high to select fast signal detection mode on
00000000
Detection Mode
channel A
LOSLVL6
Channel A LOS
Threshold Level 6
(MSB)
0000000 -> Minimum LOS assert level
1001100 -> Maximum LOS assert level
Settings out of the above range are not supported
5
4
3
2
1
0
LOSLVL5
LOSLVL4
LOSLVL3
LOSLVL2
LOSLVL1
LOSLVL0
Channel A LOS
Threshold Level 5
Channel A LOS
Threshold Level 4
Channel A LOS
Threshold Level 3
Channel A LOS
Threshold Level 2
Channel A LOS
Threshold Level 1
Channel A LOS
Threshold Level 0
(LSB)
6
7
6
INOFF
Channel B Input Off
Channel B Output Off
Set high to power down channel B input stages
00000000
OUTOFF
Set high to power down channel B output driver and
buffer
5
4
LOSOFF
OCOFF
Channel B LOS
Detector Off
Set high to power down channel B input signal
detector
Channel B Offset
Cancellation Off
Disables channel B offset cancellation circuit
3
2
Reserved
SQUELCH
Channel B Squelch
Mode
High activates channel B internal output squelch
function
1
0
POL
Channel B Polarity
Switch
Set to high to change polarity of channel B output
signal
DISABLE
Channel B Output
Disable
Set to high to disable channel B output data and
keep common mode level
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Table 20. Register Functionality (continued)
REGISTER BIT(s)
NAME
DESCRIPTION
FUNCTION
DEFAULT
7
8
9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
BW3
BW2
BW1
BW0
EQ3
EQ2
EQ1
EQ0
Channel B Bandwidth
Select 3 (MSB)
0000 -> highest bandwidth
1111 -> lowest bandwidth
00000000
Channel B Bandwidth
Select 2
Channel B Bandwidth
Select 1
Channel B Bandwidth
Select 0 (LSB)
Channel B EQ Filter
Stage 3 Control (MSB)
Set to high to switch off channel B EQ filter 3
Set to high to switch off channel B EQ filter 2
Set to high to switch off channel B EQ filter 1
Set to high to switch off channel B EQ filter 0
0000 -> no peaking
Channel B EQ Filter
Stage 2 Control
Channel B EQ Filter
Stage 1 Control
Channel B EQ Filter
Stage 0 Control (LSB)
DEEM3
DEEM2
DEEM1
DEEM0
AMP3
Channel B Output
De-emphasis 3 (MSB) 1111 -> highest peaking
00000000
Channel B Output
De-emphasis 2
Channel B Output
De-emphasis 1
Channel B Output
De-emphasis 0 (LSB)
Channel B Output
Amplitude 3 (MSB)
0000 -> 225mVp-p
1111-> 1200mVp-p
approximately 60mVp-p per step
AMP2
Channel B Output
Amplitude
AMP1
Channel B Output
Amplitude 1
AMP0
Channel B Output
Amplitude 0 (LSB)
FAST
Channel B Fast Signal Set to high to select fast signal detection mode on
Detection Mode
00000000
channel B
LOSLVL6
Channel B LOS
Threshold Level 6
(MSB)
0000000 = Minimum LOS assert level
1001100 = Maximum LOS assert level
Settings outside the above range are not supported
5
4
3
2
1
0
LOSLVL5
LOSLVL4
LOSLVL3
LOSLVL2
LOSLVL1
LOSLVL0
Channel B LOS
Threshold Level 5
Channel B LOS
Threshold Level 4
Channel B LOS
Threshold Level 3
Channel B LOS
Threshold Level 2
Channel B LOS
Threshold Level 1
Channel B LOS
Threshold Level 0
(LSB)
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Table 20. Register Functionality (continued)
REGISTER BIT(s)
NAME
Reserved
DESCRIPTION
FUNCTION
DEFAULT
10
11
12
13
14
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
00000000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LOS_CHB
LOS_CHA
00000000
00000000
00000000
00000000
LOS Channel B
LOS Channel A
Indicates LOS at input channel B
Indicates LOS at input channel A
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Table 20. Register Functionality (continued)
REGISTER BIT(s)
NAME
Reserved
DESCRIPTION
FUNCTION
DEFAULT
15
7
6
5
4
3
2
1
0
00000000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = 3.3V and TA = 25°C, VIN = 400mVp-p (signal generator output), output
swing = 600mVp-p setting, no interconnect line at the output, and with default device settings (unless otherwise
noted). Optimum input equalization level and output de-emphasis settings were used for the cable and backplane
measurements. Differential S-parameter characteristics of Spectra-Strip® SKEWCLEAR® EXD twinaxial cables
and a 40-inch N4000-13 SI™ backplane link with Amphenol XCede® backplane connectors used for the
measurements captured in this document are as shown in Figure 5.
0
-10
-20
-30
-40
-50
-60
Insertion Loss - 15m 24AWG Cable
Insertion Loss - 10m 28AWG Cable
Insertion Loss - 40in PCB Link
Return Loss - 15m 24AWG Cable
Return Loss - 10m 28AWG Cable
Return Loss - 40in PCB Link
-70
-80
-90
9
10
20
19
3
8
11
13
15 16 17 18
14
2
4
7
12
f - Frequency - GHz
0
1
5
6
Figure 5. Typical Differential S-Parameter Characteristics of Twinaxial Cable and PCB Interconnect Lines
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT 12Gbps
USING A K28.5 PATTERN
Input Interconnect: 15 meters 24AWG Twinaxial Cable
Input Interconnect: 15 meters 24AWG Twinaxial Cable
t – Time – 40 ps/div
t – Time – 500 ps/div
Input Interconnect: 10 meters 28AWG Twinaxial Cable
Input Interconnect: 10 meters 28AWG Twinaxial Cable
t – Time – 40 ps/div
t – Time – 500 ps/div
Input Interconnect: 40 inches Backplane Link
Input Interconnect: 40 inches Backplane Link
t – Time – 40 ps/div
t – Time – 500 ps/div
Figure 6. Equalizer Input and Output Signals with Different Interconnect Lines at 12Gbps
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
11.3Gbps USING A K28.5 PATTERN
Input Interconnect: 15 meters 24AWG Twinaxial Cable
Input Interconnect: 15 meters 24AWG Twinaxial Cable
t – Time – 40 ps/div
t – Time – 500 ps/div
Input Interconnect: 10 meters 28AWG Twinaxial Cable
Input Interconnect: 10 meters 28AWG Twinaxial Cable
t – Time – 40 ps/div
t – Time – 500 ps/div
Input Interconnect: 40 inches Backplane Link
Input Interconnect: 40 inches Backplane Link
t – Time – 40 ps/div
t – Time – 500 ps/div
Figure 7. Equalizer Input and Output Signals with Different Interconnect Lines at 11.3Gbps
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
10.3125Gbps USING A PRBS 231-1 PATTERN
Input Interconnect: 15 meters 24AWG Twinaxial Cable
t – Time – 40 ps/div
Input Interconnect: 10 meters 28AWG Twinaxial Cable
t – Time – 40 ps/div
Input Interconnect: 40 inches Backplane Link
t – Time – 40 ps/div
Figure 8. Equalizer Input and Output Signals with Different Interconnect Lines at 10.3125Gbps.
22
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Product Folder Link(s): TLK1102E
TLK1102E
www.ti.com ................................................................................................................................................................................................... SLLS958–MARCH 2009
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
8.5Gbps USING A K28.5 PATTERN
Input Interconnect: 15 meters 24AWG Twinaxial Cable
Input Interconnect: 15 meters 24AWG Twinaxial Cable
t – Time – 40 ps/div
t – Time – 500 ps/div
Input Interconnect: 10 meters 28AWG Twinaxial Cable
Input Interconnect: 10 meters 28AWG Twinaxial Cable
t – Time – 40 ps/div
t – Time – 500 ps/div
Input Interconnect: 40 inches Backplane Link
Input Interconnect: 40 inches Backplane Link
t – Time – 40 ps/div
t – Time – 500 ps/div
Figure 9. Equalizer Input and Output Signals with Different Interconnect Lines at 8.5Gbps.
Copyright © 2009, Texas Instruments Incorporated
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TLK1102E
SLLS958–MARCH 2009................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
RANDOM JITTER
RESIDUAL DETERMINISTIC JITTER
vs
vs
INPUT VOLTAGE (11.3Gbps, K28.5 Pattern, OC = OFF)
INPUT VOLTAGE (11.3Gbps, K28.5 Pattern, OC = OFF)
2.4
18
No Interconnect
16
14
12
10
8
2.0
1.6
1.2
0.8
0.4
0.0
15m 24AWG Twinaxial Cable
15m 24AWG Twinaxial Cable
10m 28AWG Twinaxial Cable
40-Inch Backplane Link
6
4
10m 28AWG Twinaxial Cable
2
40-Inch Backplane Link
300 600
No Interconnect
300 600
0
0
900
1200
1500
1800
0
900
1200
1500
1800
V
IN
− Input Voltage − mVpp
V
IN
− Input Voltage − mVpp
G001
G002
Figure 10.
Figure 11.
DIFFERENTIAL INPUT RETURN LOSS
DIFFERENTIAL OUTPUT RETURN LOSS
vs
vs
FREQUENCY
FREQUENCY
0
−5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−10
−15
−20
−25
−30
−35
−40
−45
−50
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
f − Frequency − GHz
f − Frequency − GHz
G003
G004
Figure 12.
Figure 13.
REGISTER 5/9 SETTING/LOSL PIN VOLTAGE
REGISTER 5/9 SETTING/LOSL PIN VOLTAGE
vs
vs
LOS THRESHOLD VOLTAGE
LOS HYSTERESIS
80
80
0.7
0.6
0.7
Assert (Pin Mode)
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2-Wire Serial I/F Mode
0.5
0.4
0.3
0.2
0.1
0.0
Assert (2-Wire
Serial I/F Mode)
Deassert (2-Wire
Serial I/F Mode)
Pin Mode
Deassert (Pin Mode)
150 200
0
50
100
250
300
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1
V
TH
− LOS Threshold Voltage − mVpp
LOS Hysteresis − dB
G005
G006
Figure 14.
Figure 15.
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Product Folder Link(s): TLK1102E
TLK1102E
www.ti.com ................................................................................................................................................................................................... SLLS958–MARCH 2009
TYPICAL CHARACTERISTICS (continued)
LOS THRESHOLD VOLTAGE/LOS HYSTERESIS
LOS THRESHOLD VOLTAGE/LOS HYSTERESIS
vs
vs
DATA RATE (V(LOSL)=700mV)
DATA RATE (V(LOSL)=OPEN)
180
160
140
120
100
80
7.0
6.5
300
250
200
150
100
50
8.5
7.5
Deassert
6.0
Deassert
5.5
6.5
5.0
Assert
Assert
5.5
4.5
3.5
2.5
4.5
4.0
60
Hysteresis
3.5
40
Hysteresis
6
20
3.0
0
2.5
14
0
0
2
4
6
8
10
12
0
2
4
8
10
12
14
Data Rate − GHz
Data Rate − GHz
G008
G007
Figure 16.
Figure 17.
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Product Folder Link(s): TLK1102E
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2009
PACKAGING INFORMATION
Orderable Device
TLK1102ERGER
TLK1102ERGET
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RGE
24
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
RGE
24
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLK1102ERGER
TLK1102ERGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.3
4.3
4.3
4.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLK1102ERGER
TLK1102ERGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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