TLK1201AIRCP [TI]
ETHERNET TRANSCEIVERS; 以太网收发器
| 型号： | TLK1201AIRCP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ETHERNET TRANSCEIVERS |
| 文件： | 总21页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
•
•
0.6-Gbps to 1.3-Gbps Serializer/Deserializer
•
•
•
•
No External Filter Capacitors Required
Comprehensive Suite of Built-In Testability
IEEE 1149.1 JTAG Support
Low Power Consumption <200 mW at 1.25
Gbps
•
LVPECL Compatible Differential I/O on High
Speed Interface
2.5-V Supply Voltage for Lowest Power
Operation
•
•
Single Monolithic PLL Design
•
•
•
3.3-V Tolerant on LVTTL Inputs
Hot Plug Protection
Support For 10-Bit Interface or Reduced
Interface 5-Bit DDR (Double Data Rate)
Clocking
64-Pin VQFP With Thermally Enhanced
Package (PowerPAD™)
•
Receiver Differential Input Thresholds 200 mV
Minimum
•
•
CPRI Data Rate Compatible (614 Mbps, 1.22
Gbps)
•
•
IEEE 802.3 Gigabit Ethernet Compliant
Industrial Temperature Range Supported:
–40°C to 85°C
ANSI X3.230-1994 (FC-PH) Fibre Channel
Compliant
•
Advanced 0.25-µm CMOS Technology
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
TD0
TD1
TD2
VDD
TD3
TD4
TD5
TD6
JTDI
48
47
46
45
44
43
42
1
2
3
4
5
6
7
8
9
SYNC/PASS
GND
RD0
RD1
RD2
VDD
41 RD3
40 RD4
39
38
37
36
35
34
33
VDD 10
TD7 11
RD5
RD6
VDD
RD7
RD8
RD9
GND
12
TD8
TD9 13
14
15
16
GND
MODESEL
PRBSEN
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DESCRIPTION
The TLK1201A/TLK1201AI gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point
data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the
IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel
standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps.
The primary application of the transceiver is to provide building blocks for point-to-point baseband data
transmission over controlled impedance media of 50 Ω or 75 Ω. The transmission media can be printed-circuit
board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer
interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over
a copper or optical media interface.
The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data
rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel
encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible
voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data,
outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and
falling edges of the reference clock. The data is clocked most significant bit first (bits 0–4 of the 8b/10b encoded
data) on the rising edge of the clock and the least significant bits (bits 5–9 of the 8b/10b encoded data) are
clocked on the falling edge of the clock.
The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and
pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also
supported.
The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of
the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is
an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is
recommended that the device PowerPAD be soldered to the thermal land on the board.
The transceiver is characterized for operation from 0°C to 70°C (TLK1201A) or –40°C to 85°C (TLK1201AI).
The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very
power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.
The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output
signal terminals, TXP, and TXN to be held in a high-impedance state.
Differences Between TLK1201A/TLK1201AI and TNETE2201
The TLK1201A/TLK1201AI transceiver is the functional equivalent of the TNETE2201. There are several
differences between the devices as noted below. See Figure 12 in the Application Information section for an
example of a typical application circuit.
•
•
The VCC is 2.5 V for the TLK1201A vs 3.3 V for TNETE2201.
The PLL filter capacitors on terminals 16, 17, 48, and 49 of the TNETE2201 are no longer required. The
TLK1201A uses these terminals to provide added test capabilities. The capacitors, if present, do not affect
the operation of the device.
•
No pulldown resistors are required on the TXP/TXN outputs.
AVAILABLE OPTIONS
PACKAGE
TA
PLASTIC QUAD FLAT PACK (RCP)
0°C to 70°C
TLK1201ARCP
TLK1201AIRCP
–40°C to 85°C
2
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
BLOCK DIAGRAM
PRBSEN
LOOPEN
PRBS
Generator
TXP
TXN
2:1
MUX
Parallel to
Serial
10 Bit
Registers
TD(0-9)
Clock
Phase Generator
REFCLK
MODESEL
ENABLE
TESTEN
Control
Logic
Clock
2:1
MUX
Interpolator
and
Clock Extraction
PRBS
Verification
RBC1
RBC0
Clock
SYNC/PASS
Serial to Parallel
and
Comma Detect
2:1
MUX
Data
RD(0-9)
RXP
RXN
SYNCEN
LOS
RBCMODE
JTMS
JTAG
Control
Register
JTDO
JTRSTN
JTDI
TCK
Terminal Functions
TERMINAL
NAME
SIGNAL
I/O
DESCRIPTION
NO.
MODESEL
15
26
I
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR
interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode
is selected. The default mode is the TBI.
P/D(1)
LOS
O
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal.
If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined.
If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal.
RBCMODE
32
I
Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output
on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is
output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full
baud-rate clock is output on RBC0 and RBC1 is held low.
P/D(1)
RBC0
RBC1
31
30
O
Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit
output data on RD0–RD9. The operation of these clocks is dependent upon the receive clock
mode selected.
In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and
RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is
aligned to the rising edge.
In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned
on both the rising and falling edges.
(1) P/D = Internal pulldown
3
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
RD0–RD9
45, 44,
43, 41,
40, 39,
38, 36,
35, 34
O
Receive data. When in TBI mode (MODESEL = low), these outputs carry 10-bit parallel data
output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and
RBC1, depending on the receive clock mode selected. RD0 is the first bit received.When in the
DDR mode (MODESEL = high), only RD0–RD4 are valid. RD5–RD9 are held low. The 5-bit
parallel data is clocked out of the transceiver on the rising edge of RBC0.
REFCLK
22
I
Reference clock. REFCLK is an external input clock that synchronizes the receiver and
transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input
data (TD0–TD9) for serialization.In the TBI mode that data is registered on the rising edge of
REFCLK.
In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the
most significant bits aligned on the rising edge of REFCLK.
RXP
RXN
54
52
PECL I
Differential input receive. RXP and RXN together are the differential serial input interface from a
copper or an optical I/F module.
SYNCEN
24
I
Synchronous function enable. When SYNCEN is high, the internal synchronization function is
activated. When this function is activated, the transceiver detects the K28.5 comma character
(0011111 negative beginning disparity) in the serial data stream and realigns data on byte
boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9.
P/U(2)
SYNC/PASS
TD0–TD9
47
O
I
Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in
the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In
PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS test results
(high = pass).
2-4, 6-9,
11-13
Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data
output from a protocol device to the transceiver for serialization and transmission. This 10-bit
parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a
serial stream with TD0 sent as the first bit.
When in the DDR mode (MODESEL = high) only TD0–TD4 are valid. The 5-bit parallel data is
clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial
stream with TD0 sent as the first bit.
TXP
TXN
62
61
PECL
O
Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper
or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high
and are active when LOOPEN is low.
TEST
ENABLE
28
48
I
When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP, and
TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally.
P/U(3)
JTDI
I
Test data input. IEEE1149.1 (JTAG)
P/U(3)
JTDO
JTMS
27
55
O
Test data output. IEEE1149.1 (JTAG)
Test mode select. IEEE1149.1 (JTAG)
I
P/U(3)
JTRSTN
LOOPEN
56
19
I
Reset signal. IEEE1149.1 (JTAG)
P/U(3)
I
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
P/D(4)
PRBSEN
16
I
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
P/D(4)
TCK
49
17
I
Test clock. IEEE1149.1 (JTAG)
Manufacturing test terminal
TESTEN
I
P/D(4)
(2) P/U = Internal pullup
(3) P/U = Internal pullup
(4) P/D = Internal pulldown
4
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
POWER
NO.
VDD
5, 10,
20, 23,
29, 37,
42, 50,
63
Supply
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
VDDA
53, 57,
59, 60
Supply
Supply
Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter
PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
VDDPLL
GROUND
GND
18
1, 14,
21,25,
33, 46
Ground
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
GNDA
51, 58
64
Ground
Ground
Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX.
PLL ground. Provides a ground for the PLL circuitry.
GNDPLL
DETAILED DESCRIPTION
Data Transmission
This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking.
When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0–TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bits 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0–TD4. In this mode, data
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and
sent to the serializer. The rising edge REFCLK clocks in bits 0–4, and the falling edge of REFCLK clocks in bits
5–9. Bit 0 is the first bit transmitted.
Transmission Latency
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit
9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The
minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times.
Measured 10-Bits
Next 10-Bit Code
TXP, TXN
b7 b8 b9 b0 b1 b2 b3
t
d(Tx latency)
10-Bit Code
TD(0−9)
REFCLK
Figure 1. Transmitter Latency Full Rate Mode
5
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
DETAILED DESCRIPTION (continued)
Data Reception
The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated
clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and
presented to the protocol controller along with receive byte clocks (RBC0 and RBC1).
Receiver Clock Select Mode
There are two modes of operation for the parallel bus: 1) the 10-bit (TBI) mode and 2) 5-bit (DDR) mode. When
in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: 1)
full-rate clock on RBC0 and 2) half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate
clock is available on RBC0; see Table 1.
Table 1. Mode Selection
RECEIVE BYTE CLOCK
MODESEL RBCMODE
MODE
TLK1201A
TBI half-rate 30–65 MHz
TLK1201AI
0
0
1
1
0
1
0
1
30–65 MHz
TBI full-rate 60–130 MHz 60–130 MHz
DDR
DDR
60–130 MHz 60–130 MHz
60–130 MHz 60–130 MHz
In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at
one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is
output with respect to the two receive byte clocks (RBC0 and RBC1) allowing a protocol device to clock the
parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received
data is valid on the rising edge of RBC1. See the timing diagram shown in Figure 2.
t
d(S)
RBC0
RBC1
SYNC
t
d(S)
t
d(H)
t
d(H)
RD(0-9)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 2. Synchronous Timing Characteristics Waveforms (TBI Half-Rate Mode)
In the normal-rate mode, only RBC0 is used and operates at full data rate (that is, 1.25-Gbps data rate produces
a 125-MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this
mode. See the timing diagram shown in Figure 3.
RBC0
t
t
d(H)
d(S)
SYNC
RD(0-9)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 3. Synchronous Timing Characteristics Waveforms (TBI Full-Rate Mode)
6
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1
is low impedance. The data is clocked bit 0 first, and aligned to the rising edge of RBC0. See the timing diagram
shown in Figure 4.
t
d(S)
RBC0
t
d(S)
t
d(H)
t
d(H)
SYNC
RD(0-4)
K28.5
K28.5 DXX.X DXX.X DXX.X DXX.X DXX.X DXX.X K28.5 K28.5 DXX.X
Bits 0-4 Bits 5-9
Figure 4. Synchronous Timing Characteristics Waveforms (DDR Mode)
The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The
received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, ±0.02% (200
PPM) for proper operation (see the recommended operating tables).
Receiver Word Alignment
This device uses the IEEE 802.3 gigabit ethernet defined 10-bit K28.5 character (comma character) word
alignment scheme. The following sections explain how this scheme works and how it realigns itself.
Comma Character on Expected Boundary
This device provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is
enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial
input data to the 7-bit synchronization pattern. The K28.5 character is defined by 8-bit/10-bit coding scheme as a
pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs (0011111),
referred to as the comma character. The K28.5 character was implemented specifically for aligning data words.
As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly
aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0, RBC1, SYNC,
and RD0–RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1.)
Comma Character Not on Expected Boundary
If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word
realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the
misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure 5. The
RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design,
the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when the K28.5 is
aligned to the falling edge of RBC1 instead of the rising edge. Figure 5 shows the timing characteristics of the
data realignment.
7
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
31 Bit
Times
30 Bit
Times (Max)
Max Receive
Path Latency
K28.5
DXX.X
K28.5
DXX.X
DXX.X
K28.5
DXX.X
DXX.X
INPUT DATA
RBC0
RBC1
Worst Case
Misaligned K28.5
Corrupt Data
DXX.X
Misalignment Corrected
DXX.X
RD(0-9)
SYNC
DXX.X
DXX.X
K28.5
DXX.X
K28.5
DXX.X
K28.5
DXX.X
Figure 5. Word Realignment Timing Characteristics Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the
SYNC pulse is present for the entire RBC0 period.
Data Reception Latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times, and the
maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is 34
bit times.
10-Bit Code
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
RXP, RXN
t
d(Rx latency)
RD(0−9)
RBC0
10-Bit Code
Figure 6. Receiver Latency - TBI Normal Mode Shown
Loss of Signal Detection
This device has a loss-of-signal (LOS) detection circuit for conditions where the incoming signal no longer has
sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of gross
signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal
coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV. The
LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.
8
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
www.ti.com
SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
Testability
The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also
allows for a BIST (built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal
TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for
factory testing, and is not intended for end-user control.
Loopback Testing
The transceiver can provide a self-test function by enabling (setting LOOPEN to high level) the internal loopback
path. Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel
data output can be compared to the parallel input data for functional verification. The external differential output
is held in a high-impedance state during the loopback testing.
Enable Function
When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an
ultralow-power idle state when the link is not active.
PRBS Function
This device has a built-in 27–1 PRBS function. When the PRBSEN control bit is set high, the PRBS test is
enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel
input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if
it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester (BERT) or to
the receiver of another TLK1201AI. Since the PRBS is not really random and is really a predetermined sequence
of 1s and 0s, the data can be captured and checked for errors by a BERT. This device also has a built-in BERT
function on the receiver side that is enabled by PRBSEN. It can receive a PRBS pattern and check for errors,
and then reports the errors by forcing the SYNC/PASS terminal low. The PRBS testing supports two modes
(normal and latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the PRBS
bit error rate test is passed to the SYNC/PASS terminal. When SYNCEN is high the result of the PRBS
verification is latched on the SYNC/PASS output (that is, a single failure forces SYNC/PASS to remain low).
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
TLK1201A/TLK1201AI
(2)
Supply voltage, VDD (see
)
–0.3 V to 3 V
–0.5 V to 4 V
Input voltage range at TTL terminals, VI
Input voltage range at any other terminal
Storage temperature, Tstg
–0.3 V to VDD +0.3 V
–65°C to 150°C
Electrostatic discharge
CDM: 1 kV, HBM:2 kV
0°C to 70°C
TLK1201A
TLK1201AI
Characterized free-air operating temperature range
–40°C to 85°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
9
TLK1201ARCP, TLK1201AIRCP
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DISSIPATION RATING TABLE
TA≤ 25°C
PACKAGE
OPERATING FACTOR(1)
TA = 70°C
POWER RATING
POWER RATING
ABOVE TA = 25°C
RCP64(2)
RCP64(3)
RCP64(4)
5.25 W
3.17 W
2.01 W
46.58 mW/°C
23.70 mW/°C
13.19 mW/°C
2.89 W
1.74 W
1.11 W
(1) This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA).
(2) 2 oz. Trace and copper pad with solder
(3) 2 oz. Trace and copper pad without solder
(4) Standard JEDEC high-K board
Thermal Characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Board-mounted, no air flow, high conductivity TI rec-
ommended test board, chip soldered or greased to thermal
land
21.47
Junction-to-free-air thermal re-
sistance
RΘJA
Board-mounted, no air flow, high conductivity TI rec-
ommended test board with thermal land but no solder or
grease thermal connection to thermal land
°C/W
42.2
75.83
0.38
Board-mounted, no air flow, JEDEC test board
Board-mounted, no air flow, high conductivity TI rec-
ommended test board, chip soldered or greased to thermal
land
Junction-to-case-thermal resist-
ance
RΘJC
Board-mounted, no air flow, high conductivity TI rec-
ommended test board with thermal land but no solder or
grease thermal connection to thermal land
°C/W
0.38
7.8
Board-mounted, no air flow, JEDEC test board
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, VDD, VDD(A)
2.3
2.5
2.7
90
V
Total supply current, IDD, IDD(A)
Frequency = 1.25 Gbps, PRBS pattern
mA
mW
mW
µA
Frequency = 1.25 Gbps, PRBS pattern
Frequency = 1.25 Gbps, worst case(1)
Enable = 0, VDD(A), VDD = 2.7 V
VDD, VDD(A) = 2.5 V, EN↑ to PLL acquire
TLK1201A
250
Total power dissipation, PD
245
50
Total shutdown current, IDD, IDD(A)
Startup lock time, PLL
500
70
µs
0
Operating free-air temperature, TA
°C
TLK1201AI
-40
85
(1) The worst case pattern is a pattern that creates a maximum transition density on the serial transceiver.
REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLK1201A
MIN
TYP–0.01%
TYP–0.01%
TYP–0.01%
100
TYP
MAX UNIT
60
60
TYP+0.01%
TYP+0.01%
TYP+0.01%
100
Frequency
Minimum data rate
Maximum data rate
TLK1201AI
MHz
ppm
ps
Frequency
Accuracy
Duty cycle
Jitter
130
40%
50%
60%
Random plus deterministic
40
10
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TTL ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
High-level Input current
Low-level Input current
Input capacitance
TEST CONDITIONS
MIN
VDD–0.2
GND
TYP
2.3
MAX UNIT
VOH
VOL
VIH
VIL
IIH
IOH= –400 µA
IOL= 1 mA
V
0.25
0.5
3.6
0.8
40
V
V
1.7
V
VDD= 2.3 V, VIN = 2 V
VDD= 2.3 V, VIN = 0.4 V
µA
µA
pF
IIL
–40
CIN
4
11
TLK1201ARCP, TLK1201AIRCP
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TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
600
800
TYP
MAX UNIT(1)
Rt = 50Ω
850
1100
1200
VOD = |TxD-TxN|
mV
mV
Rt = 75 Ω
Rt = 50Ω
Rt = 75 Ω
1050
V(cm)
Transmit common mode voltage range
1100
200
1250
1250
1400
Receiver input voltage requirement,
VID = |RxP - RxN|
1600
2250
mV
mV
Receiver common mode voltage range, (RxP
+ RxN)/2
1000
-350
Ilkg(R)
CI
Receiver input leakage current
Receiver input capacitance
350
2
µA
pF
Differential output jitter, Random +
deterministic, PRBS pattern,
Rω = 125 MHz
0.24
0.2
UI
UI
t(TJ)
Serial data total jitter (peak-to-peak)
Differential output jitter, Random +
deterministic, PRBS pattern,
Rω = 106.25 MHz
Differential output jitter, PRBS pattern,
Rω = 125 MHz
t(DJ)
tr, tf
Serial data deterministic jitter (peak-to-peak)
Differential signal rise, fall time (20% to 80%)
0.10
250
UI
ps
UI
RL = 50 Ω, CL = 5 pF, See NoLabel
and NoLabel
100
Differential input jitter, Random +
deterministic, Rω = 125 MHz
0.25
Serial data jitter tolerance minimum required
eye opening, (per IEEE-802.3 specification)
Differential input jitter, random +
determinisitc, PRBS pattern at zero
crossing
0.3
UI
µs
Receiver data acquisition lock time from
powerup
500
Data relock time from loss of synchronization
1024 Bit times
TBI modes
See Figure 1
See Figure 6
19
29
20
27
24
27
25
27
20
UI
30
td(Txlatency)
Tx latency
DDR mode
TBI modes
DDR mode
31
34
TBI mode
600–620 Mbps
600–620 Mbps
1228.8 Mbps
1228.8 Mbps
28
UI
31
td(Rxlatency)
Rx latency
DDR mode
TBI mode
29
33
DDR mode
(1) UI = serial bit time
V
80%
50%
TX+
20%
V
t
f
t
r
V
80%
50%
TX−
V
20%
t
f
t
r
1V
80%
20%
0 V
VOD
−1V
Figure 7. Differential and Common-Mode Output Voltage Definitions
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SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
C
5 pF
L
50 Ω
50 Ω
C
L
5 pF
Figure 8. Transmitter Test Setup
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Clock rise time
TEST CONDITIONS
MIN
0.3
0.3
0.3
0.3
TYP
MAX UNIT
tr(RBC)
1.5
ns
tf(RBC)
Clock fall time
Data rise time
Data fall time
1.5
80% to 20% output voltage, C = 5 pF (see
Figure 9)
tr
tf
1.5
ns
1.5
Data setup time (RD0–RD9), Data
valid prior to RBC0 rising
tsu(D1)
th(D1)
TBI normal mode, (see Figure 3)
TBI normal mode, (see Figure 3)
2.5
2
ns
ns
Data hold time (RD0–RD9), Data valid
after RBC0 rising
tsu(D2)
th(D2)
tsu(D3)
th(D3)
Data setup time (RD0–RD4)
Data hold time (RD0–RD4)
Data setup time (RD0–RD9)
Data hold time (RD0–RD9)
DDR mode, Rω = 125 MHz, (see Figure 4)
DDR mode, Rω = 125 MHz, (see Figure 4)
TBI half-rate mode, Rω = 125 MHz, (see Figure 2)
TBI half-rate mode, Rω = 125 MHz, (see Figure 2)
2
0.8
2.5
1.5
ns
ns
ns
ns
1.4 V
CLOCK
DATA
t
t
r
f
2 V
80%
50%
20%
0.8 V
t
f
t
r
Figure 9. TTL Data I/O Valid Levels for AC Measurement
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.6
0.8
0.7
0.5
TYP
MAX
UNIT
tsu(D4)
th(D4)
tsu(D5)
th(D5)
tr, tf
Data setup time (TD0–TD9)
Data hold time (TD0–TD9)
Data setup time (TD0–TD9)
Data hold time (TD0–TD9)
TD[0,9] data rise and fall time
TBI modes
ns
DDR modes
See Figure 9
ns
ns
2
13
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SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
APPLICATION INFORMATION
8B/10B TRANSMISSION CODE
The PCS maps GMII signals into 10-bit code groups and vice versa, using an 8b/10b block coding scheme. The
PCS uses the transmission code to improve the transmission characteristics of information to be transferred
across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in
the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the
likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of
information. The 8b/10b transmission code specified for use has a high-transition density, is run length limited,
and is dc-balanced. The transition density of the 8b/10b symbols range from 3 to 8 transitions per symbol. The
definition of the 8b/10b transmission code is specified in IEEE 802.3 gigabit ethernet and ANSI X3.230-1994
(FC-PH), clause 11.
The 8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit
notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the description of the 8b/10b
transmission code-groups, where A is the LSB. Each valid code group has been given a name using the
following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups,
where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K<HGF.EDCBA>).
Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as 111
11110.
V
DD
5 kΩ
TXP
Z
O
RXP
7.5 kΩ
Z
Z
O
GND
VDD
+
_
O
5 kΩ
Z
O
TXN
RXN
7.5 kΩ
GND
Receiver
Transmitter
Media
Figure 10. High-Speed I/O Directly-Coupled Mode
14
TLK1201ARCP, TLK1201AIRCP
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SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
APPLICATION INFORMATION (continued)
V
DD
5 kΩ
TXP
Z
O
RXP
7.5 kΩ
Z
Z
O
GND
VDD
+
_
O
5 kΩ
Z
O
TXN
RXN
7.5 kΩ
GND
Receiver
Transmitter
Media
Figure 11. High-Speed I/O AC-Coupled Mode
15
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
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SLLS580A–FEBRUARY 2004–REVISED JUNE 2004
APPLICATION INFORMATION (continued)
5 Ω at 100 MHz
0.01 µF
2.5 V
2.5 V
18
VDD VDDA
VDDPLL
64
GND
GNDPLL
GNDA
TLK1201AI
TLK1201AII
17
22
TESTEN
10
Controlled Impedance
Transmission Line
62
61
TD0-TD9
REFCLK
PRBSEN
TXP
TXN
16
19
LOOPEN
SYNCEN
24
47
Controlled Impedance
Transmission Line
Host
Protocol
Device
SYNC/PASS
RD0-RD9
10
2
RBC0-RBC1
ENABLE
28
Controlled Impedance
Transmission Line
54
RXP
26
32
LOS
50 Ω
50 Ω
R
t
RBCMODE
MODESEL
TCK
15
49
55
48
56
R
t
Controlled Impedance
Transmission Line
52
RXN
JTMS
JTAG
Controller
JTDI
JTRSTN
JTDO
27
Figure 12. Typical Application Circuit (AC mode)
DESIGNING WITH PowerPAD
The TLK1201A/TLK1201AI is housed in a high-performance, thermally enhanced, 64-pin VQFP (RCP64)
PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note
that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical
conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly
techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches
or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The
recommended convention, however, is to not run any etches or signal vias under the device, but to have only a
grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the
minimum size required for the keepout area for the 64-pin PFP PowerPAD package is 8 mm × 8 mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the
PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB
construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not
contain numerous thermal vias depending on PCB construction.
16
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APPLICATION INFORMATION (continued)
Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD
Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages
beginning at URL: http://www.ti.com.
Figure 13. Example of a Thermal Land
For the TLK1201AI, this thermal land must be grounded to the low-impedance ground plane of the device. This
improves not only thermal performance but also the electrical grounding of the device. It is also recommended
that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size
must be as large as possible without shorting device signal terminals. The thermal land may be soldered to the
exposed PowerPAD using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is
recommended that the thermal land be connected to the low-impedance ground plane for the device. More
information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.
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MECHANICAL DATA
RCP (S-PQFP-G84)
PowerPAD™ PLASTIC QUAD FLATPACK
0,27
M
0,08
0,50
48
0,17
33
49
32
Thermal Pad
(See Note D)
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,15
0,05
0° - 7°
11,80
0,85
0,75
0,75
0,45
Seating Plane
0,08
1,00 MAX
4147711/A 10/98
A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This
pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
#IMPLIED. Dummy target for KhKIz262casm
#IMPLIED. Dummy target for BhKIz1f4casm
18
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLK1201AIRCP
TLK1201AIRCPR
TLK1201ARCP
TLK1201ARCPR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HVQFP
HVQFP
HVQFP
HVQFP
RCP
64
64
64
64
160
1000
160
None
None
None
None
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
RCP
RCP
RCP
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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