TLV0832IPE4 [TI]

2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, GREEN, PLASTIC, DIP-8;


型号：	TLV0832IPE4
厂家：	TEXAS INSTRUMENTS
描述：	2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, GREEN, PLASTIC, DIP-8 光电二极管转换器
文件：	总20页 (文件大小：685K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLAS148 − SEPTEMBER 1996

8-Bit Resolution

2.7 V to 3.6 V V

TLV0831 . . . D OR P PACKAGE

(TOP VIEW)

Easy Microprocessor Interface or

Standalone Operation

IN+

CLK

Operates Ratiometrically or With V

Reference

IN−

GND

REF

Single Channel or Multiplexed Twin

Channels With Single-Ended or Differential

Input Options

TLV0832 . . . D OR P PACKAGE

(TOP VIEW)

Input Range 0 V to V

With V

Reference

Inputs and Outputs Are Compatible With

TTL and MOS

CH0

CH1

GND

/REF

CLK

Conversion Time of 32 µs at

= 250 kHz

(CLK)

Designed to Be Functionally Equivalent to

the National Semiconductor ADC0831 and

ADC0832 at 3 V Supply

Total Unadjusted Error . . . 1 LSB

description

These devices are 8-bit successive-approximation analog-to-digital converters. The TLV0831 has single input

channels; the TLV0832 has multiplexed twin input channels. The serial output is configured to interface with

standard shift registers or microprocessors.

The TLV0832 multiplexer is software configured for single-ended or differential inputs. The differential analog

voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the

voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of

resolution.

The operation of the TLV0831 and TLV0832 devices is very similar to the more complex TLV0834 and TLV0838

devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input

signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to V

internally on the TLV0832).

(done

The TLV0831C and TLV0832C are characterized for operation from 0°C to 70°C. The TLV0831I and TLV0832I

are characterized for operation from −40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(D)

PLASTIC DIP

(P)

0°C to 70°C

TLV0831CD

TLV0831ID

TLV0832CD

TLV0832ID

TLV0831CP

TLV0831IP

TLV0832CP

TLV0832IP

−40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

functional block diagram

Start

Flip-Flop

CLK

Shift Register

ODD/EVEN

(TLV0832

Start

CLK

only)

To Internal

Circuits

CLK

SGL/DIF

CH0/IN+

CH1/IN−

Analog

MUX

Comparator

Time

Delay

CLK

SAR

Logic

and

Ladder

and

Decoder

EOC

REF

9-Bit

Shift

Bits 0−7

(TLV0831

only)

Bit 1

LSB

Latch

MSB

First

One

Shot

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

functional description

The TLV0831 and TLV0832 use a sample-data-comparator structure that converts differential analog inputs by

a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is

compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be

assigned a positive (+) or negative (−) polarity. The TLV0831 contains only one differential input channel with

fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,

between IN+ and IN−, to the TLV0831 or can be applied to IN+ with IN− grounded as a single ended input. When

the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the

converter output is all zeros.

Channel selection and input configuration are under software control using a serial-data link from the controlling

processor. A serial-communication format allows more functions to be included in a converter package with no

increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter

at the analog sensor and communicating serially with the controlling processor. This process returns noise-free

digital data to the processor.

A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete

conversion process. A clock input is then received from the processor. An interval of one clock period is

automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance

state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares

successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates

whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,

conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock

periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the

output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low

transition followed by address information.

A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer

address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog

inputs to be enabled and determines whether the input is single ended or differential. When the input is

differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity

may also be selected. Either channel of the channel pair may be designated as the negative or positive input.

On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift

TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are

shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,

the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register

is disabled for the duration of the conversion.

The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO

terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This

is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the

high-impedance state.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

sequence of operation

TLV0831

CLK

conv

MSB-First Data

MUX

Settling Time

Hi-Z

MSB

LSB

TLV0832

CLK

conv

+Sign Bit

Start

Bit

ODD

SGL

(TLV0832

only)

Don’t Care

DIF EVEN

MUX

MSB-First Data

LSB-First Data

Settling Time

Hi-Z

MSB

LSB

MSB

TLV0832 MUX-ADDRESS CONTROL LOGIC TABLE

MUX ADDRESS

ODD/EVEN

CHANNEL NUMBER

CH0

CH1

SGL/DIF

−

H = high level, L = low level,

− or + = terminal polarity for the selected input channel

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

absolute maximum ratings over recommended operating free-air temperature range (unless

†

otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V

Input voltage range, V : Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

+ 0.3 V

Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package . . . . . . . . . . . . . . . . . . . . . 260°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

(see clock operating conditions)

2.7

3.3

3.6

High-level input voltage, V

Low-level input voltage, V

0.8

250

600

60%

= 2.7 V

= 3.3 V

kHz

Clock frequency, f

(CLK)

40%

220

350

Clock duty cycle (see Note 2)

Pulse duration, CS high, t

wH(CS)

Setup time, CS low or TLV0832 data valid before CLK↑, t

Hold time, TLV0832 data valid after CLK↑, t

C suffix

Operating free-air temperature, T

°C

I suffix

−40

NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the

recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

electrical characteristics over recommended range of operating free-air temperature, V

(CLK)

= 3.3 V,

= 250 kHz (unless otherwise noted)

digital section

C SUFFIX

I SUFFIX

†

TEST CONDITIONS

PARAMETER

UNIT

‡

TYP

‡

TYP

MIN

2.8

MAX

MIN

2.4

MAX

= 3 V,

= −360 µA

= −10 µA

= 1.6 mA

High-level output voltage

2.9

2.8

Low-level output voltage

High-level input current

Low-level input current

0.34

0.4

= 3.6 V

= 0

0.005

µA

−0.005

−1

−0.005

−1

High-level output

(source) current

At V

, DO= 0 V,

= 25°C

−6.5

−15

−6.5

−15

Low-level output (sink) current At V , DO= 0 V,

= 25°C

−16

0.01

−0.01

−16

0.01

−0.01

= 3.3 V,

= 0,

High-impedance-state output

current (DO)

µA

−3

Input capacitance

Output capacitance

†

‡

All parameters are measured under open-loop conditions with zero common-mode input voltage.

All typical values are at V = 3.3 V, T = 25°C.

analog and converter section

†

‡

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

−0.05

Common-mode input voltage

See Note 3

+0.05

On channel

Off channel

On channel

Off channel

V = 3.3 V

−1

V = 0

Standby input current (see Note 4)

Input resistance to REF

µA

kΩ

I(stdby)

V = 0

V = 3.3 V

1.3

2.4

5.9

i(REF)

†

‡

All parameters are measured under open-loop conditions with zero common-mode input voltage.

All typical values are at V = 3.3 V, T = 25°C.

NOTES: 3. When channel IN− is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two

on-chip diodes that conduct forward current for analog input voltages one diode drop above V . Care must be taken during testing

levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode

to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply

at low V

voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum V

3.25 V for all variations of temperature and load.

4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is

in a high or low steady-state conditions.

total device

‡

PARAMETER

MIN

TYP

MAX

0.75

2.5

UNIT

TLV0831

TLV0832

0.2

1.5

Supply current

‡

All typical values are at V

= 3.3 V, T = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

operating characteristics V

otherwise noted)

= V = 3.3 V, f

= 250 kHz, t = t = 20 ns, T = 25°C (unless

ref

(CLK) r f A

†

PARAMETER

Supply-voltage variation error

MIN

TYP

MAX

UNIT

TEST CONDITIONS

= 3 V to 3.6 V

= 3.3 V,

1/16

1/4

LSB

ref

Total unadjusted error (see Note 5)

Common-mode error

LSB

= MIN to MAX

Differential mode

1/16

200

1/4

Propagation delay time,

output data after CLK↑

(see Note 6)

MSB-first data

LSB-first data

500

= 100 pF

200

= 10 pF,

R = 10 kΩ

125

250

Output disable time, DO after CS↑

dis

= 100 pF,

R = 2 kΩ

Conversion time (multiplexer-addressing

time not included)

clock

periods

conv

†

All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the

appropriate value specified under recommended operating conditions.

NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.

6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response

time. LSB-first data applies only to TLV0832.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

PARAMETER MEASUREMENT INFORMATION

CLK

50%

GND

CLK

50%

GND

0.4 V

2 V

GND

50%

2 V

0.4 V

Figure 2. Data-Output Timing

GND

Figure 1. TLV0832 Data-Input Timing

Test

Point

From Output

Under Test

(see Note A)

LOAD CIRCUIT

90%

10%

50%

10%

GND

dis

S1 closed

S2 open

90%

S1 open

S2 closed

Output

10%

Output

GND

VOLTAGE WAVEFORMS

NOTE A: C includes probe and jig capacitance.

VOLTAGE WAVEFORMS

Figure 3. Output Disable Time Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

TYPICAL CHARACTERISTICS

UNADJUSTED OFFSET ERROR

LINEARITY ERROR

REFERENCE VOLTAGE

1.5

= 3.3 V

= 250 kHz

I+

= V = 0 V

I−

(CLK)

= 25°C

1.25

1.0

0.75

0.5

0.25

0.01

0.1

1.0

ref

− Reference Voltage − V

ref −

Reference Voltage − V

Figure 4

Figure 5

LINEARITY ERROR

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

0.5

0.45

0.4

2.0

1.8

1.6

1.4

1.2

= 3.3 V

ref

= 3.3 V

= 250 kHz

ref

(CLK)

85°C

0.35

0.3

0.8

0.6

0.4

25°C

−40°C

0.2

0.25

−50

−25

100

100 200 300 400 500 600 700 800

− Free-Air Tempertature − °C

− Clock Frequency − kHz

(CLK)

Figure 6

Figure 7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

TYPICAL CHARACTERISTICS

TLV0831

SUPPLY CURRENT

FREE-AIR TEMPERATURE

CLOCK FREQUENCY

0.3

0.5

0.4

= 250 kHz

= 3.3 V

(CLK)

CS = High

= 25°C

= 3.6 V

= 3.3 V

= 3 V

0.3

0.2

0.1

−50

−25

100

200

300

400

500

− Free-Air Temperature — °C

− Clock Frequency − kHz

(CLK)

Figure 8

Figure 9

OUTPUT CURRENT

FREE-AIR TEMPERATURE

16.5

= 3.3 V

15.5

OL (DO = 3.3 V)

−I

OH (DO = 0 V)

−I

OH (DO = 2.4 V)

14.5

OL (DO = 0.4 V)

−50

−25

100

− Free-Air Temperature − °C

Figure 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLAS148 − SEPTEMBER 1996

TYPICAL CHARACTERISTICS

0.5

= 3.3 V

ref

= 25°C

−0.5

−1

= 250 kHz

(CLK)

= 3.3 V

128

160

192

224

256

Output Code

Figure 11. Differential Nonlinearity With Output Code

= 3.3 V

ref

= 25°C

= 250 kHz

0.5

(CLK)

= 3.3 V

−0.5

−1

128

160

192

224

256

Output Code

Figure 12. Integral Nonlinearity With Output Code

= 3.3 V

ref

= 25°C

0.5

= 250 kHz

(CLK)

= 3.3 V

−0.5

−1

128

160

192

224

256

Output Code

Figure 13. Total Unadjusted Error With Output Code

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

TLV0831CD

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

V0831C

TLV0831CDG4

TLV0831CDR

TLV0831CDRG4

TLV0831CP

ACTIVE

Green (RoHS

& no Sb/Br)

V0831C

2500

Green (RoHS

& no Sb/Br)

V0831C

Green (RoHS

& no Sb/Br)

V0831C

Green (RoHS

& no Sb/Br)

TLV0831CP

V0831I

TLV0831CPE4

TLV0831ID

Green (RoHS

& no Sb/Br)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

TLV0831IDG4

TLV0831IDR

TLV0831IDRG4

TLV0831IP

Green (RoHS

& no Sb/Br)

V0831I

2500

Green (RoHS

& no Sb/Br)

V0831I

Green (RoHS

& no Sb/Br)

V0831I

Green (RoHS

& no Sb/Br)

TLV0831IP

V0832C

TLV0831IPE4

TLV0832CD

Green (RoHS

& no Sb/Br)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

TLV0832CDG4

TLV0832CDR

TLV0832CDRG4

TLV0832CP

Green (RoHS

& no Sb/Br)

V0832C

2500

Green (RoHS

& no Sb/Br)

V0832C

Green (RoHS

& no Sb/Br)

V0832C

Green (RoHS

& no Sb/Br)

TLV0832CP

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

TLV0832CPE4

TLV0832ID

ACTIVE

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

N / A for Pkg Type

Level-1-260C-UNLIM

N / A for Pkg Type

TLV0832CP

Green (RoHS

& no Sb/Br)

V0832I

TLV0832IDG4

TLV0832IDR

TLV0832IDRG4

TLV0832IP

Green (RoHS

& no Sb/Br)

V0832I

2500

Green (RoHS

& no Sb/Br)

V0832I

Green (RoHS

& no Sb/Br)

V0832I

Green (RoHS

& no Sb/Br)

TLV0832IP

TLV0832IPE4

Green (RoHS

& no Sb/Br)

N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV0831CDR

TLV0831IDR

TLV0832CDR

TLV0832IDR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV0831CDR

TLV0831IDR

TLV0832CDR

TLV0832IDR

SOIC

2500

367.0

35.0

Pack Materials-Page 2

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TLV0832IPE4 [TI]

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TLV0834CPWG4

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