TLV1562_14 [TI]
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN;
| 型号： | TLV1562_14 |
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| 描述： | 2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN 输入元件 |
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
2 MSPS Max Throughput at 10 Bit (Single
Channel), ±1 LSB DNL, ±1 LSB INL MAX
Built-In Internal/System Mid-Scale Error
Calibration
3 MSPS Max Throughput at 8 Bit (Single
Channel), ±1 LSB DNL, ±1 LSB INL MAX
Built-In Mux With 2 Differential or 4
Single-Ended Input Channels
7 MSPS Max Throughput at 4 Bit (Single
Channel), ±0.4 LSB DNL, ±0.4 LSB INL MAX
Low Input Capacitance (10 pF Max Fixed,
1 pF Max Switching)
No Missing Code for External Clock Up to
15 MHz at 5.5 V, 12 MHz at 2.7 V
DSP/µ P-Compatible Parallel Interface
applications
ENOB 9.4 Bit, SINAD 57.8 dB, SFDR
–70.8 dB, THD –68.8 dB, at fi = 800 kHz,
10 Bit
Portable Digital Radios
Personal Communication Assistants
Cellular
Wide Input Bandwidth for Undersampling
(75 MHz at 1 dB, >120 MHz at –3 dB) at
Pager
R = 1 kΩ
s
Scanner
Software Programmable Power Down,
(1 µA), Auto Powerdown (120 µA)
Digitizers
Process Controls
Motor Control
Remote Sensing
Automotive
Single Wide Range Supply 2.7 VDC to
5.5 VDC
Low Supply Current 11 mA at 5.5 V, 10 MHz;
7 mA at 2.7 V, 8 MHz Operating
Simultaneous Sample and Hold:
Dual Sample and Hold Matched Channels
Multi Chip Simultaneous Sample and Hold
Capable
Servo Controls
Cameras
Programmable Conversion Modes:
Interrupt-Driven for Shorter Latency
Continuous Modes Optimized for MIPS
Sensitive DSP Solutions
DW OR PW PACKAGE
(TOP VIEW)
CSTART
(LSB) D0
D1
RD
1
28
27
26
25
24
23
22
21
20
19
18
AP/CH1
AM/CH2
BP/CH3
BM/CH4
2
3
D2
4
D3
5
D4
AV
6
DD
BDV
VREFP
VREFM
AGND
WR
7
DD
BDGND
D5
8
9
D6
10
11
D7
DGND
D8 12
(MSB) D9 13
INT 14
17 DV
DD
16 CLKIN
15 CS/OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
functional block diagram
AV
DD
DV
BDV
DD
DD
AP/CH1
AM/CH2
S/H
S/H
D (0–9)
CS/OE
M
U
X
4/8/10-Bit
Recyclic
ADC
Serial/Parallel Conv
and FIFO
3-State
Buffer
Amplifier
BP/CH3
BM/CH4
Control
Register
VREFP
VREFM
VREFMID
REF
CLKIN
SysClk
(15 MHz Max)
OSC
(7.5 MHz Min)
INT
CSTART
WR
Interface
Timing
and
Control
RD
AGND
DGND
BDGND
description
The TLV1562 is a 10-bit CMOS low-power, high-speed programmable resolution analog-to-digital converter
based on a low-power recyclic architecture. The unique architecture delivers a throughput up to 2 MSPS (million
samples per second) at 10-bit resolution. The programmable resolution allows a higher conversion throughput
as a tradeoff of lower resolution. A high speed 3-state parallel port directly interfaces to a digital signal processor
(DSP) or microprocessor (µP) system data bus. D0 through D9 are the digital output terminals with D0 being
the least significant bit (LSB). The TLV1562 is designed to operate for a wide range of supply voltages
(2.7 V to 5.5 V) with very low power consumption (11 mA maximum at 5.5 V, 10 MHz CLKIN). The power saving
feature is further enhanced with a software power-down feature (1 µA maximum) and auto power-down (1 µA
maximum) feature.
Many programmable features make this device a flexible general-purpose data converter. The device can be
configured as either four single-ended inputs to maximize the capacity or two differential inputs to improve noise
immunity. The internal system clock (SYSCLK) may come from either an internally generated OSC or an
external clock source (CLKIN). Four different modes of conversion are available for different applications. The
interrupt driven modes are mostly suitable for asynchronous applications, while the continuous modes take
advantage of the high speed nature of a pipelined architecture. A pair of built-in sample-and-hold amplifiers
allow simultaneous sampling of two input channels. This makes the TLV1562 perfect for communication
applications. Conversion is started by the RD signal, which can also be used for reading data, to maximize the
throughput. Conversion can be started either by the RD or CSTART signal when the device is operating in the
interrupt-driven modes. The dedicated conversion start pin, CSTART, provides a mechanism to simultaneously
sample and convert multiple channels when multiple converters are used in an application.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
description (continued)
The converter incorporates a pair of differential high-impedance reference inputs that facilitate ratiometric
conversion, scaling, and isolation of analog circuitry from logic and supply noise. Other features such as low
input capacitance (10 pF) and very wide input bandwidth (75 MHz) make this device a perfect digital signal
processing (DSP) companion for mobile communication applications. A switched-capacitor design allows
low-error conversion over the full operating free-air temperature range.
The features that make this device truly a DSP friendly converter include: 1) programmable continuous
conversion modes, 2) programmable 2s complement output code format, and 3) programmable resolution. The
TLV1562 is offered in both 28-pin TSSOP and SOIC packages. The TLV1562C is characterized for operation
from 0°C to 70°C. The TLV1562I is characterized for operation over the full industrial temperature range of
–40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
28-TSSOP
(25 MIL PITCH)
(PW)
28-SOIC
(50 MIL PITCH)
(DW)
T
A
0°C to 70°C
TLV1562CPW
TLV1562IPW
TLV1562CDW
TLV1562IDW
–40°C to 85°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND
NO.
20
I
Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage measurements are with
respect to AGND.
AM/CH2
AP/CH1
26
27
23
8
I
I
I
I
Differential channel A input minus or single-ended channel 2
Differential channel A input plus or single-ended channel 1
Positive analog supply voltage
AV
DD
BDGND
Digital ground return for the I/O buffers. Unless otherwise noted, all digital interface voltage measurements are with
respect to DGND.
BDV
DD
7
24
25
16
15
I
I
I
I
I
Positive digital supply voltage for I/O buffers
BM/CH4
BP/CH3
CLKIN
Differential channel B input minus or single-ended channel 4
Differential channel B input plus or single-ended channel 3
External clock input. (1 MHz to 15 MHz)
CS/OE
Chipselect. A high-to-low transition on this input resets the internal counters and controls and enables the outputdata
bus D(0–9) and control inputs (RD, WR) within a maximum setup time. A low-to-high transition disables the output
data bus D(9–0) and WR within a maximum setup time. This signal also serves as an output enable signal when the
device is programmed into both mono and dual interrupt-driven modes using CSTART as the start of conversion
signal.
CSTART
D(0–4)
D(5–9)
DGND
1
I
Conversion start signal. A falling edge starts the sampling period and a rising edge starts the conversion. This signal
acts without CS activated. CSTART connects to DV
via a 10-kΩ pull-up resistor if not used.
DD
2–6 I/O The lower bits of the 3-state parallel data bus. Bidirectional. The data bus is 3-stated except when RD or WR is low
when CS is low.
9–13 I/O The higher bits of the 3-state parallel data bus. Bidirectional. The data bus is 3-stated except when RD or WR is low
when CS is low. When the host processor writes to the converter, D(9,8) are used as an index to the internal registers.
18
17
14
I
I
Digital ground return for the internal digital logic circuitry
Positive digital supply voltage
DV
DD
INT
O
Interrupt output. The falling edge of INT signals the end of conversion. This output goes from a high impedance state
to low logic level on the fifth falling edge of the system clock and remains low until reset by the rising edge of CS or
RD. INT requires connection of a 10-kΩ pull-up resistor.
RD
28
I
Processor read strobe or synchronous start of conversion/sampling. The falling edge of RD is used to 1) start the
conversion in interrupt-driven mode (if RD is programmed as the start conversion signal); 2) start both conversion
and next sampling plus release of the previous conversion data in both continuous modes. The rising edge of RD
serves as a read strobe and data is 3-stated (approximately 10 ns at 50 pF bus loading) after this edge. Connection
of a 10-kΩ pull-up resistor is optional.
VREFM
VREFP
21
22
I
I
The lower voltage reference value is applied to this terminal.
The upper reference voltage value is applied to this terminal. The maximum input voltage range is determined by the
difference between the voltage applied to this terminal and the VREFM terminal.
WR
19
I
Processor write strobe. Active low. Connection of a 10-kΩ pull-up resistor is optional.
detailed description
The TLV1562 analog-to-digital converter is based on an advanced low power recyclic architecture. Two bits of
the conversion result are presented per system clock cycle. A total of 5 system clock (SYSCLK) cycles is
required to complete the conversion. The serial conversion results are converted to a parallel word for output.
The device supports both interrupt-driven (typically found in a SAR type ADC) and continuous (natural for a
pipeline type ADC) modes of conversion. An innovative conversion scheme makes this device perfect for power
sensitive applications with uncompromised speed.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
control register
The TLV1562 is software configurable. The first two bits, MSBs (D9,8), are used to address the register set. The
rest of the 8 bits are used as data. There are two control registers, CR0 and CR1, for user configuration. All of
these register bits are written to the control register during a write cycle. A description of the control registers
and the input/output data formats are shown in Figure 1.
Input Data Format
Pin D9
Index1
Pin D8
Index0
Pin D7
Pin D6
Pin D5
Pin D4
Pin D3
Pin D2
Pin D1
Pin D0
Offset Calibration Set OMS(1,0)
0,0 = Operate with calibration
0,1 = Measure system offset
1,0 = Measure internal offset
1,1 = Operate without calibration
Conversion
Clock Select
0 = Internal
1 = External
Input Type:
0 = Single end
1 = Differential
Conversion Mode Select MS(1,0)
0,0 = Mono interrupt
Channel Select CS(1,0)
0,0 = Ch1 or pair A
0,1 = Ch2 or pair A
1,0 = Ch3 or pair B
1,1 = Ch4 or pair B
0
0
CR0
0,1 = Dual interrupt
1,0 = Mono continuous
1,1 = Dual continuous
System Offset Calibration: Short the system input to the system AGND
Internal Offset Calibration: Short the two inputs to the S/HA to AGND
0
Interrupt-Mode
Conversion
Started
Resolution Select BS(1,0)
0,0 = 10-Bit
0
Output Format Interrupt-Mode SW Power Down
0 = 2’s
Auto
0 = Normal
1 = S/W Power
Down
CR1
0
1
0,1 = 4-Bit
Complement
1 = Binary
Power Down
0 = Disabled
1 = Enabled
0 = By RD
1.0 = 8-Bit
1.1 = 12-Bit Test
1 = By CSTART
Reference delta should be greater than 2 V when swing is reduced.
Output Data Format
Pin D9
Pin D8
Pin D7
Pin D6
Pin D5
Pin D4
Pin D3
Pin D2
Pin D1
Pin D0
Register Index
Configuration Register Content
Configuration Result
MSB
MSB
MSB
LSB
LSB
LSB
CR1
D(5,4)
= 0,0
OD9
OD8
OD2
OD7
OD1
OD6
OD0
OD5
OD4
OD3
OD2
OD1
OD0
10-Bit Conversion Result
CR1
D(5,4)
= 0,1
OD3
OD7
Z
Z
Z
Z
Z
Z
4-Bit Conversion Result
CR1
D(5,4)
= 1,0
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Z
Z
8-Bit Conversion Result
NOTE: Z indicates bits write zero read zero back.
Figure 1. Input/Output Data Formats
NOTE:
Channel select bits CR0.(1,0), CS(1,0) are ignored when the device is in the dual (interrupt or
continuous) modes using differential inputs, since both differential input pairs are automatically
selected. CR0.0 (i.e., CS0 bit) is used to determine if channels 1 and 3 or channels 2 and 4 are
selected if single-ended input mode is used.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
Table 1. Select Input Channels
CR0.(3,2)
(CONVERSION MODE
SELECT)
CR0.4
(INPUT TYPE)
CR0.(1,0)
(CHANNEL SELECT)
CHANNEL(S)
SELECTED
NOTE
0 (Single-ended)
0 (Single-ended)
0 (Single-ended)
0 (Single-ended)
1 (Differential)
00 or 10
00 or 10
00 or 10
00 or 10
00 or 10
00 or 10
01 or 11
01 or 11
01 or 11
01 or 11
01 or 11
0,0
0,1
1,0
1,1
0,X
1,X
X,0
X,1
X,0
X,1
X,X
CH1
CH2
CH3
CH4
Single channel
Single channel
Single channel
Single channel
Single channel
Single channel
Dual channels
Dual channels
Dual channels
Dual channels
Dual channels
Differential pair A
1 (Differential)
Differential pair B
0 (Single-ended)
0 (Single-ended)
0 (Single-ended)
0 (Single-ended)
1 (Differential)
Both CH1 and CH3
Both CH2 and CH4
Both CH1 and CH3
Both CH2 and CH4
Both differential pairs A and B
configure the device
The device can be configured by writing to control registers CR0 and CR1. A read register is carried out by
auto-sequence when the device is put into the software power-down state. CR0 is read first and then CR1 at
the next two RD rising edges after the device is in the software power-down state. The falling edge of RD has
no meaning and does not trigger a conversion in the software power-down state.
V
IH
IL
CS
V
t
w(CSH)
t
d(WRH-CSH)
V
IH
CSTART
WR
t
d(CSL-WRL)
t
s(DATAIN)
V
V
IH
IL
t
t
h(DATAIN)
w(WRL)
V
V
IH
DATA
Configure Data
IL
Figure 2. Configuration Cycle Timing
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
The following examples show how to program configuration registers CR0 and CR1 for different settings.
Example 1:
INDEX
REGISTER
COMMENT
D9
0
D8
0
D7
1
D6
1
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
CR0
CR1
Mono interrupt mode, use RD, write 0D0h to ADC
0
1
0
0
0
0
0
0
0
0
Use 2s complementary output, use RD, write 104h to ADC
Example 2:
CR0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
Mono interrupt mode, use CSTART, write 0D0h to ADC
Use 2s complementary output, write 144h to ADC
CR1
Example 3:
CR0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
0
0
0
0
0
Dual interrupt mode, use CSTART only, write 0D4h to ADC
Use 2s complementary output, write 144h to ADC
CR1
Example 4:
CR0
0
0
0
1
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
Mono continuous mode, use RD only, write 0D8h to ADC
Use 2s complementary output, write 104h to ADC
CR1
Example 5:
CRO
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
0
0
Dual continuous mode, use RD only, write 0DCh to ADC
Binary output, write 104h to ADC
CR1
analog input
input types
The four analog inputs can be configured as two pairs of differential inputs or four single-ended inputs by setting
the control register 0 bit 4 input type selection (dual or single channel).
differential input (CR0.4=1)
Up to two channels are available when the TLV1562 is programmed for differential input. The output data format
is bipolar when the device is operated in differential input mode.
single-ended input (CR0.4=0)
Up to four channels are available when the TLV1562 is programmed for single-ended input. The output data
format is unipolar when the device is operated in single-ended input mode.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
input signal range
The analog input signal range for a specific supply voltage AV
ranges from (AV
– 1.9 V) to 0.8 V.
DD
DD
V
SWING
3 V
0.8 V
AV
DD
(V)
2.7
4.9
5.5
Linearity not Guaranteed
Limited by Noise
Figure 3. Analog Input Range vs AV
DD
VREFCM + 0.5 × V
VREFCM – 0.5 × V
≤ AV
≥ 0.8 V
–1 V
SWING
SWING
DD
Where:
VREFCM = (VREFP + VREFM)/2 is the common mode reference voltage.
V
V
= dynamic range of the input signal,
= VINP – VINM,
SWING
SWING
And the common mode input voltage is:
VINCM = (VINP + VINM)/2,
MAX V
= MIN [(AV
– 1.9 V), 3 V]
SWING
DD
For single-ended input, the analog input range is between VREFP and VREFM. So the range of
single-ended VIN is:
3 V
1 V
0.8 V
if AV
if AV
if AV
= 3 V
= 3 V
= 2.7 V
DD
DD
DD
For differential input, the input common mode voltage VINCM can be between AV
3 V ≥ (VINP–VINM) ≥ 0.8 V.
and AGND as long as
DD
This means VINCM ≥ 0.4 V.
So the range of differential analog input voltage, (VINP–VINM) is:
3 V
1 V
0.8 V
if AV
if AV
if AV
= 3 V
= 3 V
= 2.7 V
DD
DD
DD
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
equivalent input impedance
R
on(Ω)
1 k
FB
R
R
R
s
on
on
0 V
V
in
Buffer
= 0.5 pF
0.5 k
C
= 10 pF
C
pad
sample
V
CC
(V)
2.7
5.5
Figure 5. Input Mux On Resistance vs
Analog Supply Voltage
Figure 4. Equivalent Input Circuit
Req = Vin/Ieq = (Q/Cin)/(Q/T) = T/Cin = 1/(fs × Csample) = 1/(2 MHz × 0.5 pF) = 1 MΩ
Where f is the sampling frequency, and f is the conversion frequency
s
c
f = f /5
when the device is in one channel/continuous conversion mode,
when the device is in one channel/continuous conversion mode,
s
c
f = f /10
s
c
f = Conversion trigger strobe frequency when the device is in interrupt mode (RD or CSTART)
s
Csample = Input capacitance = 0.5 pF
Cparasitic = Parasitic capacitance = 0.5 pF
Cpad = Input PAD capacitance = 10 pF
Ron = Mux switch on series resistance = 1 kΩ at 2.7 V
Rs = Source output resistance = 1 kΩ
input bandwidth (full power 0 dB input, BW at –1 dB)
0
–1
–2
–3
–4
–5
50
130 140
20 30
40
70
Analog Input Frequency – MHz
BW = 1/[2 × π × (Rtotal y Cac)]
90 100 110 120
150
10
60
80
= 1/[2 × π × ((Ron + Rs) × (Csample + Cparasitic))]
= 1/[2 × π × (2K × 1 pF)]
= 79.6 MHz
(Theoretical Max)
Figure 6. Typical Analog Input Frequency Input Bandwidth
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
reference voltage inputs
The TLV1562 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The
values of VREFP, VREFM, and the analog input should not exceed the positive supply or be less than GND
consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal
is equal to or higher than VREFP and is at zero when the input signal is equal to or lower than VREFM. The
internal resistance from VREFP to VREFM may be as low as 20 kΩ (±10%).
R
R
on
s
V
REFP
10 kΩ
VREFCM
10 kΩ
C
C
C
= 1 pF
pad
= 10 pF
in
in
R
R
s
on
V
REFM
C
= 1 pF
pad
= 10 pF
The reference voltages must satisfy the following conditions:
VREFP ≤ AV – 1 V,
DD
AGND + 0.9 V < VREFM and
3 V ≥ (VREFP – VREFM) ≥ 0.8 V
Figure 7. Equivalent Circuit for Reference input
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
sampling/conversion
All of the sampling, conversion, and data output in the device are started by a trigger. This trigger can be the
RDor CSTART signal depending on the mode of conversion and configuration. The falling edge of the RDsignal
and the rising edge of the CSTART signal are extremely important since they are used to start the conversion.
These edges need to stay as close to the falling edges of the external clock, if they are used as SYSCLK. The
minimum setup time with respect to the rising edge of the external SYSCLK should be 5 ns minimum. When
the internal SYSCLK is used, this is not an issue, since these two edges start the internal clock automatically;
therefore, the setup time is always met.
USING EXTERNAL CLOCK
S/H Hold Time
V
V
IH
EXTERNAL
SYSCLK
IL
t
d(ECLKL-TRGL)
t
s(TRGL-ECLKH)
V
IH
Conversion Starts
Next Sampling Starts
RD
V
IL
V
IH
Next Sampling Starts
Conversion Starts
CSTART
V
IL
Sampling Period
Figure 8. Conversion Trigger Timing – External Clock
USING INTERNAL CLOCK
INTERNAL
CLOCK STARTS
V
V
IH
Conversion Starts
Next Sampling Starts
RD
IL
t
d(TRGL-ICLKH)
V
V
IH
Conversion Starts
CSTART
Next Sampling
Starts
IL
S/H Hold Time
V
V
IH
INTERNAL
SYSCLK
IL
Figure 9. Conversion Trigger Timing – Internal Clock
11
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Table 2. Conversion Trigger Edge
CONVERSION
TIME
(INTERNAL CLK) (EXTERNAL CLK)
CONVERSION
TIME
INTERRUPT
CANCELED
BY
CONVERSION CONVERSION
MODE TRIGGER
START OF
SAMPLING
START OF
CONVERSION
DATA OUT
‡
§
41 ns from INT low
Mono
RD
WR ↑ or
RD ↓
6 SYSCLK
5 SYSCLK
RD ↑
Interrupt
2 SYSCLK from RD ↓
†
§
41 ns from RD low
CSTART
CSTART ↓
CSTART ↑
CSTART ↑
6 SYSCLK
5 SYSCLK
RD ↓
§
41 ns from RD low
Dual
Interrupt
CSTART
CSTART ↓
12 SYSCLK
10 SYSCLK
First RD ↓
‡
§
41 ns from RD low
Mono
Continuous
RD
RD
WR ↑ or
RD ↓
RD ↓
6 SYSCLK
5 SYSCLK
N/A
N/A
2 SYSCLK from RD ↓
‡
§
41 ns from RD low
Dual
WR ↑ or
12 SYSCLK
10 SYSCLK
Continuous
7 SYSCLK from RD ↓
†
‡
CSTART works with or without CS active.
The first sampling period starts at the last RD low of the previous cycle or WR high of the configuration cycle. RD low is the falling edge of RD
and WR high is the rising edge of the WR signal. (Minimum sample/hold amp settling time = one SYSCLK, approximately 100 ns min, at Rs ≤
1 kΩ).
§
Output data enable time is dependent on bus loading and supply voltage (BDV ). For BDV
= 5 V, the enable time is 19 ns at 25 pF, 23 ns
= 2.7 V, the enable time is 37 ns at 25 pF, 41 ns at 50 pF, and 56 ns at 100 pF.
DD DD
at 50 pF, and 25 ns at 100 pF. For BDV
DD
The TLV1562 provides four types of conversion modes. The two interrupt-driven conversion modes are
asynchronous and are simple one-shot conversions. The auto-powerdown conversion feature can be enabled
when interrupt-driven conversion modes are used. The other two continuous conversion modes are
synchronous with the RD signal (as a clock) from the processor and are more suitable for repetitive signal
measurement. These different modes of conversion offer a tradeoff between simplicity and speed.
12
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
detailed description (continued)
Table 3. Maximum Conversion Speed (for 1 LSB INL and DNL at 10 bit)
†
MAXIMUM CONVERSION THROUGHPUT
CONVERSION MODE
CR0.(3,2)
EXTERNAL CLOCK INTERNAL CLOCK
(10 MHz)
1.5 MSPS
0.82 MSPS
1.5 MSPS
0.82 MSPS
1.5 MSPS
1.05 MSPS
(8 MHz)
RD
1.1 MSPS
0.68 MSPS
1.1 MSPS
0.68 MSPS
0.91 MSPS
0.83 MSPS
RD with auto power down
Mono interrupt-driven conversion mode
00
01
CSTART
CSTART with auto power down
CSTART
‡
Dual interrupt-driven conversion mode
CSTART with auto power down
§
§
Mono continuous conversion mode
Dual continuous conversion mode
RD
RD
10
11
2 MSPS
2 MSPS
1.33 MSPS
1.33 MSPS
¶
¶
†
Speed is calculated for 5-V with a 2-V reference
(5.5 V to 3 V, I-temperature and C-temperature: 2 MSPS at 10 bit, 3 MSPS at 8 bit, 7 MSPS at 4 bit;
3 V to 2.7 V, C-temperature: 2 MSPS at 10 bit, 2.5 MSPS at 8 bit, 7 MSPS at 4 bit;
3 V to 2.7 V, I-temperature: 1.6 MSPS at 10 bit, 2.5 MSPS at 8 bit, 7 MSPS at 4 bit).
Higher throughput is possible when the linearity requirement is relaxed.
Dual interrupt mode is available to 8-bit or 10-bit resolution and single-ended input type.
Throughput from single selected channel.
‡
§
¶
Combined throughputs from a pair of selected channels.
Conversion Start
RD-Strobe
Conversion Results
Mono Interrupt Mode: 0 RD-Delay
Dual Interrupt Mode: 0~1 RD-Delay
Mono Continuous Mode : 1 RD-Delay
Dual Continuous Mode : 2~3 RD-Delay
Figure 10. Digital Delays for Different Conversion Modes
13
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
mono interrupt-driven mode (CR0.(3,2) = 0,0)
The mono interrupt-driven conversion mode provides a one-shot conversion. Sampling, conversion, and data
output are all performed in a single cycle. The analog signal is sampled 2 SYSCLKs after the falling edge of RD
(or the rising edge of WR if this is the first sample after configuration) and then converted on the falling edge
of RD. Once the data is ready, INT falls and the data is output to the bus. The rising edge of RD cancels INT
and initiates a read of the data. The data bus is 3-stated when RD goes high. It is not necessary to configure
the converter for each cycle or toggle CS between cycles.
V
V
IH
IL
CS
CSTART
Sample 1
Conv 1
Sample 2
Conv 2
t
t
conv1
conv1
t
t
s1
s1
V
V
IH
IL
t
WR
RD
d(RDL-SAMPLE)
V
V
IH
IL
t
dis(DATAOUT)
V
V
IH
IL
Hi–Z
Data 1
DATA
t
d(RDL-CONV)
t
en(DATAOUT)
t
d(RDH-INTZ)
(With Pullup)
t
d(CONV-INTL)
V
IH
INT
V
t
IL
1(APDR)
t
1(APDR)
t
(APD)
Power Down
(If Autopower Down is Set)
Power Down
(If Autopower Down is Set)
Figure 11. Mono Interrupt-Driven Mode Using RD
14
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2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Conversion can also be started with CSTART. This is useful when an application requires multiple TLV1562s
for simultaneous samplings and conversions. The falling edge of CSTART starts the sampling and the rising
edge of CSTART starts the conversion. Once the data is ready INT falls. INT is terminated by the following falling
edge of RD which also outputs the data to the bus. On the rising edge of RD, the data is read and the data bus
is 3-stated.
V
V
IH
IL
CS
t
d1(WRH–CSTARTL)
t
d(RDH-CSTARTL)
t
t
d(CSL-RDL)
w(CSTARTL)
V
IH
CSTART
WR
V
V
IL
IH
V
IL
Sample 1
Conv 1
t
Sample 2
t
t
s1
t
w(RDL)
s1
conv1
V
V
IH
IL
RD
t
d(INTL-CSL)
t
dis(DATAOUT)
t
d(CSTART-SAMPLE)
DATA
t
en(DATAOUT)
Data 1
V
V
IH
IL
t
d1(CSTARTH–CONV)
t
t
d(CSTARTL-SAMPLE)
t
d(CONV-INTL)
d(RDH-INTZ)
(With Pullup)
V
V
IH
IL
INT
t
1(APDR)
t
t
(APD)
1(APDR)
Power Down
(If Autopower Down is Set)
Power Down
Figure 12. Mono Interrupt-Driven Mode Using CSTART
15
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
dual interrupt-driven mode (CR0.(3,2) = 0,1)
The dual interrupt-driven conversion mode provides a similar one-shot conversion, sampling, and conversion
but also samples both selected channels simultaneously. Conversion can only be started with the CSTART
signal. The falling edge of CSTART starts the sampling of both of the input channels selected, and the rising
edge of CSTART starts the conversion. Since it takes two consecutive conversions internally, the conversion
time required is doubled (10 SYSCLK cycles). Once the data are ready, INT falls. INT is terminated by the first
falling edge of RD, which also outputs the first data to the bus. On the rising edge of RD, data is read and the
data bus is 3-stated. The second RD falling edge outputs the second data to the bus and then reads it on the
rising edge and 3-states the bus. It is not necessary to configure the converter for each cycle or toggle CS
between cycles.
NOTE:Dual interrupt mode is available to 10-bit or 8-bit resolution and single-ended input
type.
t
t
d2(WRH–CSTARTL)
d(INT-CSL)
t
w(CSH)
V
IH
CS
V
IL
t
w(CSTARTL)
V
IH
CSTART
WR
V
V
IL
IH
V
IL
Sample 1
Conv 1
Sample 2
t
s4
t
t
t
conv2
d2(RDH–CSTARTL)
s4
t
w(RDL)
V
IH
IL
RD
V
t
dis(DATAOUT)
(With Pullup)
t
t
dis(DATAOUT)
EN(DATAOUT)
V
IH
Data 1A
Data 1B
DATA
V
IL
t
d2(CSTART–CONV)
t
en(DATAOUT)
t
d(RDL-INTZ)
V
IH
INT
V
IL
t
2(APDR)
t
t
2(APDR)
(APD)
Powerdown
(If Autopowerdown Is Set)
Powerdown
Figure 13. Dual Interrupt Conversion Mode
(Conversion can only be started with CSTART for the dual interrupt mode)
16
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2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
mono continuous mode (CR0.(3,2) = 1,0)
The mono continuous mode of conversion is synchronous with the RD signal. Its cycle time is approximately
5 SYSCLK cycles when an external SYSCLK is used (6 SYSCLK cycles when an internal SYSCLK is used).
In the mono continuous mode, the TLV1562 is always sampling the input regardless of the state of other control
signals when it is not in the hold state (the first half SYSCLK cycle after each falling edge of RD). This simplifies
control of the ADC. There is no need to generate any special signal to start the sampling.
V
V
IH
IL
CS
V
V
IH
IL
WR
t
t
c(RD)
d(CSL-RDL)
t
w(RDL)
V
V
IH
IL
RD
t
t
conv1
t
conv1
conv1
CONV 1
t
d(RDL-SAMPLE)
CONV 2
CONV 3
t
s5
Sample 1
t
t
s2
s2
Sample 3
Sample 4
t
s2
Sample 2
t
t
dis(DATAOUT)
dis(DATAOUT)
V
IH
IL
Hi-Z
Config
Data 1
Data 2
DATA
V
t
t
en(DATAOUT)
en(DATAOUT)
Figure 14. Mono Continuous Mode
17
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
dual continuous mode (CR0.(3,2) = 1,1)
When the TLV1562 operates in the dual continuous mode, it samples and then holds two preselected channels
(differential or single ended) simultaneously as RDclocks. Thesesamplesarethenconvertedinsequence. This
is designed to optimize the DSP MIPS for communication applications. Its cycle time is approximately 10
SYSCLK cycles when an external SYSCLK is used (12 SYSCLK cycles when an internal SYSCLK is used).
When operating in the dual continuous mode, the TLV1562 is always sampling the input regardless of the state
of the other control signals when it is not in the hold state. This simplifies control of the ADC. There is no need
to generate any special signal to start the sampling. The TLV1562 goes into hold mode on the odd number
(starting from the rising edge of WR) falling edge of RD for one SYSCLK clock cycle.
A two-depth FIFO is used (only in the dual continuous mode) to ensure the output correlation. Thus on every
alternate RD edge, the result of the previous two conversions is read out. This allows a slower RD clock
frequency (slower than 1/5 of the SYSCLK frequency). Each dual continuous mode cycle (while CS remains
active low) must have an even number of RD cycles to ensure the FIFO operates properly.
V
IH
IL
CS
V
WR
t
c(RD)
t
t
d(RDL-SAMPLE)
RD
t
t
t
t
s5
conv2
CONV 1
conv2
CONV 2
conv2
CONV 3
t
t
s3
Sample 2
s3
s3
Sample 4
Sample 1
GFG
Sample 3
t
dis(DATAOUT)
D 1B
DATA
D 1A
D 2A
D 2B
t
en(DATAOUT)
Figure 15. Dual Continuous Mode
system clock source
The TLV1562 uses multiple clocks for different internal tasks. SYSCLK is used for most conversion subtasks.
The source of SYSCLK is programmable via control register 0, bit 5 (CR0.5). The source of SYSCLK is changed
at the rising edge of WR of the cycle when CR0.5 is programmed.
internal oscillator (CR0.5 = 0, SYSCLK = internal OSC)
The TLV1562 has a built-in 8-MHz oscillator. When the internal OSC is selected as the source of SYSCLK, the
internal clock starts with a delay (one half of the OSC clock period max) after the falling edge of the conversion
trigger (RD or CSTART).
18
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CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
external clock input (CR0.5 = 1, SYSCLK = External Clk)
The TLV1562 is designed to operate with an external clock input (CMOS/TTL) with a frequency from 100 kHz
to 14 MHz. When an external clock is used as the source of SYSCLK, the setup time from the falling edge of
RD to the rising edge of SYSCLK, t
external clock mode is selected.
is 5 ns minimum. The internal OSC is shut down when the
s(TRGL-ECLKH)
host processor interface
parallel processor interface
The TLV1562 provides a generic high-speed parallel interface that is compatible with high-performance DSPs
and general-purpose microprocessors. These include D(0,9), RD, WR, and INT. RD transitions from high to low
to signal the end of acquisition. The parallel I/O has its own power supply to minimize digital noise.
output data format
The output data format is unipolar binary (1023 to 0) when the device is operated in the single-ended input mode
and is bipolar (511 to –512) when the device is operated in differential input mode. The output code format can
be either binary or 2s compliment. The output data format is controlled by CR1.2.
power down
The device offers two different power-down modes: Auto power-down mode for interrupt-driven conversions
and software power-down mode for all conversion modes. All configuration information is kept intact when the
device is in software or auto power-down mode.
auto-power down for interrupt-driven conversion modes
When auto-power down is enabled, the device turns off the analog section (the converter except for the
reference network) at the falling edge of INT and resumes after the falling edge of CS (if RD is the conversion
trigger) or CSTART (if CSTART is the conversion trigger). The reference current and I/O are kept alive to ensure
a fast recovery. Average power consumption can be reduced by accessing the converter less often. Special
requirements for using this feature are:
It is necessary to toggle CS between cycles so the converter knows when to resume.
There is an additional delay to a conversion after the device is accessed due to the auto-power-down
control. Therefore, the time between RD (or CSTART) triggers is longer (longer RD or CSTART high time).
software power down (CR.10 = 1, software power down enabled)
In addition to the auto-power-down feature, the device has a software powerdown feature to further reduce
power consumption when the device is idle. Writing a 1 to control register bit CR1.0 puts the TLV1562 into
software power-down mode in 200 ns after CS is up. The device consumes less than 1 µA when in the
power-down mode. Writing a 0 to control register bit CR1.0 wakes up the device. Conversion can start 1 µs after
the device is resumed. CS must be high when the device is in power-down mode. Software power-down
operation is slower than auto-power down but is more flexible and consumes almost no power.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Table 4. TLV1562 Powerdown Features
FUNCTION BLOCK/POWERDOWN MODE
DIGITAL CONTROL VOLTAGE LEVEL
SOFTWARE POWERDOWN
AUTO POWERDOWN
CMOS
Inactive
Inactive
Active
TTL
Inactive
Inactive
active
CMOS
Inactive
Active
TTL
Converter analog section
Inactive
Active
Reference current (amps)
Digital I/O buffers
Active
Active
Estimated supply current, I
Power-down time
1 µA
80 µA
120 µA
200 ns
700 ns
1 MSPS
200 µA
200 ns
700 ns
1 MSPS
CC
200 ns
200 ns
Resume time
1 µs
1 µs
†
‡
‡
1.2/0.7 MSPS
Maximum throughput
1.2/0.7 MSPS
†
‡
Dual interrupt, 10-bit, 5-V AV , 10-MHz external clock, and 2 V (REFP–REFM).
DD
This assumes the TLV1562 is software powered down between every cycle. In reality this is not the case since auto-power down makes much
more sense in this case. So the realistic maximum throughput for software power down will be close to the maximum throughput without
powerdown which is 1.2 MSPS for dual-interrupt mode (and 1.5 MSPS if mono-interrupt mode is used). But this really depends on how long the
device is powered down.
mid-scale error calibration
The device has a ±5% maximum full-scale error, mid-scale error, and zero-scale error due to the gain error in
the sample and hold amplifier.
The TLV1562 is capable of calibrating the mid-scale error. There are two calibration modes: system mid-scale
error calibration and internal mid-scale error calibration as described below.
NOTE:
Set register CR0.(7,6) = 1,1 when the device is not in mid-scale error calibration mode.
These mid-scale error calibrations affect the ADCs transfer characteristics as shown in Figure 16. The absolute
error at code 512 is zero-out (this is the reference point for mid-scale error calibration). The calibration also
makes the FS error and ZS error equal.
internal mid-scale error calibration (CR0.(7,6) = 1,0)
The internal mid-scale error calibration mode is set by writing to the configuration registers with CR0.(7,6) set
to 10. The ADC analog inputs are internally shorted to mid-voltage (REFP+REFM)/2 when the mid-scale error
calibration mode is enabled. One conversion (initiated by the falling edge of RD) is performed to calculate the
offset. The result of this conversion is stored in the mid-scale error register and is subtracted from all subsequent
conversions thus removing any offset. Internal calibration removes any offsets internal to the device. Internal
mid-scale error calibration reduces the mid-scale error to ±2.5% FS single ended inputs (0.3% FS differential
inputs).
system mid-scale error calibration (CR0.(7,6) = 0,1)
System mid-scale error calibration is set by writing to the configuration registers with CR0.(7,6) set to 01. The
analog input to be calibrated is externally connected to the voltage corresponding to mid-code. For differential
operation, this is achieved by shorting the two inputs together; for a single-ended input this is achieved by
connecting the analog input to the system mid-voltage, (SYSTEM_REFP + SYSTEM_REFM)/2. One
conversion (initiated by RD falling edge) is performed to calculate the offset. The result of this conversion is
stored in the mid-scale error register and is subtracted from all subsequent conversions thus removing any
offset. System mid-scale error calibration removes the offset of not only the ADC but any offsets in the entire
analog circuitry driving the ADC input. System mid-scale error calibration reduces the mid-scale error to ±0.4%
FS single ended inputs (0.25% FS differential inputs).
20
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CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
Full-Scale Error
(Before Calibrayion)
Code Output
Full Scale
Full-Scale Error
(After Calibration)
Ideal Transfer Function
Transfer Function After
Mid-Scale Calibration
Transfer Function Before
Mid-Scale Calibration
Mid Scale
Mid-Scale Error
(Before Calibration)
Mid-Scale Error
(After Calibration)
Zero Scale
REFM
Analog Input
V-Mid (REFCM)
Zero-Scale Error
(Before Calibration)
REFP
Zero-Scale Error
(After Calibration)
Figure 16. Mid-Scale Error Calibration
resume normal conversion from mid-scale error calibration modes
A follow on write operation sets CR0.(7,6) to 00 which resumes the normal conversion mode. Typically
mid-scale error calibration needs to be performed only once after power up. If however the operation mode is
changed from single ended to differential, then preferably mid-scale error calibration should be performed
again.
The user writes a bit to enable mid-scale error calibration. Inputs to the ADC are internally shorted therefore
the offset value can be converted to a digital word. The result (a digital word representing the offset) is stored
in a latch. This offset value is then subtracted from the digital output of all conversions except when in mid-scale
error calibration mode.
system design consideration regarding to mid-scale error calibration
Mid-scale error calibration may limit the dynamic range of the ADC. If the offset is negative and has a magnitude
x, then the range of the converter codes is x to 1023. If the offset is positive and has a magnitude of x, then the
range of converter codes is 1 to 1023 –x. Thus the ADCs dynamic range is reduced by x (say x = 20 codes) on
either side of the range effectively with mid-scale error calibration. However this should not be a limitation for
most users.
21
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2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
2.7 V
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Address Decoder
and Control
BDV
DV
CS
AV
DD
DD
DD
TMS320C541
A15
CS
WR
WR
SIG 1
SIG 2
CH1
CH3
A14
R/W
IS
RD
RD
SYSCLK/5
MODE
TLV1562
DSPCLK
DSPINT
CSTART
INT
CSTART
INT
REF
SYSCLK
CLKIN
10
PD(0–9)
D(0–9)
DGND AGND BDGND
Figure 17. Typical Interface to a TMS320 DSP
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CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
WR
Sig 1
Sig 2
CH0
CH2
RD
1562 #1
CSTART
RD
INT 1
WR
10
PD(0–9)
WR
RD
Sig 3
Sig 4
CH0
CH2
#2
C541
CS0
CSTART
A
A
0
1
CS1
CS2
INT 2
WR
RD
B I/O
(CSTART)
#3
Sig 5
CH0
CSTART
CS
Set #3 in Single Interrupt Mode
Set #1 and #2 in Dual Interrupt Mode (New Mode)
Select (Separate RD Cycle option in Req Z for #1, #2, #3
INT 3
Figure 18. Multiple Chips Simultaneous Sampling/Conversion Application
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
V
IH
CS0
CS2
CS1
RD
V
V
IL
IH
V
V
IL
IH
V
V
IL
IH
V
IL
t
en(DATAOUT)
t
dis(DATAOUT)
V
IH
Hi-Z
D Sig1
D Sig2
D Sig3
D Sig4
D Sig5
PD(0–9)
CSTART
V
V
IL
IH
V
IL
t
s4
t
conv2
Pullup
V
IH
INT1
INT2
V
IL
Pullup
V
IH
V
IL
Pullup
V
V
IH
INT3
IL
< = 0.2 µs × 5
0.1 µs
†
If CLK = 10 MHz
Figure 19. Multiple Chips Simultaneous Sampling/Conversion Application System Timing
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: AV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
DD
BDV , DV
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
DD
DD
DD
AV
to DV
or BDV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V to 6.5 V
DD
DD
Voltage range between AGND and DGND or BDGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.5 V
Digital input voltage range, CLKIN, CS, WR, RD, CSTART (see Note 2) . . . . . . . . . . . –0.3 V to DV
Digital data input voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV
Digital data output voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV
+0.3 V
+0.3 V
+0.3 V
DD
DD
DD
Analog output voltage range, INT (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V to AV + 0.1 V
DD
Reference input voltage range, REFP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V to AV + 0.1 V
DD
Reference input voltage range, REFM (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V
Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Operating free-air temperature range, T : TLV1562C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0°C to 70°C
A
TLV1562I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Measured with respect to AGND with REF – and GND wired together (unless otherwise noted).
2. Measured with respect to DGND.
recommended operating conditions
PARAMETERS
(see Note 3)
MIN NOM
MAX
UNIT
Supply voltage, AV , BDV , DV
DD DD DD
2.7
AGND +1.7
AGND +0.9
5.5
V
V
V
Positive external reference voltage input, VREFP (see Note 4)
Negative external reference voltage input, VREFM (see Note 4)
AV
AV
– 1
– 1
DD
DD
MIN of
Differential reference voltage input, (VREFP–VREFM) (see Note 4)
0.8
AV
DD
– 1.9
or 3
V
Single-ended analog input voltage, (AIN – AGND) (see Note 4)
Differential analog input voltage, (AINP–AINM)
VREFM
0.8
VREFP
3
V
V
Common mode analog input voltage, (AINP+AINM)/ 2
AGND
0.067
AV
V
DD
1
External SYSCLK 40/60 cycle time, t
c(EXTSYSCLK)
µs
t (EXT
c
External SYSCLK pulse duraton high, t
40%
60%
60%
wH(EXTSYSCLK)
wL(EXTSYSCLK)
SYSCLK)
t (EXT
c
SYSCLK)
External SYSCLK pulse duration low, t
40%
2.1
High-level digital and control input voltage, V
IH
V
V
Low-level digital and control input voltage, V
IL
0.8
70
85
TLV1562C
TLV1562I
0
Operating free-air temperature, T
°C
A
–40
NOTES: 3. The absolute difference between AV , BDV
DD
and DV
should be less than 0.5 V.
DD
DD
4. Analog input voltages greater than that applied to VREFP convert as all ones (111111111111), while input voltages less than that
applied to VREFM convert as all zeros (000000000000).
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range, differential
input, AV
(unless otherwise noted)
= DV
=BDV
= 3 V, VREFP – VREFM = 1 V, external SYSCLK = 10 MHz
DD
DD
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BDV
BDV
BDV
BDV
= 5.5 V,
= 2.7 V,
= 5.5 V,
= 2.7 V,
I
I
I
I
= –0.2 mA
= –20 µA
= 0.8 mA
= 20 µA
2.4
DD
DD
DD
DD
OH
OH
OL
OL
V
V
Digital high-level output voltage
V
OH
BDV –0.1
DD
0.4
0.1
1
Digital low-level output voltage
V
OL
V
V
= BDV
DD
= BDGND,
,
CS = BDV
CS = BDV
0.005
–0.005
0.005
Off-state output current
(high-impedance state)
O
DD
DD
I
µA
OZ
–1
O
I
I
High-level input current
Low-level input current
V = BDV
I DD
1
1
µA
µA
IH
V = BDGND
I
–0.005
IL
CS at BDGND,
SYSCLK = 10 MHz
AV
AV
AV
= 5.5 V,
= 2.7 V,
= 5.5 V,
DD
DD
DD
8.5
5
11
7
Total operating supply current, (from
mA
AV , DV , and BDV
DD DD DD
)
CS at BDGND,
SYSCLK = 8 MHz
CS at BDGND,
SYSCLK = 10 MHz,
CMOS control level, Auto powerdown = 1
85
200
0.2
60
120
300
1
Total auto-powerdown supply current
µA
(from AV , DV , and BDV
)
CS at BDGND,
SYSCLK = 10 MHz,
TTL control level, Auto powerdown = 1
AV
= 5.5 V,
DD
DD DD DD
I
DD
CS at BDGND,
SYSCLK = 10 MHz,
CMOS control level, S/W powerdown = 1
AV
= 5.5 V,
DD
Total S/W powerdown supply current
µA
(from AV , DV , and BDV
)
CS at BDGND,
SYSCLK = 10 MHz,
AV
= 5.5 V,
DD
DD DD DD
80
TTL control level, S/W powerdown = 1
Selected channel at AV
0.25
0.25
1
DD
Selected channel at AGND
VREFP = AV – 1.9 V, AV
Selected channel leakage current
µA
µA
–1
Maximum static analog reference
current into REFP
= 5.5 V,
DD
DD
VREFM = AGND + 0.9 V, SYSCLK = 10 MHz
150
25
180
Reference input impedance
Output capacitance
V
DD
= 5.5 V, CS = 0, SCLK = 10 MHz
17
30
5
kΩ
pF
Analog inputs fixed
Analog inputs switching
Control inputs
9
0.5
20
10
1
C
R
Input capacitance
pF
i
25
0.5
1
V
V
= 5.5 V
= 2.7 V
DD
Input MUX ON resistance
kΩ
ON
DD
†
All typical values are at V
= 5 V, T = 25°C.
A
DD
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
timing requirements
PARAMETER
TEST CONDITIONS
MIN
2
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time, CS↓ to WR↓, t
4
d(CSL–WRL)
Delay time, RD↑ to CSTART↓, t
Delay time, RD↑ to CSTART↓, t
100
300
100
300
2
d1(RDH – CSTARTL)
d2(RDH – CSTARTL)
Delay time, WR↑ to CSTART↓, t
Delay time, WR↑ to CSTART↓, t
d1(WRH – CSTARTL)
d2(WRH – CSTARTL)
Delay time, CS↓ to RD↓, t
4
d(CSL–RDL)
Pulse duration, CS high, t
50
5
w(CSH)
Setup time, data valid to WR↑, t
su(DATAIN)
h(DATAIN)
Hold time, WR↑ to data invalid, t
10
50
200
50
4
Interrupt modes
Pulse duration, RD low, t
w(RDL)
Continuous modes
Pulse duration, WR low, t
w(WRL)
Delay time, WR↑ to CS↑, t
d(WRH–CSH)
d(RDH–CSH)
Delay time, RD↑ to CS↑, t
4
Delay time, external SYSCLK↓ to RD↓, CSTART↑, t
0
2
6
d(ECLKL–TRGL)
su(TRGL–ECLKH)
Setup time, RD↓, CSTART↑, to external SYSCLK↑, t
5
Auto power down = 1
Auto power down = 0
800
100
10
Pulse duration, CSTART low, t
ns
ns
w(CSTARTL)
Delay time, INT↓ to CS↓, t
d(INTL–CSL)
External SYSCLK, 10 bit
Internal SYSCLK, 10 bit
External SYSCLK, 8 bit
Internal SYSCLK, 8 bit
External SYSCLK, 4 bit
Internal SYSCLK, 4 bit
External SYSCLK, 10 bit
Internal SYSCLK, 10 bit
External SYSCLK, 8 bit
Internal SYSCLK, 8 bit
External SYSCLK, 4 bit
Internal SYSCLK, 4 bit
External SYSCLK, 10 bit
Internal SYSCLK, 10 bit
External SYSCLK, 8 bit
Internal SYSCLK, 8 bit
External SYSCLK, 4 bit
Internal SYSCLK, 4 bit
5
4
5.5
6
4.5
5
Conversion time, mono continuous/interrupt mode, t
SYSCLK
SYSCLK
SYSCLK
conv1
2
2.5
3
10
8
11
12
9
Conversion time, dual continuous/interrupt mode, t
conv2
10
5
4
6
5
6
4
5
2
3
5.5
4.5
2.5
Cycle time, continuous mode RD, t
c(RD)
Mono interrupt mode sampling time or first cycle (mono interrupt or
continous mode) sampling time, t
0.2
0.3
1000
1000
µs
µs
s1
Dual interrupt mode sampling time or first cycle (dual interrupt or continuous
mode) sampling time, t
s4
Mono continuous mode sampling time, t
3
7
SYSCLK
SYSCLK
µs
s2
Dual continuous mode sampling time, t
Continuous mode first sampling time, t
s3
0.45
3
(SAMPE5)
Data rise time, t
5
10
ns
r(DATAOUT)
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
timing requirements (continued)
PARAMETER
TEST CONDITIONS
MIN
2
TYP
MAX
8
UNIT
ns
Data fall time, t
f(DATAOUT)
4
Control signal rise time, RD, RW, CSTART, CS, and DATA, t
2
1000
1000
ns
r(I/O)
Control signal fall time, RD, RW, CSTART, CS, and DATA, t
2
ns
f(I/O)
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
f = 800 kHz at 10 bit 2 MSPS, AV = 5 V, VREFP = 3.5 V
MIN NOM
MAX
UNIT
I
DD
±0.6
±1
VREFM = 1.5 V, mono continuous
f = 800 kHz at 10 bit 2.5 MSPS, AV
I
= 5 V, VREFP=3.5 V,
= 5 V,
DD
–1.5 ±0.85
±1.5
±1.5
VREFM = 1.5 V, mono continuous
f = 800 kHz at 10 bit 2.8 MSPS, AV
DD
I
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
f = 800 kHz at 10 bit 2 MSPS, AV
VREFM = 0.9 V, mono continuous
= 3 V, VREFP = 1.7 V,
= 3 V, VREFP = 1.7 V,
I
DD
±0.6
±1
±1
±1
Integral linearity error, center best fit
(see Note 5)
LSB
f = 800 kHz at 8 bit 3 MSPS, AV
VREFM = 0.9 V, mono continuous
I
DD
±0.6
f = 800 kHz at 8 bit 3.5 MSPS, AV
I
VREFM = 0.9 V, mono continuous
= 3 V, VREFP = 1.7 V,
DD
±0.65
±1
f = 800 kHz at 8 bit 3.75 MSPS, AV
DD
= 5 V,
I
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
f = 800 kHz at 4 bit 7 MSPS, AV = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
I
DD
±0.2
±0.4
±1
f = 800 kHz at 10 bit 2 MSPS, AV
DD
= 5 V, VREFP = 3.5 V,
I
±0.5
VREFM = 1.5 V, mono continuous
f = 800 kHz at 10 bit 2.5 MSPS, AV
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
= 5 V,
I
DD
–0.85
±0.5
±0.9
±0.6
±0.5
±0.5
±1
1.5
1.5
±1
f = 800 kHz at 10 bit 2.8 MSPS, AV
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
= 5 V,
I
DD
f = 800 kHz at 10 bit 2 MSPS, AV
VREFM = 0.9 V, mono continuous
= 3 V, VREFP = 1.7 V,
= 3 V, VREFP = 1.7 V,
I
DD
Differential linearity error
LSB
f = 800 kHz at 8 bit 3 MSPS, AV
VREFM = 0.9 V, mono continuous
I
DD
±1
f = 800 kHz at 8 bit 3.5 MSPS, AV
I
= 3 V, VREFP = 1.7 V,
DD
–0.8
1
VREFM = 0.9 V, mono continuous
f = 800 kHz at 8 bit 3.75 MSPS, AV
DD
= 5 V,
I
1
VREFP = 3.5 V, VREFM = 1.5 V, mono continuous
f = 800 kHz at 4 bit 7 MSPS, AV = 3 V, VREFP = 1.7 V,
VREFM = 0.9 V, mono continuous
I
DD
±0.2
±0.4
NOTE 5: Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
±5
UNIT
Before calibration
After system calibration, single-ended input
After system calibration, differential input
After internal calibration, single-ended input
After internal calibration, differential input
Before calibration
±0.4
±0.25
±2.5
±0.3
±5
Mid-scale error (see Note 6)
%FS
Offset error (see Note 6)
%FS
%FS
%FS
Gain error (see Note 6)
Before calibration
±5
Total unadjusted error (see Note 7)
Before calibration
±5
Delay time, RD↓, CSTART↑ to external
2ns
7.5
0.5 SYSCLK
SYSCLK↑, t
d(TRGL–ICLKH)
Delay time, RD↓ to start of conversion
2
ns
t
d(RDL–CONV1)
Internal OSC frequency
MHz
ns
Delay time, RD↑ to INT↑, t
1-kΩ pullup resistor, 10 pF, BDV
DD
= 5 V, use RD
10
4
d(RDH–INTZ)
At 25 pF, BDV
At 50 pF, BDV
= 5 V
= 5 V
DD
DD
5
At 100 pF, BDV
= 5 V
DD
7
Disable time, RD↑ to data invalid,
ns
t
At 25 pF, BDV
= 2.7 V
= 2.7 V
7
dis(DATAOUT)
DD
At 50 pF, BDV
DD
10
14
20
25
30
37
41
56
At 100 pF, BDV
DD
= 2.7 V
At 25 pF, BDV
= 5 V
= 5 V
DD
DD
At 50 pF, BDV
At 100 pF, BDV = 5 V
DD
Enable time, INT↓ to data valid,
ns
t
At 25 pF, BDV
= 2.7 V
= 2.7 V
en(DATAOUT)
DD
At 50 pF, BDV
DD
At 100 pF, BDV
DD
= 2.7 V
Auto powerdown = 1
Auto powerdown = 0
Auto powerdown = 1
Auto powerdown = 0
Auto powerdown = 1
Auto powerdown = 0
700
0
Delay time, mono interrupt mode pow-
er-up time, t
1(APDR)
ns
ns
ns
1000
0
Delay time, dual interrupt mode power-
up time, t
2(APD)
200
0
Delay time, INT↓ to powerdown, t
(APD)
Delay time, end of conversion to INT↓,
5
10
10
ns
ns
t
d(CONV-INTL)
Delay time, RD↓ to INT Hi-Z,
1-kΩ pullup resistor, 10 pF, BDV
= 5 V, Use CSTART
DD
t
d(RDL-INTZ)
Delay time, CSTART↑ to start of con-
version 1, t
2
4
2
ns
d1(CSTARTH-CONV)
Delay time, CSTART↑ to start of con-
version 2, t
0.2
1000
µs
d2(CSTARTH-CONV)
Delay time, RD↓ to sample,
SYSCLK
t
d(RDL-SAMPLE)
NOTES: 6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage
7. Total unadjusted error comprises linearity, zero, and full-scale errors
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10-Bit Mode
f = 800 kHz, at 10 bit 2 MSPS, AV
DD
= 5 V,
I
8.97
8.8
9.4
8.91
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
ENOB
THD
Effective number of bits
Total harmonic distortion
Signal-to-noise ratio
Bits
f = 800 kHz, at 10 bit 1.6 MSPS, AV = 3 V,
I
DD
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
f = 800 kHz, at 10 bit 2 MSPS, AV
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
= 5 V,
I
DD
–68.8 –64.5
–66.8 –64.5
58.1
dB
dB
dB
dB
f = 800 kHz, at 10 bit 1.6 MSPS, AV
= 3 V,
I
DD
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
f = 800 kHz, at 10 bit 2 MSPS, AV
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
= 5 V,
I
DD
56.4
54.4
56.2
54.2
SNR
f = 800 kHz, at 10 bit 1.6 MSPS, AV
= 3 V,
I
DD
55.6
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
f = 800 kHz, at 10 bit 2 MSPS, AV
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
= 5 V,
I
DD
57.8
SINAD
SFDR
Signal-to-noise ratio +distortion
Spurious free dynamic range
f = 800 kHz, at 10 bit 1.6 MSPS, AV
= 3 V,
I
DD
55.3
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
f = 800 kHz, at 10 bit 2 MSPS, AV
VREFP = 3.5 V, VREFM = 1.5 V, Mono continuous
= 5 V,
I
DD
–70.3 –67.5
–69.1 –66.5
f = 800 kHz, at 10 bit 1.6 MSPS, AV
= 3 V,
I
DD
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
8-Bit Mode
f = 800 kHz, at 8 bit 3 MSPS, AV
= 3 V,
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
I
DD
ENOB
Effective number of bits
7.93
Bits
THD
Total harmonic distortion
Signal-to-noise ratio
–64
49.2
49
dB
dB
dB
dB
SNR
SINAD
SFDR
Signal-to-noise ratio +distortion
Spurious free dynamic range
–65
4-Bit Mode
f = 800 kHz, at 4 bit 7 MSPS, AV
VREFP = 1.7 V, VREFM = 0.9 V, Mono continuous
= 3 V,
I
DD
ENOB
Effective number of bits
3.97
Bits
THD
Total harmonic distortion
–29
26
dB
dB
dB
dB
SINAD
SINAD
SFDR
Signal-to-noise ratio + distortion
Signal-to-noise ratio + distortion
Spurious free dynamic range
24
–30.5
Analog input
Cross talk rejection
68
120
75
dB
Full-power bandwidth, –3 dB
Full-power bandwidth, –1 dB
MHz
MHz
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution,
VREF = 3.5 V–1.5 V,
SYSCLK = 10 MHz
0.5
0
–0.5
–1
0
511
1023
Digital Output Code
Figure 20
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution,
VREF = 4 V–1 V,
SYSCLK = 12 MHz
0.5
0
–0.5
–1
0
127
255
Digital Output Code
Figure 21
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
4-Bit Resolution,
VREF = 4 V–1 V,
SYSCLK = 14 MHz
0.5
0
–0.5
–1
0
7
15
Digital Output Code
Figure 22
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution, VREF = 3.5 V–1.5 V,
SYSCLK = 10 MHz
0.5
0
–0.5
–1
0
511
1023
Digital Output Code
Figure 23
32
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, VREF = 4 V–1 V,
SYSCLK = 12 MHz
0.5
0
–0.5
–1
0
127
255
Digital Output Code
Figure 24
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution,
VREF = 4 V–1 V,
SYSCLK = 14 MHz
0.5
0
–0.5
–1
0
7
15
Digital Output Code
Figure 25
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution, AV
= 2.7 V,
VREF = 1.7 V–0.9 V, SYSCLK = 10 MHz
DD
0.5
0
–0.5
–1
0
511
1023
Digital Output Code
Figure 26
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, AV
= 3 V,
VREF = 1.7 V–0.9 V, SYSCLK = 10 MHz
DD
0.5
0
–0.5
–1
0
127
255
Digital Output Code
Figure 27
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, AV
VREF = 1.7 V–0.9 V, SYSCLK = 14 MHz
= 2.7 V,
DD
0.5
0
–0.5
–1
0
7
15
Digital Output Code
Figure 28
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
10-Bit Resolution, AV
= 2.7 V, VREFP = 1.7 V,
VREFM = 0.9 V, Internal Clock
DD
0.5
0
–0.5
–1
0
511
1023
Digital Output Code
Figure 29
35
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
8-Bit Resolution, AV
External Clock
= 2.7 V, REFP = 1.7 V, REFM = 0.9 V, 12 MHz
DD
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
127
255
Digital Output Code
Figure 30
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
0.2
4-Bit Resolution, AV
External Clock
= 2.7 V, REFP = 1.7 V, REFM = 0.9 V, 14 MHz
DD
0
–0.2
–0.4
–0.6
–0.8
–1
0
7
15
Digital Output Code
Figure 31
36
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
TYPICAL SUPPLY CURRENT
TYPICAL POWER DOWN CURRENT
vs
vs
FREQUENCY
TEMPERATURE
16
100
80
AV
DD
= 5.5 V at 90°C
14
12
10
8
AV
DD
= 5.5 V
AV
= 5.5 V at 25°C
DD
AV
= 5.5 V at 40°C
60
DD
AV
DD
= 2.7 V
AV
DD
= 3 V at 40°C
6
40
4
20
0
2
0
0
2
4
7
10
12
15
20
f – Clock Frequency – MHz
T – Temperature – °C
Figure 32
Figure 33
SPURIOUS FREE DYNAMIC RANGE
SIGNAL TO NOISE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
–68.5
–69
61
60
59
AV
DD
= 5 V, VREF+ = 4 V, VREF = 1 V
AV
DD
= 5 V, VREF+ = 3.5 V, VREF = 1.5 V
–69.5
AV
DD
= 5 V, VREF+ = 3.5 V, VREF = 1.5 V
–70
58
57
56
55
AV
DD
= 5 V, VREF+ = 4 V, VREF = 1.5 V
–70.5
AV
DD
= 3 V, VREF+ = 2 V, VREF = 1 V
–71
–71.5
–72
54
53
AV
DD
= 3 V, VREF+ = 2 V, VREF = 1 V
–72.5
50 100 200 300 400 500 600 700 800 900 1000
Analog Input Frequency – kHz
Figure 34
50 100 200 300 400 500 600 700 800 9001000
Analog Input Frequency – kHz
Figure 35
37
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TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
SIGNAL TO NOISE HARMONIC DISTORTION
EFFECTIVE NUMBER OF BITS
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
61
9.8
AV
= 5 V, VREF+ = 4 V, VREF = 1 V
AV
DD
= 5 V, VREF+ = 4 V, VREF = 1 V
DD
DD
60
59
9.6
9.4
9.2
AV
= 5 V, VREF+ = 3.5 V, VREF = 1.5 V
AV
= 5 V, VREF+ = 3.5 V, VREF = 1.5 V
DD
58
57
AV
DD
= 3 V, VREF+ = 2 V, VREF = 1 V
9
AV
= 3 V, VREF+ = 2 V, VREF = 1 V
56
55
DD
8.8
8.6
8.4
54
53
50 100 200 300 400 500 600 700 800 900 1000
50 100 200 300 400 500 600 700 800 900 1000
Analog Input Frequency – kHz
Figure 37
Analog Input Frequency – kHz
Figure 36
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
–67
–67.5
AV
DD
= 3 V, VREF+ = 2 V, VREF = 1 V
–68
–68.5
–69
AV
DD
= 5 V, VREF+ = 4 V, VREF = 1 V
–69.5
–70
AV
DD
= 5 V, VREF+ = 3.5 V, VREF = 1.5 V
–70.5
50 100 200 300 400 500 600 700 800 900 1000
Analog Input Frequency – kHz
Figure 38
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1562
2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL
CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN
SLAS162 – SEPTEMBER 1998
APPLICATION INFORMATION
1023
1111111111
See Notes A and B
1022
1021
1111111110
1111111101
V
FS
V
FT
= V
– 1/2 LSB
FS
513
512
1000000001
1000000000
V
ZT
= V + 1/2 LSB
ZS
511
0111111111
V
ZS
2
1
0
0000000010
0000000001
0000000000
0
0.0048 0.0096
2.4528 2.4576 2.4624
V – Analog Input Voltage – V
4.9056
4.9104 4.9152
I
NOTES: A. This curve is based on the assumption that V
ref+
and V have been adjusted so that the voltage at the transition from digital 0
ref–
to 1 (V ) is 0.0024 V and the transition to full scale (V ) is 4.908 V. 1 LSB = 4.8 mV.
ZT FT
B. The full-scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is
FS
ZS
the step whose nominal midstep value equals zero.
Figure 39. Ideal 12-Bit ADC Conversion Characteristics
39
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