TLV1570IDWG4_技术文档

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

features

applications

Fast Throughput Rate: 1.25 MSPS at 5 V,

625 KSPS at 3 V

Mass Storage and Hard Disk Drive

Automotive

Wide Analog Channel Input: 0 V to AV

Eight Analog Input Channels

Channel Auto-Scan

DD

Digital Servos

Process Control

General-Purpose DSP

Image Sensor Processing

Differential Nonlinearity Error: < ±1 LSB

Integral Nonlinearity Error: < ±1 LSB

Signal-to-Noise and Distortion Ratio: 57 dB

Single 2.7-V to 5.5-V Supply Operation

DW OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CH4

CH3

CH2

CH1

CH0

AIN

MO

CH5

CH6

CH7

Very Low Power: 40 mW at 5.5 V,

8 mW at 2.7 V

Autopower-Down: 300 µA Max

Software Power Down: 10 µA Max

DV

AV

DD

Glueless Serial Interface to TMS320 DSPs

and (Q)SPI Compatible Microcontrollers

DGND

AGND

REF

CS

FS

SCLK

SDIN

Programmable Internal Reference Voltage:

3.8-V Reference for 5-V Operation,

2.3-V Reference for 3-V Operation

SDOUT

description

The TLV1570 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a

high-speed 10-bit ADC, an on-chip reference, and a high-speed serial interface. The device contains an on-chip

control register allowing control of channel selection, conversion start, reference voltage levels, and power

down via the serial port. The MUX is independently accessible, which allows the user to insert a signal

conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and the ADC.

Therefore one signal conditioning circuit can be used for all eight channels.

The TLV1570 operates from a single 2.7-V to 5.5-V power supply. The device accepts an analog input range

from 0 V to AV

and digitizes the input at a maximum 1.25 MSPS throughput rate. Power dissipation is only

DD

8 mW with a 2.7-V supply or 40 mW with a 5.5-V supply. The device features an autopower-down mode that

automatically powers down to 300 µA, 10 ns after a conversion is performed. With software power down

enabled, the device is further powered down to only 10 µA.

The TLV1570 communicates with digital microprocessors via a simple 4- or 5-wire serial port that interfaces

directly to Texas Instruments TMS320 DSPs, and SPI and QSPI compatible microcontrollers without using

additional glue logic.

A very high throughput rate, a simple serial interface, and low power consumption make the TLV1570 an ideal

choice for high-speed digital signal processing requiring multiple analog inputs.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

SMALL OUTLINE

(DW)

SMALL OUTLINE

(PW)

0°C to 70°C

TLV1570CDW

TLV1570IDW

TLV1570CPW

TLV1570IPW

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

functional block diagram

AV

DD

MO

AIN

DV

DD

REFERENCE

REF

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

REF+

MUX

10-BIT

SAR ADC

REF–

AGND

SCLK

SDIN

CS

SDOUT

FS

I/O REGISTERS

AND CONTROL LOGIC

AGND

DGND

Terminal Functions

TERMINAL

NAME

AGND

AIN

AV

I/O

DESCRIPTION

NO.

14

20

15

Analog ground

I

ADC analog input

Analog supply voltage, 2.7 V to 5.5 V

Analog input channels 0 – 7

DD

CH0 – CH7

5,4,3,2,1,

18,17,16

I

CS

12

Chip select. A low level signal on CS enables the TLV1570. A high level signal on CS disables the device

and disconnects power to the TLV1570.

DGND

7

6

8

Digital ground

DV

FS

Digital supply voltage, 2.7 V to 5.5 V

DD

I

Frame sync. The falling edge of the frame sync pulse from a DSP indicates the start of a serial data frame

shifted out of the TLV1570. FS is pulled high when interfaced to a microcontroller.

MO

19

13

O

I

On-chip MUX analog output

REF

Reference voltage input. The voltage applied to REF defines the input span of the TLV1570. In external

reference mode, a 0.1 µF decoupling capacitor must be placed between the reference and AGND. This is

not required for internal reference mode.

SCLK

SDIN

9

I

Serial clock input. SCLK synchronizes the serial data transfer and is also used for internal data conversion.

Serial data input used to configure the internal control register.

10

11

SDOUT

O

Serial data output. A/D conversion results are output at SDOUT.

2

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

detailed description

analog-to-digital converter

The TLV1570 ADC uses the SAR architecture described in this section. The CMOS threshold detector in the

successive-approximation conversion system determines the value of each bit by examining the charge on a

seriesofbinary-weightedcapacitors(seeFigure1). Inthefirstphaseoftheconversionprocess, theanaloginput

is sampled by closing the S switch and all S switches simultaneously. This action charges all of the capacitors

C

T

to the input voltage.

S

C

Threshold

Detector

To Output

Latches

512

Node 512

256

128

8

4

2

1

REF+

REF–

S

T

V

I

NOTE: REF– is tied to AGND

Figure 1. Simplified Model of the Successive-Approximation System

In the next phase of the conversion process, all S and S switches are opened and the threshold detector

T

C

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)

voltage (REF– is tied to AGND). In the switching sequence, ten capacitors are examined separately until all ten

bits are identified and then the charge-convert sequence is repeated. In the first step of the conversion phase,

the threshold detector looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the

REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the

voltageatthesummingnodeisgreaterthanthetrippointofthethresholddetector(approximatelyone-halfV ),

CC

a bit 0 is placed in the output register and the 512-weight capacitor is switched to REF–. If the voltage at the

summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the

512-weight capacitor remains connected to REF+ through the remainder of the successive-approximation

process. The process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the

line until all bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

In the case of the TLV1570, REF– is tied to ground and REF+ is connected to the REF input.

The TLV1570 can be programmed to use the on-chip internal reference (DI6=1). The user can select between

two values of internal reference, 2.3 V or 3.8 V, using the control bit DI5.

During internal reference mode, the reference voltage is not output on the REF pin. Therefore it cannot be

decoupled to analog ground (AGND), which acts as the negative reference for the ADC, using an external

capacitor. Hence this mode requires the ground noise to be very low. The REF pin can be left open in this mode.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

sampling frequency, f

s

The TLV1570 requires 16 SCLKs for each sampling and conversion, therefore the equivalent maximum

sampling frequency achievable with a given SCLK frequency is:

f

= (1/16)f

SCLK

s(MAX)

power down

The TLV1570 offers two different power-down options. With autopower-down mode enabled, (DI4=0) the ADC

proceeds to power down if FS is not detected on the 17th falling SCLK edge of a cycle (a cycle starts with FS

being detected on a falling edge of SCLK) in DSP mode and after 16 SCLKs in µC mode. The TLV1570 will

recover from auto power down when FS goes high in DSP mode or when the next SCLK comes in µC mode.

In the case of software power down, the ADC goes to the software power-down state one cycle after CR.DI15

is set to 1. Unlike autopower down which recovers in 1 SCLK, software power down takes 16 SCLKs to recover.

SOFTWARE

DESCRIPTION

AUTOPOWER DOWN

POWERDOWN

CS = DV

DD

Maximum power down dissipation current

Comparator

300 µA

10 µA

Power down

Active

Powerdown

Not saved

1 µs

†

Clock buffer

Reference

Register

Not saved

1 SCLK

Minimum power down time

Minimum resume time

1 SCLK

800 ns

DSP mode

No FS present one SCLK after previous conversion completed

CR.DI15 set to 1

Power down

Microprocessor mode (FS = 1) SCLK stopped after previous conversion completed

DSP mode FS present

Microprocessor mode (FS = 1) SCLK present

Only in DSP mode is input buffer of clock in power-down mode.

Power up

†

‡

Thesoftwarepowerdownenable/disablebitisnotacteduntilthestartofthenextcycle(seesectionconfiguringtheTLV1570formoreinformation.

configuring the TLV1570

The TLV1570 is to be configured by writing the control bits to SDIN. The configuration will not take affect until

the next cycle. A new configuration is needed for each conversion. Once the channel input and other options

are selected, the conversion takes place in the next cycle. Conversion results are shifted out as conversion

progresses ( see Figure 2).

One Cycle

Second Cycle

17

32

SCLK

t

conv

s

conv

s

Configure Data 1

Configure Data 2

SDIN

SDOUT

Result 0

Result 1

Figure 2. TLV1570 Configuration Cycle Timing

4

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

configuration register (CR) definition

BIT

DESCRIPTION

5 V

3 V

Software power down:

X

DI15

DI14

0:

1:

Normal

Power down enabled

X

Reads out values of the internal register, 1 – read. Only DI15 – DI1 are read out.

X

These two bits select the self-test voltage to be applied to the ADC input during next clock cycle:

00: Allow AIN to come in normally

01: Apply AGND to AIN

10: Apply VREF/2 to AIN

11: N/A

DI13, DI12

Choose speed application

X

DI11

DI10

0:

1:

High speed (higher power consumption)

Low speed (lower power consumption)

This bit enables channel auto-scan function.

0:

1:

Autoscan disabled

Autoscan enabled

DI9 – DI7 These three bits select which of the eight DI9, DI8 These two bits select the channel swept

channels is to be used (if DI10 = 0).

sequence used by auto scan mode (if DI10 = 1)

Analog inputs CH0, CH1, CH2, ….., CH7

sequentially selected

000: Channel 0 selected as input

00:

Analog inputs CH1, CH3, CH5, CH7

001: Channel 1 selected as input

010: Channel 2 selected as input

011: Channel 3 selected as input

01:

sequentially selected

Analog inputs CH0, CH2, CH4, CH6

sequentially selected

10:

DI9, DI8, DI7

Analog inputs CH7, CH6, CH5, ….., CH0

sequentially selected

11:

100: Channel 4 selected as input

101: Channel 5 selected as input

110: Channel 6 selected as input

111: Channel 7 selected as input

Selects Internal or external reference voltage:

DI7 Auto-scan reset

0:

1:

No reset

Reset autoscan sequence

X

DI6

DI5

0:

1:

External

Internal

Selects internal reference voltage value to be applied to the ADC during next conversion cycle.

0:

1:

2.3 V

3.8 V

X

Enables/disables autopower-down function:

DI4

DI3

1:

0:

Enable

Disable

Performance optimizer – linearity

0: AV

1: AV

= 5.5 V to 3.6 V

= 3.5 V to 2.7 V

X

DD

DI2

DI1

DI0

Always write 0 (reserved bit)

X

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

initialization-software sequence

This sequence shows the default settings, unless otherwise specified. The ADC requires that the user write to

it every cycle. There is a cycle delay before control bits are implemented.

Example 1. Normal Sample Mode With Internal Reference

WRITE TO CHANNEL OUTPUT FROM

CYCLE

COMMENT

SDIN

0040h

01C0h

0040h

8040h

0040h

SAMPLED

SDOUT

1st

2nd

3rd

4th

5th

N/A

3

Invalid

No analog input channel sampled

Invalid

From Channel 3

From Channel 0

Invalid

0

Software power down enabled

N/A

Software power-down mode, no analog input channel sampled

Recovery time, no analog input channel sampled (16 SCLKs if AV

= 5 V and

DD

Wait 800 ns

f

= 20 MHz)

CLK

6th

7th

0140h

0040h

N/A

2

Invalid

Recovery time, no analog input channel sampled

From Channel 2

Example 2. Auto Scan Mode

WRITE TO CHANNEL OUTPUT FROM

CYCLE

COMMENT

SDIN

0480h

0400h

SAMPLED

SDOUT

1st

2nd

3rd

4th

N/A

0

Invalid

Autoscan reset enabled, no analog input channel sampled

No analog input channel sampled

Invalid

From Channel 0

From Channel 1

From Channel 2

From Channel 3

From Channel 4

From Channel 5

From Channel 6

From Channel 7

From Channel 0

1

5th

2

6th

3

7th

4

8th

5

9th

6

10th

11th

7

0

NOTE: If software power down is enabled during auto-scan mode, the next channel in the sequence is skipped.

6

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

initialization-software sequence (continued)

Example 3. Auto-Scan Mode

This example shows a change in sequence in the middle of the current sequence. The following shows that after

the initial autoscan reset, a reset is not necessary again when switching channel sequences.

CYCLE WRITE TO CHANNEL OUTPUT FROM

COMMENT

SDIN

0480h

0400h

0700h

SAMPLED

SDOUT

1st

2nd

3rd

4th

N/A

0

N/A

No analog input channel sampled

Autoscan reset enabled, no analog input channel sampled

Start of sequence 0

From Channel 0

From Channel 1

From Channel 7

From Channel 6

From Channel 5

From Channel 4

From Channel 3

From Channel 2

From Channel 1

From Channel 0

1

Enable channel sequence 3 (no auto-scan reset required)

Start of sequence 3

5th

7

6th

6

7th

5

8th

4

9th

3

10th

11th

12th

2

1

0

Example 4. Auto-Scan Mode

This example shows a switch in sequence in the course of a sequence. The following shows that a particular

sequence does not have to be continued if remaining channels do not need to be sampled (i.e., only channel

1 through channel 5 sampled, not channels 6, 7, 8)

CYCLE WRITE TO CHANNEL OUTPUT FROM

COMMENT

SDIN

0480h

0400h

0480h

0400h

SAMPLED

SDOUT

1st

2nd

3rd

4th

N/A

0

N/A

No analog input channel sampled

Autoscan reset enabled, no analog input channel sampled

From Channel 0

From Channel 1

From Channel 2

From Channel 3

From Channel 4

From Channel 5

From Channel 0

From Channel 1

From Channel 2

1

5th

2

6th

3

7th

4

8th

5

Autoscan reset enabled

9th

0

Sequence is reset to channel 0

10th

11th

1

2

The TLV1570 is a 800-ns 10-bit 8-analog input channel analog-to-digital converter with a throughput of up to

1.25 MSPS at 5 V and up to 625 KSPS at 3 V respectively. To run at its fastest conversion rate, it must be clocked

at 20 MHz at 5-V or 10 MHz at 3-V. The TLV1570 can be easily interfaced to microcontrollers, ASICs, DSPs,

or shift registers. The TLV1570 serial interface is designed to be fully compatible with serial peripheral interface

(SPI) and TMS320 DSP serial ports. No additional hardware is required to interface between the TLV1570 and

a microcontroller (µCs) with a SPI serial port or a TMS320 DSP. However, the speed is limited by the SCLK rate

of the µC or the DSP.

7

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

initialization-software sequence (continued)

The TLV1570 interfaces to a DSP over five lines: CS, SCLK, SDOUT, SDIN, and FS, and interfaces to a µC over

fourlines:CS, SCLK, SDOUT, andSDIN. TheFSinputshouldbepulledhighinµCmode. Thedeviceisin3-state

and power-down mode when CS is high. After CS falls, the TLV1570 checks the FS input at the CS falling edge

to determine the operation mode. If FS is low, DSP mode is set, otherwise µC mode is set.

TLV1570

TMS320

TLV1570

µC

CS

XF

I/O Terminal

SCLK

FS

CLKX

CLKR

FSX

FSR

DX

SCLK

FS

DV

DD

SDIN

DX

DR

SDOUT

Figure 3. DSP to TLV1570 Interface

Figure 4. µC to TLV1570 Interface

grounding and decoupling considerations

General practices should apply to the PCB design to limit high frequency transients and noise that are fed back

into the supply and reference lines (see Figure 5). This requires that the supply and reference pins be sufficiently

bypassed. In most cases 0.1 µF ceramic chip capacitors are adequate to keep the impedance low over a wide

frequency range. Since their effectiveness depends largely on the proximity to the individual supply pin. They

should be placed as close to the supply pins as possible.

To reduce high frequency and noise coupling, it is highly recommended that digital and analog ground be

shorted immediately outside the package. This can be accomplished by running a low impedance line between

DGND and AGND, under the package.

TLV1570

DV

AV

DD

100 nF

DGND

AGND

REF

Figure 5. Placement of Decoupling Capacitors

power supply ground layout

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.

Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected

together at the low-impedance power-supply source. The best ground connection may be achieved by

connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground

currents are well managed.

8

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

simplified analog input analysis

Using the equivalent circuit in Figure 6, the time required to charge the analog input capacitance from 0 to V

S

within 1/2 LSB, t (1/2 LSB), can be derived as follows:

ch

The capacitance charging voltage is given by:

–t

R C

t

ch

1–e

i

V

C(t)

S

Where:

(1)

R = R + R

i

t

s

R = R

+ R

i(MUX)

i

i(ADC)

t

= Charge time

ch

The input impedance R is 718 Ω at 5 V, and is higher (~1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given

i

by:

(2)

V (1/2 LSB) = V – (V /2048)

C

S

Equating equation 1 to equation 2 and solving for cycle time t gives:

c

–t

R C

t

ch

1–e

i

V

2048

V

S

(3)

and time to change to 1/2 LSB (minimum sampling time) is:

(1/2 LSB) = R × C × ln(2048)

t

ch

t

i

Where:

ln(2048) = 7.625

Therefore, with the values given, the time for the analog input signal to settle is:

(1/2LSB)=(R + 718 Ω)× 15 pF × ln(2048)

(4)

(5)

(6)

t

ch

s

This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.

(1/2 LSB) ≤ 6x 1/f

t

ch

(SCLK)

Therefore the maximum SCLK frequency is:

Max(f ) = 6/t (1/2 LSB) = 6/(ln(2048) × R × C )

(SCLK)

ch

t

i

†

Driving Source

TLC1570

V

= Input Voltage at AIN

= External Driving Source Voltage

= Source Resistance

I

S

s

MO

R

i(MUX)

AIN

R

C

V

R

s

i(ADC)

V

I

= Input Resistance of ADC

= Input Resistance (MUX on resistance)

= Input Capacitance

i(ADC)

i(MUX)

V

S

V

C

i

C

= Capacitance Charging Voltage

i

C

15 pF

†

Driving source requirements:

•

Noise and distortion for the source must be equivalent to the resolution of the converter.

R must be real at the input frequency.

s

Figure 6. Equivalent Input Circuit Including the Driving Source

9

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

definitions of specifications and terminology

integral nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.

The point used as zero occurs 1/2 LSB before the first code transition. The full scale point is defined as level

1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to

the true straight line between these two points.

differential nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.

A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

zero offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition

should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual

difference between first and last code transitions and the ideal difference between first and last code transitions.

signal-to-noise ratio + distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components

below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in

decibels.

effective number of bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

It is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective

number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its

measured SINAD.

total harmonic distortion (THD)

Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the

measured input signal and is expressed as a percentage or in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak

spurious signal.

10

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, AGND to AV , DGND to DV

Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV +0.3 V

Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV +0.3 V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV +0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V

DD

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C

J

Operating free-air temperature range, T : TLV1570C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

TLV1570I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN

2.7

TYP

MAX

5.5

UNIT

V

Analog supply voltage, AV

(see Note 1)

DD

Digital supply voltage, DV

2.7

5.5

V

DD

NOTE 1: Abs (AV

– DV ) < 0.5 V

DD

analog inputs

MIN

TYP

MAX

UNIT

Analog input voltage, AIN

AGND

V

REF

V

DV

= 3.3 V to 2.7 V

= 5.5 V to 4.5 V

55% AV

AV

DD

Reference input voltage, REF

V

60% AV

AV

DD

digital inputs

MIN

TYP

MAX

UNIT

V

High-level input voltage, V

IH

DV

= 2.7 V to 5.5 V

= 5.5 V to 4.5 V

= 3.6 V to 2.7 V

= 5.5 V to 4.5 V

= 3.6 V to 2.7 V

= 5.5 V to 4.5 V

2.1

DD

Low-level input voltage, V

0.8

20

10

V

IL

Input SCLK frequency

MHz

ns

1

23

46

23

SCLK pulse duration, clock high, t

w(SCLKH)

SCLK pulse duration, clock low, t

ns

w(SCLKL)

DV

= 3.6 V to 2.7 V

46

DD

electrical characteristics,over recommended operating free-air temperature range, supply

voltages, and reference voltages (unless otherwise noted)

digital specifications (SDOUT at 25 pF)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic inputs

I

High-level input current

Low-level input current

Input capacitance

DV

= 5 V,

V = 5 V

1

–1

15

µA

pF

IH

DD

I

V = 0 V

I

IL

C

Control inputs

5

I

Logic outputs

11

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

V

High-level output voltage

I

= 50 µA – 0.5 mA

DV –0.4

DD

V

OH

Low-level output voltage

0.4

1

V

OL

I

High-impedance-state output current

Low-impedance-state output current

Output capacitance

µA

pF

OZH

–1

OZL

C

5

O

12

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

electrical characteristics, over recommended operating free-air temperature range, supply

voltages, and reference voltages (unless otherwise noted) (continued)

dc specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

10

Bits

Accuracy

Integral nonlinearity, INL

Differential nonlinearity, DNL

Offset error

Best fit

±0.6

±1

LSB

±0.65

E

±0.1 ±0.15 %FSR

O

Gain error

±0.1

±0.2 %FSR

G

Analog input

C

Input capacitance

15

20

±1

pF

µA

Ω

i

I

Input leakage current

V

= 0 V to AV

lkg

AIN DD

DV

= 3 V,

= 5 V,

= 3 V,

= 5 V,

AV

= 3 V

= 5 V

= 3 V

= 5 V

265

235

158

140

780

450

465

268

DD

R

Input MUX ON resistance

i(MUX)

i(ADC)

Ω

Voltage reference

REF Internal reference voltage

Internal reference mode, V

= 3 V

= 5 V

2.08

3.48

2.26

3.82

100

2.48

4.15

V

DD

Temperature coefficient

Input resistance

ppm/°C

kΩ

r

External reference mode

3

i

C

Input capacitance

300

pF

i(VR)

Power supply

†

‡

AV

= 2.7 V, DV

= 5.5 V, DV

= 2.7 V, DV

= 5.5 V, DV

= 2.7 V,

= 5.5 V,

= 2.7 V

= 5.5 V

f

= 10 MHz

= 20 MHz

3

7.2

8

5

8.5

13

mA

DD

SCLK

I

+ I

Operating supply current

Power dissipation

DD REF

SCLK

mW

P

D

40

47

CS = AV

DD

3

10

AVDD = 2.7 V

AVDD = 5.5 V

µA

CS = AGND

500

3

Software

I + I

DD REF

CS = AV

DD

CS = AGND

10

Supply current in

power down

2000

175

200

AVDD = 2.7V

AVDD = 5.5V

275

300

µA

Auto

I + I

DD REF

†

‡

I

= 0.7 mA typ.

= 1.5 mA typ.

REF

13

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

electrical characteristics, over recommended operating free-air temperature range, supply

voltages, and reference voltages (unless otherwise noted) (continued)

ac specifications

PARAMETER

TEST CONDITIONS

External reference

MIN

58

TYP

61

MAX

UNIT

f = 1.25 MSPS,

s

AV

DD

= 5 V

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

External reference

Internal reference

53

56

f = 100 kHz,

i

70% of FS

56

61

f = 625 KSPS,

s

AV

= 3 V

53

55

DD

SNR

Signal-to-noise ratio

dB

61

f = 1.25 MSPS,

s

AV

= 5 V

56

DD

f = 50 kHz,

i

90% of FS

61

f = 625 KSPS,

s

AV

= 3 V

55

DD

55

53

52

58

f = 1.25 MSPS,

s

AV

= 5 V

55

DD

f = 100 kHz,

i

70% of FS

58

f = 625 KSPS,

s

AV

= 3 V

54

DD

SINAD Signal-to-noise ratio + distortion

dB

59

f = 1.25 MSPS,

s

AV

= 5 V

55

DD

f = 50 kHz,

i

90% of FS

60

f = 625 KSPS,

s

AV

= 3 V

55

DD

–60

–70

–60

–66

–64

–72

–63

–68

–63

–73

–61

–68

–66

–75

–65

–70

9.3

8.9

9.3

8.8

9.5

8.9

9.5

8.9

–55

–58

–55

–58

f = 1.25 MSPS,

s

AV

= 5 V

DD

f = 100 kHz,

i

70% of FS

f = 625 KSPS,

s

AV

= 3 V

DD

THD

Total harmonic distortion

Spurious-free dynamic range

Effective number of bits

f = 1.25 MSPS,

s

AV

= 5 V

DD

f = 50 kHz

i

90% of FS

f = 625 KSPS,

s

AV

= 3 V

DD

–57

–59

–57

–60

f = 1.25 MSPS,

s

AV

= 5 V

DD

f = 100 kHz,

i

70% of FS

f = 625 KSPS,

s

AV

= 3 V

DD

SFDR

f = 1.25 MSPS,

s

AV

= 5 V

DD

f = 50 kHz,

i

90% of FS

f = 625 KSPS,

s

AV

= 3 V

DD

8.8

8.6

8.4

f = 1.25 MSPS,

s

AV

= 5 V

DD

f = 100 kHz,

i

70% of FS

f = 625 KSPS,

s

AV

= 3 V

DD

ENOB

f = 1.25 MSPS,

s

AV

= 5 V

DD

f = 50 kHz,

i

90% of FS

f = 625 KSPS,

s

AV

= 3 V

DD

14

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

ac specifications (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Input

Channel-to-channel crosstalk

–75

15

dB

–1 dB full-scale input sine wave

12

15

MHz

BW

Full-power bandwidth

Small-signal bandwidth

–3 dB full-scale input sine wave

25

–1 dB

–3 dB

20

35

AV

= 5 V

= 3 V

0.0625

1.25

DD

f

s

Sampling rate

MSPS

0.625

DD

†

timing requirements

PARAMETER

TEST CONDITIONS

MIN

50

TYP

MAX

UNIT

DV

= 5.5 V to 4.5 V

= 3.6 V to 2.7 V

ns

DD

t

SCLK cycle time

c(SCLK)

100

t

Pulse duration, chip select

Sampling period

ns

w(1)

(s)

SLCK

cycles

t

6

SLCK

cycles

t

Conversion period

10

(conv)

t

Setup time, FS to SCLK falling edge in DSP mode

Hold time, FS to SCLK falling edge in DSP mode

Setup time, FS to CS falling edge in DSP mode

5

2

ns

su(1)

h(1)

su(2)

h(2)

d(1)

d(2)

d(3)

5.5

9

Hold time, FS to CS falling edge in DSP mode

Delay time, FS falling edge to next SCLK falling edge in DSP mode

Delay time, SCLK rising edge after CS falling edge in µC mode

6

4

Delay time, output after SCLK rising edge in µC mode and DSP

mode

10

20

t

Setup time, serial input data to SCLK falling edge

Hold time, serial input data to SCLK falling edge

Rise time

10

4

ns

su(3)

h(3)

r

3

200

†

Specifications subject to change without notice.

15

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

PARAMETER MEASUREMENT INFORMATION

t

c(SCLK)

1

2

3

SCLK

CS

t

w(1)

t

su(1)

t

h(1)

t

d(1)

FS

t

h(3)

su(3)

t

h(2)

su(2)

DI15

MSB

DI14

DI13

SDIN

t

d3

0

SDOUT

Figure 7. DSP Mode Timing Diagrams

t

1

2

3

4

d(2)

SCLK

CS

t

w(1)

FS

t

h(3)

su(3)

DI15

MSB

DI14

DI13

DI12

SDIN

t

d(3)

0

SDOUT

Figure 8. µC Mode Timing Diagrams

16

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

ANALOG MUX INPUT RESISTANCE

TOTAL SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

vs

FREE-AIR TEMPERATURE

350

300

8

6

4

AV

DD

= 5.5 V

AV

DD

= 2.7 V, AIN = 2 V

250

200

AV

DD

= 5.5 V, AIN = 3.8 V

AV

DD

= 2.7 V

150

100

2

0

50

0

–45

25

90

–45

25

90

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 9

Figure 10

SUPPLY CURRENT

vs

GAIN

vs

CLOCK FREQUENCY (SCLK)

INPUT FREQUENCY

8

7

1

V

= 5.5 V

DD

0

6

–1

––2

–3

V

= 5 V, AIN = 90% of FS,

5

4

3

DD

REF = 5 V, T = 25°C

A

V

= 2.7 V

2

–4

–5

1

0

2.5

5

6.2 7.5

10

12.5 15.4 18

20

0

1

10

100

f – Clock Frequency – MHz

f – Input Frequency – MHz

Figure 11

Figure 12

17

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

0.8

0.6

0.4

V

= 2.7 V, Internal REF = 2.3 V,

CC

SCLK = 10 MHz,

= 25°C

T

A

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 13

INTEGRAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

V

= 2.7 V, Internal REF = 2.3 V,

CC

SCLK = 10 MHz,

= 25°C

0.8

0.6

0.4

0.2

T

A

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 14

18

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

0.8

0.6

0.4

V

= 2.7 V, External REF = 2.7 V,

CC

SCLK = 10 MHz,

= 25°C

T

A

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 15

INTEGRAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

V

= 2.7 V, External REF = 2.7 V,

CC

SCLK = 10 MHz,

= 25°C

0.8

0.6

0.4

T

A

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 16

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

0.8

0.6

V

= 5.5 V, Internal REF = 3.8 V,

CC

SCLK = 20 MHz,

= 25°C

T

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 17

INTEGRAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

0.8

0.6

0.4

0.2

0

V

= 5.5 V, Internal REF = 3.8 V,

CC

SCLK = 20 MHz,

= 25°C

T

A

–0.2

–0.4

–0.6

–0.8

0

511

1023

Samples

Figure 18

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

0.8

0.6

V

= 5.5 V, External REF = 5.5 V,

CC

SCLK = 20 MHz,

= 25°C

T

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 19

INTEGRAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

V

= 5.5 V, External REF = 5.5 V,

CC

SCLK = 20 MHz,

= 25°C

0.8

0.6

0.4

T

A

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 20

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

0.8

0.6

V

= 5.5 V, External REF = 3.3 V,

CC

SCLK = 20 MHz,

= 25°C

T

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

511

1023

Samples

Figure 21

INTEGRAL NONLINEARITY ERROR

vs

DIGITAL OUTPUT CODE

1

0.8

0.6

0.4

0.2

0

V

= 5.5 V, External REF = 3.3 V,

CC

SCLK = 20 MHz,

= 25°C

T

A

–0.2

–0.4

–0.6

–0.8

0

511

1023

Samples

Figure 22

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

INPUT FREQUENCY

12

10

8

12

10

8

AV

DD

= DV

= 5 V,

DD

External REF = 5 V

AV

DD

= DV

= 3 V,

DD

External REF = 3 V

6

4

2

0

100

200

300

400

500

600

0

50

100

150

200

250

300

f – Input Frequency – kHz

Figure 23

Figure 24

EFFECTIVE NUMBER OF BITS

vs

INPUT FREQUENCY

10

9

8

9

8

7

6

7

6

5

4

3

2

5

4

3

2

AV

DD

= DV

= 3 V,

AV

DD

= DV

= 5 V,

DD

Internal REF = 2.3 V

DD

Internal REF = 3.8 V

1

0

1

0

50

100

150

200

250

300

0

100

200

300

400

500

600

f – Input Frequency – kHz

f – Input Frequency _ kHz

Figure 25

Figure 26

23

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM

vs

FREQUENCY

AIN = 200 kHz,

SCLK = 20 MHz,

0

AV

= DV

= 3 V,

DD

Internal REF = 2.3 V

–20

–40

–60

–80

–100

–120

0

100

200

300

400

500

600

Frequency – KHz

Figure 27

FAST FOURIER TRANSFORM

vs

FREQUENCY

AIN = 200 kHz,

SCLK = 20 MHz,

0

AV

= DV

= 5 V,

DD

Internal REF = 3.8 V

–20

–40

–60

–80

–100

–120

0

100

200

300

400

500

600

Frequency – KHz

Figure 28

24

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM

vs

FREQUENCY

AIN = 200 kHz,

SCLK = 20 MHz,

0

AV

= DV

= External REF = 3 V

DD

–20

–40

–60

–80

–100

–120

0

100

200

300

Frequency – KHz

400

500

600

Figure 29

FAST FOURIER TRANSFORM

vs

FREQUENCY

AIN = 200 kHz,

0

SCLK = 20 MHz,

AV = DV = External REF = 5 V

DD

–20

–40

–60

–80

–100

–120

0

100

200

300

400

500

600

Frequency – KHz

Figure 30

25

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

Figure 31. Typical Timing Diagram for DSP Application

26

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TLV1570

2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER

SLAS169B – DECEMBER 1997– REVISED OCTOBER 2000

TYPICAL CHARACTERISTICS

Figure 32. Typical Timing Diagram for µC Application

27

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device

TLV1570CDW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

20

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLV1570CDWG4

TLV1570CDWR

TLV1570CDWRG4

TLV1570CPW

SOIC

DW

PW

DW

PW

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

SOIC

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLV1570CPWG4

TLV1570CPWR

TLV1570CPWRG4

TLV1570IDW

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLV1570IDWG4

TLV1570IPW

SOIC

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLV1570IPWG4

TLV1570IPWR

TLV1570IPWRG4

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

TLV1570CPWR

TLV1570IPWR

TSSOP

PW

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV1570CPWR

TLV1570IPWR

TSSOP

PW

20

2000

346.0

33.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

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Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

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acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

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such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

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products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLV1570IDWG4
厂家：	TEXAS INSTRUMENTS
描述：	8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20, GREEN, SOIC-20 光电二极管转换器
文件：	总32页 (文件大小：641K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV1570IDWG4 [TI]

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