TLV1702-Q1 [TI]
汽车类双路高电压、低功耗比较器;
| 型号： | TLV1702-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类双路高电压、低功耗比较器 比较器 |
| 文件： | 总20页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV1702-Q1
ZHCSED6 –NOVEMBER 2015
TLV1702-Q1 2.2V 至 36V 微功耗比较器
1 特性
3 说明
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
TLV1702-Q1 器件可提供宽电源电压范围、轨到轨输
入、低静态电流和低传播延迟。 凭借符合行业标准且
在极小型封装内集成的上述特性，此类器件成为当前市
场中的最佳通用比较器。
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
–
–
器件人体模型 (HBM) 分类等级 1C
集电极开路输出具有能够将输出拉至任意电压轨（最多
可高出负电源 36 V）且不受 TLV1702-Q1 电源电压影
响的优势。
器件充电器件模型 (CDM) 分类等级 C6
•
•
•
•
•
•
电源电压范围：2.2V 至 36V 或 ±1.1V 至 ±18V
低静态电流：每个比较器 55µA
输入共模范围包括两个电源轨
低传播延迟：560ns
该器件是一款双通道微功耗比较器。 低输入偏移电
压、低输入偏置电流、低电源电流和集电极开路配置使
TLV1702-Q1 器件能够灵活处理从简单电压检测到驱
动单个继电器的多数应用。
低输入偏移电压：300µV
集电极开路输出：
–
最多可高出负电源电压 36V 且不受电源电压影
响
该器件在 –40°C 至 +125°C 的扩展级工业温度范围内
额定运行。
•
•
工业温度范围：-40°C 至 +125°C
器件信息(1)
小型封装：
部件号
封装
封装尺寸（标称值）
–
双列：超薄小外形尺寸 (VSSOP)-8
超薄小外形尺寸封装
(VSSOP) (8)
TLV1702-Q1
3.00mm × 3.00mm
2 应用范围
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
•
•
•
•
•
过压和欠压检测器
窗口比较器
过流检测器
零交叉检测器
针对以下应用的系统监控：
–
–
–
–
–
电源
白色家电
工业传感器
汽车
医疗
TLV1702-Q1 用作窗口比较器
稳定传播延迟与温度
V
(PULLUP)
1200n
V
I
18 V Low-to-High
V
S
R
(PULLUP)
V
(th+)
18 V High-to-Low
+
1000n
V
V
1
(th+)
½
V
O
2.2 V Low-to-High
Device
V
(thœ)
_
800n
600n
400n
200n
2.2 V High-to-Low
t
t
GND
V
V
O
I
V
S
V
(PULLUP)
+
½
Device
_
(thœ)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
GND
C012
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS890
TLV1702-Q1
ZHCSED6 –NOVEMBER 2015
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Related Products ................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics.......................................... 6
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
9
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 器件和文档支持 ..................................................... 15
12.1 文档支持................................................................ 15
12.2 社区资源................................................................ 15
12.3 商标....................................................................... 15
12.4 静电放电警告......................................................... 15
12.5 Glossary................................................................ 15
13 机械、封装和可订购信息....................................... 15
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 11 月
*
最初发布版本。
2
Copyright © 2015, Texas Instruments Incorporated
TLV1702-Q1
www.ti.com.cn
ZHCSED6 –NOVEMBER 2015
5 Related Products
DEVICE
FEATURES
TLC3702-Q1
TLC3704-Q1
TLV3012-Q1
TLV3501-Q1
TLV3502-Q1
TLV3701-Q1
TLV3702-Q1
REF50xx-Q1
TL4050xx-Q1
TLVH431-Q1
Push-Pull, 20 µA, 20 mA drive
Push-Pull, 5 µA, Integrated 1.242-V Reference
Push-Pull, 3.2 mA, 4.5-ns Propagation Delay
Push-Pull, 560 nA, Reverse Battery to 16 V
Series Reference, 0.1% Tolerance, 8 ppm/°C
Shunt Reference, 0.1% Tolerance, 50 ppm/°C
Adjustable Shunt Reference 1.24 to 18 V
Copyright © 2015, Texas Instruments Incorporated
3
TLV1702-Q1
ZHCSED6 –NOVEMBER 2015
www.ti.com.cn
6 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
1OUT
1INœ
1IN+
V-
1
2
3
4
8
7
6
5
V+
2OUT
2INœ
2IN+
Pin Functions
PIN
I/O
DESCRIPTION
NAME
1IN+
2IN+
1IN–
2IN–
1OUT
2OUT
V+
NO.
3
I
I
Noninverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 1
Inverting input, channel 2
Output, channel 1
5
2
I
6
I
1
O
O
—
—
7
Output, channel 2
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
4
Copyright © 2015, Texas Instruments Incorporated
TLV1702-Q1
www.ti.com.cn
ZHCSED6 –NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40 (±20)
(VS+) + 0.5
±10
UNIT
V
Supply voltage
Voltage(2)
Current(2)
(VS–) – 0.5
V
Signal input pins
mA
mA
°C
Output short-circuit(3)
Continuous
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
–55
–65
150
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground; one comparator per package.
7.2 ESD Ratings
VALUE
±1000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2 (±1.1)
–40
NOM
MAX
36 (±18)
125
UNIT
Supply voltage VS = (VS+) – (VS–)
Specified temperature
V
°C
7.4 Thermal Information
TLV1702-Q1
DGK (VSSOP)
8 PINS
199
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
89.5
120.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22
ψJB
118.7
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
5
TLV1702-Q1
ZHCSED6 –NOVEMBER 2015
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7.5 Electrical Characteristics
at TA = 25°C, VS = 2.2 V to 36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
TA = 25°C, VS = 2.2 V
±0.5
±0.3
±3.5
±2.5
±5.5
±20
mV
mV
VOS
Input offset voltage
TA = 25°C, VS = 36 V
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = 25°C
mV
dVOS/dT
PSRR
Input offset voltage drift
±4
15
20
μV/°C
μV/V
μV/V
100
Power-supply rejection ratio
TA = –40°C to +125°C
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
TA = –40°C to +125°C
(V–)
(V+)
V
INPUT BIAS CURRENT
TA = 25°C
5
15
20
nA
nA
nA
IB
Input bias current
TA = –40°C to +125°C
IOS
Input offset current
0.5
CLOAD
OUTPUT
Capacitive load drive
See Typical Characteristics
I
O ≤ 4 mA, input overdrive = 100 mV,
900
600
mV
mV
VS = 36 V
VO
Voltage output swing from rail
IO = 0 mA, input overdrive = 100 mV,
VS = 36 V
ISC
Short circuit sink current
Output leakage current
20
70
mA
nA
VIN+ > VIN–
POWER SUPPLY
VS
Specified voltage range
2.2
36
75
V
IO = 0 A
55
μA
μA
IQ
Quiescent current (per channel)
IO = 0 A, TA = –40°C to +125°C
100
7.6 Switching Characteristics
at TA = 25°C, VS = +2.2 V to +36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless otherwise noted)
PARAMETER
Propagation delay time, high-to-low
Propagation delay time, low-to-high
Rise time
TEST CONDITIONS
Input overdrive = 100 mV
Input overdrive = 100 mV
Input overdrive = 100 mV
Input overdrive = 100 mV
MIN
TYP
460
560
365
240
MAX
UNIT
ns
tpHL
tpLH
tR
ns
ns
tF
Fall time
ns
6
Copyright © 2015, Texas Instruments Incorporated
TLV1702-Q1
www.ti.com.cn
ZHCSED6 –NOVEMBER 2015
7.7 Typical Characteristics
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
75
70
65
60
55
50
45
40
35
6
4
2
0
VS = 2.2 V
VS = ±18 V
VS = ±18 V
VS = 2.2 V
Ibn
Ibp
5
20 35 50 65 80 95 110 125
0
25
50
75
100
125
œ40 œ25 œ10
œ50
œ25
Temperature (°C)
Temperature (°C)
C017
C015
Figure 1. Quiescent Current vs Temperature
Figure 2. Input Bias Current vs Temperature
1
0.75
0.5
0
œ2
VS = ±1.1 V
œ4
œ6
VS = ±18 V
œ8
œ10
œ12
œ14
œ16
œ18
0.25
0
VS = 2.2 V
VS = ±18 V
0
25
50
75
100
125
œ50
œ25
0
5
10
15
20
Temperature (°C)
Output Current (mA)
C014
C011
Figure 3. Input Offset Current vs Temperature
Figure 4. Output Voltage vs Output Current
3
2
1
0
3
2
1
0
-1
-1
-2
-3
-2
-3
0
6
12
18
24
30
36
0
0.5
1
1.5
2
Common-Mode Voltage (V)
Common-Mode Voltage (V)
D003
D002
VS = ±18 V
14 typical units shown
VS = 2.2 V
13 typical units shown
Figure 5. Offset Voltage vs Common-Mode Voltage
Figure 6. Offset Voltage vs Common-Mode Voltage
Copyright © 2015, Texas Instruments Incorporated
7
TLV1702-Q1
ZHCSED6 –NOVEMBER 2015
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
3
1000n
800n
600n
400n
200n
±18 V Low-to-High
±18 V High-to-Low
2.2 V Low-to-High
2.2 V High-to-Low
2
1
0
-1
-2
-3
0
200
400
600
800
1000
0
6
12
18
24
30
36
Input Overdrive (mV)
C020
Supply Voltage (V)
D001
16 typical units shown
Figure 8. Propagation Delay vs Input Overdrive
Figure 7. Offset Voltage vs Supply Voltage
4.0ꢀ
3.5ꢀ
3.0ꢀ
2.5ꢀ
2.0ꢀ
1.5ꢀ
1.0ꢀ
0.5ꢀ
0.0ꢀ
1200n
1000n
800n
600n
400n
200n
2.2 V Supply
18 V Low-to-High
18 V High-to-Low
2.2 V Low-to-High
2.2 V High-to-Low
±18 V Supply
tPLH
tPHL
20p
200p
2n
-40 -25 -10
5
20 35 50 65 80 95 110 125
Output Capacitive Load (F)
Temperature (C)
C020
C012
VOD = 100 mV
Figure 9. Propagation Delay vs Capacitive Load
Figure 10. Propagation Delay vs Temperature
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VS = 36 V
Overdrive = 100 mV
VS = 36 V
Overdrive = 100 mV
Figure 11. Propagation Delay (TpLH
)
Figure 12. Propagation Delay (TpHL)
8
Copyright © 2015, Texas Instruments Incorporated
TLV1702-Q1
www.ti.com.cn
ZHCSED6 –NOVEMBER 2015
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
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VS = 2.2 V
Overdrive = 100 mV
VS = 2.2 V
Overdrive = 100
mV
Figure 13. Propagation Delay (TpLH
)
Figure 14. Propagation Delay (TpHL
)
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
D005
D004
Offset Voltage (mV)
Offset Voltage (mV)
VS = ±18 V
Distribution taken from 2524 comparators
VS = 2.2 V
Distribution taken from 2524 comparators
Figure 15. Offset Voltage Production Distribution
Figure 16. Offset Voltage Production Distribution
30
VS = 2.2 V
25
20
15
10
5
0
0
6
12
18
24
30
36
Supply Voltage (V)
C016
Sink current
Figure 17. Short-Circuit Current vs Supply Voltage
Copyright © 2015, Texas Instruments Incorporated
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TLV1702-Q1
ZHCSED6 –NOVEMBER 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TLV1702-Q1 comparator features rail-to-rail input and output on supply voltages as high as 36 V. The rail-to-
rail input stage enables detection of signals close to the supply and ground. The open collector configuration
allows the device to be used in wired-OR configurations, such as a window comparator. A low supply current of
55 μA per channel with small, space-saving packages, makes these comparators versatile for use in a wide
range of applications, from portable to industrial.
8.2 Functional Block Diagram
V+
OUT
IN+
IN-
IN+
IN-
V-
10
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TLV1702-Q1
www.ti.com.cn
ZHCSED6 –NOVEMBER 2015
8.3 Feature Description
8.3.1 Comparator Inputs
The TLV1702-Q1 device is a rail-to-rail input comparator, with an input common-mode range that includes the
supply rails. The TLV1702-Q1 device is designed to prevent phase inversion when the input pins exceed the
supply voltage. Figure 18 shows the TLV1702-Q1 device response when input voltages exceed the supply,
resulting in no phase inversion.
Output Voltage
Input Voltage
Time (5 ms/div)
C030
Figure 18. No Phase Inversion: Comparator Response to Input Voltage
(Propagation Delay Included)
8.4 Device Functional Modes
8.4.1 Setting Reference Voltage
Using a stable reference is important when setting the transition point for the TLV1702-Q1 device. The REF3333,
as shown in Figure 19, provides a 3.3-V reference voltage with low drift and only 3.9 μA of quiescent current.
V
S
REF3333
GND
V
(PULLUP)
V
S+
R
(PULLUP)
+
Device
_
V
O
V
Sœ
V
I
Figure 19. Reference Voltage for the TLV1702-Q1
Copyright © 2015, Texas Instruments Incorporated
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ZHCSED6 –NOVEMBER 2015
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV1702-Q1 device can be used in a wide variety of applications, such as zero crossing detectors, window
comparators, over and undervoltage detectors, and high-side voltage sense circuits.
9.2 Typical Application
Comparators are used to differentiate between two different signal levels. For example, a comparator
differentiates between an overtemperature and normal-temperature condition. However, noise or signal variation
at the comparison threshold causes multiple transitions. This application example sets upper and lower
hysteresis thresholds to eliminate the multiple transitions caused by noise.
5 V
Rp
5 kΩ
-
+V
+
Vout
5 V
Vin
5 V
Rx
100 kΩ
Rh
576 kΩ
Ry
100 kΩ
Figure 20. Comparator Schematic with Hysteresis
9.2.1 Design Requirements
The design requirements are as follows:
•
•
•
•
•
•
Supply voltage: 5 V
Input: 0 V to 5 V
Lower threshold (VL) = 2.3 V ±0.1 V
Upper threshold (VH) = 2.7 V ±0.1 V
VH – VL = 2.4 V ±0.1 V
Low-power consumption
12
Copyright © 2015, Texas Instruments Incorporated
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ZHCSED6 –NOVEMBER 2015
Typical Application (continued)
9.2.2 Detailed Design Procedure
Make a small change to the comparator circuit to add hysteresis. Hysteresis uses two different threshold voltages
to avoid the multiple transitions introduced in the previous circuit. The input signal must exceed the upper
threshold (VH) to transition low, or below the lower threshold (VL) to transition high.
Figure 20 illustrates hysteresis on a comparator. Resistor Rh sets the hysteresis level. An open-collector output
stage requires a pullup resistor (Rp). The pullup resistor creates a voltage divider at the comparator output that
introduces an error when the output is at logic high. This error can be minimized if Rh > 100 Rp.
When the output is at a logic high (5 V), Rh is in parallel with Rx (ignoring Rp). This configuration drives more
current into Ry, and raises the threshold voltage (VH) to 2.7 V. The input signal must drive above VH = 2.7 V to
cause the output to transition to logic low (0 V).
When the output is at logic low (0 V), Rh is in parallel with Ry. This configuration reduces the current into Ry, and
reduces the threshold voltage to 2.3 V. The input signal must drive below VL = 2.3 V to cause the output to
transition to logic high (5 V).
For more details on this design and other alternative devices that can be used in place of the TLV1702, refer to
Precision Design TIPD144, Comparator with Hysteresis Reference Design.
9.2.3 Application Curve
Figure 21 shows the upper and lower thresholds for hysteresis. The upper threshold is 2.76 V and the lower
threshold is 2.34 V, both of which are close to the design target.
Figure 21. TLV1701 Upper and Lower Threshold with Hysteresis
10 Power Supply Recommendations
The TLV1702-Q1 device is specified for operation from 2.2 V to 36 V (±1.1 to ±18 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement; see the Layout
Guidelines section.
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11 Layout
11.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, maintain the following layout guidelines:
•
•
•
Use a printed circuit board (PCB) with a good, unbroken low-inductance ground plane. Proper grounding (use
of ground plane) helps maintain specified performance of the TLV1702-Q1 device.
To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) as close
as possible to VS as shown in Figure 22.
On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from the output.
•
•
Solder the device directly to the PCB rather than using a socket.
For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to propagation delay when the impedance is low. Run the topside ground plane between the
output and inputs.
•
Run the ground pin ground trace under the device up to the bypass capacitor, shielding the inputs from the
outputs.
11.2 Layout Example
V+
IN+
IN-
+
OUT
V-
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Use low-ESR, ceramic
bypass capacitor
VS+
IN+
IN+
GND
V+
VSœ or GND
Vœ
OUT
OUT
IN-
IN-
GND
Only needed for
dual-supply
operation
Figure 22. Comparator Board Layout
14
版权 © 2015, Texas Instruments Incorporated
TLV1702-Q1
www.ti.com.cn
ZHCSED6 –NOVEMBER 2015
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
《高精度设计，采用滞后参考设计的比较器》，TIDU020
《REF33xx 3.9μA，SC70-3、SOT-23-3 和 UQFN-8，30ppm/°C 漂移电压基准》，SBOS392
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知
且不对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
15
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV1702AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1702Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
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