TLV1704-Q1 [TI]
汽车类四路高电压、低功耗比较器;
| 型号： | TLV1704-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类四路高电压、低功耗比较器 比较器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
TLV170x-Q1 2.2-V to 36-V, microPower Comparator
1 Features
3 Description
The TLV1701-Q1 (Single), TLV1702-Q1 (Dual) and
1
•
•
Qualified for Automotive Applications
TLV1704-Q1 (Quad) devices offers a wide supply
range, rail-to-rail inputs, low quiescent current, and
low propagation delay. All these features come in
industry-standard, extremely-small packages, making
these devices the best general-purpose comparators
available.
AEC Q100-Qualified With the Following Results
–
–
–
–
Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Device HBM ESD Classification Level 2
(TLV1701-Q1)
The open collector output offers the advantage of
allowing the output to be pulled to any voltage rail up
to 36 V above the negative power supply, regardless
of the TLV170x-Q1 supply voltage.
Device HBM ESD Classification Level 1C
(TLV1702-Q1,TLV1704-Q1)
Device CDM ESD Classification Level C6
•
•
•
•
•
•
Supply Range: 2.2 V to 36 V or ±1.1 V to ±18 V
Low Quiescent Current: 55 µA per Comparator
Input Common-Mode Range Includes Both Rails
Low Propagation Delay: 560 ns
The device is a microPower comparator. Low input
offset voltage, low input bias currents, low supply
current, and open-collector configuration make the
TLV170x-Q1 device flexible enough to handle almost
any application, from simple voltage detection to
driving a single relay.
Low Input Offset Voltage: 300 µV
Open Collector Outputs:
The device is specified for operation across the
expanded industrial temperature range of –40°C to
+125°C.
–
Up to 36 V Above Negative Supply Regardless
of Supply Voltage
•
•
Industrial Temperature Range: –40°C to +125°C
Small Packages:
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
1.60 mm × 2.90 mm
1.25 mm × 2.00 mm
3.00 mm × 3.00 mm
4.40 mm × 5.00 mm
–
–
–
Single: SOT23-5 and SC-70-5
Dual: VSSOP-8
SOT-23 (5)
TLV1701-Q1
SC-70 (5)
Quad: TSSOP-14
TLV1702-Q1
TLV1704-Q1
VSSOP (8)
TSSOP (14)
2 Applications
(1) For all available packages, see the package option addendum
at the end of the data sheet.
•
•
•
•
•
Overvoltage and Undervoltage Detectors
Window Comparators
Overcurrent Detectors
Zero-Crossing Detectors
System Monitoring for:
–
–
–
White Goods
Automotive
Medical
TLV1702-Q1 as a Window Comparator
Stable Propagation Delay vs Temperature
V
(PULLUP)
1200n
18 V Low-to-High
V
I
V
S
R
18 V High-to-Low
(PULLUP)
1000n
V
(th+)
+
V
(th+)
½
Device
2.2 V Low-to-High
V
O
V
(thœ)
_
800n
600n
400n
200n
2.2 V High-to-Low
t
GND
V
V
O
I
V
S
V
(PULLUP)
+
½
Device
_
V
(thœ)
t
GND
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
C012
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
www.ti.com
Table of Contents
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics.......................................... 6
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
9
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1 Documentation Support ........................................ 15
12.2 Related Links ........................................................ 15
12.3 Receiving Notification of Documentation Updates 15
12.4 Support Resources ............................................... 15
12.5 Trademarks........................................................... 15
12.6 Electrostatic Discharge Caution............................ 15
12.7 Glossary................................................................ 15
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2017) to Revision C
Page
•
•
•
Added DCK Package Information........................................................................................................................................... 1
Changed incorrect front page HBM ESD classification level from 3A to 2 for TLV1701-Q1 ................................................. 1
Changed incorrect front page CDM from C5 back to C6 ....................................................................................................... 1
Changes from Revision A (December 2015) to Revision B
Page
•
•
Added TLV1701-Q1 device to data sheet .............................................................................................................................. 1
Added TLV1701-Q1 to ESD table and specified the ESD ratings under each device........................................................... 5
Changes from Original (November 2015) to Revision A
Page
•
Added TLV1704-Q1 device to data sheet .............................................................................................................................. 1
2
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Copyright © 2015–2019, Texas Instruments Incorporated
Product Folder Links: TLV1701-Q1 TLV1702-Q1 TLV1704-Q1
TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
www.ti.com
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
5 Device Comparison Table
Table 1. Related Products
DEVICE
FEATURES
TLC3702-Q1
TLC3704-Q1
TLV3012-Q1
TLV3501-Q1
TLV3502-Q1
TLV3701-Q1
TLV3702-Q1
REF50xx-Q1
TL4050xx-Q1
TLVH431-Q1
Push-pull, 20-µA, 20-mA drive
Push-pull, 5-µA, integrated 1.242-V reference
Push-Pull, 3.2 mA, 4.5-ns propagation delay
Push-pull, 560-nA, reverse battery to 16 V
Series reference, 0.1% tolerance, 8 ppm/°C
Shunt reference, 0.1% tolerance, 50 ppm/°C
Adjustable Shunt Reference, 1.24 V to 18 V
Copyright © 2015–2019, Texas Instruments Incorporated
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TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
www.ti.com
6 Pin Configuration and Functions
TLV1701-Q1 DBV and DCK Packages
5-Pin SOT-23 and SC70
Top View
IN+
V-
1
2
3
5
4
V+
OUT
INœ
TLV1702-Q1 DGK Package
8-Pin VSSOP
TLV1704-Q1 PW Package
14-Pin TSSOP
Top View
Top View
1OUT
1INœ
1IN+
V-
1
2
3
4
8
7
6
5
V+
2OUT
1OUT
V+
1
2
3
4
5
6
7
14 3OUT
2OUT
2INœ
2IN+
4OUT
V-
13
12
11
10
9
1INœ
1IN+
4IN+
4INœ
2INœ
3IN+
2IN+
3INœ
8
Pin Functions
PIN
I/O
DESCRIPTION
TLV1701-Q1
DBV, DCK
TLV1702-Q1
DGK
TLV1704-Q1
PW
NAME
IN+
1
—
3
—
5
I
I
Noninverting input
1IN+
2IN+
3IN+
4IN+
IN–
—
—
—
—
3
Noninverting input, channel 1
Noninverting input, channel 2
Noninverting input, channel 3
Noninverting input, channel 4
Inverting input
5
7
I
—
—
—
2
9
I
11
—
4
I
I
1IN–
2IN–
3IN–
4IN–
OUT
1OUT
2OUT
3OUT
4OUT
V+
—
—
—
—
4
I
Inverting input, channel 1
Inverting input, channel 2
Inverting input, channel 3
Inverting input, channel 4
Output
6
6
I
—
—
—
1
8
I
10
—
2
I
O
O
O
O
O
—
—
—
—
—
—
5
Output, channel 1
7
1
Output, channel 2
—
—
8
14
13
3
Output, channel 3
Output, channel 4
Positive (highest) power supply
Negative (lowest) power supply
V–
2
4
12
4
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Product Folder Links: TLV1701-Q1 TLV1702-Q1 TLV1704-Q1
TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
www.ti.com
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40 (±20)
(VS+) + 0.5
±10
UNIT
V
Supply voltage
Voltage(2)
Current(2)
(VS–) – 0.5
V
Signal input pins
mA
mA
°C
Output short-circuit(3)
Continuous
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
–55
–65
150
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground; one comparator per package.
7.2 ESD Ratings
VALUE
UNIT
TLV1701-Q1
V(ESD)
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
±2000
±1000
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
V
TLV1702-Q1
V(ESD)
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
±1000
±1000
V
V
TLV1704-Q1
V(ESD)
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
±1000
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2 (±1.1)
–40
NOM
MAX
36 (±18)
125
UNIT
Supply voltage VS = (VS+) – (VS–)
Specified temperature
V
°C
7.4 Thermal Information
TLV1701-Q1
TLV1702-Q1
TLV1704-Q1
THERMAL METRIC(1)
DBV (SOT-23) DCK (SC-70) DGK (VSSOP) PW (TSSOP) UNIT
5 PINS
233.1
156.4
60.6
5 PINS
222.5
137.2
71.3
8 PINS
199
14 PINS
128.1
56.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
89.5
120.4
22
RθJB
ψJT
Junction-to-board thermal resistance
69.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
35.7
44.6
9.1
ψJB
59.7
71.0
118.7
N/A
69.3
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
www.ti.com
7.5 Electrical Characteristics
at TA = 25°C, VS = 2.2 V to 36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
TA = 25°C, VS = 2.2 V
±0.5
±0.3
±3.5
±2.5
±5.5
±3.2
±6.3
±20
mV
mV
TA = 25°C, VS = 36 V
VOS
Input offset voltage
TA = –40°C to +125°C
TA = 25°C, VS = 36 V, TLV1701-Q1 Only
TA = –40°C to +125°C, TLV1701-Q1 Only
TA = –40°C to +125°C
±0.4
mV
dVOS/dT
PSRR
Input offset voltage drift
±4
15
20
μV/°C
μV/V
μV/V
TA = 25°C
100
Power-supply rejection ratio
TA = –40°C to +125°C
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
TA = –40°C to +125°C
(V–)
(V+)
V
INPUT BIAS CURRENT
TA = 25°C
5
15
20
nA
nA
nA
IB
Input bias current
TA = –40°C to +125°C
IOS
Input offset current
0.5
CLOAD
OUTPUT
Capacitive load drive
See Typical Characteristics
I
O ≤ 4 mA, input overdrive = 100 mV,
900
600
mV
mV
VS = 36 V
VO
Voltage output swing from rail
IO = 0 mA, input overdrive = 100 mV,
VS = 36 V
ISC
Short circuit sink current
Output leakage current
20
70
mA
nA
VIN+ > VIN–
POWER SUPPLY
VS
Specified voltage range
2.2
36
75
V
IO = 0 A
55
μA
μA
IQ
Quiescent current (per channel)
IO = 0 A, TA = –40°C to +125°C
100
7.6 Switching Characteristics
at TA = 25°C, VS = +2.2 V to +36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless otherwise noted)
PARAMETER
Propagation delay time, high-to-low
Propagation delay time, low-to-high
Rise time
TEST CONDITIONS
Input overdrive = 100 mV
Input overdrive = 100 mV
Input overdrive = 100 mV
Input overdrive = 100 mV
MIN
TYP
460
560
365
240
MAX
UNIT
ns
tpHL
tpLH
tR
ns
ns
tF
Fall time
ns
6
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SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
7.7 Typical Characteristics
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
75
70
65
60
55
50
45
40
35
6
4
2
0
VS = 2.2 V
VS
= 18 V
VS
= 18 V
VS = 2.2 V
Ibn
Ibp
5
20 35 50 65 80 95 110 125
0
25
50
75
100
125
œ40 œ25 œ10
œ50
œ25
Temperature (°C)
Temperature (°C)
C017
C015
Figure 1. Quiescent Current vs Temperature
Figure 2. Input Bias Current vs Temperature
1
0.75
0.5
0
œ2
VS
=
1.1 V
œ4
œ6
VS
= 18 V
œ8
œ10
œ12
œ14
œ16
œ18
0.25
0
VS = 2.2 V
VS
= 18 V
0
25
50
75
100
125
œ50
œ25
0
5
10
Output Current (mA)
15
20
Temperature (°C)
C014
C011
Figure 3. Input Offset Current vs Temperature
Figure 4. Output Voltage vs Output Current
3
2
1
0
3
2
1
0
-1
-1
-2
-3
-2
-3
0
6
12
Common-Mode Voltage (V)
18
24
30
36
0
0.5
1
Common-Mode Voltage (V)
1.5
2
D003
D002
VS = ±18 V
14 typical units shown
VS = 2.2 V
13 typical units shown
Figure 5. Offset Voltage vs Common-Mode Voltage
Figure 6. Offset Voltage vs Common-Mode Voltage
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SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
www.ti.com
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
3
1000n
800n
600n
400n
200n
±18 V Low-to-High
±18 V High-to-Low
2.2 V Low-to-High
2.2 V High-to-Low
2
1
0
-1
-2
-3
0
200
400
600
800
1000
0
6
12
18
Supply Voltage (V)
24
30
36
Input Overdrive (mV)
C020
D001
16 typical units shown
Figure 8. Propagation Delay vs Input Overdrive
Figure 7. Offset Voltage vs Supply Voltage
4.0ꢀ
3.5ꢀ
3.0ꢀ
2.5ꢀ
2.0ꢀ
1.5ꢀ
1.0ꢀ
0.5ꢀ
0.0ꢀ
1200n
1000n
800n
600n
400n
200n
2.2 V Supply
18 V Low-to-High
18 V High-to-Low
2.2 V Low-to-High
2.2 V High-to-Low
±18 V Supply
tPLH
tPHL
20p
200p
2n
-40 -25 -10
5
20 35 50 65 80 95 110 125
Output Capacitive Load (F)
Temperature (C)
C020
C012
VOD = 100 mV
Figure 9. Propagation Delay vs Capacitive Load
Figure 10. Propagation Delay vs Temperature
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W
ꢀ ꢀꢈꢃꢃꢀQVꢀ
3/+
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VS = 36 V
Overdrive = 100 mV
VS = 36 V
Overdrive = 100 mV
Figure 11. Propagation Delay (TpLH
)
Figure 12. Propagation Delay (TpHL)
8
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SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
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3/+
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VS = 2.2 V
Overdrive = 100 mV
VS = 2.2 V
Overdrive = 100
mV
Figure 13. Propagation Delay (TpLH
)
Figure 14. Propagation Delay (TpHL
)
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
D005
D004
Offset Voltage (mV)
Offset Voltage (mV)
VS = ±18 V
Distribution taken from 2524 comparators
VS = 2.2 V
Distribution taken from 2524 comparators
Figure 15. Offset Voltage Production Distribution
Figure 16. Offset Voltage Production Distribution
30
VS = 2.2 V
25
20
15
10
5
0
0
6
12
18
24
30
36
Supply Voltage (V)
C016
Sink current
Figure 17. Short-Circuit Current vs Supply Voltage
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SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
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8 Detailed Description
8.1 Overview
The TLV170x-Q1 comparator features rail-to-rail input and output on supply voltages as high as 36 V. The rail-to-
rail input stage enables detection of signals close to the supply and ground. The open-collector configuration
allows the device to be used in wired-OR configurations, such as a window comparator. A low supply current of
55 μA per channel with small, space-saving packages, makes these comparators versatile for use in a wide
range of applications, from portable to industrial.
8.2 Functional Block Diagram
V+
OUT
IN+
IN-
IN+
IN-
V-
10
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SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
8.3 Feature Description
8.3.1 Comparator Inputs
The TLV170x-Q1 device is a rail-to-rail input comparator, with an input common-mode range that includes the
supply rails. The TLV170x-Q1 device is designed to prevent phase inversion when the input pins exceed the
supply voltage. Figure 18 shows the TLV170x-Q1 device response when input voltages exceed the supply,
resulting in no phase inversion.
Output Voltage
Input Voltage
Time (5 ms/div)
C030
Figure 18. No Phase Inversion: Comparator Response to Input Voltage
(Propagation Delay Included)
8.4 Device Functional Modes
8.4.1 Setting Reference Voltage
Using a stable reference is important when setting the transition point for the TLV170x-Q1 device. The REF3333,
as shown in Figure 19, provides a 3.3-V reference voltage with low drift and only 3.9 μA of quiescent current.
V
S
REF3333
GND
V
(PULLUP)
V
S+
R
(PULLUP)
+
Device
V
O
_
V
Sœ
V
I
Figure 19. Reference Voltage for the TLV170x-Q1
Copyright © 2015–2019, Texas Instruments Incorporated
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TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV170x-Q1 device can be used in a wide variety of applications, such as zero crossing detectors, window
comparators, over and undervoltage detectors, and high-side voltage sense circuits.
9.2 Typical Application
Comparators are used to differentiate between two different signal levels. For example, a comparator
differentiates between an overtemperature and normal-temperature condition. However, noise or signal variation
at the comparison threshold causes multiple transitions. This application example sets upper and lower
hysteresis thresholds to eliminate the multiple transitions caused by noise.
5 V
Rp
5 kΩ
-
+V
+
Vout
5 V
Vin
5 V
Rx
100 kΩ
Rh
576 kΩ
Ry
100 kΩ
Figure 20. Comparator Schematic With Hysteresis
9.2.1 Design Requirements
The design requirements are as follows:
•
•
•
•
•
•
Supply voltage: 5 V
Input: 0 V to 5 V
Lower threshold (VL) = 2.3 V ±0.1 V
Upper threshold (VH) = 2.7 V ±0.1 V
VH – VL = 2.4 V ±0.1 V
Low-power consumption
12
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Copyright © 2015–2019, Texas Instruments Incorporated
Product Folder Links: TLV1701-Q1 TLV1702-Q1 TLV1704-Q1
TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
www.ti.com
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
Typical Application (continued)
9.2.2 Detailed Design Procedure
Make a small change to the comparator circuit to add hysteresis. Hysteresis uses two different threshold voltages
to avoid the multiple transitions introduced in the previous circuit. The input signal must exceed the upper
threshold (VH) to transition low, or below the lower threshold (VL) to transition high.
Figure 20 illustrates hysteresis on a comparator. Resistor Rh sets the hysteresis level. An open-collector output
stage requires a pullup resistor (Rp). The pullup resistor creates a voltage divider at the comparator output that
introduces an error when the output is at logic high. This error can be minimized if Rh > 100 Rp.
When the output is at a logic high (5 V), Rh is in parallel with Rx (ignoring Rp). This configuration drives more
current into Ry, and raises the threshold voltage (VH) to 2.7 V. The input signal must drive above VH = 2.7 V to
cause the output to transition to logic low (0 V).
When the output is at logic low (0 V), Rh is in parallel with Ry. This configuration reduces the current into Ry, and
reduces the threshold voltage to 2.3 V. The input signal must drive below VL = 2.3 V to cause the output to
transition to logic high (5 V).
For more details on this design and other alternative devices that can be used in place of the TLV1702, refer to
Precision Design TIPD144, Comparator with Hysteresis Reference Design.
9.2.3 Application Curve
Figure 21 shows the upper and lower thresholds for hysteresis. The upper threshold is 2.76 V and the lower
threshold is 2.34 V, both of which are close to the design target.
Figure 21. TLV1701 Upper and Lower Threshold With Hysteresis
10 Power Supply Recommendations
The TLV170x-Q1 device is specified for operation from 2.2 V to 36 V (±1.1 to ±18 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement; see the Layout
Guidelines section.
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Links: TLV1701-Q1 TLV1702-Q1 TLV1704-Q1
TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
www.ti.com
11 Layout
11.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, maintain the following layout guidelines:
•
•
•
Use a printed-circuit board (PCB) with a good, unbroken low-inductance ground plane. Proper grounding (use
of ground plane) helps maintain specified performance of the TLV170x-Q1 device.
To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) as close
as possible to VS as shown in Figure 22.
On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from the output.
•
•
Solder the device directly to the PCB rather than using a socket.
For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to propagation delay when the impedance is low. Run the topside ground plane between the
output and inputs.
•
Run the ground pin ground trace under the device up to the bypass capacitor, shielding the inputs from the
outputs.
11.2 Layout Example
V+
IN+
IN-
+
OUT
V-
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Use low-ESR, ceramic
bypass capacitor
VS+
IN+
IN+
GND
V+
VSœ or GND
Vœ
OUT
OUT
IN-
IN-
GND
Only needed for
dual-supply
operation
Figure 22. Comparator Board Layout
14
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Copyright © 2015–2019, Texas Instruments Incorporated
Product Folder Links: TLV1701-Q1 TLV1702-Q1 TLV1704-Q1
TLV1701-Q1, TLV1702-Q1, TLV1704-Q1
www.ti.com
SLOS890C –OCTOBER 2015–REVISED DECEMBER 2019
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
Precision Design, Comparator with Hysteresis Reference Design, TIDU020
REF33xx 3.9-μA, SC70-3, SOT-23-3, and UQFN-8, 30-ppm/°C Drift Voltage Reference, SBOS392
12.2 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TLV1701-Q1
TLV1702-Q1
TLV1704-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015–2019, Texas Instruments Incorporated
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15
Product Folder Links: TLV1701-Q1 TLV1702-Q1 TLV1704-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV1701AQDCKRQ1
TLV1701QDBVRQ1
TLV1702AQDGKRQ1
TLV1704AQPWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SC70
DCK
DBV
DGK
PW
5
5
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1FG
Samples
Samples
Samples
Samples
SOT-23
VSSOP
TSSOP
NIPDAU
NIPDAUAG
NIPDAU
1701
8
1702Q
14
T1704Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV1701-Q1, TLV1702-Q1, TLV1704-Q1 :
Catalog : TLV1701, TLV1702, TLV1704
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV1701AQDCKRQ1
TLV1701QDBVRQ1
TLV1702AQDGKRQ1
TLV1704AQPWRQ1
SC70
DCK
DBV
DGK
PW
5
5
3000
3000
2500
2000
178.0
178.0
330.0
330.0
9.0
9.0
2.4
3.23
5.3
2.5
3.17
3.4
1.2
1.37
1.4
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
SOT-23
VSSOP
TSSOP
8
12.4
12.4
12.0
12.0
14
6.9
5.6
1.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV1701AQDCKRQ1
TLV1701QDBVRQ1
TLV1702AQDGKRQ1
TLV1704AQPWRQ1
SC70
DCK
DBV
DGK
PW
5
5
3000
3000
2500
2000
190.0
180.0
366.0
356.0
190.0
180.0
364.0
356.0
30.0
18.0
50.0
35.0
SOT-23
VSSOP
TSSOP
8
14
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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