TLV172 [TI]
适用于成本敏感型应用的单路、36V、10MHz、低功耗运算放大器;
| 型号： | TLV172 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于成本敏感型应用的单路、36V、10MHz、低功耗运算放大器 放大器 运算放大器 |
| 文件： | 总45页 (文件大小：2444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV172, TLV2172, TLV4172
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
适用于成本敏感型系统的 TLVx172 36V 单电源、低功耗
运算放大器
1 特性
大多数运算放大器仅有一个额定电源电压，而
1
TLVx172器件的额定电压范围为 4.5V 至 36V。超过电
源轨的输入信号不会导致相位反转。TLVx172器件可
在容性负载高达 300pF 时保持稳定。输入可在负电源
轨以下 100mV 以及正电源轨 2V 之内正常运行。请注
意，此系列器件可在超出正电源轨 100mV 的完整轨至
轨输入范围内运行，但是在正电源轨 2V 之内运行时，
性能会受到影响。
•
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电源电压范围：4.5V 至 36V，±2.25V 至 ±18V
低噪声：9 nV/√Hz
低温漂：±1μV/°C（典型值）
抗电磁干扰 (EMI)
输入范围包括负电源
轨到轨输出
增益带宽：10MHz
转换速率：10V/μs
TLVx172运算放大器的额定工作温度范围为 –40°C 至
+125°C。
低静态电流：每个放大器 1.6mA
高共模抑制：116dB（典型值）
低输入偏压电流：10pA
器件信息(1)
封装
器件型号
封装尺寸（标称值）
4.90mm × 3.91mm
2.00mm × 1.25mm
2.90mm × 1.60mm
4.90mm × 3.91mm
3.00mm × 3.00mm
8.65mm × 3.91mm
5.00mm × 4.40mm
SOIC (8)
2 应用
TLV172
SC70 (5)
SOT-23 (5)
SOIC (8)
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薄膜晶体管 (TFT) - 液晶显示屏 (LCD) 驱动电路
触摸屏显示屏
无线 LAN
TLV2172
TLV4172
VSSOP (8)
SOIC (14)
便携式仪表
TSSOP (14)
模数转换器 (ADC) 缓冲器
有源滤波器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
线路驱动器或线路接收器
超声波
简化原理图
点钞机
VCC
VCC
VEE
变频器放大器
R1
3.9 kΩ
R2
3.9 kΩ
VEE
V1
15 V
V2
15 V
3 说明
VOUT
TLVx172 系列 36V 单电源、低噪声抗电磁干扰 (EMI)
运算放大器在 1kHz 频率下 具有 0.0002% 的
THD+N，能够在 4.5V (±2.25V) 至 36V (±18V) 的电源
电压范围内正常工作。这些 特性和低噪声、高 PSRR
特性，使TLVx172能够 在 HEV 和 EV 汽车及动力传动
系统、医疗仪器等应用中放大毫伏级信号。TLVx172
器件具有良好的失调电压和温漂、10MHz 高带宽和
10V/µs 压摆率，且在工作温度范围内的静态电流仅有
2.3mA（最大值）
+
+
R3
LSK489
VCC
1.13 kΩ
Q1
Q2
VCC
R4
11.5 Ω
R6
27.4 kΩ
Q3
MMBT4401
Q4
MMBT4401
R5
300 Ω
VEE
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS784
TLV172, TLV2172, TLV4172
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information: TLV172 ................................... 8
7.5 Thermal Information: TLV2172 ................................. 8
7.6 Thermal Information: TLV4172 ................................. 8
7.7 Electrical Characteristics........................................... 9
7.8 Typical Characteristics............................................ 10
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ...................................... 15
8.3 Feature Description................................................. 16
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 24
12.1 器件支持................................................................ 24
12.2 文档支持................................................................ 24
12.3 相关链接................................................................ 25
12.4 接收文档更新通知 ................................................. 25
12.5 社区资源................................................................ 25
12.6 商标....................................................................... 25
12.7 静电放电警告......................................................... 25
12.8 术语表 ................................................................... 25
13 机械、封装和可订购信息....................................... 25
8
4 修订历史记录
Changes from Revision B (September 2018) to Revision C
Page
•
将数据表标题从“TLV2172 36V、单电源、低功耗...” 更改成了“TLVx172 36V、单电源、低功耗...”....................................... 1
Changes from Revision A (May 2018) to Revision B
Page
•
•
•
•
Deleted the Device Family Comparison table ........................................................................................................................ 3
Added the 5-pin SC70 and SOT-23, and the 8-pin SOIC pinout diagrams to the data sheet ............................................... 4
Added TLV172 Pin Functions table to the data sheet............................................................................................................ 4
Added 14-pin SOIC and TSSOP pinout diagram to the data sheet ...................................................................................... 6
Changes from Original (November 2016) to Revision A
Page
•
Updated supply voltage values in Absolute Maximum Ratings table..................................................................................... 7
2
Copyright © 2016–2019, Texas Instruments Incorporated
TLV172, TLV2172, TLV4172
www.ti.com.cn
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
5 Device Comparison Table
DEVICE
PACKAGE
TLV172 (single)
TLV2172 (dual)
TLV4172 (quad)
SC70-5, SOT-23-5, SOIC-8
SOIC-8, VSSOP-8
SOIC-14, TSSOP-14
Copyright © 2016–2019, Texas Instruments Incorporated
3
TLV172, TLV2172, TLV4172
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
www.ti.com.cn
6 Pin Configuration and Functions
TLV172 DCK Package
5-Pin SC70
TLV172 DBV Package
5-Pin SOT-23
Top View
Top View
+IN
Vœ
1
2
3
5
V+
OUT
Vœ
1
2
3
5
V+
+
œ
œIN
4
OUT
+IN
4
œIN
Not to scale
Not to scale
TLV172 D Package
8-Pin SOIC
Top View
NC
1
2
3
4
8
7
6
5
NC
V+
œIN
+IN
Vœ
œ
OUT
NC
+
Not to scale
NC- no internal connection
Pin Functions: TLV172
PIN
I/O
DESCRIPTION
NAME
–IN
SC70
SOT-23
SOIC
3
1
4
3
2
I
Negative (inverting) input
+IN
NC
OUT
V–
3
I
Positive (noninverting) input
—
4
—
1
1, 5, 8
—
O
—
—
No internal connection (can be left floating)
Output
6
4
7
2
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
5
4
Copyright © 2016–2019, Texas Instruments Incorporated
TLV172, TLV2172, TLV4172
www.ti.com.cn
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
TLV2172 D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Pin Functions: TLV2172
PIN
I/O
DESCRIPTION
SOIC
(D)
VSSOP
(DGK)
NAME
–IN A
–IN B
+IN A
+IN B
OUT A
OUT B
V–
2
6
3
5
1
7
4
8
2
6
3
5
1
7
4
8
I
I
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
I
I
O
O
—
—
Output, channel B
Negative (lowest) power supply
Positive (highest) power supply
V+
Copyright © 2016–2019, Texas Instruments Incorporated
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TLV172, TLV2172, TLV4172
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
www.ti.com.cn
TLV4172 D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
Pin Functions: TLV4172
PIN
I/O
DESCRIPTION
SOIC
(D)
TSSOP
(PW)
NAME
–IN A
2
6
2
6
I
I
Inverting input, channel A
–IN B
–IN C
–IN D
+IN A
+IN B
+IN C
+IN D
OUT A
OUT B
OUT C
OUT D
V–
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Output, channel A
9
9
I
13
3
13
3
I
I
5
5
I
10
12
1
10
12
1
I
I
O
O
O
O
—
—
7
7
Output, channel B
8
8
Output, channel C
14
11
4
14
11
4
Output, channel D
Negative (lowest) power supply
Positive (highest) power supply
V+
6
Copyright © 2016–2019, Texas Instruments Incorporated
TLV172, TLV2172, TLV4172
www.ti.com.cn
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage, [(V+) – (V−)]
40
40
Single-supply voltage
Voltage
Common-mode
Differential(3)
(V–) – 0.5
–0.5
(V+) + 0.5
0.5
Signal input pin(2)
Signal input pin
Current
–10
10
mA
Output short-circuit(4)
Continuous
Operating, TA
–55
150
150
150
Temperature
Junction, TJ
Storage, Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transient conditions that exceed these voltage ratings must be current limited to 10 mA or less.
(3) See the Electrical Overstress section for more information.
(4) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
Single-supply
Dual-supply
Supply voltage, (V+) – (V–)
Specified temperature
V
±2.25
–40
±18
125
°C
Copyright © 2016–2019, Texas Instruments Incorporated
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TLV172, TLV2172, TLV4172
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
www.ti.com.cn
7.4 Thermal Information: TLV172
TLV172
DBV (SOT-23)
5 PINS
227.9
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.5
80.6
DCK (SC70)
5 PINS
285.2
60.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
115.7
67.1
65.9
78.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
31.0
10.7
0.8
ψJB
65.6
65.3
77.9
RθJC(bot)
—
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: TLV2172
TLV2172
THERMAL METRIC(1)
D (SOIC)
8 PINS
116.1
69.8
DGK (VSSOP)
UNIT
8 PINS
158
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
48.6
78.7
3.9
56.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.5
ψJB
56.1
77.3
—
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: TLV4172
TLV4172
THERMAL METRIC(1)
D (SOIC)
14 PINS
82.7
PW (TSSOP)
14 PINS
111.1
40.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
42.3
37.3
54.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.9
3.8
ψJB
37
53.3
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8
Copyright © 2016–2019, Texas Instruments Incorporated
TLV172, TLV2172, TLV4172
www.ti.com.cn
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
7.7 Electrical Characteristics
at TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
TA = 25°C
0.5
1.7
2
VOS
Input offset voltage
mV
TA = –40°C to +125°C
TA = –40°C to +125°C
dVOS/dT Input offset voltage drift
1
120
5
µV/°C
dB
PSRR
Power-supply rejection ratio
Channel separation, dc
VS = 4 V to 36 V, TA = –40°C to +125°C
100
µV/V
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
TA = 25°C
TA = 25°C
±10
±2
pA
pA
IOS
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 100 Hz
2.5
14
9
µVPP
nV/√Hz
nV/√Hz
fA/√Hz
en
in
Input voltage noise density
f = 1 kHz
Input current noise density
f = 1 kHz
1.6
INPUT VOLTAGE
(V–) –
0.1
VCM
Common-mode voltage range(1)
(V+) – 2
V
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
CMRR
Common-mode rejection ratio
94
116
dB
INPUT IMPEDANCE
Differential
100 || 4
6 || 4
MΩ || pF
1013 Ω ||
pF
Common-mode
OPEN-LOOP GAIN
(V–) + 0.35 V < VO < (V+) – 0.35 V, TA = –40°C to +125°C
97
115
107
AOL
Open-loop voltage gain
dB
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ, TA = –40°C to +125°C
FREQUENCY RESPONSE
GBP
SR
Gain bandwidth product
10
10
MHz
V/µs
Slew rate
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
To 0.01% (12-bit), VS = ±18 V, G = +1, 10-V step
VIN × gain > VS
2
tS
Settling time
µs
ns
3.2
Overload recovery time
200
THD+N
Total harmonic distortion + noise VS = 36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS
0.0002%
OUTPUT
TA = 25°C
70
95
VS = ±18 V, RL = 10 kΩ
Voltage output swing from rail
TA = –40°C to +125°C
TA = 25°C
VO
mV
330
470
±75
400
530
VS = ±18 V, RL = 2 kΩ
TA = –40°C to +125°C
ISC
Short-circuit current
Capacitive load drive
mA
pF
Ω
CLOAD
RO
See Typical Characteristics
Open-loop output resistance
f = 1 MHz, IO = 0 A
60
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
4.5
36
2.3
V
IO = 0 A, TA = –40°C to +125°C
1.6
mA
(1) The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation
sections for additional information.
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TLV172, TLV2172, TLV4172
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
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7.8 Typical Characteristics
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
表 1. Characteristic Performance Measurements
DESCRIPTION
Offset Voltage Production Distribution
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Input Bias Current vs Temperature
FIGURE
图 1
图 2
图 3
图 4
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to-Input)
0.1-Hz to 10-Hz Noise
图 5
图 6
图 7
Input Voltage Noise Spectral Density vs Frequency
Quiescent Current vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
图 8
图 9
图 10
图 11
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load
No Phase Reversal
图 12
图 13, 图 14
图 15
Small-Signal Step Response (10 mV)
Large-Signal Step Response
图 16, 图 17
图 18, 图 19
图 20, 图 21
图 22
Large-Signal Settling Time
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR IN+ vs Frequency
图 23
图 24
10
版权 © 2016–2019, Texas Instruments Incorporated
TLV172, TLV2172, TLV4172
www.ti.com.cn
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
225
150
75
25
20
15
10
5
VCM = -18.1 V
VCM = 16 V
0
-75
-150
-225
0
-20
-15
-10
-5
0
5
10
15
20
-1 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8
1
Common-Mode Voltage (V)
D001
D013
Offset Voltage (mV)
5 typical units shown, VS = ±18 V
Distribution taken from 5185 amplifiers
图 2. Offset Voltage vs Common-Mode Voltage
图 1. Offset Voltage Production Distribution Histogram
20
8000
6000
4000
2000
0
IB+
IB-
IOS
10
0
-10
-20
-30
-40
-50
-2000
14
15
16
17
18
-50
-25
0
25
50
75
100
125
150
Common-Mode Voltage (V)
Temperature (èC)
D015
D009
5 typical units shown, VS = ±18 V
图 3. Offset Voltage vs Common-Mode Voltage
图 4. Input Bias Current vs Temperature
(Upper Stage)
(V+)
1
160
140
120
100
80
+
(V )
+
-
(V
(V
+
)
1
2
3
4
5
-
+
)
-
-
(V )
+
(V )
+
125°C
85°C
25°C
-
(V )
+
~
~
~
~
(V- )
5
4
3
2
1
+
+
-40°C
-
(V )
60
-
(V )
+
40
-
(V )
+
+
+PSRR
-PSRR
CMRR
-
(V )
20
-
(V )
(V )
- -
1
0
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
1
10
100
1k
10k
100k
1M
Frequency (Hz)
D008
D012
图 5. Output Voltage Swing vs Output Current (Maximum
图 6. CMRR and PSRR vs Frequency (Referred-to-Input)
Supply)
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
10
1
1
10
100
1k
10k
100k
Frequency (Hz)
C001
图 7. 0.1-Hz to 10-Hz Noise
图 8. Input Voltage Noise Spectral Density vs Frequency
140
180
135
90
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
Open-Loop Gain
Phase
120
100
80
60
40
20
45
0
-20
0
0
4
8
12
16
20
24
28
32
36
1
10
100
1k
10k
100k
1M
10M
Supply Voltage (V)
Frequency (Hz)
D007
D004
CLOAD = 15 pF
图 10. Open-Loop Gain and Phase vs Frequency
图 9. Quiescent Current vs Supply Voltage
100
10
1
25
20
15
10
5
0
-5
-10
-15
-20
G = +1
G = -10
G = -1
1000
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
100M
C003
Frequency (Hz)
Frequency (Hz)
D017
图 11. Closed-Loop Gain vs Frequency
图 12. Open-Loop Output Impedance vs Frequency
12
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
60
50
40
30
20
10
0
50
40
30
20
10
0
RI
=
1
k
RF
=
1 k
+
18
V
-
ROUT
+
-
VIN
= 100mV
+
CL
18
V
+
18 V
ROUT = 0
ROUT= 0
-
ROUT
+
+
-
RL
CL
R = 25
RO = 25
OUT
RRO ==2255
OUT
VIN
= 100mV
18
V
RRO ==5500
OUT
RO = 50
ROUT= 50
0p
100p
200p
300p
400p
500p
0p
100p
200p
300p
400p
500p
Capacitive Load (F)
C013
Capacitive Load (F)
C013
100-mV output step, G = –1
100-mV output step, G = 1
图 13. Small-Signal Overshoot vs Capacitive Load
图 14. Small-Signal Overshoot vs Capacitive Load
+ 18 V
-
+18 V
-
VOUT
+
-18 V
+
37 VPP
Sine Wave
CL
+
-
+
-
- 18 V
VIN = 10 mV
(
18.5 V)
VOUT
VIN
Time (200 µs/div)
Time (200 ns/div)
D011
D016
CL = 10 pF
10-mV step
图 15. No Phase Reversal
图 16. Small-Signal Step Response
+ 18 V
-
+
CL
+
-
- 18 V
VIN = 10 mV
RI = 1 NW RF = 1 NW
+18 V
+
-
VIN = 10 mV
-
+
RL
CL
-18 V
rIrrr
Time (200 ns/div)
Time (500 ns/div)
D006
D014
RL = 1 kΩ
CL = 10 pF
10-mV step
CL = 10 pF
图 18. Large-Signal Step Response
图 17. Small-Signal Step Response
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
20
15
10
5
0
-5
0.1% Settling = 10 mV
-10
-15
-20
RI
= 1 NW RF = 1 NW
+18
V
+
-
VIN
= 10 V
-
+
RL
CL
-18
V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (s)
C034
Time (500 ns/div)
10-V positive step
G = 1
CL = 10 pF
D005
RL = 1 kΩ
CL = 10 pF
图 20. Large-Signal Settling Time
图 19. Large-Signal Step Response
20
15
10
5
100
75
50
25
0
ISC, Sink ±18 V
ISC, Source ±18 V
0
-5
0.1% Settling = 10 mV
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (s)
-75
-50
-25
0
25
50
75
100 125 150
C034
Temperature (èC)
CL = 10 pF
10-V negative step
G = 1
D010
图 22. Short-Circuit Current vs Temperature
图 21. Large-Signal Settling Time
160
30
25
20
15
10
5
150
140
130
120
110
100
90
80
70
60
50
Maximum output voltage without
slew-rate induced distortion.
VS
VS
VS
=
=
=
15 V
5 V
2.25 V
40
30
20
10
0
10M
0
10k
100k
1M
Frequency (Hz)
10M
100M
Frequency (Hz)
1G
10G
C033
D018
PRF = –10 dBm
VSUPPLY = ±18 V
VCM = 0 V
图 23. Maximum Output Voltage vs Frequency
图 24. EMIRR IN+ vs Frequency
14
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8 Detailed Description
8.1 Overview
The TLVx172 operational amplifier provides high overall performance, making these devices designed for many
general-purpose applications. The excellent offset drift of only 1 μV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL
.
8.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
OUT
Output
Stage
-IN
NCH
Input Stage
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8.3 Feature Description
8.3.1 Operating Characteristics
The TLVx172 amplifier is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in the Typical Characteristics section.
8.3.2 Phase-Reversal Protection
The TLVx172 device has an internal phase-reversal protection. Many operational amplifiers exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the TLVx172 prevents phase reversal with
excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown
in 图 25.
+18 V
-
VOUT
VOUT
+
+
-18 V
37 VPP
Sine Wave
(-18.5V)
-
VIN
Time (200 ms/div)
图 25. No Phase Reversal
8.3.3 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. 图
26 shows the ESD circuits contained in the TLVx172 (indicated by the dashed box). The ESD protection circuitry
involves several current-steering diodes connected from the input and output pins and routed back to the internal
power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This
protection circuitry is intended to remain inactive during normal circuit operation.
16
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Feature Description (接下页)
TVS
R
F
+V
S
R
1
2.5 kΩ
INœ
2.5 kΩ
R
S
IN+
+
Power-Supply
ESD Cell
I
R
L
D
+
V
IN
œ
œV
S
TVS
图 26. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLVx172 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit, as shown in 图 26, the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
图 26 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500
mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, then one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current and any resistance in the input path.
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Feature Description (接下页)
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see 图 26. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The input pins of the TLVx172 are protected from excessive differential voltage with back-to-back diodes; see 图
26. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits,
fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond
rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, then limit
the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can limit the input signal current. This input series resistor degrades the low-noise performance of the
TLVx172. 图 26 shows an example configuration that implements a current-limiting feedback resistor.
8.3.4 Capacitive Load and Stability
The dynamic characteristics of the TLVx172 are optimized for common operating conditions. The combination of
low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain
peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way
to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. 图
27 and 图 28 show graphs of small-signal overshoot versus capacitive load for several values of ROUT. See the
Feedback Plots Define Op Amp AC Performance application note for details of analysis techniques and
application circuits.
60
50
40
30
20
10
0
50
40
30
20
10
0
RI
=
1
k
RF
=
+
1 k
18
V
-
ROUT
+
-
VIN
= 100mV
+
CL
18
V
+
18 V
ROUT = 0
ROUT= 0
-
ROUT
+
+
-
RL
CL
R = 25
RO = 25
OUT
RRO ==2255
OUT
VIN
= 100mV
18
V
RO = 50
ROUT= 50
RRO ==5500
OUT
0p
100p
200p
Capacitive Load (F)
100-mV output step, G = 1
300p
400p
500p
0p
100p
200p
300p
400p
500p
C013
Capacitive Load (F)
100-mV output step, G = –1
C013
图 28. Small-Signal Overshoot vs Capacitive Load
图 27. Small-Signal Overshoot vs Capacitive Load
18
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8.4 Device Functional Modes
8.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the TLVx172 device extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. 表 2 lists the typical performances in this range.
表 2. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
PARAMETER
Input common-mode voltage
Offset voltage
MIN
TYP
MAX
UNIT
V
(V+) – 2
(V+) + 0.1
7
12
mV
Offset voltage vs temperature
Common-mode rejection
Open-loop gain
µV/°C
dB
65
60
dB
Gain-bandwidth product
Slew rate
0.3
0.3
MHz
V/µs
8.4.2 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from the
saturated state to the linear state. The output devices of the operational amplifier enter the saturation region
when the output voltage exceeds the rated operating voltage, which is a result from the high input voltage or the
high gain. After the device enters the saturation region, the charge carriers in the output devices require time to
return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to
slew at the normal slew rate. As a result, the propagation delay in case of an overload condition is the sum of the
overload recovery time and the slew time. The overload recovery time for the TLVx172 is approximately 2 µs.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLVx172 operational amplifier provides high overall performance in a large number of general-purpose
applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional
recommendations in the Layout Guidelines section to achieve the maximum performance from this device. Many
applications introduce capacitive loading to the output of the amplifier (which potentially causes instability). To
stabilize the amplifier, add an isolation resistor between the amplifier output and the capacitive load. Typical
Application section shows the process for selecting a resistor.
9.2 Typical Application
This circuit can drive capacitive loads (such as cable shields, reference buffers, MOSFET gates, and diodes).
The circuit uses an isolation resistor (RISO) to stabilize the output of an operational amplifier. RISO modifies the
open-loop gain of the system to ensure that the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
VIN
-VS
œ
Copyright © 2017, Texas Instruments Incorporated
图 29. Unity-Gain Buffer With RISO Stability Compensation
9.2.1 Design Requirements
The design requirements are:
•
•
•
Supply voltage: 30 V (±15 V)
Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
Phase margin: 45° and 60°
9.2.2 Detailed Design Procedure
图 29 shows a unity-gain buffer driving a capacitive load. 公式 1 shows the transfer function for the circuit in 图
29.图 29 does not show the open-loop output resistance of the operational amplifier (Ro).
1 + CLOAD × RISO × s
T(s) =
1 + R + R
× C
× s
o
ISO
LOAD
(1)
The transfer function in 公式 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO
)
and CLOAD. The RISO and CLOAD components determine the frequency of the zero (fz). A stable system is obtained
by selecting RISO so that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB per
decade. 图 30 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.
20
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Typical Application (接下页)
120
AOL
100
80
60
40
20
0
1
fp
=
2 ì Œ ì
R
+ Ro ì C
(
)
ISO
LOAD
40 dB
1
fz
=
2 ì Œ ì RISO ì CLOAD
1 dec
1/ꢀ
20 dB
dec
ROC =
100M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
图 30. Unity-Gain Amplifier With RISO Compensation
Typically, ROC stability analysis is simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. 表 3
shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can replace the TLVx172, see the Capacitive Load
Drive Solution Using an Isolation Resistor precision design.
表 3. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
8.8%
2.35 dB
0.28 dB
60°
9.2.3 Application Curve
The values of RISO that yield phase margins of 45º and 60º for various capacitive loads are determined using the
described methodology. 图 31 shows the results.
1000
60°Phase Margin
45°Phase Margin
100
10
1
0.01
0.1
1
10
CLOAD (nF)
100
1000
C041
图 31. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
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10 Power Supply Recommendations
The TLVx172 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-
impedance power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI)
noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of
the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in 图 33, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
22
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11.2 Layout Example
VIN
+
VOUT
RG
RF
Copyright © 2016, Texas Instruments Incorporated
图 32. Schematic Representation
Place components
close to device
and to each other
to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
RG
GND
VIN
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
Use low-ESR,
ceramic bypass
capacitor
GND
Use low-ESR,
ceramic bypass
capacitor
VSœ
VOUT
Copyright © 2016, Texas Instruments Incorporated
图 33. Operational Amplifier Board Layout for a Noninverting Configuration
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12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.1.2 开发支持
12.1.2.1 TINA-TI™（免费软件下载）
TINA-TI™ 是一款基于 SPICE 引擎的电路仿真程序，简单易用并且功能强大。 TINA-TI™是 TINA 软件的一款免费
全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI™ 提供所有传统的
SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI™ 提供全面的后处理能力，便于用户以多种方式获得结果，用户可从 Analog eLab Design Center（模拟
电子实验室设计中心）免费下载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的功能，从而构建一
个动态快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI™ 软件。请下载 TINA-
TI™ 文件夹中的免费 TINA-TI™ 软件。
12.1.2.2 DIP 适配器 EVM
DIP 适配器 EVM 工具为小型表面贴装器件的原型设计提供了一种简易的低成本方法。评估工具使用以下 TI 封
装：D 或 U (SOIC-8)、PW (TSSOP-8)、DGK (VSSOP-8)、DBV（SOT23-6、SOT23-5 和 SOT23-3）、DCK
（SC70-6 和 SC70-5）以及 DRL (SOT563-6)。DIP 适配器 EVM 也可搭配引脚排使用，或者直接与现有电路相
连。
12.1.2.3 通用运放 EVM
通用运放 EVM 是一系列通用空白电路板，可简化采用各种器件封装类型的电路板原型设计。借助评估模块电路板
设计，可以轻松快速地构造多种不同电路。共有
5
个模型可供选用，每个模型都对应一种特定封装类型。支持
PDIP、SOIC、VSSOP、TSSOP 和 SOT23 封装。
注
这些电路板均为空白电路板，用户必须自行提供相关器件。TI 建议您在订购通用运算放大器
EVM 时申请几个运算放大器器件样品。
12.1.2.4 TI 高精度设计
TI 高精度设计是由 TI 公司高精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选
择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。TI 高精度设计可从
http://www.ti.com.cn/ww/analog/precision-designs/ 在线获取。
12.1.2.5 WEBENCH®滤波器设计器
WEBENCH® 滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。借助 WEBENCH 滤波设计
器，用户可使用精选 TI 运算放大器和 TI 供应商合作伙伴提供的无源组件打造最佳滤波器设计方案。
WEBENCH® 设计中心以基于网络的工具形式提供 WEBENCH® 滤波器设计器。用户通过该工具可在短时间内完
成多级有源滤波器解决方案的设计、优化和仿真。
12.2 文档支持
12.2.1 相关文档
如需相关文档，请参阅：
24
版权 © 2016–2019, Texas Instruments Incorporated
TLV172, TLV2172, TLV4172
www.ti.com.cn
ZHCSFN0C –NOVEMBER 2016–REVISED JANUARY 2019
文档支持 (接下页)
•
•
•
•
《反馈曲线图定义运算放大器交流性能》
《运算放大器的 EMI 抑制比》
《用直观方式补偿跨阻放大器》
《高速运算放大器噪声分析》
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
TLV172
TLV2172
TLV4172
12.4 接收文档更新通知
如需接收文档更新通知，请访问 TI.com.cn 上的器件产品文件夹。单击右上角的“通知我”进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.6 商标
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
DesignSoft is a trademark of DesignSoft, Inc.
12.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2019, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV172IDBVR
TLV172IDBVT
TLV172IDCKR
TLV172IDCKT
TLV172IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
5
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
18VV
18VV
15W
15W
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU | SN
NIPDAU
5
SC70
5
NIPDAU
SOIC
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
TLV172
14P6
TLV2172IDGKR
TLV2172IDGKT
TLV2172IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU
8
250
RoHS & Green
14P6
8
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
TL2172
TLV4172
TLV4172
TLV4172IDR
SOIC
D
14
14
NIPDAU
TLV4172IPWR
TSSOP
PW
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2172 :
Automotive : TLV2172-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV172IDBVR
TLV172IDBVT
TLV172IDCKR
TLV172IDCKT
TLV172IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
5
3000
250
180.0
180.0
178.0
178.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
8.4
8.4
3.23
3.23
2.4
2.4
6.4
5.3
5.3
5.3
5.3
6.4
6.5
6.9
3.17
3.17
2.5
2.5
5.2
3.4
3.4
3.4
3.4
5.2
9.0
5.6
1.37
1.37
1.2
1.2
2.1
1.4
1.4
1.4
1.4
2.1
2.1
1.6
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
5
3000
250
9.0
8.0
SC70
5
9.0
8.0
SOIC
8
2500
2500
2500
250
12.4
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
TLV2172IDGKR
TLV2172IDGKR
TLV2172IDGKT
TLV2172IDGKT
TLV2172IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
250
8
2500
2500
2000
TLV4172IDR
SOIC
D
14
14
TLV4172IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV172IDBVR
TLV172IDBVT
TLV172IDCKR
TLV172IDCKT
TLV172IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
5
3000
250
223.0
202.0
180.0
180.0
356.0
366.0
366.0
366.0
366.0
356.0
356.0
356.0
270.0
201.0
180.0
180.0
356.0
364.0
364.0
364.0
364.0
356.0
356.0
356.0
35.0
28.0
18.0
18.0
35.0
50.0
50.0
50.0
50.0
35.0
35.0
35.0
5
3000
250
SC70
5
SOIC
8
2500
2500
2500
250
TLV2172IDGKR
TLV2172IDGKR
TLV2172IDGKT
TLV2172IDGKT
TLV2172IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
250
8
2500
2500
2000
TLV4172IDR
SOIC
D
14
14
TLV4172IPWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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重要声明和免责声明
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