TLV1805-Q1 [TI]
具有推挽输出和关断模式的汽车级高电压比较器;
| 型号： | TLV1805-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有推挽输出和关断模式的汽车级高电压比较器 比较器 |
| 文件： | 总36页 (文件大小：1932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
具有关断功能的 TLV1805-Q1 40V、轨至轨输入、推挽输出、高电压汽车
比较器
1 特性
3 说明
1
•
具有符合 AEC-Q100 标准的下列特性：
TLV1805-Q1 高电压比较器集独特的宽电源范围、推
挽输出、轨至轨输入、低静态电流、关断功能和快速输
出响应组合特性于一体。所有这些 特性 使该比较器非
常适合 需要 在正电压轨或负电压轨上进行检测的应
用，例如智能二极管控制器的反向电流保护、过流检测
和过压保护电路，其中推挽输出级用于驱动 P 沟道或
N 沟道 MOSFET 开关的栅极。
–
器件温度等级 1：–40°C 至 +125°C 的环境工作
温度范围
–
–
器件 HBM ESD 分类等级 2
器件 CDM ESD 分类等级 C6
•
•
•
•
•
•
•
•
•
•
电源电压范围：3.3V 至 40V
低静态电流：135µA
高峰值电流推挽输出
具有相位反转保护功能的轨至轨输入
内置迟滞：14mV
高峰值电流推挽输出级是高电压比较器的一个特色，它
具有允许输出以较快的边沿速率主动将负载驱动至任一
电源轨的优势。对于需要快速 将 MOSFET 栅极 驱动
至高电平或低电平以将主机连接至电压高于预期的电源
或与其断开的应用而言，这特别有用。其他 特性 （如
低输入失调电压、低输入偏置电流和高阻态关断）使
TLV1805-Q1 能够灵活地处理各种 应用的要求。上电
复位可防止加电时产生错误输出。
250ns 传播延迟
低输入失调电压：500µV
关断后具有高阻态输出
上电复位 (POR)
SOT-23-6 封装
2 应用
TLV1805-Q1 采用 6 引脚 SOT-23 封装并符合 AEC-
Q100 标准，具有 –40°C 至 +125°C 的汽车 1 级温度
范围。
•
•
•
•
•
•
反向电流保护智能二极管控制器
过压、欠压和过流检测
OR-ing MOSFET 控制器
MOSFET 栅极驱动器
高电压振荡器
器件信息(1)
器件型号
封装
SOT-23 (6)
封装尺寸（标称值）
TLV1805-Q1
1.60mm × 2.90mm
针对以下应用的系统监控：
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
–
–
汽车信息娱乐系统和仪表组
HEV/EV 和动力总成
采用 P 沟道 MOSFET 的反向电流和过压保护
采用 N 沟道 MOSFET 的反向电流保护
P-Channel MOSFETs
Clock
Source
Charge
Pump
iBAT
D
S
S
D
System
Power
+
TLV1805-Q1
+
SD
N-Channel MOSFET
Q1
Q2
D2
-
iBAT
System
Power
V
BAT
+
D1
VBAT
-
SD
+
TLV1805-Q1
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSD52
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ............................................... 21
Power Supply Recommendations...................... 28
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
8
9
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
11 器件和文档支持 ..................................................... 29
11.1 文档支持................................................................ 29
11.2 接收文档更新通知 ................................................. 29
11.3 支持资源................................................................ 29
11.4 商标....................................................................... 29
11.5 静电放电警告......................................................... 29
11.6 Glossary................................................................ 29
12 机械、封装和可订购信息....................................... 29
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (May 2019) to Revision B
Page
•
•
已添加 向 “应用” 列表添加了链接 ........................................................................................................................................... 1
已更改 Output High and Low vs Supply Graphs .................................................................................................................. 10
Changes from Original (August 2018) to Revision A
Page
•
已更改 将“预告信息”更改为“生产数据”.................................................................................................................................... 1
Changes from Revision A (May 2019) to Revision B
Page
•
•
已添加 向 “应用” 列表添加了链接 ........................................................................................................................................... 1
已更改 Output High and Low vs Supply Graphs .................................................................................................................. 10
2
Copyright © 2018–2020, Texas Instruments Incorporated
TLV1805-Q1
www.ti.com.cn
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
5 Pin Configuration and Functions
TLV1805-Q1 DBV Package
6-Pin SOT-23
Top View
OUT
V-
1
2
3
6
5
4
V+
SHDN
+IN
-IN
Note the reversed positions of the input pins. This differs from a similar popular pinout.
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
IN+
NO.
4
I
I
Noninverting input
IN–
3
Inverting input
OUT
SHDN
V+
1
O
I
Output
5
Shutdown (active high)
Positive (highest) power supply
Negative (lowest) power supply
6
P
P
V–
2
Copyright © 2018–2020, Texas Instruments Incorporated
3
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
MAX
42
UNIT
V
Supply voltage: VS = (V+) – (V–)
Input pins (IN+, IN–)(2)
Shutdown pin (SHDN)(3)
Current into Input pins (IN+, IN–, SHDN)(2)
Output (OUT)
(V–) – 0.3
(V–) – 0.3
(V+) + 0.3
(V–) + 5.5
±10
V
V
mA
V
(V–) – 0.3
–65
(V+) + 0.3
150
Junction temperature, TJ
Storage temperature, Tstg
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
(3) Shutdown pin is diode-clamped to (V–). Input to SHDN that can swing more than 0.3 V below (V–) must be current-limited to 10 mA or
less.
6.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.3
MAX
UNIT
Supply voltage: VS = (V+) – (V–)
Ambient temperature, TA
40
V
–40
125
°C
6.4 Thermal Information
TLV1805-Q1
DBV (SOT23)
6 PINS
166.9
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
104.2
46.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
31.3
ψJB
46.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018–2020, Texas Instruments Incorporated
TLV1805-Q1
www.ti.com.cn
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
6.5 Electrical Characteristics
VS = 3.3 V to 40 V, VCM = VS / 2; TA = 25°C (unless otherwise noted). Typical values are at VS = 12 V and TA = 25°C,VCM = VS
/ 2
PARAMETER
TEST CONDITIONS
MIN
-4.5
-6.5
TYP
MAX
UNIT
VS = 3.3V, 12V and 40V
±0.5
4.5
VIO
Input offset voltage
mV
VS = 3.3V, 12V and 40V, TA = –40°C to +125°C
TA = –40°C to +125°C
6.5
dVIO/dT
VHYS
VCM
Input offset voltage drift
Input hysteresis voltage
Common-mode voltage range
Input bias current
±2.5
14
μV/°C
mV
V
TA = -40℃ to +125℃
(V–) – 0.2
(V+) + 0.2
IB
0.05
0.05
95
pA
IOS
Input offset current
pA
PSRR
CMRR
Power-supply rejection ratio
Common-mode rejection ratio
VCM = V-
dB
(V–) < VCM < (V+)
80
dB
I
SINK ≤ 5mA, input overdrive = –100 mV,
VOL
Voltage output swing from (V–)
Voltage output swing from (V+)
300
300
mV
VS = 5V, TA = –40°C to +125°C
ISOURCE ≤ 5mA, input overdrive = +100 mV,
VOH
mV
mA
mA
µA
VS = 5V, TA = –40°C to +125°C
Peak charging current (sourcing)
Isc_source
Isc_sink
Vs = 5 V to 40 V
100
100
135
(1)
with output shorted to V-
Peak dis-charging current (sinking)
Vs = 5 V to 40 V
(1)
with output shorted to V+
VS = 12 V, no load, VID = –0.1 V (output low), TA
= 25°C
200
400
IQ
Quiescent current
VS =12V to 40V no load, VID = –0.1 V (output
low), TA = –40°C to +125°C
µA
tOFF
Time to enter shutdown
Time to exit shutdown
CL = 15 pF
1.0
2.3
µs
µs
V
tON
CL = 15 pF
(2)
VSD
Shutdown input: voltage range
V s= 3.3 to 40V, TA = -40 to 125 °C
VS = 3.3 V and 40V, TA = -40 to 125 °C
VS = 3.3 V and 40V, TA = -40 to 125 °C
VS = VSD = 5.5 V
0
2
5.5
0.4
VSD_VIH
VSD_VIL
SHDN pin input high level
SHDN pin input low level
1.35
0.65
V
V
0.015
0.001
9.5
nA
nA
µA
IB-SDH
IQ-SD
SHDN bias current
VS = 5 V, VSD = 0 V
Quiescent current (Shutdown)
VS = 12V; TS = 25°C; VSD > VSD_VIH Min
13
(1) Continuous short circuit can result in excessive heating and exceeding the maximum allowed junction temperature of 150°C. Please
refer to the Maximum Output Current Derating curve in the Typical Operation Plots.
(2) The recommended voltage range if VSD is independent of VS.
6.6 Switching Characteristics
Typical values are at TA = 25°C, VS = 12 V, VCM = VS / 2; Input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
250
450
250
500
18
MAX
UNIT
ns
CL = 15 pF
CL = 4 nF
CL = 15 pF
CL = 4 nF
Propagation delay time, high-to-low
tPHL
tPLH
tR
(1)
ns
ns
Propagation delay time, low-to-high
(1)
ns
20% to 80%, CL = 15 pF
20% to 80%, CL = 4 nF
20% to 80%, CL = 15 pF
20% to 80%, CL = 4 nF
ns
Rise time
Fall time
0.3
µs
10
ns
tF
0.26
45
µs
(2)
tSTART
Power-up time
µs
(1) High-to-low and low-to-high refers to the transition at the input.
(2) During power on, VS must exceed 3.3 V for tON before the output is in a correct state.
Copyright © 2018–2020, Texas Instruments Incorporated
5
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
图 1. Propagation Delay
图 2. Shutdown Timing
6
版权 © 2018–2020, Texas Instruments Incorporated
TLV1805-Q1
www.ti.com.cn
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
6.7 Typical Characteristics
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
500
450
400
350
300
250
200
150
100
50
3
2
Distribution of 2917 Units
30 Typical Units Shown
1
0
-1
-2
-3
0
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
40
Offset Voltage (mV)
图 4. Offset Voltage Histogram
图 3. Input Offset Voltage vs. Supply Voltage
3
2
3
2
30 Typical Units Shown
30 Typical Units Shown
1
1
0
0
-1
-2
-3
-1
-2
-3
-1
0
1
2
3
4
5
6
7
8
9
Input Common Mode Voltage (V)
10 11 12 13
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图 5. Offset Voltage vs. Common Mode
图 6. Offset Voltage vs Temperature
250
225
200
175
150
125
100
75
250
225
200
175
150
125
100
75
125°C
85°C
25°C
-40°C
125°C
85°C
25°C
-40°C
50
50
25
25
0
0
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
VCM = V-
Output Low (VID = -0.1 V)
VCM = V-
Output High (VID = 0.1 V)
图 7. Supply Current vs. Supply Voltage, Output Low
图 8. Supply Current vs. Temperature, Output High
版权 © 2018–2020, Texas Instruments Incorporated
7
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
200
160
120
80
40
35
30
25
20
15
10
5
40V
12V
3.3V
40
0
-40
-80
-120
-160
-200
0
-5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
1
2
3
4
5
6
VCM (V)
7
8
9
10 11 12
TA = 125 °C
图 9. Input Bias Current vs. Temperature
图 10. Input Bias Current vs. Common Mode, 125°C
0.5
0.4
0.3
0.2
0.1
0
0.1
0.08
0.06
0.04
0.02
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.02
-0.04
-0.06
-0.08
-0.1
0
1
2
3
4
5
6
VCM (V)
7
8
9
10 11 12
0
1
2
3
4
5
6
VCM (V)
7
8
9
10 11 12
TA = 25 °C
TA = -40 °C
图 11. Input Bias Current vs. Common Mode, 25°C
图 12. Input Bias Current vs. Common Mode, -40°C
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
125 °C
85 °C
25 °C
-40 °C
125 °C
85 °C
25 °C
-40 °C
4
4
2
2
0
0
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
VCM = V-
图 13. Shutdown Supply Current vs. Supply Votlage
VCM = V-
图 14. Shutdown Supply Current vs. Supply Votlage
8
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TLV1805-Q1
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ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
1.85
0.8
0.75
0.7
40V
36V
24V
12V
5V
3.3V
40V
36V
24V
12V
5V
3.3V
Referenced to V-
Referenced to V-
1.7
1.55
1.4
0.65
0.6
1.25
1.1
0.55
0.5
0.95
0.8
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图 15. Shutdown Voltage High Threshold vs. Temperature
图 16. Shutdown Voltage Low Threshold vs. Temperature
2
0.8
125°C
85°C
50°C
25°C
0°C
-40°C
-40°C
0°C
25°C
50°C
85°C
125°C
Referenced to V-
Referenced to V-
0.75
0.7
1.8
1.6
1.4
1.2
1
0.65
0.6
0.55
0.5
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
图 17. Shutdown Voltage High Threshold vs. Supply Voltage
图 18. Shutdown Voltage Low Threshold vs. Supply Voltage
12
18
125°C
85°C
10
25°C
-40°C
16
14
12
10
8
8
6
4
6
4
2
2
0
0
-2
-2
0
1
2
Shutdown Voltage (V)
3
4
5
6
0
1
2
Shutdown Voltage (V)
3
4
5
6
图 19. Shutdown Input Bias Current vs. Shutdown Input
图 20. Shutdown Input Bias Current vs. Shutdown Input
Voltage, High Temperatures
Voltage, Low Temperatures
版权 © 2018–2020, Texas Instruments Incorporated
9
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
20
10
5
100
90
80
70
60
50
40
30
20
10
0
5V
12V
21V
30V
40V
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
VSD = 5 V
DBV SOT-23-6 Package
图 21. Shutdown Input Bias Current vs. Temperature
图 22. Maximum Continuous Output Current vs. Ambient
Temperature
0.10
0.10
125 °C
85 °C
25 °C
0 °C
125 °C
85°C
25 °C
0 °C
-40 °C
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.09
0.08
-40 °C
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
ISINK = 1 mA
ISOURCE = 1 mA
图 23. Output Low Voltage vs. Supply Voltage
图 24. Output High Voltage vs. Supply Voltage
10
1
10
1
125 °C
85 °C
50 °C
25 °C
0 °C
125 °C
85 °C
50 °C
25 °C
0 °C
-40 °C
-40 °C
100m
10m
1m
100m
10m
1m
100m
100m
1 10
Output Sinking Current (mA)
100
100m
1 10
Output Sourcing Current (mA)
100
VS = 3.3 V
VS = 3.3 V
图 25. Output Voltage vs. Output Sinking Current
图 26. Output Voltage vs. Output Sourcing Current
at 3.3V
at 3.3V
10
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Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
10
10
125 °C
85 °C
50 °C
25 °C
0 °C
125 °C
85 °C
50 °C
25 °C
0 °C
1
1
-40 °C
-40 °C
100m
10m
1m
100m
10m
1m
100m
100m
1 10
Output Sinking Current (mA)
100
100m
1 10
Output Sourcing Current (mA)
100
VS = 12 V
VS = 12 V
图 27. Output Voltage vs. Output Sinking Current
图 28. Output Voltage vs. Output Sourcing Current
at 12V
at 12V
10
1
10
125 °C
85 °C
50 °C
25 °C
0 °C
125 °C
85 °C
50 °C
25 °C
0 °C
1
100m
10m
1m
-40 °C
-40 °C
100m
10m
1m
100m
100m
1 10
Output Sinking Current (mA)
100
100m
1 10
Output Sourcing Current (mA)
100
VS = 40 V
VS = 40 V
图 29. Output Voltage vs. Output Sinking Current
图 30. Output Voltage vs. Output Sourcing Current
at 40V
at 40V
25
20
15
10
5
25
20
15
10
5
3V
5V
12V
24V
40V
125°C
85°C
25°C
-40°C
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
2
6
10
14
18
22
26
Supply Voltage (V)
30
34
38
图 31. Hysteresis vs. Temperature
图 32. Hysteresis vs. Supply Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
25
20
15
10
5
1000
900
800
700
600
500
400
300
200
100
0
Distribution of 2917 Units
125°C
85°C
25°C
-40°C
0
0
1
2
3
4
5
6
7
Common Mode Voltage (V)
8
9
10 11 12
Hysteresis (mV)
图 33. Hysteresis vs Common-Mode Voltage
图 34. Hysteresis Histogram
1000
1000
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
125 °C
85 °C
50 °C
25 °C
0 °C
800
700
800
700
600
500
600
500
-40 °C
400
300
400
300
200
200
100
100
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 3.3 V
CL = 15pF
VS = 3.3 V
CL = 15pF
图 35. TPLH Response Time vs. Overdrive
图 36. TPHL Response Time vs. Overdrive
at 3.3V
at 3.3V
1000
1000
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
800
700
800
700
600
500
600
500
400
300
400
300
200
200
100
100
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 5 V
CL = 15pF
VS = 5 V
CL = 15pF
图 37. TPLH Response Time vs. Overdrive
图 38. TPHL Response Time vs. Overdrive
at 5V
at 5V
12
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Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
1000
1000
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
800
700
800
700
600
500
600
500
400
300
400
300
200
200
100
100
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 12 V
CL = 15pF
VS = 12 V
CL = 15pF
图 39. TPLH Response Time vs.
图 40. TPHL Response Time vs. Overdrive
Overdrive at 12V
at 12V
2000
1000
2000
1000
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
800
700
800
700
600
500
600
500
400
300
400
300
200
200
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 40 V
CL = 15pF
VS = 40 V
CL = 15pF
图 41. TPLH Response Time vs. Overdrive
图 42. TPHL Response Time vs. Overdrive
at 40V
at 40V
1000
900
1000
900
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
800
700
800
700
600
500
600
500
-40 °C
0 °C
25 °C
50 °C
85 °C
125 °C
400
400
300
300
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 3.3 V
CL = 4nF
VS = 3.3 V
CL = 4nF
图 43. TPLH Response Time vs. Overdrive
图 44. TPHL Response Time vs. Overdrive
at 3.3V
at 3.3V
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Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
1000
1000
125 °C
85 °C
50 °C
25 °C
0 °C
125 °C
85 °C
50 °C
25 °C
0 °C
900
900
800
700
800
700
-40 °C
-40 °C
600
500
600
500
400
400
300
300
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 5 V
CL = 4nF
VS = 5 V
CL = 4nF
图 45. TPLH Response Time vs. Overdrive
图 46. TPHL Response Time vs. Overdrive
at 5V
at 5V
1000
900
1000
900
125 °C
125 °C
85 °C
50 °C
25 °C
0 °C
85 °C
50 °C
25 °C
0 °C
800
700
800
700
-40 °C
-40 °C
600
500
600
500
400
400
300
300
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 12 V
CL = 4nF
VS = 12 V
CL = 4nF
图 47. TPLH Response Time vs.
图 48. TPHL Response Time vs. Overdrive
Overdrive at 12V
at 12V
3000
2000
3000
2000
125 °C
85 °C
50 °C
25 °C
0 °C
125 °C
85 °C
50 °C
25 °C
0 °C
-40 °C
-40 °C
1000
900
1000
900
800
800
700
600
700
600
500
500
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
20
30 40 50 70 100 200 300
Input Overdrive Voltage (mV)
500 700 1000
VS = 40 V
CL = 4nF
VS = 40 V
CL = 4nF
图 49. TPLH Response Time vs. Overdrive
图 50. TPHL Response Time vs. Overdrive
at 40V
at 40V
14
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Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
1000
1000
500
500
300
200
300
200
100
100
50
50
30
20
30
20
10
10
125 °C
85 °C
25 °C
- 40°C
125 °C
85 °C
25 °C
-40 °C
5
5
3
2
3
2
1
0.01 0.02
1
0.01 0.02
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
VS = 3.3 V
VS = 3.3 V
图 51. tRISE vs. Capacitive Load
图 52. tFALL vs. Capacitive Load
at 3.3V
at 3.3V
1000
500
1000
500
300
200
300
200
100
100
50
50
30
20
30
20
10
10
125 °C
85 °C
25 °C
- 40°C
125 °C
85 °C
25 °C
-40 °C
5
5
3
2
3
2
1
0.01 0.02
1
0.01 0.02
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
VS = 5 V
VS = 5 V
图 53. tRISE vs. Capacitive Load
图 54. tFALL vs. Capacitive Load
at 5V
at 5V
1000
500
1000
500
300
200
300
200
100
100
50
50
30
20
30
20
10
10
125 °C
85 °C
25 °C
- 40°C
125 °C
85 °C
25 °C
-40 °C
5
5
3
2
3
2
1
0.01 0.02
1
0.01 0.02
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
VS = 12 V
VS = 12 V
图 55. tRISE vs. Capacitive Load
图 56. tFALL vs. Capacitive Load
at 12V
at 12V
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Typical Characteristics (接下页)
at TA = 25°C, VS = 12 V, VCM = VS/2, and input overdrive = 100 mV (unless otherwise noted)
3000
2000
3000
2000
1000
500
1000
500
200
100
50
200
100
50
20
10
5
20
10
5
125 °C
85 °C
25 °C
- 40°C
125 °C
85 °C
25 °C
-40 °C
2
1
2
1
0.01 0.02
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
0.01 0.02
0.05 0.1 0.2 0.3 0.5
Capacitive Load (nF)
1
2
3 4 567 10
VS = 40 V
VS = 40 V
图 57. tRISE vs. Capacitive Load
图 58. tFALL vs. Capacitive Load
at 40V
at 40V
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
-40 °C
25 °C
85 °C
125 °C
-40 °C
25 °C
85 °C
125 °C
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
0
4
8
12
16
Supply Voltage (V)
20
24
28
32
36
40
图 59. Turn-On Time vs Supply Voltage
图 60. Turn-Off Time vs Supply Voltage
110
100
90
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
-40 °C
0 °C
25 °C
85 °C
125 °C
80
70
60
50
40
30
20
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图 61. Start-Up Time vs Supply Voltage
图 62. Power On Reset Voltage vs. Temperature
16
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7 Detailed Description
7.1 Overview
The TLV1805-Q1 comparator features a rail-to-rail inputs with a push-pull output stage that operates at supply
voltages as high as 40 V or ±20 V. The rail-to-rail input stage enables detection of signals close to the supply
and ground while the push-pull output stage creates fast transition edges to either supply rail. A low supply
current of 135 μA per channel with small, space-saving packages, makes these comparators versatile for use in
a wide range of applications, from portable to industrial.
7.2 Functional Block Diagram
VCC
IN+
IN-
+
OUT
œ
SHDN
Bias
Power-on-reset
GND
7.3 Feature Description
7.3.1 Rail to Rail Inputs
The TLV1805-Q1 comparator features a CMOS input with a common-mode range that includes both supply rails.
The TLV1805-Q1 is designed to prevent phase inversion when the input pins exceed the supply voltage.
7.3.2 Power On Reset
The TLV1805-Q1 incorporates a power-on reset that holds the output in a High-Z state until the minimum
operating supply voltage has been reached for at least 20µs. After this time the output will start responding to the
inputs. This feature prevents false outputs during power-up and power-down.
7.3.3 High Power Push-Pull Output
The push-pull output stage, which is unique for high-voltage comparators, offers the advantage of allowing the
output to actively drive the load to either supply rail with a fast edge rate. A high output sink and source peak
current of over 100mA allows quickly charging and dis-cahrging capacitive loads such as cables and power
MOSFET gates. Caution must be taken to ensure that the package power dissipation is not exceeded when
switching at these high supply voltages. See 图 22 for the output current derating curve.
7.3.4 Shutdown Function
The TLV1805-Q1 has a logic level SHDN input. When the shutdown SHDN input is 1.4V above V-, the TLV1805-
Q1 is disabled. When disabled, the output becomes high impedance (Hi-Z), and the supply current drops to
below 10µA. The input bias current remains unchanged. Voltages may still be applied to the comparator inputs
as long as V+ power is still applied and the applied input voltages are still within the specified input voltage
range.
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Feature Description (接下页)
CAUTION
The maximum voltage on the shutdown pin is +5.5V referred to V-, regardless of
supply voltage. Connect the SHDN pin to V- if shutdown is not used. Do not float the
SHDN pin.
A high value pull-up or pull-down resistor on the output may be required if a specific logic level is required during
shutdown (when the output is High-Z). This prevents logic inputs from floating to illegal states when the
comparator output is in High-Z mode.
Since the Shutdown threshold voltage is a tested parameter, the shutdown pin can also be used as a second
comparison input to provide a secondary measurment, such as overvoltage monitoring, as shown in the P-
Channel Reverse Current Protection With Overvotlage Protection circuit.
7.3.5 Internal Hysteresis
The TLV1805-Q1 contains 14mV of internal hysteresis.
The hysteresis transfer curve is shown in 图 63. This curve is a function of three components: VTH, VOS, and
VHYST
:
•
•
VTH is the actual set voltage or threshold trip voltage.
VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
•
VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(14 mV for the TLV1805-Q1).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
图 63. Hysteresis Transfer Curve
7.4 Device Functional Modes
7.4.1 External Hysteresis
External Hysteresis may be added to further improve response to noisy or slow-moving input signals.
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Device Functional Modes (接下页)
7.4.1.1 Inverting Comparator With Hysteresis
+VCC
+5 V
R1
1 MW
VIN
5 V
0 V
RLOAD
VA
VO
100 kW
VA2
1.67 V
VA1
3.33 V
R3
1 MW
VIN
R2
1 MW
VO High
+VCC
VO Low
+VCC
R1
VA1
R2
R3
R1
VA2
R2
R3
Copyright © 2016, Texas Instruments Incorporated
图 64. TLV1805-Q1 in an Inverting Configuration With Hysteresis
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in 图 64. When VIN at the inverting input is less than VA, the output voltage is
high (for simplicity, assume VO switches as high as VCC). The three network resistors can be represented as R1
|| R3 in series with R2. 公式 1 defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low, very close to ground. In this case, the three network
resistors can be presented as R2 || R3 in series with R1. Use 公式 2 to define the low to high trip voltage (VA2).
R2 || R3
VA2 = VCC ´
R1 + (R2 || R3)
(2)
(3)
公式 3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
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Device Functional Modes (接下页)
7.4.1.2 Noninverting Comparator With Hysteresis
+VCC
+5 V
VREF
VO
+2.5 V
VA
VIN
RLOAD
R1
330 kW
R2
1 MW
VO High
+VCC
VO Low
VIN1
5 V
0 V
R2
R1
VA = VREF
R2
VO
VA = VREF
R1
VIN2
VIN1
1.675 V 3.325 V
VIN
VIN2
Copyright © 2016, Texas Instruments Incorporated
图 65. TLV1805-Q1 in a Noninverting Configuration With Hysteresis
A noninverting comparator with hysteresis requires a two-resistor network, as shown in 图 65, and a voltage
reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low
to high, VIN must rise to VIN1. Use 公式 4 to calculate VIN1
VREF
.
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is high, the output is also high. For the comparator to switch back to a low state, VIN must drop to VIN2
such that VA is equal to VREF. Use 公式 5 to calculate VIN2
VREF (R1 + R2) - VCC ´ R1
.
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in 公式 6.
R1
DVIN = VCC
´
R2
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV1805-Q1 family of devices can be used in a wide variety of applications, such as MOSFET gate drivers,
zero crossing detectors, window comparators, over and undervoltage detectors, and high-side voltage sense
circuits.
8.2 Typical Applications
Comparators are used to differentiate between two different signal levels. For example, a comparator
differentiates between an over-temperature and normal-temperature condition. However, noise or signal variation
at the comparison threshold causes multiple transitions. This application example sets upper and lower
hysteresis thresholds to eliminate the multiple transitions caused by noise.
R
H
576 kΩ
5 V
5 V
R
X
V
+
100 kΩ
OUT
œ
R
Y
+
100 kΩ
œ
V
IN
图 66. Comparator with Hysteresis
8.2.1 Design Requirements
The design requirements are as follows:
•
•
•
•
•
•
Supply voltage: 5 V
Input: 0 V to 5 V
Lower threshold (VL) = 2.3 V ±0.1 V
Upper threshold (VH) = 2.7 V ±0.1 V
VH – VL = 2.4 V ±0.1 V
Low-power consumption
8.2.2 Detailed Design Procedure
A small change to the comparator circuit can be made to add hysteresis. Hysteresis uses two different threshold
voltages to avoid the multiple transitions introduced in the previous circuit. The input signal must exceed the
upper threshold (VH) to transition low, or below the lower threshold (VL) to transition high.
图 66 illustrates hysteresis on a comparator. Resistor RH sets the hysteresis level.
When the output is at a logic high (5 V), RH is in parallel with RX. This configuration drives more current into Ry,
and raises the threshold voltage (VH) to 2.7 V. The input signal must drive above VH = 2.7 V to cause the output
to transition to logic low (0 V).
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Typical Applications (接下页)
When the output is at logic low (0 V), Rh is in parallel with Ry. This configuration reduces the current into Ry, and
reduces the threshold voltage to 2.3 V. The input signal must drive below VL = 2.3 V to cause the output to
transition to logic high (5 V).
For more details on this design, refer to Precision Design TIPD144, Comparator with Hysteresis Reference
Design.
8.2.3 Application Curve
图 67 shows the upper and lower thresholds for hysteresis. The upper threshold is 2.76 V and the lower
threshold is 2.34 V, both of which are close to the design target.
图 67. TLV1805-Q1 Upper and Lower Threshold with Hysteresis
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Typical Applications (接下页)
8.2.4 Reverse Current Protection Using MOSFET and TLV1805-Q1
An N-Channel or P-Channel MOSFET may be used to protect against reverse current. Reverse current is
defined as current flowing from the load (VLOAD) to the source (VBATT). Both the P-Channel and N-Channel
circuits work on the same basic principle, where a comparator monitors the voltage across the MOSFET's
Source and Drain terminals (monitoring VDS). The described circuits also protect against reverse voltage.
MOSFET
Intrinsic
Body Diode
—Off“
VBATT
VLOAD
Source
Drain
—On“
R
DS(ON)
Gate
+
Load
Battery
图 68. Simplified Operational Theory
When the current is flowing from the battery (VBATT) to the load (VLOAD), the battery voltage will be higher than
the load voltage due to voltage drop across the MOSFET caused by the RDS(ON) or the intrinsic body diode
forward voltage drop. The comparator will detect this and turn "on" the MOSFET so that the load current is now
flowing through the low loss RDS(ON) path.
In a reverse current condition, VLOAD will be higher than VBATT. The comparator will detect this and drive the gate
to set VGS = 0 to turn "off" the MOSFET (non-conducting). The body diode is reverse biased and will block
current flow.
For a P-Channel MOSFET, the gate must be driven at least 4V or more below the battery voltage to turn "on" the
MOSFET.
For a N-Channel MOSFET, the gate must be driven 4V or more above the battery voltage to turn "on" the
MOSFET. If a higher voltage is not available in the system, a charge pump is usually required to generate a
voltage higher than the battery voltage to provide the necessary positive gate drive voltage.
8.2.4.1 Minimum Reverse Current
There is a minimum amount of reverse current that is needed to trip the comparator. To detect this reverse
current, a voltage must be dropped across the MOSFET (VMEAS).
When the MOSFET is off, VGS will be in the -600mV to -1V range due to the forward voltage drop (VF) of the
MOSFET body diode. Response to this large voltage will be immediate.
However, with the MOSFET "on" (conducting), the current required to create the trip voltage will be much
greater. The trip voltage drop required across the MOSFET RDS(ON) will be the comparator offset voltage plus half
of the hysteresis.
The maximum offset voltage of the TLV1805-Q1 is 5mV with a typical hysteresis of 14mV. The trip voltage can
be calculated from:
VTRIP = VOS(max) + ( VHYST / 2) = 5 mV + 7 mV = 12 mV
(7)
The actual current trip point will depend on the MOSFET RDS(ON) and VGS drive level. Assuming the MOSFET
has a 22 mΩ on resistance, the trip current is found from:
ITRIP = VTRIP / RDS(ON) = 12 mV / 22 mΩ = 546mA
(8)
23
版权 © 2018–2020, Texas Instruments Incorporated
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
Typical Applications (接下页)
8.2.4.2 N-Channel Reverse Current Protection Circuit
In order to turn "on" the N-Channel MOSFET, the MOSFET gate must be brought "High" above VBATT. If a higher
voltage is not available, a charge pump circuit is required to provide the comparator with a supply voltage above
VBATT
.
J1
External Clock
Input
Charge
Pump
R2
Comparator
Supply Clamp
Clock
Select
EXT
INT
C1
D2
10 kΩ
R1
U1
TLV1805-Q1
47 Ω
Q1
SQ4850EY
N-Channel
100V
1µF
BAT46
D3
15 V
3
4
6
œ
R3
1
C3
35V
10µF
+
47 Ω
G
C2
100V
1µF
2
5
R4
100 kΩ
D4
BAT64
D1
BAT64
VBATT_NCH
VLOAD_OUT_NCH
D
S
Input
Protection
Internal Oscillator Output œ 10kHz
JP1
Short
C6
50V
Oscillator Supply
C4
50V
0.22µF
D5
SMAJ28CA
0.22µF
D6
DB2430100L
C7
50V
0.22µF
R7
56 kΩ
R6
56 kΩ
R5
56 kΩ
Oscillator
Circuit
GND
GND
3
6
œ
1
+
2
U2
TLV1805-Q1
4
5
C5
1nF
R8
56 kΩ
图 69. N-Channel Reverse Current Schematic with Oscillator
C1, D1, D2 & C2 form the charge pump. The AC drive signal is applied through C1 into the charge pump. The
result is a voltage across C2 that is approximately equal to the peak-to-peak amplitude of the AC waveform,
minus 700mV. If a 12Vpp waveform is applied to the C1 input, 11.3V will be generated across C2. This voltage is
on top of the VBATT voltage, so the voltage seen from the D2-C2 junction ground is 23.3V. This provides the
needed higher voltage to drive the MOSFET and power the comparator.
An external oscillator source may be used, such as the gate drive output of a switcher, system clock or any
avaialbe clock source in the 1kHz to 10MHz range. The charge pump should be fed by a 50 percent duty cycle
square wave source of 5Vpp or more. Since the input capacitor of the charge-pump effectively AC-couples the
input, the oscillator may be ground referenced.
R1 and D3 form the comparator supply clamp to limit the gate drive to prevent exceeding the VGS(MAX) of the
MOSFET during an overvotlage event. R1 must be sized to dissapate any expected overvoltage.
D4 and R2 clamp the input should VBATT drop below VLOAD (as in a supply reversal).
The output diode D6 is used to anchor the output during light or floating loads. At light or no loads, there is a
possibility the MOSFET could turn on due to the comparator offset voltage. The diode provides enough of a
negative leakage to turn the MOSFET off.
8.2.4.2.1 N-Channel Oscillator Circuit
The oscillation frequency is determined by R5 and C5. The default configuration oscillates around 10kHz
(depending on RC component tolerances). For further information on selecting these RC values, please see the
Engineers Cookbook Circuit entitled Oscillator Circuit (SNOA990). Do note that R5 does present an AC load to
the oscillator output, and should be sized appropriately to minimize the peak charging currents of C5 (use large
resistors and small capacitors).
24
版权 © 2018–2020, Texas Instruments Incorporated
TLV1805-Q1
www.ti.com.cn
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
Typical Applications (接下页)
The output amplitude is roughly equivalent to the VLOAD voltage minus the TLV1805-Q1 output saturation
(approximately 300mV). With a maximum supply voltage of 40V for the TLV1805-Q1, the oscillator circuit is
capable of generating up to 39Vpp!
The TLV1805-Q1 oscillator typically starts oscillating when VLOAD reaches 2.8V, though full specified operation
does not occur until 3.3V.
For more information, please see the TLV1805-Q1 Evaluation Module Users Guide TLV1805-Q1 Evaluation
Module Users Guide (SNOU158).
8.2.5 P-Channel Reverse Current Protection Circuit
图 70 shows the P-Channel circuit. In order to turn "on" the P-Channel MOSFET, the gate must be brought "Low"
below VBATT . To accomplish this, the comparators Inverting input is tied to the battery side of the MOSFET to set
the output low during forward current.
R2
47 Ω
Q1
SQJ459EP
P-Channel
G
R3
100 kΩ
VBATT_PCH
VLOAD_OUT_PCH
S
D
U1
TLV1805-Q1
6
Input
Protection
4
+
C2
50V
0.22µF
1
C1
25V
10µF
R1
10 kΩ
3
œ
2
D1
SMAJ28CA
5
D5
DB2430100L
D3
15 V
D2
BAT64
C3
50V
0.22µF
GND
GND
D4
BAT64
R4
560 Ω
图 70. P-Channel Reverse Current Schematic
This design implements a "floating ground" topology, using D3, D4 and R12, to allow for clamping the
comparator supply voltage as to not exceed the VGS(MAX) of the MOSFET. During a reverse voltage or supply
drop, D4 also prevents C1 from discharging to allow some standby time to keep the comparator powered during
the event.
During "normal" forward current operation, the quiescent current of the comparator circuit flows through D4 and
R4. D3 provides the clamping during an overvoltage event.
R4 is sized to allow for minimum voltage drop during "normal" operation, but also to allow for dissipation during
overvoltage events. R4 will see the battery voltage minus the D3 Zener voltage during an overvoltage event.
Since the comparator supply voltage is clamped by D3, the maximum battery voltage is determined by the power
dissipated by R4 and the VDS(MAX) of the MOSFET.
R2 limits the gate current should there be any transients and should be a low value to allow the peak currents
needed to drive the MOSFET gate capacitance. R3 provides the pull-down needed when the comparator output
goes high-Z during power-off to ensure the gate is pulled to zero volts to turn off the MOSFET.
R1 and D2 clamp the input voltage should the VBATT input go below the floating ground Voltage (such as in a
battery reversal). A bonus feature is that during a reverse battery voltage condition, D2 and R1 pull the floating
ground down towards the negative potential, providing power to the comparator during reverse voltage.
The output clamp diode D5 is used to anchor the output during light or floating loads. At light or no loads, there is
a possibility the MOSFET could turn on due to the comparator offset voltage. The diode provides enough of a
negative leakage to turn the MOSFET off.
版权 © 2018–2020, Texas Instruments Incorporated
25
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
Typical Applications (接下页)
If shutdown of the comparator circuit is desired, a transistor or MOSFET switch can be placed between the
ground end of R4 and ground. The MOSFET will be in body diode mode when the comparator is disabled.
8.2.6 P-Channel Reverse Current Protection With Overvotlage Protection
The SHDN pin can be utilized to add Overvotlage Protection (OVP) by adding a second MOSFET, zener diode
and resistor, as shown in 图 71.
G
G
R2
100 kΩ
R3
22 Ω
Q1
P-Channel
Q2
P-Channel
VBATT
VLOAD_OUT
S
D
S
D
U1
TLV1805-Q1
6
1
2
C1
50V
1µF
4
+
R1
10 kΩ
3
œ
5
ZD1
13 V
GND
GND
Shutdown when > 1.35V
RPD
13.7 kΩ
图 71. Adding Overvoltage Protection Using SHDN Pin
When the SHDN pin is pulled 1.35 V above V-, the comparator is placed in shutdown. During shutdown, the
comparator output goes Hi-Z and R2 pulls the gate and source together to turn off the MOSFET (VGS = 0 V).
RPD pulls the SHDN pin low while the Zener diode is not conducting (< VZ). When ZD1 reaches its breakdown
voltage and starts conducting, it will pull RPD up to a voltage calculated to place >1.35 V on the shutdown pin.
The Zener diode ZD1 should be chosen so that the breakdown voltage (VB) is 1.35 V below the desired
overvoltage point. The Zener should have low sub-threshold leakage and a sharp knee, such as the low power
1N47xx or BZD series.
The pull-down resistor RPD should be chosen to create 1.35 V at the desired Zener diode current (usually 100uA
to 1mA) at the Zener breakdown voltage. Actual resistor value should be verified on the bench due to differences
in actual Zener diode threshold voltages.
If a 14.3 V overvotlage trip point (OVP) is desired, the Zener Diode voltage should be 12.95 V. We will choose a
100uA Zener current. The required Zener diode breakdown voltage is determined from:
VB = VOV - 1.35 V = 14 .3V - 1.35 V = 12.95 V
(9)
RPD = 1.35 V / 100 µA = 13.5 kΩ (13.7kΩ nearest value)
(10)
Resistor RPD may be split into two resistors to create a voltage divider if more precise trip points are needed, or
a more convenient zener voltage is desired. Series voltage references can also be used if more accuracy is
desired. A second resistor in series with the Zener or reference can extend the breakdown voltage.
The maximum voltage allowed on the Shutdown pin is 5.5V, so make sure the highest VBATT voltage does not
exceed 5.5 V.
Note that the above circuit, as shown for simplicity, does not protect against reverse voltage. Reverse clamping
diodes would be needed on the -IN, SHDN and Load Output. Also make sure VBATT does not exceed the
VGS(MAX) of the MOSFET.
26
版权 © 2018–2020, Texas Instruments Incorporated
TLV1805-Q1
www.ti.com.cn
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
Typical Applications (接下页)
8.2.7 ORing MOSFET Controller
The previous reverse current circuits may be combined to create an OR'ing supply controller, utilizing either the
P-Channel or N-Channel topologies.
For the previous P-Channel circuit, if no negative input voltages are possible, and the input voltage is below the
MOSFET's VGS(MAX) , then D3, D4 and R4 may be eliminated (the D2 anode, U1 pins 2 and 5, and C1 can be
directly grounded).
For the N-Channel circuit, the oscillator drive can be shared between the channels, or eliminated if a higher
system voltage is available to provide the higher votlage.
Charge Pump
Gate
Drive
+
TLV1805-Q1
+
SD
Q1
-
Power
Supply
#1
Charge Pump
System
Gate
Power
Drive
+
TLV1805-Q1
+
SD
Q2
-
Power
Supply
#2
图 72. N-Channel OR'ing MOSFET Controller
版权 © 2018–2020, Texas Instruments Incorporated
27
TLV1805-Q1
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
www.ti.com.cn
9 Power Supply Recommendations
The TLV1805-Q1 family of devices is specified for operation from 3.3 V to 40 V (±1.65 to ±20 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Recommended Operating Conditions section.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement; see the Layout
Guidelines section.
The TLV1805-Q1 does not contain reverse battery protection, so applying negative voltage to the supply pins
must be avoided. The TLV1805-Q1 cannot withstand ISO 16750 type waveforms alone and requires external
protection circuitry.
10 Layout
10.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, maintain the following layout guidelines:
•
•
•
Use a printed circuit board (PCB) with a good, unbroken low-inductance ground plane. Proper grounding (use
of ground plane) helps maintain specified performance of the TLV1805-Q1 family of devices.
To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) as close
as possible to VS as shown in 图 73.
On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from the output.
•
•
Solder the device directly to the PCB rather than using a socket.
Run the ground pin ground trace under the device up to the bypass capacitor, shielding the inputs from the
outputs.
10.2 Layout Example
图 73. Oscillator Circuit Layout Example
28
版权 © 2018–2020, Texas Instruments Incorporated
TLV1805-Q1
www.ti.com.cn
ZHCSJD8B –AUGUST 2018–REVISED JANUARY 2020
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
精密设计，《具有迟滞功能的比较器参考设计》- TIDU020
参考设计，《窗口比较器参考设计》- TIPD178
应用报告，《在反向电流 应用中使用比较器》- SNOAA23
应用报告，《TLV1805-Q1 EVM ISO 测试结果》- SNOAA13
EVM 用户指南，《TLV1805-Q1 反向电流评估模块用户指南》- SNOU158
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2020, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV1805QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1ULF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV1805QDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TLV1805QDBVRQ1
6
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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