TLV1861DBVR [TI]
具有开漏输出的单路毫微功耗高压比较器 | DBV | 5 | -40 to 125;
| 型号： | TLV1861DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有开漏输出的单路毫微功耗高压比较器 | DBV | 5 | -40 to 125 高压 比较器 |
| 文件： | 总31页 (文件大小：1449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV1861
ZHCSOE4 –DECEMBER 2022
TLV185x 和TLV186x 系列40V 毫微功耗比较器
所有器件均具有上电复位 (POR) 特性，这可确保输出
处于已知状态，直到达到最小电源电压，然后输出才对
输入做出响应，从而防止系统上电和断电期间出现错误
输出。
1 特性
• 低电源电流：每通道440nA
• 宽电源电压范围：1.8V 至40V
• 过轨输入：共模范围比(V-) 高40V，与(V+) 无关
• 失效防护输入：无电源时为高阻抗输入
• 内部上电复位可提供已知的启动条件
• 过驱动输入无相位反转
输入具有过轨功能，其中两个输入均可超过电源电压高
达 40V，并且仍能正常运行。这使得比较器非常适合
高电源电压和低电源电压系统，而不会限制可比较的输
入电压范围。同样，内部反向电池保护功能可防止电源
引脚上的电池安装不当时损坏比较器。
• 高达40V 的反向电池保护
• 推挽输出选项(TLV185x)
TLV185x 比较器具有推挽输出级，而 TLV186x 比较器
具有开漏输出级，因此适用于电平转换。
• 开漏输出选项(TLV186x)
• 温度范围：-40°C 至+125°C
器件信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
TLV1851
• 移动电话和平板电脑
• 耳麦/耳机和耳塞
• PC 和笔记本电脑
• 气体检测仪
• 烟雾和热量探测器
• 运动检测器
• 燃气表
1.60mm x 2.90mm
SOT-23 (5)（预发布）
SOT-23 (5)
TLV1861
3.91mm × 4.90mm
3.00mm × 3.00mm
2.00mm × 2.00mm
1.60mm × 2.90mm
SOIC (8)（预发布）
VSSOP (8)（预发布）
WSON (8)（预发布）
SOT-23 (8)（预发布）
SOIC (14)（预发布）
TLV1852、TLV1862
• 伺服驱动器位置传感器
3.91 mm x 8.65 mm
4.40mm × 5.00mm
3 说明
TSSOP (14)（预发
布）
TLV1854、TLV1864
TLV185x 和TLV186x 是40V 毫微功耗比较器系列，具
有单通道、双通道和四通道选项。该系列提供具有推挽
和开漏输出选项的失效防护 (FS) 输入。这些特性与在
1.8V 至 40V 宽电源电压范围内的毫微功耗运行相结
合，使此系列非常适合在低功耗、常开系统中的电压和
4.20mm x 2.00mm
3.00mm × 3.00mm
SOT-23 (14)（预发
布）
WQFN (16)（预发布）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
温度监测等辅助控制功能。
V+
Open-Drain
only
IN+
IN-
+
-
Output
Control
OUT
SNAPBACK
ESD
CLAMPS
V-
V-
V-
Power-On
Reset
Bias
V-
电源电流与电源电压间的关系
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDE7
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Applications.................................................. 22
8.3 Power Supply Recommendations.............................24
9 Layout.............................................................................25
9.1 Layout Guidelines..................................................... 25
9.2 Layout Example........................................................ 25
10 器件和文档支持............................................................. 26
10.1 Documentation Support.......................................... 26
10.2 接收文档更新通知................................................... 26
10.3 支持资源..................................................................26
10.4 Trademarks.............................................................26
10.5 Electrostatic Discharge Caution..............................26
10.6 术语表..................................................................... 26
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Configuration.............................................................. 3
Pin Configurations: TLV1852 and TLV1862......................4
Pin Configurations: TLV1854 and TLV1864......................5
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Thermal Information....................................................6
6.4 Recommended Operating Conditions.........................7
6.5 Electrical Characteristics.............................................8
6.6 Switching Characteristics............................................9
6.7 Typical Characteristics..............................................10
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagrams....................................... 15
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
5 Pin Configuration and Functions
Pin Configuration
OUT
V-
1
2
3
5
4
V+
IN-
IN+
TLV1851, TLV1861 DBV Package,
SOT-23-5
Top View
(Standard "north west" pinout)
Pin Functions: TLV1851 and TLV1861
PIN
I/O
DESCRIPTION
NAME
NO.
1
OUT
V-
O
-
Output
2
Negative Supply Voltage
Non-Inverting (+) Input
Inverting (-) Input
IN+
IN-
V+
3
I
4
I
5
-
Positive Supply Voltage
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
Pin Configurations: TLV1852 and TLV1862
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
8
V+
OUT1
1
2
Exposed
Thermal
Die Pad
on
OUT2
IN2œ
IN2+
IN1œ
7
6
OUT2
IN2œ
IN1+
3
4
Underside
5
IN2+
Vœ
D, DGK, DDF Packages
8-Pin SOIC, VSSOP, SOT-23-8
Top View
NOTE: Connect exposed thermal pad directly to V- pin.
DSG Package,
8-Pad WSON With Exposed Thermal Pad,
Top View
Pin Functions: TLV1852 and TLV1862
PIN
I/O
DESCRIPTION
NAME
OUT1
NO.
1
O
I
Output pin of the comparator 1
2
Inverting input pin of comparator 1
Noninverting input pin of comparator 1
Negative supply voltage
IN1–
IN1+
V-
3
I
4
—
IN2+
IN2–
OUT2
V+
5
I
Noninverting input pin of comparator 2
Inverting input pin of comparator 2
Output pin of the comparator 2
Positive supply voltage
6
I
7
O
—
8
Connect directly to V- pin
(DSG Package only)
Thermal Pad
—
—
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
Pin Configurations: TLV1854 and TLV1864
OUT1
IN1-
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4-
IN4+
V-
IN1+
V+
1
2
3
4
12
11
10
9
IN4+
V-
IN1+
V+
Thermal
Pad
NC
NC
IN2+
IN3+
IN2+
IN2-
IN3+
IN3-
OUT3
(TOP view,
not to scale)
OUT2
8
NOTE: Connect exposed thermal pad directly to V- pin.
RTE Package, 16-Pad WQFN With Exposed
Thermal Pad, Top View
Not to scale
D, PW, DYY Package, 14-Pin SOIC, TSSOP, SOT-23,
Top View
Pin Functions: TLV1854 and TLV1864
PIN
SOIC
I/O
DESCRIPTION
NAME
WQFN
OUT1
IN1-
1
2
3
4
15
16
1
O
I
Output pin of the comparator 1
Negative input pin of the comparator 1
Positive input pin of the comparator 1
IN1+
I
V+
2
-
Positive supply voltage
IN2+
IN2-
5
6
7
8
4
5
6
I
I
Positive input pin of the comparator 2
Negative input pin of the comparator 2
Output pin of the comparator 2
Output pin of the comparator 3
OUT2
OUT3
O
7
O
I
IN3-
9
8
9
Negative input pin of the comparator 3
Positive input pin of the comparator 3
IN3+
10
I
V-
11
12
13
14
—
—
11
-
Negative supply voltage
IN4+
IN4-
OUT4
NC
12
13
14
3
I
Positive input pin of the comparator 4
Negative input pin of the comparator 4
Output pin of the comparator 4
I
O
—
—
No Internal Connection - Leave floating or GND
No Internal Connection - Leave floating or GND
NC
10
Connect directly to V- pin.
(RTE Package only)
Thermal Pad
PAD
—
—
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
42
Supply voltage: VS = (V+) –(V–)
Differential Input Voltage, VID
42
V
–42
–0.3
–10
–0.3
–0.3
-10
Input pins (IN+, IN–) from (V–)(2)
Current into Input pins (IN+, IN–)(3)
Output (Open-drain version only) from (V–)(4)
Output (OUT) (Push-Pull) from (V–)
Output short circuit current(5)
42
10
V
mA
V
42
(V+) + 0.3
10
V
mA
°C
°C
Junction temperature, TJ
150
Storage temperature, Tstg
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input terminals are diode-clamped to (V–). Inputs (IN+, IN–) can be greater than (V+) and OUT as long as it is within the –0.3 V to
42 V range
(3) Input terminals are diode-clamped to (V–). Input signals that swing more than 0.3 V below (V–) must be current-limited to 10 mA or
less.
(4) Output (OUT) for open drain can be greater than (V+) and inputs (IN+, IN–) as long as it is within the –0.3 V to 42 V range
(5) Short-circuit to (V–) or (V+).
6.2 ESD Ratings
VALUE
±1500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TLV185x/6x
DBV
DGK
PW
RTE
(WQFN)
THERMAL METRIC(1)
(SOT-23 D (SOIC)
)
UNIT
(VSSOP) (TSSOP)
5 pin
168.1
68.1
8 pin
8 pin 14 pin
16 pin
RqJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RqJC(top)
RqJB
37.4
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.4
yJB
37.1
RqJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
MAX
40
UNIT
V
Supply voltage: VS = (V+) –(V–)
Input voltage range from (V–)
40
V
–0.1
0
40
V
Common-mode input voltage range from (V–)
Output voltage for open drain from (V–)
Ambient temperature, TA
40
V
–0.1
–40
125
°C
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
UNIT
6.5 Electrical Characteristics
For VS = (V+) –(V–) = 12V, VCM = VS/2 at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OFFSET VOLTAGE
Input offset
voltage
VOS
±0.25
4.7
5.5
mV
mV
–4.7
–5.5
Input offset
voltage
VOS
TA = –40°C to +125°C
Input offset
dVIO/dT
3
µV/°C
mV
voltage drift
Input hysteresis
voltage
VHYS
1
0
2.8
5
Common-mode
voltage range from
(V–)
VS = 1.8 V to 40 V
TA = –40°C to +125°C
VCM-Range
40
V
POWER SUPPLY
Quiescent current
IQ
per comparator
(output high)
Open Drain Output option, no pull-up resistor
440
1.5
700
850
nA
Quiescent current
per comparator
(output high)
Open Drain Output option, no pull-up resistor, TA
= –40 °C to 125°C
IQ
nA
V
During power on, VS must exceed VPOR for
tON before the output will reflect the input.
VPOR
INPUT BIAS CURRENT
1
250
1500
100
pA
pA
pA
pA
Input bias current
IB
(1)
TA = –40°C to +125°C
TA = –40°C to +125°C
0.1
Input offset
IOS
(1)
current
1000
INPUT CAPACITANCE
OUTPUT
ISINK = 50 µA
20
200
300
mV
mV
Voltage swing
from (V–)
VOL
ISINK = 50 µA
TA = –40°C to +125°C
Open-drain output
leakage current
ILKG
VID = +0.1 V, VPULLUP = (V+)
0.3
pA
(1) This parameter is ensured by design and/or characterization and is not tested in production.
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6.6 Switching Characteristics
For VS = (V+) –(V–) = 12 V, VCM = VS / 2 at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOD = 10 mV, CL = 25 pF, VSTEP = 100 mV
VOD = 50mV, CL = 25 pF, VSTEP = 100 mV
VOD = 100mV, CL = 25 pF, VSTEP = 200 mV
45
16
13
µs
µs
µs
Propagation delay time, high-
to-low
TPD-HL
VOD = 10 mV, CL = 25 pF, RP = 1 MΩ,
57
36
µs
µs
VSTEP = 100 mV
Propagation delay time, low-to-
high (Open-Drain output)
VOD = 50 mV, CL = 25 pF, RP = 1 MΩ,
VSTEP = 100 mV
TPD-LH
VOD = 100 mV, CL = 25 pF, RP = 1 MΩ,
35
µs
µs
VSTEP = 200 mV
TFALL
Output Fall Time, 80% to 20% CL = 25 pF
0.2
POWER ON TIME
TON
Power on-time
2
ms
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics
At TA = 25°C, VS = 12 V, VCM = VS/2 V, RP = 1MΩ (Open Drain only), CL = 25 pF, VOVERDRIVE = 100 mV unless
otherwise noted.
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
VS = 1.8V
VS = 12V
VS = 40V
2.2
2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
图6-1. Offset vs. Temperature
图6-2. Hysteresis vs. Temperature
5
4.6
4.2
3.8
3.4
3
5
4
For 29 units
3
2
1
0
2.6
2.2
1.8
1.4
1
-1
-2
-3
-4
-5
-40C
25C
85C
125C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
图6-4. Hysteresis vs. Common-Mode, 1.8 V
图6-3. Offset vs. Common-Mode, 1.8 V
For 29 units
5
4
3
2
1
0
-1
-2
-3
-4
-5
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Input Common-Mode Voltage (V)
图6-6. Hysteresis vs. Common-Mode, 12 V
图6-5. Offset vs. Common-Mode, 12 V
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics (continued)
5
5
4.6
4.2
3.8
3.4
3
For 29 units
4
3
2
1
0
-1
-2
-3
-4
-5
2.6
2.2
1.8
1.4
1
-40C
25C
85C
125C
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
16
20
24
28
32
36
40
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
图6-7. Offset vs. Common-Mode, 40 V
图6-8. Hysteresis vs. Common-Mode, 40 V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
-40C
25C
85C
125C
-40C
25C
85C
125C
-10
-10
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
图6-10. Bias Current vs. Common-Mode, 12 V
图6-9. Bias Current vs. Common-Mode, 1.8 V
100
90
80
70
60
50
40
30
20
10
0
1n
100p
10p
1p
-40C
25C
85C
125C
100
10
VPU = 1.8V
VPU = 12V
VPU = 40V
-10
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
0
4
8
12
16
20
24
28
32
36
40
Input Common-Mode Voltage (V)
图6-12. Leakage Current vs. Temperature (Open Drain only)
图6-11. Bias Current vs. Common-Mode, 40 V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics (continued)
100
100
10
10
1
1
100m
10m
1m
100m
10m
1m
-40C
25C
85C
125C
-40C
25C
85C
125C
100
100
1
10
100
1m
10m
1
10
100
1m
10m
Output Sinking Current (A)
Output Sinking Current (A)
图6-13. Output Voltage vs. Output Sinking Current, 1.8 V
图6-14. Output Voltage vs. Output Sinking Current, 12 V
100
650
600
550
500
450
400
350
300
250
200
10
1
100m
10m
-40C
-40C
25C
85C
125C
150
100
50
25C
85C
125C
1m
100
1
10
100
1m
10m
0
Output Sinking Current (A)
0
4
8
12
16
20
24
28
32
36
40
Supply Voltage (V)
图6-15. Output Voltage vs. Output Sinking Current, 40 V
图6-16. Supply Current vs. Supply Voltage (Output Low)
650
600
550
500
450
400
350
300
250
200
150
VS = 1.8V
VS = 12V
VS = 40V
100
50
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
图6-18. Supply Current vs. Temperature (Output Low)
图6-17. Supply Current vs. Supply Voltage (Output High)
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics (continued)
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
-40C
25C
85C
125C
0
10
20 30 40 50 70 100
200 300 500 7001,000
Input Overdrive (mV)
图6-19. Supply Current vs. Temperature (Output High)
图6-20. Propagation Delay, Low to High, 1.8 V, Open Drain
output
80
-40C
25C
85C
125C
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
20 30 40 50 70 100
200 300 500 7001,000
Input Overdrive (mV)
图6-21. Propagation Delay, High to Low, 1.8 V
图6-22. Propagation Delay, Low to High, 12 V, Open Drain
output
80
80
-40C
25C
85C
125C
-40C
25C
85C
125C
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0
10
20 30 40 50 70 100
200 300 500 7001,000
10
20 30 40 50 70 100
200 300 500 7001,000
Input Overdrive (mV)
Input Overdrive (mV)
图6-23. Propagation Delay, High to Low, 12 V
图6-24. Propagation Delay, Low to High, 40 V, Open Drain
output
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics (continued)
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
-40C
25C
85C
125C
0
10
20 30 40 50 70 100
200 300 500 7001,000
Input Overdrive (mV)
图6-25. Propagation Delay, High to Low, 40 V
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TLV185x and TLV186x devices are nanopower comparators with push-pull and open-drain output options.
Operating down to 1.8 V while only consuming only 440 nA per channel, the TLV185x and TLV186x are well
suited for voltage, current, and temperature sensing in low and high voltage low-power, always-on systems. An
internal power-on reset circuit ensures that the output remains in a known state during power-up and power-
down. Inputs have fail-safe inputs that can tolerate input transients without damage or false outputs.
7.2 Functional Block Diagrams
V+
Open-Drain
only
IN+
+
Output
Control
OUT
IN-
-
SNAPBACK
ESD
CLAMPS
V-
V-
V-
Power-On
Reset
Bias
V-
图7-1. Block Diagram
7.3 Feature Description
The TLV185x (push-pull output) and TLV186x (open-drain output) devices are nano-power comparators that are
capable of operating at high voltages. This family of comparators feature a fail safe input stage and over the rail
operating condition mode capable of operating up to 40 V, independent of V+. The comparators also have an
internal reverse battery protection feature and Power-On-Reset for known start-up conditions.
7.4 Device Functional Modes
7.4.1 Inputs
7.4.1.1 Operating Common-Mode Ranges
The TLV185x and TLV186x devices have two operating common-mode ranges: within-the-rail and over-the-rail.
Within-the-rail operation: IN+ and IN- are less than (V+)
When an input pin is operating less than (V+), there are two operating regions defined where input voltages can
be compared: low common-mode and high-common mode. In low-common mode which extends typically from 0
V to (V+) - 1 V, the typical input bias current is less than 1 pA. In high common-mode which extends typically
from (V+) - 1 V to (V+), the typical input bias current is less than 14 nA.
Over-the-rail operation: IN+ and/or IN- are greater than (V+)
The TLV185x and TLV186x devices have a distinctive input stage that allows the input common mode range to
extend from 0 V to 40 V independent of the supply voltage. This feature means that operation at low supply
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
voltages does not limit the range of input voltages that can be compared. When an input pin is operating over-
the-rail (above (V+)), the bias current increases to a typical value of 55 nA.
See Figure 6-9 to 6-11 in the Typical Characteristics section for input bias current vs. common-mode voltages.
7.4.1.2 Fail-Safe Inputs
A feature of the TLV185x and TLV186x family is that the inputs are fail safe up to 40 V, independent of (V+). The
inputs are maintained as high input impedance and can be of any value between -0.1 V and 40 V, even while
(V+) is unpowered or below the minimum supply voltage. This feature avoids power sequencing or transient
issues since the inputs are not diode clamped to (V+).
7.4.1.3 Unused Inputs
If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low
offset voltage, tying the inputs directly together can cause high frequency oscillations as the device triggers on
it's own internal wideband noise. Instead, the inputs should be tied to any available voltage that resides within
the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input
can be grounded and the other input connected to a reference voltage, or even (V+).
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in 图 7-2. This curve is a function of three components: VTH, VOS
and VHYST
,
:
• VTH is the actual set voltage or threshold trip voltage.
• VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
• VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise.
(2.8 mV for the TLV185x/6x family)
V
+ V œ (V
/ 2)
V
TH
+ V
V
+ V + (V
OS
/ 2)
TH
OS
HYST
OS
TH
HYST
图7-2. Hysteresis Transfer Curve
7.4.3 Outputs
7.4.3.1 TLV185x Push-Pull Output
The TLV185x features a push-pull output stage capable of both sinking and sourcing current. This allows driving
loads such as LED's and MOSFET gates, as well as eliminating the need for a power-wasting external pull-up
resistor. The push-pull output must never be connected to another output.
Directly shorting the output to the supply rails ((V+) when output "low" or (V-) when output "High") can result in
thermal runaway and eventual device destruction at high (>12 V) supply voltages. If output shorts are possible, a
series current limiting resistor is recommended to limit the power dissipation.
Unused push-pull outputs should be left floating, and never tied to a supply, ground, or another output.
7.4.3.2 TLV186x Open-Drain Output
The TLV186x features an open-drain (also commonly called open collector) sinking-only output stage enabling
the output logic levels to be pulled up to an external voltage from 0 V up to 40 V, independent of the comparator
supply voltage (V+). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
level translation. TI recommends setting the pull-up resistor current to less than 100 uA to optimize VOL logic
levels. Lower pull-up resistor values will help increase the rising edge risetime, but at the expense of increasing
VOL and higher power dissipation. The risetime will be dependent on the time constant of the total pull-up
resistance and total load capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising
edge due to the output RC time constant and increase the risetime.
Directly shorting the output to (V+) can result in thermal runaway and eventual device destruction at high (>12 V)
pull-up voltages. If output shorts are possible, a series current limitng resistor is recommended to limit the power
dissipation.
Unused open drain outputs should be left floating, or can be tied to the (V-) pin if floating pins are not desired.
7.4.4 ESD Protection
7.4.4.1 Inputs
The fail-safe inputs incorporates internal ESD protection circuits on all pins. The fail-safe inputs have ESD
protection from each pin to (V-) which allows these pins to exceed the supply voltage (V+) up to 40 V. If input
voltages are to exceed 40 V, an external clamp would be required. Likewise, negative voltages on the inputs are
ESD clamped to (V-) and should be limited to less than -0.1 V.
If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line,
TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the
clamps conduct. The current should be limited to 10 mA or less. This series resistance can be part of any
resistive input dividers or networks.
7.4.4.2 Outputs
The TLV185x push-pull output protection also contains a conventional diode-type ESD clamps between the
output and (V-), as the output should not exceed the supply rails.
The TLV186x open-drain output ESD protection also consists of a snapback ESD clamp between the output and
(V-) to allow the output to be pulled above (V+) to a maximum of 40 V.
7.4.5 Power-On Reset (POR)
The TLV185x and TLV186x devices have an internal Power-on-Reset (POR) circuit for known start-up or power-
down conditions. While the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated
for up to 2 ms after the VPOR of 1.5 V is crossed. When the supply voltage is equal to or greater than the
minimum supply voltage, and after the delay period, the comparator output reflects the state of the differential
input (VID).
For the TLV185x push-pull output devices, the output is held low during the POR period (ton).
For the TLV186x open drain output devices, the POR circuit will keep the output high impedance (Hi-Z) during
the POR period (ton).
tON
GND
GND + 1.5V
VCC
VOH/2
GND
OUT
图7-3. Power-On Reset Timing Diagram
Note that it the nature of an open collector output that the output will rise with the pull-up voltage during the POR
period.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
7.4.6 Reverse Battery Protection
The TLV185x and TLV186x devices have an internal reverse battery protection feature that prevents damage to
the comparator in the event of improper battery installation to the supply pins. This protection feature works up to
40 V.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Basic Comparator Definitions
8.1.1.1 Operation
The basic comparator compares the input voltage (VIN) on one input to a reference voltage (VREF) on the other
input. In the 图 8-1 example below, if VIN is less than VREF, the output voltage (VO) is logic low (VOL). If VIN is
greater than VREF, the output voltage (VO) is at logic high (VOH). 表 8-1 summarizes the output conditions. The
output logic can be inverted by simply swapping the input pins.
表8-1. Output Conditions
Inputs Condition
IN+ > IN-
Output
HIGH (VOH
)
IN+ = IN-
Indeterminate (chatters - see Hysteresis)
LOW (VOL
IN+ < IN-
)
8.1.1.2 Propagation Delay
There is a delay between from when the input crosses the reference voltage and the output responds. This is
called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input
transitions. This is shown as tpLH and tpHL in 图 8-1 and is measured from the mid-point of the input to the
midpoint of the output.
图8-1. Comparator Timing Diagram
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
8.1.1.3 Overdrive Voltage
The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input
peak-to-peak voltage). The overdrive voltage is 100 mV as shown in the 图 8-1 example. The overdrive voltage
can influence the propagation delay (tp). The smaller the overdrive voltage, the longer the propagation delay,
particularly when <100mV. If the fastest speeds are desired, it is recommended to apply the highest amount of
overdrive possible.
The risetime (tr) and falltime (tf) is the time from the 20% and 80% points of the output waveform.
8.1.2 Hysteresis
The basic comparator configuration may produce a noisy "chatter" output if the applied differential input voltage
is near the comparator's offset voltage. This usually occurs when the input signal is moving very slowly across
the switching threshold of the comparator. This problem can be prevented by adding external hysteresis to the
comparator.
Since the TLV185x and TLV186x devices only have a minimal amount of internal hysteresis of 2.7 mV, external
hysteresis can be applied in the form of a positive feedback loop that adjusts the trip point of the comparator
depending on its current output state.
The hysteresis transfer curve is shown in 图 8-2. This curve is a function of three components: VTH, VOS, and
VHYST
:
• VTH is the actual set voltage or threshold trip voltage.
• VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
• VHYST is the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise.
V
+ V œ (V
/ 2)
V
TH
+ V
V
+ V + (V
OS
/ 2)
TH
OS
HYST
OS
TH
HYST
图8-2. Hysteresis Transfer Curve
For more information, please see Application Note SBOA219 "Comparator with and without hysteresis circuit".
8.1.2.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in 图8-3.
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
+V
CC
+5 V
R
1
1 MΩ
5 V
0 V
V
IN
œ
V
O
V
O
V
A
+
V
A2
V
A1
1.67 V
3.33 V
V
IN
R
3
R
2
1 MΩ
1 MΩ
图8-3. TLV185x in an Inverting Configuration With Hysteresis
The equivalent resistor networks when the output is high and low are shown in 图8-3.
V
High
V Low
O
O
+V
+V
CC
CC
R
R
R
1
1
3
V
A1
V
A2
R
3
R
R
2
2
图8-4. Inverting Configuration Resistor Equivalent Networks
When VIN is less than VA, the output voltage is high (for simplicity, assume VO switches as high as VCC). The
three network resistors can be represented as R1 || R3 in series with R2, as shown in 图8-4.
方程式1 below defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low. In this case, the three network resistors can be presented
as R2 || R3 in series with R1, as shown in 方程式2.
Use 方程式2 to define the low to high trip voltage (VA2).
R2 || R3
VA2 = VCC
´
R1 + (R2 || R3)
(2)
(3)
方程式3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
8.1.2.2 Non-Inverting Comparator With Hysteresis
A non-inverting comparator with hysteresis requires a two-resistor network and a voltage reference (VREF) at the
inverting input, as shown in 图8-5,
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
5 V
0 V
V
œ
REF 2.5 V
V
O
V
O
V
A
V
+
IN
V
V
IN2
IN1
R
1
1.675 V
3.325 V
330 kΩ
V
IN
R
2
1 MΩ
图8-5. TLV185x in a Non-Inverting Configuration With Hysteresis
The equivalent resistor networks when the output is high and low are shown in 图8-6.
V
Low
IN1
V
High
O
O
+V
+V
CC
R
R
R
R
2
1
V
A
= V
V
= V
A REF
REF
1
2
V
IN2
图8-6. Non-Inverting Configuration Resistor Networks
When VIN is less than VREF,, the output is low. For the output to switch from low to high, VIN must rise above the
V
IN1 threshold. Use 方程式4 to calculate VIN1.
VREF
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is greater than VREF, the output is high. For the comparator to switch back to a low state, VIN must
drop below VIN2. Use 方程式5 to calculate VIN2
.
VREF (R1 + R2) - VCC ´ R1
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in 方程式6.
R1
DVIN = VCC
´
R2
For more information, please see Application Notes SNOA997 "Inverting comparator with hysteresis circuit" and
SBOA313 "Non-Inverting Comparator With Hysteresis Circuit".
8.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
It is also possible to use an open drain output device, such as the TLV186x, but the output pull-up resistor must
also be taken into account in the calculations. The pull-up resistor is seen in series with the feedback resistor
when the output is high. Thus, the feedback resistor is actually seen as R2 + RPULLUP. TI recommends that the
pull-up resistor be at least 10 times less than the feedback resistor value.
8.2 Typical Applications
8.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. 图 8-7 shows a
simple window comparator circuit. Window comparators require open drain outputs (TLV186x if the outputs are
directly connected together.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
3.3 V
RPU
R
1
Low when V > V
IN
TH+
10 MΩ
UV_OV
+
V
TH+
Micro-
Controller
œ
Sensor
Open Drain Output Only!
V
IN
R
2
10 MΩ
Low when V < V
IN
TH-
+
Output high
when V is
IN
œ
V
TH-
within window
R
3
Open Drain Output Only!
10 MΩ
图8-7. Window Comparator
8.2.1.1 Design Requirements
For this design, follow these design requirements:
• Alert (logic low output) when an input signal is less than 1.1 V
• Alert (logic low output) when an input signal is greater than 2.2 V
• Alert signal is active low
• Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in 图 8-7. Connect V+ to a 3.3-V power supply and VEE to ground. Make R1, R2
and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds for
the window comparator (VTH+ and VTH–).
With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V. Large resistor values such as 10-MΩare used to
minimize power consumption. The resistor values may be recalculated to provide the desired trip point values.
The sensor output voltage is applied to the inverting and noninverting inputs of the two comparators. Using two
open-drain output comparators allows the two comparator outputs to be Wire-OR'ed together.
The respective comparator outputs will be low when the sensor is less than 1.1 V or greater than 2.2 V. The
respective comparator outputs will be high when the sensor is in the range of 1.1 V to 2.2 V (within the
"window"), as shown in 图8-8.
8.2.1.3 Application Curve
V
IN
V + = 2.2 V
TH
V
= 1.1 V
THœ
OUT
图8-8. Window Comparator Results
For more information, please see Application note SBOA221 "Window comparator circuit".
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
8.3 Power Supply Recommendations
Due to the fast output edges, it is critical to have bypass capacitors on the supply pin to prevent supply ringing
and false triggers and oscillations. Bypass the supply directly at each device with a low ESR 0.1 µF ceramic
bypass capacitor directly between the (V+) pin and ground pins. Narrow peak currents will be drawn during the
output transition time, particularly for the push-pull output device. These narrow pulses can cause un-bypassed
supply lines and poor grounds to ring, possibly causing variation that can eat into the input voltage range and
create an inaccurate comparison or even oscillations.
The device may be powered from both "split" supplies ((V+) &(V-)), or "single" supplies ((V+) and GND), with
GND applied to the (V-) pin. Input signals must stay within the recommended input range for either type. Note
that with a "split" supply the output will now swing "low" (VOL) to (V-) potential and not GND.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
9 Layout
9.1 Layout Guidelines
For accurate comparator applications it is important maintain a stable power supply with minimized noise and
glitches. Output rise and fall times are in the tens of nanoseconds, and should be treated as high speed logic
devices. The bypass capacitor should be as close to the supply pin as possible and connected to a solid ground
plane, and preferably directly between the (V+) and GND pins.
Minimize coupling between outputs and inputs to prevent output oscillations. Do not run output and input traces
in parallel unless there is a (V+) or GND trace between output to reduce coupling. When series resistance is
added to inputs, place resistor close to the device. A low value (<100 ohms) resistor may also be added in series
with the output to dampen any ringing or reflections on long, non-impedance controlled traces. For best edge
shapes, controlled impedance traces with back-terminations should be used when routing long distances.
9.2 Layout Example
Ground
Be er
ꢀꢁ !F
V+
1
2
3
4
8
7
6
5
OUT1
IN1-
IN1+
V-
V+
OUT2
IN2-
Input Resistors
Close to device
OK
V+ or GND
Ground
IN2+
图9-1. Dual Layout Example
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TLV1861
TLV1861
ZHCSOE4 –DECEMBER 2022
www.ti.com.cn
10 器件和文档支持
10.1 Documentation Support
10.1.1 Related Documentation
Analog Engineers Circuit Cookbook: Amplifiers (See Comparators section) - SLYY137
Precision Design, Comparator with Hysteresis Reference Design—TIDU020
Window comparator circuit - SBOA221
Reference Design, Window Comparator Reference Design—TIPD178
Comparator with and without hysteresis circuit - SBOA219
Inverting comparator with hysteresis circuit - SNOA997
Non-Inverting Comparator With Hysteresis Circuit - SBOA313
A Quad of Independently Func Comparators - SNOA654
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TLV1861
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV1861DBVR
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1861
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明