TLV2474AQDRQ1_技术文档

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SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

D

Qualification in Accordance With

AEC-Q100

D

High Output Drive Capability

†

−

10 mA at 180 mV

35 mA at 500 mV

D

Qualified for Automotive Applications

D

Input Offset Voltage . . . 250 µV (typ)

Supply Voltage Range . . . 2.7 V to 6 V

D

Customer-Specific Configuration Control

Can Be Supported Along With

Major-Change Approval

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

TLV2471

D PACKAGE

(TOP VIEW)

D

CMOS Rail-To-Rail Input/Output

Input Bias Current . . . 2.5 pA

NC

IN−

NC

1

2

3

4

8

7

6

5

V

DD

Low Supply Current . . . 600 µA/Channel

Gain-Bandwidth Product . . . 2.8 MHz

IN+

OUT

NC

GND

†

Contact Texas Instruments for details. Q100 qualification data

available on request.

description

The TLV247x is a family of CMOS rail-to-rail input/output operational amplifiers that establishes a new

performance point for supply current versus ac performance. These devices consume just 600 µA/channel

while offering 2.8 MHz of gain-bandwidth product. Along with increased ac performance, the amplifier provides

high output drive capability, solving a major shortcoming of older micropower operational amplifiers. The

TLV247x can swing to within 180 mV of each supply rail while driving a 10-mA load. For non-RRO applications,

the TLV247x can supply 35 mA at 500 mV off the rail. Both the inputs and outputs swing rail-to-rail for increased

dynamic range in low-voltage applications. This performance makes the TLV247x family ideal for sensor

interface, portable medical equipment, and other data acquisition circuits.

The family is fully specified at 3 V and 5 V across the automotive temperature range (−40°C to 125°C).

FAMILY TABLE

NUMBER OF UNIVERSAL EVM

DEVICE

CHANNELS

BOARD

TLV2471

TLV2472

TLV2474

1

2

4

See the EVM

selection guide

(SLOU060)

‡

A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS

V

BW

SLEW RATE

I (per channel)

DD

OUTPUT

DD

IO

DEVICE

RAIL-TO-RAIL

(V)

(µV)

250

20

(MHz)

(V/µs)

(µA)

DRIVE

35 mA

10 mA

90 mA

10 mA

TLV247X

TLV245X

TLV246X

TLV277X

2.7 − 6

2.5 − 6

2.8

0.22

6.4

1.5

0.11

1.6

600

23

I/O

O

150

360

550

1000

5.1

10.5

‡

All specifications measured at 5 V.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2004 Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

†

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

T

A

PACKAGE

SOP − D

Tape and reel

TLV2471QDRQ1

TLV2471AQDRQ1

TLV2471QDBVRQ1

TLV2472QDRQ1

TLV2472AQDRQ1

TLV2472QDGNRQ1

TLV2474QDRQ1

TLV2474AQDRQ1

2471Q1

2471AQ

471Q

SOP − D

Tape and reel

−40°C to 125°C

SOT23 − DBV

SOP − D

2472Q1

2472AQ

SOP − D

‡

MSOP − DGN

SOP − D

2474Q1

2474AQ1

2474Q1

2474AQ1

SOP − D

−40°C to 125°C

TSSOP − PWP Tape and reel

TLV2474QPWPRQ1

TLV2474APWPRQ1

†

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Product Preview.

TLV247x PACKAGE PINOUTS

TLV2474

D OR PWP PACKAGE

TLV2471

DBV PACKAGE

TLV2472

D OR DGN PACKAGE

(TOP VIEW)

1

2

3

5

4

V

1OUT

1IN−

1IN+

GND

V

DD

OUT

GND

IN+

1

2

3

4

8

7

6

5

DD

1

2

3

4

5

6

7

14

13

12

11

10

9

1OUT

1IN−

1IN+

4OUT

4IN−

4IN+

GND

3IN+

3IN−

3OUT

2OUT

2IN−

2IN+

V

IN−

DD

2IN+

2IN−

8

2OUT

NC − No internal connection

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

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SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

Differential input voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

V

ID

DD

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltage values, except differential voltages, are with respect to GND.

DISSIPATION RATING TABLE

θ

T ≤ 25°C

A

JC

JA

PACKAGE

(°C/W)

38.3

26.9

55

(°C/W)

POWER RATING

D (8)

D (14)

176

710 mW

122.3

324.1

52.7

1022 mW

385 mW

DBV (3)

DGN (8)

PWP (14)

4.7

2370 mW

4070 mW

2.07

30.7

recommended operating conditions

MIN

2.7

1.35

0

MAX

UNIT

Single supply

Split supply

6

3

Supply voltage, V

DD

V

Common-mode input voltage range, V

ICR

V

DD

125

V

Operating free-air temperature, T

−40

°C

A

†

Relative to GND

3

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SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

electrical characteristics at specified free-air temperature, V

= 3 V (unless otherwise noted)

DD

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

2200

2400

1600

1800

T

A

UNIT

25°C

Full range

25°C

250

TLV247x

V

R

= V /2,

DD

= 50 Ω

IC

O

S

= V /2,

V

IO

Input offset voltage

µV

250

TLV247xA

Full range

V

R

= V /2,

DD

= 50 Ω

IC

O

S

Temperature coefficient of input

offset voltage

= V /2,

α

0.4

1.5

µV/°C

VIO

V

R

= V /2,

DD

25°C

Full range

25°C

50

300

50

IC

O

= V /2,

I

IO

Input offset current

Input bias current

DD

= 50 Ω

S

pA

V

R

= V /2,

DD

2

IC

O

= V /2,

I

IB

DD

Full range

300

= 50 Ω

S

25°C

Full range

25°C

2.85

2.8

2.6

2.5

2.94

2.74

0.07

0.2

I

= −2.5 mA

OH

OL

V

High-level output voltage

Low-level output voltage

V

= V /2

DD

V

OH

IC

= −10 mA

= 2.5 mA

= 10 mA

Full range

25°C

0.15

0.2

Full range

25°C

V

= V /2

DD

OL

IC

0.35

0.5

Full range

25°C

30

20

30

20

Sourcing

Sinking

Full range

25°C

I

Short-circuit output current

Output current

mA

OS

Full range

25°C

V

= 0.5 V from rail

= 1 V,

O(PP)

22

O

25°C

90

88

116

Large-signal differential voltage

amplification

A

VD

V

dB

Ω

R

= 10 kΩ

L

Full range

25°C

12

10

r

Differential input resistance

i(d)

Common-mode input

capacitance

C

f = 10 kHz

f = 10 kHz,

25°C

19.3

pF

Ω

IC

z

Closed-loop output impedance

A

= 10

25°C

2

o

V

58

56

68

60

70

60

78

V

R

= 0 to 3 V,

= 50 Ω

IC

S

CMRR

Common-mode rejection ratio

dB

µA

Full range

25°C

90

92

V

= 2.7 V to 6 V,

V

= V

/2,

DD

IC

DD

No load

Full range

25°C

Supply voltage rejection ratio

k

SVR

(∆V

DD

/∆V )

IO

V

= 3 V to 5 V,

V

IC

DD

No load

DD

Full range

25°C

550

750

800

I

Supply current (per channel)

V

O

= 1.5 V,

No load

DD

Full range

†

Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.

4

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SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

operating characteristics at specified free-air temperature, V

= 3 V (unless otherwise noted)

DD

†

PARAMETER

TEST CONDITIONS

MIN

1.1

TYP

MAX

UNIT

T

A

25°C

Full range

25°C

1.4

V

R

= 0.8 V,

O(PP)

= 10 kΩ

C

= 150 pF,

L

SR

Slew rate at unity gain

V/µs

0.6

L

f = 100 Hz

f = 1 kHz

28

15

nV/√Hz

pA/√Hz

V

I

Equivalent input noise voltage

Equivalent input noise current

n

25°C

0.405

0.02%

0.1%

0.5%

2.8

n

A

= 1

V

R

= 2 V,

O(PP)

= 10 kΩ,

A

V

= 10

THD + N Total harmonic distortion plus noise

Gain-bandwidth product

25°C

L

f = 1 kHz

A

= 100

R = 600 Ω

L

V

MHz

f = 10 kHz,

V

= 2 V,

(STEP)PP

0.1%

1.5

3.9

1.6

4

A

= −1,

V

C

R

= 10 pF,

= 10 kΩ

L

0.01%

0.1%

t

s

Settling time

25°C

µs

V

(STEP)PP

A

= −1,

V

C

R

= 56 pF,

= 10 kΩ

L

0.01%

φ

m

Phase margin

Gain margin

25°C

61°

R

= 10 kΩ,

C

= 1000 pF

L

15

dB

= 1000 pF

†

‡

Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.

Depending on package dissipation rating

5

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SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

electrical characteristics at specified free-air temperature, V

= 5 V (unless otherwise noted)

DD

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

2200

2400

1600

2000

T

A

UNIT

25°C

Full range

25°C

250

TLV247x

V

R

= V /2,

DD

= 50 Ω

IC

O

S

= V /2,

V

IO

Input offset voltage

µV

250

TLV247xA

Full range

V

R

= V /2,

DD

= 50 Ω

IC

O

S

Temperature coefficient of input

offset voltage

= V /2,

α

0.4

1.7

µV/°C

VIO

V

R

= V /2,

DD

25°C

Full range

25°C

50

300

50

IC

O

= V /2,

I

IO

Input offset current

Input bias current

DD

= 50 Ω

S

pA

V

R

= V /2,

DD

2.5

IC

O

= V /2,

I

IB

DD

Full range

300

= 50 Ω

S

25°C

Full range

25°C

4.85

4.8

4.96

4.82

I

= −2.5 mA

OH

OL

V

High-level output voltage

Low-level output voltage

V

= V /2

DD

V

OH

IC

4.72

4.65

= −10 mA

= 2.5 mA

= 10 mA

Full range

25°C

0.07

0.15

0.2

Full range

25°C

V

= V /2

DD

OL

IC

0.178

0.28

0.35

Full range

25°C

110

60

Sourcing

Sinking

Full range

25°C

I

Short-circuit output current

Output current

mA

OS

90

Full range

25°C

60

V

= 0.5 V from rail

= 3 V,

O(PP)

35

O

25°C

92

91

120

Large-signal differential voltage

amplification

A

VD

V

dB

Ω

R

= 10 kΩ

L

Full range

25°C

12

10

r

Differential input resistance

i(d)

Common-mode input

capacitance

C

f = 10 kHz

f = 10 kHz,

25°C

18.9

pF

Ω

IC

z

Closed-loop output impedance

A

= 10

25°C

1.8

84

o

V

62

58

68

60

70

60

V

R

= 0 to 5 V,

= 50 Ω

IC

S

CMRR

Common-mode rejection ratio

dB

µA

Full range

25°C

90

92

V

= 2.7 V to 6 V,

V

= V

/2,

DD

IC

DD

No load

Full range

25°C

Supply voltage rejection ratio

k

SVR

(∆V

DD

/∆V )

IO

V

= 3 V to 5 V,

V

IC

DD

No load

DD

Full range

25°C

600

900

I

Supply current (per channel)

V

O

= 2.5 V,

No load

DD

Full range

1000

†

Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

ꢌꢋ

ꢍ

ꢎ

ꢁꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇ

µ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

operating characteristics at specified free-air temperature, V

= 5 V (unless otherwise noted)

DD

†

PARAMETER

TEST CONDITIONS

MIN

1.1

TYP

MAX

UNIT

T

A

25°C

Full range

25°C

1.5

V

R

= 2 V,

O(PP)

= 10 kΩ

C

= 150 pF,

L

SR

Slew rate at unity gain

V/µs

0.7

L

f = 100 Hz

f = 1 kHz

28

15

nV/√Hz

pA/√Hz

V

I

Equivalent input noise voltage

Equivalent input noise current

n

25°C

0.39

n

A

= 1

0.01%

0.05%

0.3%

2.8

V

R

= 4 V,

O(PP)

= 10 kΩ,

A

V

= 10

THD + N Total harmonic distortion plus noise

Gain-bandwidth product

25°C

L

f = 1 kHz

A

= 100

R = 600 Ω

L

V

MHz

f = 10 kHz,

V

= 2 V,

(STEP)PP

0.1%

1.8

3.3

1.7

3

A

= −1,

V

C

R

= 10 pF,

= 10 kΩ

L

0.01%

0.1%

t

s

Settling time

25°C

µs

V

(STEP)PP

A

= −1,

V

C

R

= 56 pF,

= 10 kΩ

L

0.01%

φ

m

Phase margin

Gain margin

25°C

68°

R

= 10 kΩ,

C

= 1000 pF

L

23

dB

= 1000 pF

†

Full range is −40°C to 125°C for Q suffix. If not specified, full range is −40°C to 125°C.

7

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ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

ꢘ ꢎꢞ ꢘꢇꢟ ꢚ ꢎ ꢂꢠ ꢐꢜꢠ ꢚꢋꢀꢎ ꢐ ꢛꢋ ꢁ ꢋꢍ ꢜꢁ ꢎ ꢌꢎ ꢠ ꢚꢡ

ꢒ

ꢇ

µ

ꢋ

ꢓ

ꢔ

ꢕ

ꢃ

ꢖ

ꢗ

ꢇ

ꢍ

ꢘ

ꢙ

ꢚ

ꢋ

ꢎ

ꢁ

ꢇ

ꢀ

ꢐ

ꢇ

ꢚ

ꢋ

ꢎ

ꢁ

ꢎ

ꢛ

ꢜ

ꢝ

ꢀ

ꢓ

ꢐ

ꢝ

ꢀ

ꢜ

ꢝ

ꢀ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

V

Input offset voltage

vs Common-mode input voltage

vs Free-air temperature

1, 2

IO

I

Input bias current

IB

IO

3, 4

I

Input offset current

V

High-level output voltage

Low-level output voltage

Output impedance

vs High-level output current

vs Low-level output current

vs Frequency

5, 7

6, 8

OH

OL

o

Z

9

I

Supply current

vs Supply voltage

vs Frequency

10

DD

PSRR

CMRR

Power supply rejection ratio

Common-mode rejection ratio

Equivalent input noise voltage

Maximum peak-to-peak output voltage

Differential voltage gain and phase

Phase margin

11

vs Frequency

12

V

vs Frequency

13

n

vs Frequency

14, 15

16, 17

18, 19

20, 21

22

O(PP)

A

vs Frequency

VD

φ

vs Load capacitance

vs Supply voltage

vs Free-air temperature

vs Frequency

m

Gain margin

Gain-bandwidth product

23

SR

Slew rate

24, 25

26

Crosstalk

THD+N

Total harmonic distortion + noise

Large and small signal follower

vs Frequency

27, 28

29 − 32

V

O

vs Time

8

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ꢒ ꢋꢓ ꢔꢕ ꢃ ꢖꢗ ꢇꢍ ꢘꢙ ꢚꢋꢎ ꢁ ꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀꢓ ꢐ ꢝ ꢀꢜ ꢝꢀ

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ꢌꢋ

ꢍ

ꢎ

ꢁꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇ

µ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

INPUT BIAS AND INPUT OFFSET

INPUT OFFSET VOLTAGE

vs

CURRENTS

vs

COMMON-MODE INPUT VOLTAGE

FREE-AIR TEMPERATURE

600

50

40

30

20

10

0

V

=3 V

DD

V

=5 V

V

=3 V

DD

400

200

400

T

A

=25 °C

T

A

=25° C

200

0

I

IB

0

−200

−400

−600

−800

−200

−400

−600

−800

I

IO

−10

−0.5

0.5

1.5

2.5

3.5

4.5

5.5

−0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

−55 −35 −15

5

25 45 65 85 105 125

V

− Common-Mode Input Voltage − V

V

− Common-Mode Input Voltage − V

ICR

T

− Free-Air Temperature − °C

ICR

A

Figure 2

Figure 1

Figure 3

INPUT BIAS AND INPUT OFFSET

LOW-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT VOLTAGE

vs

CURRENTS

vs

LOW-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT CURRENT

FREE-AIR TEMPERATURE

3.0

2.5

2.0

1.5

1.0

0.5

0.0

50

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V

=5 V

V

=3 V

DD

V

=3 V

DD

40

30

20

10

0

T

=125°C

A

T

=85°C

=25°C

A

T

A

T

=−40°C

A

T

=125°C

=85°C

I

A

IB

T

A

T

=25°C

A

I

IO

T

=−40°C

A

−10

−55 −35 −15

0

10

20

30

40

50

5

25 45 65 85 105 125

0

10

20

30

40

50

60

I

− Low-Level Output Current − mA

T

− Free-Air Temperature − °C

OL

I

− High-Level Output Current − mA

A

OH

Figure 4

Figure 6

Figure 5

HIGH-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT VOLTAGE

vs

OUTPUT IMPEDANCE

vs

HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT CURRENT

FREQUENCY

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.0

1000

100

V

=3 & 5 V

T

=125°C

DD

=25°C

A

V

=5 V

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

DD

T

A

T

=85°C

A

AV=100

T

=25°C

A

10

1

T

=−40°C

AV=10

A

T

=125°C

A

T

=85°C

A

AV=1

0.1

T

=25°C

A

T

=−40°C

A

V

=5 V

DD

0.01

0

20 40 60 80 100 120 140 160

0

20

40

60

80 100 120 140

100

1k

10k

100k

1M

10M

I

− High-Level Output Current − mA

I

− Low-Level Output Current − mA

f − Frequency − Hz

OH

OL

Figure 8

Figure 9

Figure 7

9

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ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

ꢘ ꢎꢞ ꢘꢇꢟ ꢚ ꢎ ꢂꢠ ꢐꢜꢠ ꢚꢋꢀꢎ ꢐ ꢛꢋ ꢁ ꢋꢍ ꢜꢁ ꢎ ꢌꢎ ꢠ ꢚꢡ

ꢒ

ꢇ

µ

ꢋ

ꢓ

ꢔ

ꢕ

ꢃ

ꢖ

ꢗ

ꢇ

ꢍ

ꢘ

ꢙ

ꢚ

ꢋ

ꢎ

ꢁ

ꢇ

ꢀ

ꢐ

ꢇ

ꢚ

ꢋ

ꢎ

ꢁ

ꢎ

ꢛ

ꢜ

ꢝ

ꢀ

ꢓ

ꢐ

ꢝ

ꢀ

ꢜ

ꢝ

ꢀ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

POWER SUPPLY REJECTION RATIO

SUPPLY CURRENT

COMMON-MODE REJECTION RATIO

vs

FREQUENCY

100

vs

SUPPLY VOLTAGE

1.0

vs

FREQUENCY

130

V

R

=3 & 5 V

=5 kΩ

PSRR+

DD

F

I

T

=125°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

A

120

110

100

90

80

70

60

50

40

30

T

=85°C

A

R =50 Ω

T

=25°C

A

PSRR−

T

=25°C

A

V

=5 V

DD

=2.5 V

90

80

70

60

50

IC

T

=−40°C

A

V

=3 V

DD

=1.5 V

A

= 1

SHDN= V

IC

V

DD

Per Channel

10

100

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

10M

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

f − Frequency − Hz

V

− Supply Voltage − V

DD

Figure 11

Figure 12

Figure 10

MAXIMUM PEAK-TO-PEAK

OUTPUT VOLTAGE

vs

MAXIMUM PEAK-TO-PEAK

OUTPUT VOLTAGE

vs

EQUIVALENT NOISE VOLTAGE

vs

FREQUENCY

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

80

THD+N ≤ 2.0%

V

A

V

T

=3 & 5 V

= 10

DD

V

IN

A

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

R =600 Ω

R =10 kΩ

70

60

50

40

30

20

10

0

L

A

L

A

T

=25°C

T

=25°C

= V /2

V

=5 V

O(PP)

DD

=25°C

V

=5 V

O(PP)

V

=3 V

O(PP)

V

=3 V

O(PP)

10k

100k

1M

10k

100k

1M

10

100

1k

10k

100k

f − Frequency − Hz

Figure 14

Figure 15

Figure 13

DIFFERENTIAL VOLTAGE GAIN AND PHASE

vs

FREQUENCY

100

45

100

45

V

= 3

DD

L

V

= 5

DD

L

80

60

40

20

0

R =600 Ω

C =0

80

60

40

20

0

R =600 Ω

C =0

T

=25°C

A

T

=25°C

−45

−90

−135

−45

−90

−135

A

0

−180

−225

0

−180

−225

−20

−40

100

−270

100M

−40

100

−270

100M

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

Frequency − Hz

Figure 16

Figure 17

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇ

µ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

PHASE MARGIN

vs

PHASE MARGIN

vs

GAIN MARGIN

vs

LOAD CAPACITANCE

90

80

70

60

50

40

30

20

10

0

100

0

V =3V

DD

V

=3 V

Rnull=50

V

=5V

DD

R =10 kΩ

DD

R =10 kΩ

90

80

70

60

50

40

30

20

10

0

R =10 kΩ

L

Rnull=50

L

T

=25°C

5

T

=25°C

A

T

=25°C

A

Rnull=0

See Figure 42

Rnull=100

10

15

Rnull=100

Rnull=20

Rnull=100

Rnull=20

20

Rnull=20

10k

25

30

Rnull=50

1k

Rnull=0

1k

Rnull=0

1k

100

10k

100k

100

100k

100

10k

100k

C

− Load Capacitance − pF

C

− Load Capacitance − pF

C − Load Capacitance − pF

L

Figure 18

Figure 19

Figure 20

SLEW RATE

vs

GAIN MARGIN

vs

GAIN-BANDWIDTH PRODUCT

vs

SUPPLY VOLTAGE

LOAD CAPACITANCE

SUPPLY VOLTAGE

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0

5

SR−

SR+

R =10 kΩ

L

Rnull=0

10

15

R =600 Ω

L

Rnull=20

20

25

C =11 pF

L

Rnull=100

Rnull=50

f=10 kHz

V

A

=1.5 V

O(PP)

T

=25°C

A

=−1

V

=5V

DD

R =10 kΩ

C =150 pF

L

30

35

L

T

=25°C

A

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

100

1k

10k

100k

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

V

− Supply Voltage − V

DD

C

− Load Capacitance − pF

V

− Supply Voltage − V

DD

L

Figure 23

Figure 21

Figure 22

SLEW RATE

vs

FREE-AIR TEMPERATURE

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

SR−

SR+

SR−

V

=5 V

DD

L

V

=3 V

R =10 kΩ

C =150 pF

DD

L

V

R =10 kΩ

C =150 pF

A

=−1

A

=−1

−55 −35 −15

5

25 45 65 85 105 125

−55 −35 −15

5

25 45 65 85 105 125

T

− Free-Air Temperature − °C

T

− Free-Air Temperature − °C

A

Figure 24

Figure 25

11

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ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

ꢘ ꢎꢞ ꢘꢇꢟ ꢚ ꢎ ꢂꢠ ꢐꢜꢠ ꢚꢋꢀꢎ ꢐ ꢛꢋ ꢁ ꢋꢍ ꢜꢁ ꢎ ꢌꢎ ꢠ ꢚꢡ

ꢒ

ꢇµ

ꢋ

ꢓ

ꢔ

ꢕ

ꢃ

ꢖ

ꢗ

ꢇ

ꢍ

ꢘ

ꢙ

ꢚ

ꢋ

ꢎ

ꢁ

ꢇ

ꢀ

ꢐ

ꢇ

ꢚ

ꢋ

ꢎ

ꢁ

ꢎ

ꢛ

ꢜ

ꢝ

ꢀ

ꢓ

ꢐ

ꢝ

ꢀ

ꢜ

ꢝ

ꢀ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

TOTAL HARMONIC

DISTORTION PLUS NOISE

vs

TOTAL HARMONIC

DISTORTION PLUS NOISE

vs

CROSSTALK

vs

FREQUENCY

0

V

A

R

= 3V & 5V

= 1

1

0.1

DD

V

L

A

= 100

V

A

= 100

−20

V

= 600Ω

V

=2V

I(PP)

−40

−60

All Channels

A

= 10

= 1

V

A

= 10

= 1

V

0.1

0.01

−80

−100

−120

−140

0.01

0.001

V

R

V

= 3 V

V

R

V

= 5 V

= 10 kΩ

= 4 V

DD

= 10 kΩ

L

0

A

L

0

A

= 2 V

PP

T

= 25°C

T

= 25°C

0.001

−160

10

100

1k

10k

100k

10

100

1k

10k

100k

10

100

1 k

10 k

100 k

f − Frequency − Hz

Figure 26

Figure 27

Figure 28

LARGE SIGNAL FOLLOWER

SMALL SIGNAL FOLLOWER

PULSE RESPONSE

vs

TIME

V (2 V/DIV)

I

V (50 mV/DIV)

I

V (2 V/DIV)

I

V

R

C

= 3 V

= 10 kΩ

= 8 pF

DD

L

f = 1 MHz

= 25°C

V

(1 V/DIV)

T

O

A

V

(1 V/DIV)

O

V

= 5 V

DD

V

R

C

= 3 V

= 10 kΩ

= 8 pF

DD

L

R

C

= 10 kΩ

= 8 pF

L

V

(50 mV/DIV)

O

f = 85 kHz

= 25°C

f = 85 kHz

= 25°C

T

A

0

100

200

300

400

500

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

t − Time − µs

Figure 29

Figure 30

Figure 31

SMALL SIGNAL FOLLOWER

PULSE RESPONSE

vs

TIME

V (50 mV/DIV)

I

V

R

C

= 5 V

= 10 kΩ

= 8 pF

DD

L

f = 1 MHz

T

A

= 25°C

V

(50 mV/DIV)

O

0

100

200

300

400

500

t − Time − µs

Figure 32

12

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ꢒ ꢋꢓ ꢔꢕ ꢃ ꢖꢗ ꢇꢍ ꢘꢙ ꢚꢋꢎ ꢁ ꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀꢓ ꢐ ꢝ ꢀꢜ ꢝꢀ

ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇ

µ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

PARAMETER MEASUREMENT INFORMATION

R

_

+

null

R

L

C

L

Figure 33

APPLICATION INFORMATION

driving a capacitive load

When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s

phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than

10 pF, it is recommended that a resistor be placed in series (R

) with the output of the amplifier, as shown

NULL

in Figure 34. A minimum value of 20 Ω should work well for most applications.

R

F

R

G

R

_

+

NULL

Input

Output

LOAD

C

Figure 34. Driving a Capacitive Load

offset voltage

The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times

OO

IO

IB

the corresponding gains. The following schematic and formula can be used to calculate the output offset

voltage.

R

F

I

IB−

R

G

+

−

+

V

I

V

O

R

S

I

IB+

R

F

V

+ V

1 ) ǒ Ǔ " I

R

1 ) ǒ Ǔ " I

R

ǒ Ǔ ǒ Ǔ

OO

IO

IB)

S

IB–

F

R

G

Figure 35. Output Offset Voltage Model

13

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ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

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ꢒ

ꢒ ꢋꢓ ꢔ ꢕ ꢃ ꢖ ꢗ ꢇꢍꢘꢙ ꢚꢋ ꢎ ꢁꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀ ꢓꢐ ꢝꢀ ꢜꢝ ꢀ

ꢇµ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

general configurations

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often

required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier

(see Figure 36).

R

F

G

−

V

1

O

+

V

I

R1

V

C1

f

+

–3dB

2pR1C1

R

O

F

1

ǒ

Ǔ

+

ǒ

1 )

Ǔ

V

R

1 ) sR1C1

I

G

Figure 36. Single-Pole Low-Pass Filter

If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this

task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.

Failure to do this can result in phase shift of the amplifier.

C1

R1 = R2 = R

C1 = C2 = C

Q = Peaking Factor

(Butterworth Q = 0.707)

+

_

V

I

1

R1

R2

f

+

–3dB

2pRC

C2

R

F

1

R

=

G

R

F

2 −

)

R

(

Q

G

Figure 37. 2-Pole Low-Pass Sallen-Key Filter

14

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ꢒ ꢋꢓ ꢔꢕ ꢃ ꢖꢗ ꢇꢍ ꢘꢙ ꢚꢋꢎ ꢁ ꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀꢓ ꢐ ꢝ ꢀꢜ ꢝꢀ

ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

ꢌꢋ

ꢍ

ꢎ

ꢁꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇµ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

circuit layout considerations

To achieve the levels of high performance of the TLV247x, follow proper printed-circuit board design techniques.

A general set of guidelines is given in the following.

D

Ground planes − It is highly recommended that a ground plane be used on the board to provide all

components with a low inductive ground connection. However, in the areas of the amplifier inputs and

output, the ground plane can be removed to minimize the stray capacitance.

D

Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic

capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers

depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal

of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply

terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less

effective. The designer should strive for distances of less than 0.1 inches between the device power

terminals and the ceramic capacitors.

D

Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins

often leads to stability problems. Surface-mount packages soldered directly to the printed-circuit board is

the best implementation.

Short trace runs/compact part placements − Optimum high performance is achieved when stray series

inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,

thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of

the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the

input of the amplifier.

D

Surface-mount passive components − Using surface-mount passive components is recommended for high

performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of

surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small

size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray

inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be

kept as short as possible.

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ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

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ꢒ

ꢒ ꢋꢓ ꢔ ꢕ ꢃ ꢖ ꢗ ꢇꢍꢘꢙ ꢚꢋ ꢎ ꢁꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀ ꢓꢐ ꢝꢀ ꢜꢝ ꢀ

ꢇ

µ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

general PowerPAD design considerations

The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are

constructed using a downset leadframe upon which the die is mounted [see Figure 38(a) and Figure 38(b)]. This

arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see

Figure 38(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance

can be achieved by providing a good thermal path away from the thermal pad.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.

During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be

soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,

heat can be conducted away from the package into either a ground plane or other heat dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of

surface mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Side View (a)

Thermal

Pad

DIE

End View (b)

Bottom View (c)

NOTE A: The thermal pad is electrically isolated from all terminals in the package.

Figure 38. Views of Thermally Enhanced DGN Package

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the

recommended approach.

Thermal Pad Area

Quad

Single or Dual

68 mils x 70 mils) with 5 vias

78 mils x 94 mils) with 9 vias

(Via diameter = 13 mils

(Via diameter = 13 mils)

Figure 39. PowerPAD PCB Etch and Via Pattern

PowerPAD is a trademark of Texas Instruments Incorporated.

16

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ꢒ ꢋꢓ ꢔꢕ ꢃ ꢖꢗ ꢇꢍ ꢘꢙ ꢚꢋꢎ ꢁ ꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀꢓ ꢐ ꢝ ꢀꢜ ꢝꢀ

ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

ꢌ

ꢋ

ꢍ

ꢎ

ꢁꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇµ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

general PowerPAD design considerations (continued)

1. Prepare the PCB with a top side etch pattern as shown in Figure 39. There should be etch for the leads as

well as etch for the thermal pad.

2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils

in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.

3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps

dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13-mil

diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad

area to be soldered so that wicking is not a problem.

4. Connect all holes to the internal ground plane.

5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection

methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat

transfer during soldering operations. This makes the soldering of vias that have plane connections easier.

In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,

the holes under the TLV247x PowerPAD package should make their connection to the internal ground plane

with a complete connection around the entire circumference of the plated-through hole.

6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five

holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes

of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the

reflow process.

7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.

8. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder

reflow operation as any standard surface-mount component. This results in a part that is properly installed.

For a given θ , the maximum power dissipation is shown in Figure 40 and is calculated by the following formula:

JA

T

–T

MAX

A

P

+

ǒ Ǔ

D

q

JA

Where:

P

= Maximum power dissipation of TLV247x IC (watts)

= Absolute maximum junction temperature (150°C)

= Free-ambient air temperature (°C)

D

T

MAX

T

A

θ

= θ + θ

JA

JC CA

θ

= Thermal coefficient from junction to case

JC

= Thermal coefficient from case to ambient air (°C/W)

CA

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢋ

ꢇ

ꢈ

ꢉ

ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇµ

ꢋ

ꢓ

ꢔ

ꢕ

ꢃ

ꢖ

ꢗ

ꢇ

ꢍ

ꢘ

ꢙ

ꢚ

ꢋ

ꢎ

ꢁ

ꢇ

ꢀ

ꢐ

ꢇ

ꢘ ꢎꢞ ꢘꢇꢟ ꢚ ꢎ ꢂꢠ ꢐꢜꢠ ꢚꢋꢀꢎ ꢐ ꢛꢋ ꢁ ꢋꢍ ꢜꢁ ꢎ ꢌꢎ ꢠ ꢚꢡ

ꢚ

ꢋ

ꢎ

ꢁ

ꢎ

ꢛ

ꢜ

ꢝ

ꢀ

ꢓ

ꢐ

ꢝ

ꢀ

ꢜ

ꢝ

ꢀ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

general PowerPAD design considerations (continued)

MAXIMUM POWER DISSIPATION

vs

FREE-AIR TEMPERATURE

7

6

5

4

3

2

PWP Package

T

= 150°C

J

Low-K Test PCB

= 29.7°C/W

θ

JA

SOT-23 Package

Low-K Test PCB

= 324°C/W

θ

JA

DGN Package

Low-K Test PCB

θ

= 52.3°C/W

JA

SOIC Package

Low-K Test PCB

θ

= 176°C/W

JA

1

0

−55 −40 −25 −10

5

20 35 50 65 80 95 110 125

T

A

− Free-Air Temperature − °C

NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.

Figure 40.

The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent

power and output power. The designer should never forget about the quiescent heat generated within the

device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most

of the heat dissipation is at low output voltages with high output currents. Figure 41 to Figure 46 show this effect,

along with the quiescent heat, with an ambient air temperature of 70°C and 125°C. When using V

= 3 V, there

= 5 V, the

DD

is generally not a heat problem with an ambient air temperature of 70°C. But, when using V

DD

packages are severely limited in the amount of heat it can dissipate. The other key factor when looking at these

graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat

dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation

properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted

on the PCB. As more trace and copper area is placed around the device, θ decreases and the heat dissipation

JA

capability increases. The currents and voltages shown in these graphs are for the total package. For the dual

or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the

proper package.

18

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ꢒ ꢋꢓ ꢔꢕ ꢃ ꢖꢗ ꢇꢍ ꢘꢙ ꢚꢋꢎ ꢁ ꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀꢓ ꢐ ꢝ ꢀꢜ ꢝꢀ

ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

ꢌꢋ

ꢍ

ꢎ

ꢁꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇµ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

general PowerPAD design considerations (continued)

†

TLV2471

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

180

160

140

120

100

180

160

140

120

100

Maximum Output

Current Limit Line

Maximum Output

Current Limit Line

B

Packages With

B

θ

JA

≤ 110°C/W

at T = 125°C

A

or

A

θ

≤ 355°C/W

JA

at T = 70°C

A

80

60

40

80

60

40

A

Packages With

Safe Operating Area

θ

≤ 210°C/W

JA

at T = 70°C

A

V

T

A

=

3 V

DD

J

V

=

5 V

DD

= 150°C

= 125°C

20

0

20

0

T

= 150°C

= 125°C

J

Safe Operating Area

1.5 2.5

A

0

0.25

0.5

0.75

1

1.25

1.5

0

0.5

1

2

| V | − RMS Output Voltage − V

O

| V | − RMS Output Voltage − V

O

Figure 41

Figure 42

†

TLV2472

†

TLV2472

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

180

160

140

120

100

180

160

140

120

100

Maximum Output

Current Limit Line

Maximum Output

Current Limit Line

B

Packages With

C

θ

JA

≤ 55°C/W

at T = 125°C

A

or

C

80

60

40

80

60

40

θ

≤ 178°C/W

JA

at T = 70°C

B

A

Packages With

θ

≤ 105°C/W

JA

at T = 70°C

A

Safe Operating Area

V

T

A

=

3 V

DD

J

V

=

5 V

DD

= 150°C

= 125°C

20

0

20

0

T

= 150°C

= 125°C

J

Safe Operating Area

1.5 2.5

A

0

0.25

0.5

0.75

1

1.25

1.5

0

0.5

1

2

| V | − RMS Output Voltage − V

O

| V | − RMS Output Voltage − V

O

Figure 43

Figure 44

†

A − SOT23(5); B − SOIC (8); C − SOIC (14); D − TSSOP PP (14)

19

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ꢌ

ꢋ

ꢍ

ꢎ

ꢁ

ꢏ

ꢐ

ꢌ

ꢑ

ꢘ ꢎꢞ ꢘꢇꢟ ꢚ ꢎ ꢂꢠ ꢐꢜꢠ ꢚꢋꢀꢎ ꢐ ꢛꢋ ꢁ ꢋꢍ ꢜꢁ ꢎ ꢌꢎ ꢠ ꢚꢡ

ꢒ

ꢒ ꢋꢓ ꢔ ꢕ ꢃ ꢖ ꢗ ꢇꢍꢘꢙ ꢚꢋ ꢎ ꢁꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀ ꢓꢐ ꢝꢀ ꢜꢝ ꢀ

ꢇµ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

general PowerPAD design considerations (continued)

†

TLV2474

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

180

160

140

120

100

180

160

140

120

100

Maximum Output

Current Limit Line

Maximum Output

Current Limit Line

D

Packages With

80

60

40

80

60

40

θ

≤ 88°C/W

V

T

A

=

5 V

JA

at T = 70°C

C

DD

J

C

= 150°C

= 125°C

A

Packages With

V

= 3 V

= 150°C

= 125°C

DD

20

0

20

0

θ

JA

≤ 52°C/W

T

J

T

Safe Operating Area

0.75 1.25

at T = 70°C

Safe Operating Area

A

0

0.25

0.5

1

1.5

0

0.5

1

1.5

2

2.5

| V | − RMS Output Voltage − V

O

| V | − RMS Output Voltage − V

O

Figure 45

Figure 46

†

A − SOT23(5); B − SOIC (8); C − SOIC (14); D − TSSOP PP (14)

20

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ꢒ ꢋꢓ ꢔꢕ ꢃ ꢖꢗ ꢇꢍ ꢘꢙ ꢚꢋꢎ ꢁ ꢇꢀꢐ ꢇꢚꢋꢎ ꢁ ꢎꢛ ꢜꢝꢀꢓ ꢐ ꢝ ꢀꢜ ꢝꢀ

ꢘꢎ ꢞꢘ ꢇꢟꢚꢎꢂ ꢠ ꢐ ꢜꢠꢚ ꢋꢀ ꢎꢐ ꢛꢋꢁ ꢋꢍ ꢜ ꢁꢎ ꢌꢎ ꢠꢚ ꢡ

ꢌꢋ

ꢍ

ꢎ

ꢁꢏ

ꢐ

ꢌ

ꢑ

ꢒ

ꢇµ

SGLS180A − AUGUST 2003 − REVISED OCTOBER 2004

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim Parts, the model generation software used

with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 47 are generated using

the TLV247x typical electrical and operating characteristics at T = 25°C. Using this information, output

A

simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

D

Maximum positive output voltage swing

Maximum negative output voltage swing

Slew rate

D

Unity-gain frequency

Common-mode rejection ratio

Phase margin

Quiescent power dissipation

Input bias current

DC output resistance

AC output resistance

Short-circuit output current limit

Open-loop voltage amplification

NOTE 1: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

3

99

V

DD

+

−

egnd

rd1

11

rd2

12

rss

ro2

css

fb

rp

c1

7

+

c2

vlim

−

8

1

2

+

−

r2

9

6

IN+

IN−

vc

D

S

D

S

+

vb

ga

G

−

ro1

gcm

ioff

53

OUT

dp

5

dlp

dln

91

90

92

10

−

+

−

+

−

iss

dc

vlp

hlim

vln

−

+

GND

+ 54

4

de

ve

* TLV247x operational amplifier ”macromodel” subcircuit

* created using Parts release 8.0 on 4/27/99 at 14:31

* Parts is a MicroSim product.

iss

hlim

ioff

j1

10

90

0

4

dc

10.714E−6

75E−9

0

vlim 1K

dc

6

*

11

12

6

2

10 jx1

10 jx2

* connections: non−inverting input

j2

1

*

| inverting input

r2

9

100.00E3

12.527E3

10

| | positive power supply

| | | negative power supply

| | | | output

rd1

rd2

ro1

ro2

rp

3

11

12

5

3

8

| | | | |

7

99

4

10

.subckt TLV247x 1 2 3 4 5

*

3

3.8023E3

18.667E6

dc 0

rss

vb

vc

ve

vlim

vlp

vln

.model

.ends

*$

10

9

99

0

c1

11

6

12

7

99

53

5

91

90

3

0

99

1.1094E−12

c2

5.5000E−12

3

53

4

dc .842

dc 0

dc 110

css

dc

de

dlp

dln

dp

egnd

fb

10

5

556.53E−15

54

7

dy

dx

8

54

90

92

4

91

0

92

dx

dy

jx1

jx2

D(Is=800.00E−18)

D(Is=800.00E−18 Rs=1m Cjo=10p)

99

7

poly(2) (3,0) (4,0) 0 .5 .5

poly(5) vb vc ve vlp vln 0

NJF(Is=1.0825E−12 Beta=594.78E−06 + Vto=−1)

+ 39.614E6 −1E3 1E3 40E6 −40E6

ga

gcm

6

0

6

11

10

12 79.828E−6

99 32.483E−9

Figure 47. Boyle Macromodel and Subcircuit

PSpice and Parts are trademarks of MicroSim Corporation.

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

25-Feb-2005

PACKAGING INFORMATION

Orderable Device

TLV2471AQDRQ1

TLV2471QDBVRQ1

TLV2472AQDRQ1

TLV2472QDRQ1

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

5

8

2500

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SOT-23

SOIC

DBV

D

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SOIC

D

2500

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

TLV2474APWPRQ1

TLV2474AQDRQ1

ACTIVE

HTSSOP

SOIC

PWP

D

14

2000

2500

None

Call TI

Level-1-220C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

TLV2474QDRQ1

ACTIVE

SOIC

D

14

2500

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

TLV2474QPWPRQ1

HTSSOP

PWP

None

Call TI

Level-1-220C-UNLIM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

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Use of such information may require a license from a third party under the patents or other intellectual property

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TLV2474AQDRQ1
厂家：	TEXAS INSTRUMENTS
描述：	FAMILY OF 600-uA.CH 2.8-HHz RAIL-TO-RAIL INPUT-OUTPUT HIGH-DRIVE OPERATIONAL AMPLIFIERS 家庭的600-uA.CH 2.8 HHZ轨到轨输入 - 输出高驱动运算放大器运算放大器放大器电路光电二极管输出元件输入元件驱动
文件：	总27页 (文件大小：660K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV2474AQDRQ1 [TI]

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