TLV2548QDWRG4 [TI]
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN; 3 V至5.5 V ，12位， 200 KSPS ，4 / 8通道，低功耗串行模拟数字转换器具有自功率谱-DOWN
| 型号： | TLV2548QDWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN |
| 文件： | 总41页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
Maximum Throughput 200-KSPS
Hardware Controlled and Programmable
Sampling Period
Built-In Reference, Conversion Clock and
8× FIFO
Low Operating Current (1-mA at 3.3-V,
2-mA at 5.5-V With External Ref, 1.7-mA at
3.3-V, 2.4-mA at 5.5-V With Internal Ref)
Differential/Integral Nonlinearity Error:
±1.2 LSB at –55°C to 125°C
Power Down: Software/Hardware
Power-Down Mode (1 µA Typ, Ext Ref),
Autopower-Down Mode (1 µA Typ, Ext Ref)
Signal-to-Noise and Distortion Ratio:
65 dB, f = 12-kHz at –55°C to 125°C
i
Spurious Free Dynamic Range: 75 dB,
Programmable Auto-Channel Sweep
f = 12- kHz
i
Available in Q-Temp Automotive
SPI/DSP-Compatible Serial Interfaces With
SCLK up to 20-MHz
High Reliability Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
Single Wide Range Supply 3 Vdc to
5.5 Vdc
Analog Input Range 0-V to Supply Voltage
With 500 kHz BW
TLV2544Q . . . D PACKAGE
(TOP VIEW)
TLV2548M . . . FK PACKAGE
(TOP VIEW)
TLV2548Q . . . DW PACKAGE
(TOP VIEW)
SDO
SDI
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
16
15
14
13
12
SDO
SDI
CS
REFP
REFM
FS
REFP
REFM
FS
SCLK
SCLK
3
2
1
20 19
EOC/(INT)
EOC/(INT)
EOC/(INT)
REFM
FS
4
5
6
7
8
18
17
16
15
14
V
PWDN
V
PWDN
GND
CSTART
A7
CC
CC
V
CC
A0
A1
A2
11 GND
A0
A1
A2
A3
A4
A0
A1
A2
PWDN
GND
10 CSTART
9
A3
A6
CSTART
A5
9
10 11 12 13
description
The TLV2544Q, TLV2548Q, and TLV2548M are a family of high performance, 12-bit low power, 3.5 µs, CMOS
analog-to-digital converters (ADC) which operate from a single 3-V to 5.5-V power supply. These devices have
three digital inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input
(SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host
microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the
start of a serial data frame.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
description (continued)
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog
multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special
pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be
programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular
among high-performance signal processors. The TLV2548 and TLV2544 are designed to operate with very low
power consumption. The power-saving feature is further enhanced with software/hardware/autopower-down
modes and programmable conversion speeds. The conversion clock (OSC) and reference are built-in. The
converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 2.8 µs when
a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional
external reference can also be used to achieve maximum flexibility.
The TLV2544Q and the TLV2548Q are characterized for operation from –40°C to 125°C. The TLV2548M is
characterized for operation from –55°C to 125°C.
functional block diagram
V
CC
4/2 V
Reference
REFP
REFM
FIFO
12 Bit × 8
2548 2544
A0
A1
A2
A3
A4
A5
A6
A7
A0
Low Power
12-BIT
SAR ADC
X
A1
X
A2
X
S/H
OSC
Conversion
Clock
Command
Decode
A3
X
M
U
X
SDO
CFR
SDI
CMR (4 MSBs)
SCLK
CS
FS
Control Logic
EOC/(INT)
CSTART
PWDN
GND
AVAILABLE OPTIONS
20-SOIC
(DW)
16-SOIC
(D)
20-LCCC
(FK)
T
A
–40°C to 125°C TLV2548QDW
–55°C to 125°C
TLV2544QD
—
—
—
TLV2548MFK
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
Terminal Functions
TERMINAL
NO.
TLV2544 TLV2548
I/O
DESCRIPTION
NAME
A0
A0
A1
A2
A3
A4
A5
A6
A7
6
7
8
9
6
7
8
I
Analog signal inputs. The analog inputs are applied to these terminals and are internally
multiplexed. The driving source impedance should be less than or equal to 1 kΩ.
A1
A2
A3
For a source impedance greater than 1 kΩ, use the asynchronous conversion start signal CSTART
(CSTART low time controls the sampling period) or program long sampling period to increase the
sampling time.
9
10
11
12
13
CS
16
10
4
20
14
4
I
I
Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter, enables SDI,
and removes SDO from 3-state within a maximum setup time. SDI is disabled within a setup time
after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS whichever
happens first.
NOTE: CSfallingandrisingedgesneedtohappenwhenSCLKislowforamicroprocessorinterface
such as SPI.
CSTART
This terminal controls the start of sampling of the analog input from a selected multiplex channel.
Sampling time starts with the falling edge of CSTART and ends with the rising edge of CSTART as
long as CS is held high. In mode 01, select cycle, CSTART can be issued as soon as CHANNEL
is selected which means the fifth SCLK during the select cycle, but the effective sampling time is
not started until CS goes to high. The rising edge of CSTART (when CS = 1) also starts the
conversion. Tie this terminal to V
if not used.
CC
EOC/(INT)
O
End of conversion or interrupt to host processor.
[PROGRAMMED AS EOC]: This output goes from a high-to-low logic level at the end of the
sampling period and remains low until the conversion is complete and data are ready for transfer.
EOC is used in conversion mode 00 only.
[PROGRAMMEDAS INT]:Thispincanalsobeprogrammedasaninterruptoutputsignaltothehost
processor. The falling edge of INT indicates data are ready for output. The following CS↓ or FS
clears INT.
FS
13
17
I
DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If FS
remains low after the falling edge of CS, SDI is not enabled until an active FS is presented. A
high-to-low transition on the FS input resets the internal 4-bit counter and enables SDI within a
maximum setup time. SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock
edges) or a low-to-high transition of CS whichever happens first.
Tie this terminal to V
CC
the state of CS signal.
if not used. NOTE: The current silicon will react to FS input irrespective of
GND
11
12
3
15
16
3
I
I
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with
respect to GND.
PWDN
SCLK
Both analog and reference circuits are powered down when this pin is at logic zero. The device can
be restarted by active CS, FS or CSTART after this pin is pulled back to logic one.
Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is used to
clock the input SDI to the input register. When programmed, it may also be used as the source of
the conversion clock.
NOTE: This device supports CPOL (clock polarity) = 0, which is SCLK returns to zero when idling
for SPI compatible interface.
SDI
2
2
I
Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,
D(15–12) are decoded as one of the 16 commands (12 only for the TLV2544). The configure write
commands require an additional 12 bits of data.
When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS and is
latched in on the rising edges of SCLK (after CS↓).
When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected after the
falling edge of FS and is latched in on the falling edges of SCLK.
3
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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
Terminal Functions (Continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
SDO
TLV2544 TLV2548
1
1
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state
when CS is high and after the CS falling edge and until the MSB (D15) is presented. The output
format is MSB (D15) first.
When FS is not used (FS = 1 at the falling edge of CS), the MSB (D15) is presented to the SDO pin
after the CS falling edge, and successive data are available at the rising edge of SCLK.
When FS is used (FS = 0 at the falling edge of CS), the MSB (D15) is presented to SDO after the
fallingedge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK.
(This is typically used with an active FS from a DSP.)
For conversion and FIFO read cycles, the first 12 bits are result from previous conversion (data)
followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should be ignored.
The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit.
REFM
REFP
14
15
18
19
I
I
External reference input or internal reference decoupling.
External reference input or internal reference decoupling. (Shunt capacitors of 10 µF and 0.1 µF
between REFP and REFM.) The maximum input voltage range is determined by the difference
between the voltage applied to this terminal and the REFM terminal when an external reference is
used.
V
CC
5
5
I
Positive supply voltage
detailed description
analog inputs and internal test voltages
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection
resulting from channel switching.
converter
The TLV2544/48 uses a 12-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the ADC.
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, theSARcontrollogicandchargeredistributionDACareusedtoaddandsubtractfixedamountsofcharge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
Charge
Redistribution
DAC
_
Ain
Control
Logic
ADC Code
+
REFM
Figure 1. Simplified Model of the Successive-Approximation System
4
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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
detailed description (continued)
serial interface
INPUT DATA FORMAT
MSB
D15–D12
Command
LSB
D11–D0
Configuration data field
Input data is binary. All trailing blanks can be filled with zeros.
OUTPUT DATA FORMAT READ CFR
MSB
LSB
D15–D12
Don’t care
D11–D0
Register content
OUTPUT DATA FORMAT CONVERSION/READ FIFO
MSB LSB
D15–D4
D3–D0
Don’t care
Conversion result
The output data format is binary (unipolar straight binary).
binary
Zero scale code = 000h, Vcode = VREFM
Full scale code = FFFh, Vcode = VREFP – 1 LSB
control and timing
power up and initialization requirements
Determine processor type by writing A000h to the TLV2544/48 (CS must be toggled)
Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode; i.e.,
active FS.)
The first conversion after power up or resuming from power down is not valid.
start of the cycle:
When FS is not used (FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle.
When FS is used (FS is an active signal from a DSP), the falling edge of FS is the start of the cycle.
first 4-MSBs: the command register (CMR)
The TLV2544/TLV2548 have a 4-bit command set (see Table 1) plus a 12-bit configuration data field. Most of
the commands require only the first 4 MSBs, i.e., without the 12-bit data field.
NOTE:
The device requires a write CFR (configuration register) with 000h data (write A000h to the serial
input) at power up to initialize host select mode.
The valid commands are listed in Table 1.
5
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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
Table 1. TLV2544/TLV2548 Command Set
SDI D(15–12) BINARY
TLV2548 COMMAND
Select analog input channel 0
Select analog input channel 1
Select analog input channel 2
Select analog input channel 3
Select analog input channel 4
Select analog input channel 5
Select analog input channel 6
Select analog input channel 7
SW power down (analog + reference)
TLV2544 COMMAND
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Select analog input channel 0
N/A
Select analog input channel 1
N/A
Select analog input channel 2
N/A
Select analog input channel 3
N/A
Read CFR register data shown as SDO D(11–0)
Write CFR followed by 12-bit data, e.g., 0A100h means external reference,
short sampling, SCLK/4, single shot, INT
1010b
Ah plus data
1011b
1100b
1101b
1110b
1111b
Bh
Ch
Dh
Eh
Select test, voltage = (REFP+REFM)/2
Select test, voltage = REFM
Select test, voltage = REFP
FIFO read, FIFO contents shown as SDO D(15–4), D(3–0) = 0000
Fh plus data Reserved
configuration
Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once
configured after first power up, the information is retained in the H/W or S/W power down state. When the device
is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops
after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed. The status of
the CFR can be read with a read CFR command when the device is programmed for one-shot conversion mode
(CFR D[6,5] = 00).
6
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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
control and timing (continued)
Table 2. TLV2544/TLV2548 Configuration Register (CFR) Bit Definitions
BIT
D11
DEFINITION
Reference select
0: External
1: internal
D10
D9
Internal reference voltage select
0: Internal ref = 4 V 1: internal ref = 2 V
Sample period select
0: Short sampling 12 SCLKs (1x sampling time)
1: Long sampling 24 SCLKs (2x sampling time)
D(8–7)
Conversion clock source select
00: Conversion clock = internal OSC
01: Conversion clock = SCLK
10: Conversion clock = SCLK/4
11: Conversion clock = SCLK/2
D(6,5)
Conversion mode select
00: Single shot mode [FIFO not used, D(1,0) has no effect.]
01: Repeat mode
10: Sweep mode
11: Repeat sweep mode
†
D(4,3)
TLV2548
TLV2544
Sweep auto sequence select
00: 0–1–2–3–4–5–6–7
01: 0–2–4–6–0–2–4–6
10: 0–0–2–2–4–4–6–6
11: 0–2–0–2–0–2–0–2
Sweep auto sequence select
00: N/A
01: 0–1–2–3–0–1–2–3
10: 0–0–1–1–2–2–3–3
11: 0–1–0–1–0–1–0–1
D2
EOC/INT – pin function select
0: Pin used as INT
1: Pin used as EOC
D(1,0)
FIFO trigger level (sweep sequence length)
00: Full (INT generated after FIFO level 7 filled)
01: 3/4 (INT generated after FIFO level 5 filled)
10: 1/2 (INT generated after FIFO level 3 filled)
11: 1/4 (INT generated after FIFO level 1 filled)
†
These bits only take effect in conversion modes 10 and 11.
sampling
The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion
commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).
normal sampling
When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short
sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input
source resistance is high.
7
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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
extended sampling
CSTART – An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used in order
to have total control of the sampling period and the start of a conversion. This extended sampling is user-defined
and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling
period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal
totheminimumt
. Inaselectcycleusedinmode01(REPEATMODE), CSTARTcanbestartedassoon
(SAMPLE)
as the channel is selected (after the fifth SCLK). In this case the sampling period is not started until CS has
become inactive. Therefore the nonoverlapped CSTART low time must meet the minimum sampling time
requirement. The low-to-high transition of CSTART terminates the sampling period and starts the conversion
period. The conversion clock can also be configured to use either internal OSC or external SCLK. This function
is useful for an application that requires:
The use of an extended sampling period to accommodate different input source impedance
The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed
number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance
at lower supply voltage.
Oncetheconversioniscomplete, theprocessorcaninitiateareadcyclebyusingeitherthereadFIFOcommand
to read the conversion result or by simply selecting the next channel number for conversion. Since the device
has a valid conversion result in the output buffer, the conversion result is simply presented at the serial data
output. To completely get out of the extended sampling mode, CS must be toggled twice from a high-to-low
transition while CSTART is high. The read cycle mentioned above followed by another configuration cycle of
the ADC qualifies this condition and will successfully put the ADC back to its normal sampling mode. This can
be viewed in Figure 9.
Table 3. Sample and Convert Conditions
CONDITIONS SAMPLE
No sampling clock (SCLK) required. Sampling
CONVERT
period is totally controlled by the low time of CSTART.
The high-to-low transition of CSTART (when CS=1)
starts the sampling of the analog input signal. The low
time of CSTART dictates the sampling period. The
low-to-high transition of CSTART ends sampling
period and begins the conversion cycle. (Note: this
trigger only works when internal reference is selected
for conversion modes 01, 10, and 11.)
CS = 1
CSTART
1) If internal clock OSC is selected a minimum of 3 MHz
(equivalent to 4.6 µs conversion speed) can be
achieved.
SCLK is required. Sampling period is programmable
undernormalsampling. Whenprogrammedtosample
under short sampling, 12 SCLKs are generated to
complete sampling period. 24 SCLKs are generated
when programmed for long sampling. A command set
to configure the device requires 4 SCLKs thereby ex-
tendingto 16 or 28 SCLKs respectively before conver-
sion takes place. (Note: Because the ADC only
bypasses a valid channel select command, the user
can use select channel 0, 0000b, as the SDI input
wheneitherCS or FS is used as trigger for conversion.
The ADC responds to commands such as SW power-
down, 1000b.)
2) If external SCLK is selected, conversion time is
CSTART = 1
FS = 1
CS
FS
t
= 14 × DIV/f
, where DIV can be 1, 2,
(SCLK)
conv
or 4.
CSTART = 1
CS = 0
8
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TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
TLV2544/TLV2548 conversion modes
The TLV2544 and TLV2548 have four different conversion modes (mode 00, 01, 10, 11). The operation of each
mode is slightly different, depending on how the converter performs the sampling and which host interface is
used. The trigger for a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPI
interface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be held
active, i.e. CS does not need to be toggled through the trigger sequence. SDI can be one of the channel select
commands, suchasSELECTCHANNEL0. Differenttypesoftriggersshouldnotbemixedthroughouttherepeat
and sweep operations. When CSTART is used as the trigger, the conversion starts on the rising edge of
CSTART. The minimum low time for CSTART is equal to t
. If an active CS or FS is used as the trigger,
(SAMPLE)
the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) should be allowed
between consecutive triggers so that no conversion is terminated prematurely.
one shot mode (mode 00)
One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress
(or INT is generated after the conversion is done).
repeat mode (mode 01)
Repeat mode (mode 01) uses the FIFO. This mode setup requires configuration cycle and channel select cycle.
Once the programmed FIFO threshold is reached, the FIFO must be read, or the data is lost when the sequence
starts over again with the SELECT cycle and series of triggers. No configuration is required except for
reselecting the channel unless the operation mode is changed. This allows the host to set up the converter and
continue monitoring a fixed input and come back to get a set of samples when preferred.
Triggered by CSTART: The first conversion can be started with a select cycle or CSTART. To do so, the user
can issue CSTART during the select cycle, immediately after the four-bit channel select command. The first
sample started as soon as the select cycle is finished (i.e., CS returns to 1). If there is enough time (2 µs) left
between the SELECT cycle and the following CSTART, a conversion is carried out. In this case, you will need
one less trigger to fill the FIFO. Succeeding samples are triggered by CSTART.
sweep mode (mode 10)
Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in
the selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This
sweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows
the system designer to change the sweep sequence length. Once the FIFO has reached its programmed
threshold, aninterrupt(INT)isgenerated. ThehostmustissueareadFIFOcommandtoreadandcleartheFIFO
before the next sweep can start.
repeat sweep mode (mode 11)
Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continue
even if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT)
is generated. Then two things may happen:
1. The host may choose to act on it (read the FIFO) or ignore it. If the next cycle is a read FIFO cycle, all of
the data stored in the FIFO is retained until it has been read in order.
2. If the next cycle is not a read FIFO cycle, or another CSTART is generated, all of the content stored in the
FIFO is cleared before the next conversion result is stored in the FIFO, and the sweep is continued.
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3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
TLV2544/TLV2548 conversion modes (continued)
Table 4. TLV2544/TLV2548 Conversion Mode
CONVERSION
MODE
CFR
D(6,5)
SAMPLING
TYPE
OPERATION
Single conversion from a selected channel
CS or FS to start select/sampling/conversion/read
One INT or EOC generated after each conversion
One shot
00
Normal
•
•
•
•
Host must serve INT by selecting channel, and converting and reading the previous output.
Extended
•
•
•
•
•
Single conversion from a selected channel
CS to select/read
CSTART to start sampling and conversion
One INT or EOC generated after each conversion
Host must serve INT by selecting next channel and reading the previous output.
Repeat
01
Normal
•
•
•
•
Repeated conversions from a selected channel
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the
threshold, then repeat conversions from the same selected channel or 2) writing another
command(s) to change the conversion mode. If the FIFO is not read when INT is served, it is
cleared.
Extended
Normal
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
Sweep
10
11
•
•
•
•
One conversion per channel from a sequence of channels
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by (FIFO read) reading out all of the FIFO contents up to the threshold, then
write another command(s) to change the conversion mode.
Extended
Normal
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
Repeat sweep
•
•
•
•
Repeated conversions from a sequence of channels
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the
threshold, then repeat conversions from the same selected channel or 2) writing another
command(s) to change the conversion mode. If the FIFO is not read when INT is served it is
cleared.
Extended
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
NOTES: 1. Programming the EOC/INT pin as the EOC signal works for mode 00 only. The other three modes automatically generate an INT
signal irrespective of how EOC/INT is programmed.
2. When using CSTART to sample in extended mode, the falling edge of the next CSTART trigger should occur no more than 2.5 µs
after the falling CS edge (or falling FS edge if FS is active) of the channel select cycle. This is to prevent an ongoing conversion from
being canceled.
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
timing diagrams
The timing diagrams can be categorized into two major groups: nonconversion and conversion. The
nonconversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversion
cycles are those four modes of conversion.
read cycle (read FIFO or read CFR)
read CFR cycle:
The read command is decoded in the first 4 clocks. SDO outputs the contents of the CFR after the 4th SCLK.
16
7
12 13
14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID15 ID14 ID13 ID12
ID15
SDI
INT
EOC
SDO
OD11 OD10 OD9
OD4 OD3 OD2 OD1 OD0
Figure 2. TLV2544/TLV2548 Read CFR Cycle (FS active)
16
7
12 13 14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID15
ID14 ID13 ID12
ID15 ID14
SDI
INT
EOC
SDO
OD11 OD10 OD9
OD4 OD3 OD2 OD1 OD0
Figure 3. TLV2544/TLV2548 Read CFR Cycle (FS = 1)
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
read cycle (read FIFO or read CFR) (continued)
FIFO read cycle
The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read
command. The first FIFO content is output immediately before the command is decoded. If this command is
not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read
command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is
because the read cycle does not generate EOC or INT, nor does it carry out any conversion.
16
7
12 13 14 15
1
2
3
4
5
6
1
2
SCLK
CS
FS
ID15 ID14 ID13 ID12
ID15 ID14
SDI
INT
EOC
SDO
OD11 OD10 OD9 OD8 OD7 OD6 OD5
OD0
OD11 OD10
These Devices can Perform Continuous FIFO Read Cycle (FS = 1) Controlled by SCLK, SCLK can Stop Between Each 16 SCLKs.
Figure 4. TLV2544/TLV2548 FIFO Read Cycle (FS = 1)
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
write cycle (write CFR)
The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycle
does not generate an EOC or INT, nor does it carry out any conversion (see power up and initialization
requirements).
16
7
12 13 14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID11 ID10
ID9
ID4
ID3
ID2
ID1
ID0
ID15 ID14 ID13 ID12
ID15
SDI
INT
EOC
SDO
Figure 5. TLV2544/TLV2548 Write Cycle (FS Active)
16
7
12 13 14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID11 ID10
ID9
ID4
ID3
ID2
ID1
ID0
ID15 ID14 ID13 ID12
ID15 ID14
SDI
INT
EOC
SDO
Figure 6. TLV2544/TLV2548 Write Cycle (FS = 1)
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
conversion cycles
DSP/normal sampling
16 – Short Sampling
28 – Long Sampling
30 – Short Sampling
42 – Long Sampling
(If CONV
CLK = SCLK0
1
2
3
4
5
6
7
12
SCLK
CS
t
c
(30 or 42 SCLKs)
FS
ID15 ID14 ID13 ID12
ID15
SDI
INT
t
(12 or 24 SCLKs)
(sample)
EOC
SDO
(SDOZ on SCLK16L Regardless
of Sampling Time)
t
(conv)
MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 MSB-6
LSB
MSB
MSB
Figure 7. Mode 00 Single Shot/Normal Sampling (FS Signal Used)
16 – Short Sampling
28 – Long Sampling
30 – Short Sampling
42 – Long Sampling
(If CONV
CLK = SCLK0
1
1
2
3
4
5
6
7
12
13
SCLK
t
c
(30 or 42 SCLKs)
CS
FS
ID15 ID14 ID13 ID12
ID15
SDI
INT
t
(12 or 24 SCLKs)
(sample)
EOC
SDO
(SDOZ on SCLK16L Regardless
of Sampling Time)
t
(conv)
MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 MSB-6
LSB
MSB
MSB
Figure 8. Mode 00 Single Shot/Normal Sampling (FS = 1, FS Signal not Used)
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
conversion cycles (continued)
Device Get Out
Extended Sampling
Mode
Device Going Into
Extended Sampling Mode
Select/Read
Cycle
Select/Read
Cycle
Read
Cycle
CS
t
(sample )
Normal
Cycle
CSTART
FS
t
(conv)
†
†
SDI
INT
EOC
Previous Conversion
Result
Previous Conversion
Result
Hi-Z
Hi-Z
Hi-Z
SDO
†
This is one of the single shot commands. Conversion starts on next rising edge of CSTART.
Figure 9. Mode 00 Single Shot/Extended Sampling (FS Signal Used, FS Pin Connected to TMS320 DSP)
modes using the FIFO: modes 01, 10, 11 timing
Conversion #1
Configure Select From Channel 2
Conversion #4
From Channel 2
Select
CS
FS
CSTART
§
¶
¶
¶
¶
†
‡
‡
‡
‡
§
SDI
INT
Hi-Z
Hi-Z
SDO
Read FIFO
#1
#2
#3
#4
Next #1
Top of FIFO
†
Command = Configure write for mode 01, FIFO threshold = 1/2
Command = Read FIFO, 1st FIFO read
Command = Select ch2.
‡
§
¶
Use any channel select command to trigger SDI input.
Figure 10. TLV2544/TLV2548 Mode 01 DSP Serial Interface (Conversions Triggered by FS)
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
modes using the FIFO: modes 01, 10, 11 timing (continued)
Conversion #1 From Channel 2
Configure Select
Conversion #4 From Channel 2
Select
CS
¶
FS
(DSP)
t
t
(sample)
(sample)
t
(sample)
t
(sample)
CSTART
§
‡
‡
‡
‡
§
†
SDI
INT
Hi-Z
Hi-Z
SDO
Read FIFO
#1
#2
#3
#4
Sample Times ≥ MIN t
(sample)
(See Operating Characteristics)
First FIFO Read
†
Command = Configure write for mode 01, FIFO threshold = 1/2
Command = Read FIFO, 1st FIFO read
Command = Select ch2.
Minimum CS low time for select cycle is 6 SCLKs. The same amount of time is required between FS low to CSTART for proper channeldecoding.
The low time of CSTART, not overlapped with CS low time, is the valid sampling time for the select cycle (see Figure 18).
‡
§
¶
Figure 11. TLV2544/TLV2548 Mode 01 µp/DSP Serial Interface (Conversions Triggered by CSTART)
Conversion
Conversion
Conversion
Conversion
From Channel 3
From Channel 0
From Channel 3
Configure
From Channel 0
CS
FS
(DSP)
CSTART
SDI
‡
‡
‡
‡
†
§
§
§
§
§
§
§
§
‡
INT
SDO
Read FIFO #1
#2
#3
#4
Read FIFO #1
Repeat
Repeat
Top of FIFO
First FIFO Read
Second FIFO Read
†
‡
§
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.
Command = Read FIFO
Use any channel select command to trigger SDI input.
Figure 12. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by FS)
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
modes using the FIFO: modes 01, 10, 11 timing (continued)
Conversion
Conversion
Conversion
Conversion
From Channel 0
From Channel 3
From Channel 3
From Channel 0
Configure
CS
FS
(DSP)
CSTART
t
(sample)
t
(sample)
t
(sample)
t
(sample)
‡
‡
‡
‡
†
‡
SDI
INT
SDO
Read FIFO #1
#2
#3
#4
Read FIFO
#1
Repeat
Repeat
Top of FIFO
Second FIFO Read
First FIFO Read
†
‡
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.
Command = Read FIFO
Figure 13. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by CSTART)
Conversion
Conversion
Conversion
From Channel 0
Conversion
From Channel 0
From Channel 3
From Channel 3
Configure
CS
CSTART
SDI
‡
‡
‡
‡
†
‡
INT
SDO
Read FIFO #1
#2
#3
#4
Read FIFO
#1
Repeat
Repeat
Top of FIFO
First FIFO Read
Second FIFO Read
†
‡
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.
Command = Read FIFO
Figure 14. TLV2544/TLV2548 Mode 10/11 µp Serial Interface (Conversions Triggered by CS)
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
FIFO operation
Serial
OD
12-BIT×8
FIFO
ADC
7
6
5
4
3
2
1
0
FIFO Full
FIFO 1/2 Full
FIFO 3/4 Full
FIFO 1/4 Full
FIFO Threshold Pointer
Figure 15. TLV2544/TLV2548 FIFO
The device has an 8-layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host
after the preprogrammed threshold is reached. The FIFO can be used to store data from either a fixed channel
or a series of channels based on a preprogrammed sweep sequence. For example, an application may require
eight measurements from channel 3. In this case, the FIFO is filled with eight data sequentially taken from
channel 3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an
orderly manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0–2–4–6–0–2–4–6 is chosen.
An interrupt is sent to the host as soon as all four data are in the FIFO.
In single shot mode, the FIFO automatically uses a 1/8 FIFO depth. Therefore the CFR bits (D1,0) controlling
FIFO depth are don’t care.
SCLK and conversion speed
There are two ways to adjust the conversion speed.
The SCLK can be used as the source of the conversion clock.
The onboard OSC is approximately 4 MHz and 14 conversion clocks are required to complete a conversion.
(Corresponding 3.5 µs conversion time) The devices can operate with an SCLK up to 20 MHz for the supply
voltage range specified. When a more accurate conversion time is desired, the SCLK can be used as the
source of the conversion clock. The clock divider provides speed options appropriate for an application
whereahighspeedSCLKisusedforfasterI/O. Thetotalconversiontimeis14×(DIV/f
2, or 4. For example a 20 MHz SCLK with the divide by 4 option produces a {14 × (4/20 M)} = 2.8 µs
)whereDIVis1,
SCLK
conversion time. When an external serial clock (SCLK) is used as the source of the conversion clock, the
maximum equivalent conversion clock (f
/DIV) should not exceed 6 MHz.
SCLK
Autopower down can be used. This mode is always on. If the device is not accessed (by CS or CSTART),
the converter is powered down to save power. The built-in reference is left on in order to quickly resume
operation within one half SCLK period. This provides unlimited choices to trade speed with power savings.
reference voltage
The device has a built-in reference with a programmable level of 2 V or 4 V. If the internal reference is used,
REFP is set to 2 V or 4 V and REFM is set to 0 V. An external reference can also be used through two reference
input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to
these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale
reading respectively. The values of REFP, REFM, and the analog input should not exceed the positive supply
or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale
when the input signal is equal to or higher than REFP and at zero when the input signal is equal to or lower than
REFM.
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
reference block equivalent circuit
INT REF
Close = Int Ref Used
Open = Ext Ref Used
REFP
Sample
Convert
10 µF
0.1 µF
Decoupling
Cap
Internal
Reference
Compensation
Cap
~50 pF
CDAC
REFM
External to the Device
NOTES: A. If internal reference is used, tie REFM to AGND and install a 10 µF (or 4.7 µF) internal reference compensation capacitor between
REFP and REFM to store the charge as shown in the figure above.
B. If external reference is used, the 10 µF (internal reference compensation) capacitor is optional. REFM can be connected to external
REFM or AGND.
C. Internalreference voltage drift, due to temperature variations, is approximately ±10 mV about the nominal 2 V (typically) from –10°C
to 100°C . The nominal value also varies approximately ±50 mV across devices.
D. Internalreference leakage during low ON time: Leakage resistance is on the order of 100 MΩ or more. This means the time constant
is about 1000 s with 10 µF compensation capacitance. Since the REF voltage does not vary much, the reference will come up quickly
after resuming from auto power down. At power up and power down the internal reference sees a glitch of about 500 µV when 2
V internal reference is used (1 mV when 4 V internal reference is used). This glitch settles out after about 50 µs.
power down
Writing 8000h to the device puts the device into a software power down state. For a hardware power-down, the
dedicated PWDN pin provides another way to power down the device asynchronously. These two power-down
modes power down the entire device including the built-in reference to save power. It requires 20 ms to resume
from either a software or hardware power down.
Auto power-down mode is always enabled. This mode maintains the built-in reference if an internal reference
is used so resumption is fast enough to be used between cycles.
The configuration register is not affected by any of the power down modes but the sweep operation sequence
has to be started over again. All FIFO contents are cleared by the power-down modes.
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, GND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
CC
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
+ 0.3 V
CC
CC
CC
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
J
Operating free-air temperature range, T : TLV2544/48Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
A
TLV2548M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
‡
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
1110 mW
8.9 mW/°C
10.4 mW/°C
11.0 mW/°C
710 mW
577 mW
222 mW
DW
FK
1294 mW
828 mW
673 mW
259 mW
1375 mW
880 mW
715 mW
275 mW
‡
This is the inverse of the traditional junction-to-ambient thermal resistance (R
given are for informational purposes only.
). Thermal resistance is not production tested and the values
ΘJA
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SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, V
CC
3
3.3
5.5
V
V
V
V
Analog input voltage (see Note 3)
High level control input voltage, V
0
V
CC
2.1
IH
IL
Low-level control input voltage, V
0.6
Setup time, t
SCLK rising edge (FS=1) or before SCLK falling
edge (when FS is active)
CS falling edge before
V
CC
V
CC
V
CC
V
CC
= 4.5 V, SCLK = 20 MHz
= 3 V, SCLK = 20 MHz
= 4.5 V
20
30
10
su(CS-SCLK)
ns
ns
Hold time, CS rising edge after SCLK rising edge
(FS=1) or after SCLK falling edge (when FS is
= 3 V
15
active), t
h(SCLK-CS)
Delay time, delay from CS falling edge to FS rising edge, t
0.5
SCLKs
SCLKs
d(CSL-FSH)
Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active),
0.5
t
d(SCLK16L-CSH)
Setup time, FS rising edge before SCLK falling edge, t
20
30
ns
ns
su(FSH-SCLKL)
h(FSH-SCLKL)
Hold time, FS hold high after SCLK falling edge, t
Pulse width, CS high time, t
37
1
100
0.75
67
ns
wH(CS)
Pulse width, FS high time, t (FS)
SCLKs
ns
wH
= 3 V to 3.6V, t
SCLK cycle time, V
SCLK cycle time, V
10000
10000
CC
CC
c(SCLK)
= 4.5 V to 5.5V, t
50
ns
c(SCLK)
V
V
V
V
= 4.5 V
= 3 V
22
CC
CC
CC
CC
Pulse width, SCLK low time, t
ns
wL(SCLK)
Pulse width, SCLK high time, t
27
= 4.5 V
= 3 V
22
ns
ns
ns
wH(SCLK)
27
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of
SCLK (FS=1), t
25
5
su(DI-SCLK)
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge
of SCLK (FS=1), t
h(DI-SCLK)
Delay time, delay from CS falling edge to SDO valid, t
25
25
ns
ns
d(CSL-DOV)
d(FSL-DOV)
Delay time, delay from FS falling edge to SDO valid, t
0.5 SCLK
+ 5
SDO = 0 pF
SDO = 60 pF
SDO = 0 pF
SDO = 60 pF
V
= 5.5 V
CC
CC
0.5 SCLK
+ 24
Delay time, delay from SCLK falling edge (FS is
active) or SCLK rising edge (FS=1) to SDO valid,
ns
0.5 SCLK
+ 12
t
d(SCLK-DOV)
V
= 3.3 V
0.5 SCLK
+ 33
Delay time, delay from CS rising edge to SDO 3-state, t
80
45
ns
ns
d(CSH-DOZ)
Delay time, delay from 17th SCLK rising edge (FS is active) or the 16th falling edge
(FS=1) to EOC falling edge, t
d(SCLK-EOCL)
Delay time, delay from 16th SCLK falling edge to INT falling edge (FS =1) or from the
Min t
µs
(conv)
17th rising edge SCLK to INT falling edge (when FS active), t
d(SCLK-INT)
d(CSL-INTH)
Delay time, delay from CS falling edge to INT rising edge, t
50
50
ns
ns
ns
µs
Delay time, delay from CS rising edge to CSTART falling edge, t
d(CSH-CSTARTL)
Delay time, delay from CSTART rising edge to EOC falling edge, t
100
d(CSTARTH-EOCL)
Pulse width, CSTART low time, t (CSTART)
wL
Min t
(sample)
NOTE 3: When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while
input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to
1 V. (VREFP – VREFM – 1); however, the electrical specifications are no longer applicable.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
recommended operating conditions (continued)
MIN
Max t
NOM
MAX
UNIT
µs
Delay time, delay from CSTART rising edge to CSTART falling edge,
(conv)
t
d(CSTARTH-CSTARTL)
Delay time, delay from CSTART rising edge to INT falling edge, t
Max t
µs
d(CSTARTH-INTL)
TLV2544Q/TLV2548Q
TLV2548M
(conv)
–40
–55
125
125
Operating free-air temperature, T
°C
A
electrical characteristics over recommended operating free-air temperature range, V
= V
=
CC
REFP
3 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
= 5.5 V, I = –0.2 mA at 30 pF load
MIN
2.4
TYP
MAX
UNIT
V
V
V
V
CC
CC
CC
CC
OH
V
High-level output voltage
V
OH
OL
= 3 V, I = -20 µA at 30 pF load
V
–0.2
CC
OH
= 5.5 V, I = 0.8 mA at 30 pF load
0.4
0.1
OL
V
I
Low-level output voltage
V
= 3 V, I = 20 µA at 30 pF load
OL
Off-state output current
(high-impedance-state)
V
V
= V
CC
1
2.5
µA
µA
CS = V
CS = V
OZ
O
CC
CC
Off-state output current
(high-impedance-state)
I
= 0
O
–2.5
–1
OZ
I
I
High-level input current
Low-level input current
V = V
CC
0.005
2.5
2.5
2
µA
µA
IH
IL
I
V = 0 V
I
–0.005
V
V
V
V
V
V
V
V
= 4.5 V to 5.5 V
= 3 V to 3.3 V
= 4.5 V to 5.5 V
= 3 V to 3.3 V
= 4.5 V to 5.5 V
= 3 V to 3.3 V
= 4.5 V to 5.5 V
= 3 V to 3.3 V
CC
CC
CC
CC
CC
CC
CC
CC
mA
mA
mA
mA
mA
CS at 0 V, Ext ref
CS at 0 V, Int ref
CS at 0 V, Ext ref
CS at 0 V, Int ref
1
Operating supply current, normal
sampling (short)
2.4
1.7
I
CC
1.1
1
Operating supply current, extended
sampling
2.1
1.7
CS at 0 V,
V
= 4.5 V to 5.5 V
1
CC
Internal reference supply current
V
V
= 3 V to 3.3 V
0.7
CC
CC
Power down supply current
for all digital inputs,
= 4.5 V to 5.5 V, Ext clock
1
1
I
I
µA
CC(PD)
0 ≤ V ≤ 0.3 V or
I
V
= 3 V to 3.3 V, Ext clock
CC
V ≥ V – 0.3 V, SCLK = 0
I
CC
‡
Auto power-down current for all
V
V
= 4.5 V to 5.5 V, Ext clock, Ext ref
= 3 V to 3.3 V, Ext ref, Ext clock
1
CC
CC
digital inputs, 0 ≤ V ≤ 0.3 V or
µA
µA
µA
I
CC(AUTOPWDN)
§
1
V ≥ V – 0.3 V, SCLK = 0
I
CC
Selected channel at V
2.5
2.5
CC
Selected channel leakage current
Selected channel at 0 V
= V = 5.5 V, V = GND
REFM
Maximum EXT analog reference
current into REFP (use external
reference)
V
20
REFP
CC
Analog inputs
Control Inputs
45
5
50
25
C
i
Input capacitance
pF
V
V
= 4.5 V
= 3 V
500
600
CC
CC
Z
i
Input MUX ON resistance
Ω
†
‡
§
All typical values are at V
1.2 mA typical if internal reference is used, 165 µA typical if internal clock is used.
0.8 mA typical if internal reference is used, 116 µA typical if internal clock is used.
= 5 V, T = 25°C.
A
CC
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature range, V
= V
=
CC
REFP
3 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
f = 12 kHz at 200 KSPS
MIN
TYP
71
MAX
UNIT
SINAD
THD
Signal-to-noise ratio +distortion
65
dB
I
T
= –55°C
–82
–82
11.6
–84
–73
–75
A
Total harmonic distortion
f = 12 kHz at 200 KSPS
dB
I
All other temperatures
ENOB
SFDR
Effective number of bits
f = 12 kHz at 200 KSPS
I
Bits
dB
Spurious free dynamic range
f = 12 kHz at 200 KSPS
I
–75
Analog input
Full power-bandwidth, –3 dB
Full-power bandwidth, –1 dB
1
MHz
kHz
500
reference specifications (0.1 µF and 10 µF between REFP and REFM pins)
PARAMETER
TEST CONDITIONS
= 3 V to 5.5 V
MIN
2
TYP
MAX
UNIT
Positive reference input voltage, REFP
Negative reference input voltage, REFM
V
V
V
CC
2
V
V
CC
= 3 V to 5.5 V
0
CC
CS = 1, SCLK = 0, (off)
100
20
MΩ
kΩ
MΩ
kΩ
V
V
= 5.5 V
CC
CC
CS = 0, SCLK = 20 MHz (on)
CS = 1, SCLK = 0 (off)
25
25
Reference Input impedance
100
20
V
= 3 V
CS = 0, SCLK = 20 MHz (on)
Reference Input voltage difference, REFP – REFM
Internal reference voltage, REFP – REFM
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V to 5.5 V
= 5.5 V
2
V
CC
VREF SELECT = 4 V
VREF SELECT = 2 V
VREF SELECT = 2 V
3.85
1.925
1.925
4
2
4.15
2.075
2.075
V
= 5.5 V
V
= 3 V
2
V
Internal reference start-up time
= 5.5 V, 3 V with 10 µF compensation cap
20
16
ms
PPM/°C
†
40
Internal reference temperature coefficient
= 3 V to 5.5 V
†
Not assured
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
operating characteristics over recommended operating free-air temperature range, V
= 3 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)
= V
REFP
CC
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
±1.2
±1
UNIT
LSB
LSB
E
E
Integral linearity error (INL) (see Note 5)
Differential linearity error (DNL)
L
See Note 4
D
Q Suffix
±2
M Suffix, T = 25°C
A
–4
–4
+6
E
Offset error (see Note 6)
See Note 4
See Note 4
LSB
LSB
O
and 125°C
M Suffix, T = –55°C
+6.2
A
Q Suffix
±1.1
±1.1
±1.1
±4
M Suffix, T = 25°C
A
–4
–4
+6
E
FS
Full scale error (see Note 6)
and 125°C
M Suffix, T = –55°C
+7.6
A
800h
SDI = B000h
SDI = C000h
SDI = D000h
(2048D)
Self-test output code (see Table 1 and
Note 7)
000h (0D)
FFFh
(4095D)
Internal OSC
OSC = 3 MHz to 6 MHz
3.2
4.65
t
Conversion time
External SCLK
µs
(14
DIV)
(conv)
f
SCLK
With a maximum of 1-kΩ input source
impedance
t
Sampling time
600
ns
(sample)
†
All typical values are at T = 25°C.
A
NOTES: 4. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that
applied to REFM convert as all zeros (000000000000).
5. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage.
7. Both the input data and the output codes are expressed in positive logic.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
IH
CS
IL
t
wH(CS)
t
t
WH(FS)
d(CSL-FSH)
V
V
IH
FS
IL
t
h(FSH-SCLKL)
t
d(CSL-INTH)
t
t
wH(SCLK)
d(SCLK-CSH)
16
t
t
c(SCLK)
su(FSH-SCLKL)
t
d(FSH-INTH)
1
2
15
SCLK
t
wL(SCLK)
t
t
su(DI-SCLK)
d(CSL-DOV)
t
h(DI-SCLK)
V
V
IH
SDI
ID15
ID14
ID1
ID0
IL
t
t
d(FSL-DOV)
d(FSL-DOV)
V
OH
Hi-Z
Hi-Z
SDO
OD11
OD10
don’t care
don’t care
OD15
V
OL
t
t
d(SCLK-EOCL)
d(SCLK-DOV)
t
V
OH
(conv)
EOC
INT
V
OL
t
d(SCLK-INTL)
V
OH
V
OL
Figure 16. Critical Timing (Normal Sampling, FS is Active)
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
SELECT CYCLE
CS
V
V
IH
IL
t
d(CSH-CSTARTL)
t
wL(CSTART)
V
V
IH
CSTART
IL
†
t
d(CSTARTH-INTL)
t
c
V
OH
EOC
INT
V
OL
t
d(CSTARTH-EOCL)
t
d(CSL-INTH)
V
OH
V
OL
†
CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE.
Figure 17. Critical Timing (Extended Sampling, Single Shot)
SELECT CYCLE
V
IH
CS
t
V
wL(CSTART)
IL
t
t
d(CSTARTH–CSTARTL)
d(CSH-CSTARTL)
CSTART
V
V
IH
IL
†
V
OH
EOC
INT
t
V
d(CSL-INTH)
OL
t
d(CSTARTH-EOCL)
t
d(CSTARTH-INTL)
V
OH
V
OL
†
CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE.
Figure 18. Critical Timing (Extended Sampling, Repeat/Sweep/Repeat Sweep)
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
IH
CS
IL
t
wH(CS)
t
t
wH(SCLK)
d(SCLK16L-CSH)
t
c(SCLK)
1
t
su(CS-CLK)
2
15
16
V
V
IH
SCLK
IL
t
wL(SCLK)
t
su(DI-CLK)
V
V
IH
SDI
ID15
ID14
ID1
ID0
IL
t
d(CSL-DOV)
V
OH
Hi-Z
Hi-Z
SDO
OD15
OD14
OD1
OD0
V
OL
t
t
d(CLK-EOCL)
d(SCLK-DOV)
t
V
OH
(conv)
ECO
INT
V
OL
t
t
d(SCLK-INTL)
d(CSL-INTH)
V
OH
V
OL
Figure 19. Critical Timing (Normal Sampling, FS = 1)
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
INTEGRAL NONLINEARITY
vs
vs
TEMPERATURE
TEMPERATURE
0.53
0.52
0.51
0.6
0.595
0.59
0.585
0.5
0.58
0.575
0.49
V
= 2.7 V, Internal Reference = 2 V,
CC
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
0.57
0.565
0.56
V
= 5.5 V, Internal Reference = 2 V,
CC
0.48
0.47
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
–40
25
85
–40
25
85
T
A
– Temperature – °C
T
A
– Temperature – °C
Figure 20
Figure 21
DIFFERENTIAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
vs
vs
TEMPERATURE
TEMPERATURE
0.496
0.494
0.492
0.49
0.48
0.47
0.46
0.45
0.44
0.43
0.42
0.488
0.486
0.484
0.482
V
= 5.5 V, Internal Reference = 2 V,
CC
V
= 2.7 V, Internal Reference = 2 V,
CC
Internal Oscillator, Single Shot,
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
Short Sample, Mode 00 µP Mode
0.48
0.478
–40
25
85
–40
25
85
T
A
– Temperature – °C
T
A
– Temperature – °C
Figure 22
Figure 23
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
OFFSET ERROR
vs
GAIN ERROR
vs
TEMPERATURE
TEMPERATURE
1.2
1
0.5
0
0.8
–0.5
0.6
0.4
–1
–1.5
V
CC
= 5 V, Internal Reference = 4 V,
V
CC
= 5 V, Internal Reference = 4 V,
External Oscillator = SCLK/4,
Single Shot, Long Sample,
Mode 00 µP Mode
External Oscillator = SCLK/4,
Single Shot, Long Sample,
Mode 00 µP Mode
0.2
0
–2
–2.5
–40
25
85
–40
25
85
T
A
– Temperature – °C
T – Temperature – °C
A
Figure 24
Figure 25
SUPPLY CURRENT
vs
POWER DOWN CURRENT
vs
TEMPERATURE
TEMPERATURE
1.4
0.4
0.2
External Reference = 4 V, Internal Oscillator,
Single Shot, Short Sample, Mode 00 µP Mode
Long Sample
V
CC
= 5 V
1.2
1
0
–0.2
Short Sample
–0.4
–0.6
V
= 2.7 V
CC
0.8
0.6
V
CC
= 5.5 V
V
= 5 V, External Reference = 4 V,
CC
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
–0.8
–1
–40
25
85
–40
25
– Temperature – °C
85
T
A
– Temperature – °C
T
A
Figure 26
Figure 27
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
SAMPLES
1.0
V
= 2.7 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.5
0.0
–0.5
–1.0
0
4097.00
Samples
Figure 28
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
1.0
0.5
V
= 2.7 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.0
–0.5
–1.0
0
4097.00
Samples
Figure 29
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
SAMPLES
1.0
0.5
V
= 5 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.0
–0.5
–1.0
0
4097.00
Samples
Figure 30
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
1.0
0.5
V
= 5 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.0
–0.5
–1.0
0
4097.00
Samples
Figure 31
100%
160
150
140
130
120
110
100
90
V
= 5 V, External Reference = 4 V,
CC
Internal Oscillator , Single Shot, Long Sample, Mode 00 µP
Mode @ 200 KSPS
80
70
60
50
40
30
20
10
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
f – Frequency – kHz
Figure 32
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
SIGNAL-TO-NOISE + DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
12
11.7
11.4
11.1
10.8
80
75
70
65
10.5
10.2
9.9
60
55
50
9.6
9.3
9
V
= 5 V, External Reference = 4 V,
CC
8.7
8.4
8.1
7.8
7.5
Internal Oscillator, Single Shot,
Long Sample, Mode 00 µP Mode
V
= 5 V, External Reference = 4 V,
CC
Internal Oscillator, Single Shot,
Long Sample, Mode 00 µP Mode
45
40
1
250
500
1
250
500
f – Frequency – kHz
f – Frequency – kHz
Figure 33
Figure 34
TOTAL HARMONIC DISTORTION
SPURIOUS FREE DYNAMIC RANGE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
–60
0
–20
–40
–60
V
= 5 V, External Reference = 4 V,
CC
V
= 5 V, External Reference = 4 V,
CC
Internal Oscillator, Single Shot,
Long Sample, Mode 00 µP Mode
–65
–70
Internal Oscillator, Single Shot,
Long Sample, Mode 00 µP Mode
–75
–80
–80
–85
–90
–100
1
50
100
1
50
100
f – Frequency – kHz
f – Frequency – kHz
Figure 35
Figure 36
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
v
cc
10 kΩ
V
DD
XF
TXD
RXD
CS
SDI
SDO
A
IN
CLKR
CLKX
SCLK
TLV2544/
TLV2548
TMS320 DSP
BIO
INT
FSR
FSX
FS
GND
Figure 37. Typical Interface to a TMS320 DSP
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
28
0.710
DIM
0.410
0.462
0.510
0.610
A MAX
A MIN
(10,41) (11,73) (12,95) (15,49) (18,03)
0.400
0.453
0.500
0.600
0.700
(10,16) (11,51) (12,70) (15,24) (17,78)
4040000/E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED SEPTEMBER 2002
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
SOIC
SOIC
Drawing
5962-9957001Q2A
TLV2544QD
ACTIVE
ACTIVE
ACTIVE
FK
D
20
16
16
1
TBD
TBD
POST-PLATE N / A for Pkg Type
CU NIPDAU Level-1-220C-UNLIM
40
TLV2544QDG4
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2544QDR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2544QDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2548MFKB
TLV2548QDW
ACTIVE
ACTIVE
ACTIVE
LCCC
SOIC
SOIC
FK
DW
DW
20
20
20
1
TBD
TBD
POST-PLATE N / A for Pkg Type
CU NIPDAU Level-1-220C-UNLIM
25
TLV2548QDWG4
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2548QDWR
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
20
20
2000
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2548QDWRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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