TLV2762CDGKT [TI]

IC OP-AMP, Operational Amplifier;


型号：	TLV2762CDGKT
厂家：	TEXAS INSTRUMENTS
描述：	IC OP-AMP, Operational Amplifier 放大器
文件：	总43页 (文件大小：1760K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ

ꢌꢍꢎ ꢏ ꢁꢐ ꢑ ꢌ ꢈ ꢒꢓ ꢂ ꢎ ꢏꢔꢕꢑ ꢖ ꢑꢗ ꢘꢕ ꢕꢍꢏ ꢁ ꢙꢀꢑ ꢙꢕꢍꢏ ꢁ ꢏꢚ ꢖꢛꢀꢜ ꢑ ꢛ ꢀꢖ ꢛꢀ

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

Operational Amplifier

Low Supply Voltage . . . 1.8 V to 3.6 V

Very Low Supply Current . . . 20 µA (per

channel)

−

Ultralow Power Shut-Down Mode

− I

= 10 nA/Channel

DD(SHDN)

CMOS Rail-to-Rail Input/Output

Input Common-Mode Voltage

SUPPLY CURRENT

Range . . . −0.2 V to V

+ 0.2 V

SUPPLY VOLTAGE

Input Offset Voltage . . . 550 µV

Wide Bandwidth . . . 500 kHz

Slew Rate . . . 0.20 V/µs

Specified Temperature Range:

0°C to 70°C . . . Commercial Grade

−40°C to 85°C . . . Industrial Grade

Ultrasmall Packaging

5 or 6 Pin SOT-23 (TLV2760/1)

8 or 10 Pin MSOP (TLV2762/3)

= 1

= V

DD/2

= 25° C

Universal Op-Amp EVM

0.6

1.2

1.8

2.4

3.6

− Supply Voltage − V

description

The TLV276x single supply operational amplifiers provide 500 kHz bandwidth from only 20 µA while operating

down to 1.8 V over the industrial temperature range. The maximum recommended supply voltage is 3.6 V, which

allows the devices to be operated from ("1.8 V supplies down to "0.9 V) two AA or AAA cells. The devices

have been characterized at 1.8 V (end of life of 2 AA(A) cells) and at 2.4 V (nominal voltage of 2 NiCd/NiMH

cells). The TLV276x have rail-to-rail input and output capability which is a necessity at 1.8 V.

The low supply current is coupled with extremely low input bias currents enabling them to be used with

mega-ohm resistors. Low shutdown current of only 10 nA make these devices ideal for low frequency

measurement applications desiring long active battery life.

All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,

and quads in the TSSOP package.

SELECTION OF SINGLE SUPPLY AMPLIFIER PRODUCTS

(V)

/Ch

GBW

(MHz)

(V/µs)

Vn,1kHz

(nV/√Hz)

SHUT-

DOWN

RAIL-TO-

RAIL

(µA)

DEVICE

(µV)

600

450

550

(pA)

100

(mA)

0.2

0.4

TLV224x

TLV2211

2.5 − 12

2.7 − 10

1.8 − 3.6

2.7 − 6

0.0055

0.065

0.5

0.002

0.025

0.23

0.11

1.6

—

I/O

TLV276x

I/O

TLV245x(A)

TLV246x(A)

TLV278x(A)

500

1300

2.5

0.22

6.4

2.5

2.7 − 6

150

250

550

650

1.8 − 3.6

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢧ ꢫ ꢨ ꢧꢠ ꢡꢴ ꢣꢢ ꢦ ꢮꢮ ꢬꢦ ꢤ ꢦ ꢥ ꢫ ꢧ ꢫ ꢤ ꢨ ꢒ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

(1)

TLV2760 and TLV2761 AVAILABLE OPTIONS

PACKAGED DEVICES

max

SOT-23

‡

SMALL OUTLINE

PLASTIC DIP

(P)

AT 25°C

†

(D)

(DBV)

SYMBOL

TLV2760CD

TLV2761CD

—

0°C to 70°C

3500 µV

TLV2760ID

TLV2761ID

TLV2760IDBV

TLV2761IDBV

VANI

VAXI

TLV2760IP

TLV2761IP

−40°C to 85°C

†

‡

This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2760CDR).

This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (i.e., TLV2760CDBVR). For

smaller quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g. TLV2760CDBVT).

(1)

TLV2762 and TLV2763 AVAILABLE OPTIONS

PACKAGED DEVICES

max

SMALL

PLASTIC

DIP

PLASTIC

DIP

MSOP

SYMBOL

AT 25°C

OUTLINE

†

DGK

DGS

SYMBOL

(D)

(N)

(P)

TLV2762CD

TLV2763CD

—

0°C to 70°C

3500 µV

TLV2762ID

TLV2763ID

TLV2762IDGK

—

xxTIAJP

—

xxTIAJR

—

TLV2762IP

—

−40°C to 85°C

TLV2763IDGS

TLV2763IN

†

This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2762CDR).

(1)

TLV2764 and TLV2765 AVAILABLE OPTIONS

PACKAGED DEVICES

max

SMALL OUTLINE

PLASTIC DIP

(N)

TSSOP

(PW)

AT 25°C

3500 µV

†

(D)

TLV2764CD

TLV2765CD

—

0°C to 70°C

TLV2764ID

TLV2765ID

TLV2764IN

TLV2765IN

TLV2764IPW

TLV2765IPW

−40°C to 85°C

†

This package is available taped and reeled. To order this packaging option, add an R suffix to the part

number (e.g., TLV2764CDR).

1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website

at www.ti.com.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ

ꢌꢍꢎ ꢏ ꢁꢐ ꢑ ꢌ ꢈ ꢒꢓ ꢂ ꢎ ꢏꢔꢕꢑ ꢖ ꢑꢗ ꢘꢕ ꢕꢍꢏ ꢁ ꢙꢀꢑ ꢙꢕꢍꢏ ꢁ ꢏꢚ ꢖꢛꢀꢜ ꢑ ꢛ ꢀꢖ ꢛꢀ

ꢑ ꢖꢘꢕ ꢍꢀ ꢏꢑ ꢚꢍꢁ ꢍꢎ ꢖꢁ ꢏꢌ ꢏꢘ ꢕꢝ ꢗ ꢏꢀ ꢞ ꢝꢞꢛ ꢀꢟ ꢑ ꢗꢚ

SLOS326E − JUNE 2000 − REVISED JANUARY 2005

TLV276x PACKAGE PINOUTS

TLV2760

D OR P PACKAGE

(TOP VIEW)

TLV2761

DBV PACKAGE

(TOP VIEW)

TLV2760

DBV PACKAGE

(TOP VIEW)

OUT

GND

IN+

OUT

GND

IN+

IN−

SHDN

IN−

IN+

OUT

GND

IN−

TLV2761

D OR P PACKAGE

(TOP VIEW)

TLV2763

DGS PACKAGE

(TOP VIEW)

TLV2762

D, DGK, OR P PACKAGE

(TOP VIEW)

1OUT

1IN−

1IN+

GND

1SHDN

2OUT

2IN−

2IN+

IN−

1OUT

1IN−

1IN+

GND

2OUT

2IN−

2IN+

IN+

OUT

GND

2SHDN

TLV2764

TLV2763

TLV2765

D, N, OR PW PACKAGE

D OR N PACKAGE

D, N, OR PW PACKAGE

(TOP VIEW)

1OUT

1IN−

1IN+

4OUT

4IN−

1OUT

1IN−

1IN+

GND

1OUT

1IN−

1IN+

4OUT

4IN−

4IN+

GND

3IN+

3IN−

3OUT

2OUT

2IN−

2IN+

4IN+

GND

2IN+

2IN−

3IN+

2IN+

2IN−

3IN−

1SHDN

2SHDN

2OUT

3OUT

3/4SHDN

2OUT

1/2SHDN

NC − No internal connection

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

Differential input voltage range, V

Input current range, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Output current range, I

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential voltages, are with respect to GND

DISSIPATION RATING TABLE

≤ 25°C

T = 85°C

POWER RATING

PACKAGE

POWER RATING

(°C/W)

D (8)

38.3

176

710 mW

369 mW

D (14)

D (16)

26.9

25.7

122

114

324

294

260

1022 mW

1090 mW

385 mW

425 mW

481 mW

531 mW

567 mW

201 mW

221 mW

250 mW

DBV (5)

DBV (6)

DGK(8)

54.2

DGS(10)

N (14,16)

54.1

258

485 mW

1600 mW

1200 mW

720 mW

774 mW

252 mW

833 mW

625 mW

374 mW

403 mW

104

174

161

PW (14)

PW (16)

29.3

28.7

recommended operating conditions

MIN

1.8

0.8

−0.2

MAX

3.6

UNIT

Single supply

Supply voltage, V

Split supply

1.8

Common-mode input voltage range, V

ICR

+0.2

C-suffix

I-suffix

Operating free-air temperature, T

°C

−40

< 2.7 V

0.75 V

= 2.7 to 3.6 V

Shutdown on/off voltage level (see Note 2)

NOTE 2: Relative to GND

0.6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ

ꢌꢍꢎ ꢏ ꢁꢐ ꢑ ꢌ ꢈ ꢒꢓ ꢂ ꢎ ꢏꢔꢕꢑ ꢖ ꢑꢗ ꢘꢕ ꢕꢍꢏ ꢁ ꢙꢀꢑ ꢙꢕꢍꢏ ꢁ ꢏꢚ ꢖꢛꢀꢜ ꢑ ꢛ ꢀꢖ ꢛꢀ

ꢑ ꢖꢘꢕ ꢍꢀ ꢏꢑ ꢚꢍꢁ ꢍꢎ ꢖꢁ ꢏꢌ ꢏꢘ ꢕꢝ ꢗ ꢏꢀ ꢞ ꢝꢞꢛ ꢀꢟ ꢑ ꢗꢚ

SLOS326E − JUNE 2000 − REVISED JANUARY 2005

electrical characteristics at recommended operating conditions, V

otherwise noted)

= 1.8 V, 2.4 V (unless

dc performance

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

3500

6800

UNIT

= V /2,

25°C

550

Input offset voltage

Offset voltage drift

TLV276x

µV

µV/°C

Full range

= 300 kΩ,

= 50 Ω

VIO

25°C

Full range

25°C

= 1.8 V

= 0 V to V

ICR

= 2.4 V

= 50 Ω

Full range

CMRR Common-mode rejection ratio

25°C

Full range

25°C

= 3.6 V

= 1.2 V to V

ICR

= 2.4 V, 3.6 V

= 50 Ω

Full range

25°C

= 1.8 V

= 2.4 V

= 3.6 V

Full range

25°C

V/mV

Large-signal differential voltage

amplification

= 10 kΩ,

= V /2

Full range

25°C

O(PP)

120

Full range

†

Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.

input characteristics

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

25°C

Full range

25°C

TLV276xC

TLV276xI

100

200

Input offset current

= V /2,

= 300 kΩ,

= 50 Ω

TLV276xC

TLV276xI

Full range

25°C

100

200

Input bias current

Differential input resistance

1000

GΩ

i(d)

Common-mode input capacitance

f = 16 kHz

25°C

i(c)

†

Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

electrical characteristics at recommended operating conditions, V

otherwise noted) (continued)

= 1.8 V, 2.4 V (unless

output characteristics

†

PARAMETER

TEST CONDITIONS

MIN

1.77

1.76

2.38

2.37

3.58

3.57

1.725

1.7

TYP

MAX

UNIT

25°C

Full range

25°C

1.79

= 1.8V

= 2.4V

= 3.6V

= 1.8V

= 2.4V

= 3.6V

2.39

3.59

1.75

2.35

3.55

= V /2,

= −100 µA

Full range

25°C

Full range

25°C

High-level output voltage

Full range

25°C

2.325

2.3

= V /2,

= −500 µA

Full range

25°C

3.525

3.5

Full range

25°C

= V /2,

= 100 µA

= 500 µA

Full range

25°C

Low-level output voltage

Output current

= V /2,

Full range

100

Positive rail

Negative rail

Positive rail

Negative rail

Sourcing

4.8

7.2

7.3

10.2

= 1.8 V,

= 0.5 V from

25°C

= 2.4 V,

= 0.5 V from

= 1.8 V

= 2.4 V

Sinking

Short-circuit output current

Sourcing

Sinking

†

Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.

power supply, V

= 1.8 V, 2.4 V, 3.6 V (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

25°C

Full range

25°C

Supply current (per channel)

= V /2,

µA

SHDN = V

= 1.8 V to 2.4 V,

= V

Full range

25°C

Supply voltage rejection ratio

= 2.4 V to 3.6 V,

No load

SVR

(∆V

/∆V

)

= V

Full range

25°C

= 1.8 V to 3.6 V,

= V

Full range

†

Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ

ꢌꢍꢎ ꢏ ꢁꢐ ꢑ ꢌ ꢈ ꢒꢓ ꢂ ꢎ ꢏꢔꢕꢑ ꢖ ꢑꢗ ꢘꢕ ꢕꢍꢏ ꢁ ꢙꢀꢑ ꢙꢕꢍꢏ ꢁ ꢏꢚ ꢖꢛꢀꢜ ꢑ ꢛ ꢀꢖ ꢛꢀ

ꢑ ꢖꢘꢕ ꢍꢀ ꢏꢑ ꢚꢍꢁ ꢍꢎ ꢖꢁ ꢏꢌ ꢏꢘ ꢕꢝ ꢗ ꢏꢀ ꢞ ꢝꢞꢛ ꢀꢟ ꢑ ꢗꢚ

SLOS326E − JUNE 2000 − REVISED JANUARY 2005

electrical characteristics at recommended operating conditions, V

otherwise noted) (continued)

= 1.8 V, 2.4 V (unless

dynamic performance

†

PARAMETER

TEST CONDITIONS

MIN

TYP

500

MAX

UNIT

UGBW Unity gain bandwidth

25°C

kHz

= 300 kΩ,

= 10 pF

0.11

0.09

0.11

0.09

0.11

0.09

0.08

0.07

0.10

0.09

0.10

0.09

0.20

= 1.8 V

= 2.4 V

= 3.6 V

= 1.8 V

= 2.4 V

= 3.6 V

= 100 pF

Full range

25°C

V/µs

0.22

0.23

0.15

0.18

0.22

Positive slew rate at

unity gain

= 1 V, R = 300 kΩ,

O(PP) L

SR+

= 50 pF,

Full range

25°C

Full range

25°C

Full range

25°C

Negative slew rate at

unity gain

= 1 V, R = 300 kΩ,

O(PP) L

SR−

= 50 pF,

Full range

25°C

Full range

25°C

Phase margin

Gain margin

= 300 kΩ,

25°C

0.1%

6.4

13.7

= 1.8 V, V

= 1 V,

(STEP)PP

= 10 pF, R = 300 kΩ

= −1,

0.01%

0.1%

Settling time

25°C

µs

= 2.4 V,

= 1 V,

(STEP)PP

= 10 pF, R = 300 kΩ

= −1,

0.01%

13.9

†

Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.

noise/distortion

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

= 1

0.08%

0.10%

0.27%

0.06%

0.08%

0.24%

= 1.8 V,

O(PP)

= 300 kΩ,

= V /2 V,

= 10

= 100

= 1

25°C

f = 1 kHz

THD + N Total harmonic distortion plus noise

= 2.4 V,

O(PP)

= V /2 V,

= 10

= 100

= 300 kΩ,

f = 1 kHz

f = 10 kHz

25°C

nV/√Hz

fA/√Hz

Equivalent input noise voltage

Equivalent input noise current

f = 1 kHz

0.8

shutdown characteristics

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

25°C

Full range

25°C

Supply current, all channels in shutdown mode

(TLV2760, TLV2763, TLV2765) (per channel)

SHDN = 0 V

DD(SHDN)

400

Amplifier turnon time (see Note 3)

Amplifier turnoff time (see Note 3)

= 300 kΩ

µs

(on)

25°C

0.8

(off)

†

Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.

NOTE 3: Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply

current has reached half its final value.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

1, 2

Input offset voltage

vs Common-mode input voltage

vs Frequency

CMRR

Common-mode rejection ratio

High-level output voltage

Low-level output voltage

Maximum peak-to-peak output voltage

Supply current

vs High-level output current

vs Low-level output current

vs Frequency

4, 6

5, 7

O(PP)

vs Supply voltage

vs Free-air temperature

vs Frequency

Supply current

PSRR

Power supply rejection ratio

Differential voltage amplification & phase

vs Frequency

vs Temperature

vs Supply voltage

vs Free-air temperature

vs Load capacitance

vs Frequency

Gain-bandwidth product

Slew rate

16, 17

Phase margin

Equivalent input noise voltage

Supply current and output voltage

Voltage-follower large-signal pulse response

Voltage-follower small-signal pulse response

Inverting large-signal response

Inverting small-signal response

Crosstalk

vs Time

vs Frequency

Shutdown forward & reverse isolation

Shutdown supply current

vs Frequency

vs Supply voltage

vs Free-air temperature

vs Shutdown pin voltage

vs Time

DD(SHDN)

Shutdown supply current

Shutdown pin leakage current

Shutdown supply current/output voltage

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ

ꢌꢍꢎ ꢏ ꢁꢐ ꢑ ꢌ ꢈ ꢒꢓ ꢂ ꢎ ꢏꢔꢕꢑ ꢖ ꢑꢗ ꢘꢕ ꢕꢍꢏ ꢁ ꢙꢀꢑ ꢙꢕꢍꢏ ꢁ ꢏꢚ ꢖꢛꢀꢜ ꢑ ꢛ ꢀꢖ ꢛꢀ

ꢑ ꢖꢘꢕ ꢍꢀ ꢏꢑ ꢚꢍꢁ ꢍꢎ ꢖꢁ ꢏꢌ ꢏꢘ ꢕꢝ ꢗ ꢏꢀ ꢞ ꢝꢞꢛ ꢀꢟ ꢑ ꢗꢚ

SLOS326E − JUNE 2000 − REVISED JANUARY 2005

TYPICAL CHARACTERISTICS

INPUT OFFSET VOLTAGE

COMMON-MODE REJECTION RATIO

COMMON-MODE INPUT VOLTAGE

FREQUENCY

300

350

140

=1.8 V

=2.4 V

=25° C

130

120

110

100

300

250

200

=25 °C

250

200

150

100

= 2.4 V

150

100

= 1.8 V

−50

−100

−50

−0.2

0.2 0.4 0.6 0.8

1 1.2 1.4 1.6 1.8 2

0.2

0.6

1.4 1.8

2.2 2.6

100

10k

100k 1M

− Common-Mode Input Voltage − V

f − Frequency − Hz

ICR

Figure 2

Figure 1

Figure 3

HIGH-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT CURRENT

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.4

1.8

= 2.4 V

=1.8 V

2.1

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.8

1.5

1.2

0.9

=85°C

=70°C

=85°C

=70°C

=85°C

=70°C

=25°C

=0°C

=25°C

=−40°C

=0°C

=−40°C

=25°C

0.6

0.3

=0°C

=−40°C

10 12 14 16 18 20

9 10 11 12

− Low-Level Output Current − mA

− High-Level Output Current − mA

Figure 5

Figure 4

Figure 6

MAXIMUM PEAK-TO-PEAK

OUTPUT VOLTAGE

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

FREQUENCY

2.4

2.1

1.8

2.8

2.6

= 2.4 V

2.4

2.2

= 2.4 V

O(PP)

=85°C

2.0

= 70°C

1.5

1.2

1.8

1.6

1.4

1.2

=25°C

=0°C

= 1.8 V

O(PP)

=−40°C

0.9

0.6

1.0

0.8

0.6

0.4

0.2

= −10

R =300 kΩ

= 10 pF

0.3

0.0

= 25° C

2.5

7.5 10 12.5 15 17.5 20 22.5 25

100

10k

100k

− Low-Level Output Current − mA

f − Frequency − Hz

Figure 8

Figure 7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

POWER SUPPLY REJECTION RATIO

SUPPLY CURRENT

FREE-AIR TEMPERATURE

FREQUENCY

SUPPLY VOLTAGE

100

=2.4 V

= 1

=25°C

= V

DD/2

= 85°C

= 3.6 V

= 25°C

= 2.4 V

= 0°C

= 1.8 V

= −40°C

= 70°C

−20

−40

0.6

1.2

1.8

2.4

3.6

100

10k

100k

−15

− Free-Air Temperature − °C

− Supply Voltage − V

f − Frequency − Hz

Figure 9

Figure 10

Figure 11

DIFFERENTIAL VOLTAGE GAIN AND PHASE

GAIN BANDWIDTH PRODUCT

FREQUENCY

TEMPERATURE

180

150

120

100

700

= 300 kΩ

= 10 pF

= 2.4 V

600

500

400

300

200

f = 10 kHz

Phase

= 1.8 V

−30

−60

Gain

= 1.8 V & 2.4 V

R = 300 kΩ

−90

−120

= 10 pF

= 25° C

100

−20

−150

−180

−40

−40 −25 −10

20 35 50 65 80 85

100

10k

100k

f − Frequency − Hz

− Temperature − °C

Figure 13

Figure 12

GAIN-BANDWIDTH PRODUCT

SLEW RATE

SUPPLY VOLTAGE

560

540

0.36

0.32

= 300 kΩ

= 10 pF

f = 10 kHz

Ta = 25°C

0.28

0.24

520

500

480

460

SR+

SR−

0.20

0.16

= 1

= 300 kΩ

=50 pF

= 25° C

0.12

0.08

440

420

400

0.04

0.00

1 1.2 1.4 1.61.8 2 2.2 2.42.62.8 3 3.2 3.4 3.6

− Supply Voltage − V

1.8

2.2 2.4 2.6 2.8

3.2 3.4 3.6

− Supply Voltage − V

Figure 14

Figure 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ

ꢌꢍꢎ ꢏ ꢁꢐ ꢑ ꢌ ꢈ ꢒꢓ ꢂ ꢎ ꢏꢔꢕꢑ ꢖ ꢑꢗ ꢘꢕ ꢕꢍꢏ ꢁ ꢙꢀꢑ ꢙꢕꢍꢏ ꢁ ꢏꢚ ꢖꢛꢀꢜ ꢑ ꢛ ꢀꢖ ꢛꢀ

ꢑ ꢖꢘꢕ ꢍꢀ ꢏꢑ ꢚꢍꢁ ꢍꢎ ꢖꢁ ꢏꢌ ꢏꢘ ꢕꢝ ꢗ ꢏꢀ ꢞ ꢝꢞꢛ ꢀꢟ ꢑ ꢗꢚ

SLOS326E − JUNE 2000 − REVISED JANUARY 2005

TYPICAL CHARACTERISTICS

SLEW RATE

PHASE MARGIN

FREE-AIR TEMPERATURE

LOAD CAPACITANCE

0.32

0.28

0.32

Rnull=0 Ω

0.28

0.24

0.20

0.16

SR+

SR−

SR+

SR−

0.24

0.20

Rnull=100 Ω

0.16

0.12

0.08

0.04

0.00

= 1.8 V

= 1

= 2.4 V

= 1

0.08

= 2.4 V

= 300 kΩ

= Open Loop

= 25°C

R = 300 kΩ

R =300 kΩ

= 50 pF

= V /2

C =50 pF

0.04

0.00

= V /2

−40 −25 −10

20 35 50 65 8085

−40

−15

100

− Free-Air Temperature − °C

− Load Capacitance − pF

Figure 16

Figure 17

Figure 18

SUPPLY CURRENT AND OUTPUT VOLTAGE

EQUIVALENT INPUT NOISE VOLTAGE

TIME

FREQUENCY

500

= 25°C

450

400

350

300

250

200

150

100

= 2.4 V

1.5

= 3.6 V

= 1

= V /2

0.5

= 300 kΩ

= 10 pF

= 25°C

= 1.8 V

100

−0.5

10k

100k

t − Time − µs

f − Frequency − Hz

Figure 19

Figure 20

VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE

VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE

TIME

1.26

2.5

1.24

1.22

1.20

1.18

1.16

1.14

1.5

= 2.4 V

= 300 kΩ

= 10 pF

= 25°C

0.5

1.26

1.24

1.22

1.20

1.18

1.16

1.14

2.5

= 2.4 V

= 1

1.5

= 300 kΩ

= 10 pF

= 25°C

0.5

0.2 0.4 0.6 0.8

1 1.2 1.4 1.6 1.8

t − Time − µs

Figure 21

Figure 22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

TYPICAL CHARACTERISTICS

INVERTING SMALL-SIGNAL PULSE RESPONSE

INVERTING LARGE-SIGNAL RESPONSE

TIME

1.28

2.5

1.24

1.20

1.5

1.16

1.12

0.5

= 2.4 V

= 300 kΩ

= 10 pF

= 1

1.28

1.24

1.20

2.5

= 2.4 V

= 1

= 300 kΩ

= 10 pF

= 25°C

1.5

1.16

1.12

0.5

10 15 20 25 30 35 40 45

10 20 30 40 50 60 70 80 90

t − Time − µs

Figure 23

Figure 24

SHUTDOWN FORWARD AND

REVERSE ISOLATION

CROSSTALK

FREQUENCY

100

= 1.8 V & 2.4 V

V = V /2

−20

Forward and Reverse Isolation

= 1

R = 300 kΩ

= 25°C

−40

−60

All Channels

Crosstalk in Shutdown

−80

= 1.8 & 2.4 V

V = V

= 300 kΩ

−100

−120

−140

C = 10 pF

= +1

= 25°C

Crosstalk/No Shutdown

1k 10k

100

10k

100k

100

100k

f − Frequency − Hz

Figure 25

Figure 26

SHUTDOWN PIN LEAKAGE CURRENT

SHUTDOWN SUPPLY CURRENT

SHUTDOWN PIN VOLTAGE

SUPPLY VOLTAGE

FREE-AIR TEMPERATURE

.12

.10

.08

.06

.04

.02

.014

.012

= 3.6 V

SHDN = 0 V

= V /2

IN DD

= 1

= 1.8, 2.4, 3.6 V

= 85°C

SHDN = 0V

= V /2

= 1

.010

.008

.006

.004

= 25°C

= 0°C

−5

= −40°C

−10

−15

.002

0.4 0.8 1.2 1.6

2.4 2.8 3.2 3.6

−40 −25 −10

20 35 50 65 80 85

0.4 0.8 1.2 1.6

2.4 2.8 3.2 3.6

− Supply Voltage − V

− Free-Air Temperature − °C

Shutdown Pin Voltage − V

Figure 27

Figure 28

Figure 29

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

TYPICAL CHARACTERISTICS

SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE

TIME

3.0

2.5

2.0

1.5

SHDN

1.0

0.5

0.0

−0.5

1.5

1.3

1.0

0.8

0.5

0.3

0.0

= 2.4 V

−0.3

= 1

= 300 kΩ

= 10 pF

= V /2

= 25° C

DD(SHDN = 0)

−2

100

120

140

160

t − Time − µs

Figure 30

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

APPLICATION INFORMATION

driving a capacitive load

When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the

device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater

than 10 pF, it is recommended that a resistor be placed in series (R

) with the output of the amplifier, as

NULL

shown in Figure 31. A minimum value of 20 Ω should work well for most applications.

NULL

−

Input

Output

LOAD

Figure 31. Driving a Capacitive Load

offset voltage

The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times

the corresponding gains. The following schematic and formula can be used to calculate the output offset

voltage:

IB−

−

IB+

+ V

1 ) ǒ^RFǓ " I

_IOǒ Ǔ ǒ Ǔ

1 ) ǒ^RFǓ " I

IB)

IB–

Figure 32. Output Offset Voltage Model

general configurations

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often

required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier

(see Figure 33).

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

APPLICATION INFORMATION

general configurations (continued)

−

–3dB

2pR1C1

ǒ_{1 ) 2pfR1C1}Ǔ

1 )

Figure 33. Single-Pole Low-Pass Filter

If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this

task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.

Failure to do this can result in phase shift of the amplifier.

R1 = R2 = R

C1 = C2 = C

Q = Peaking Factor

(Butterworth Q = 0.707)

–3dB

2pRC

2 −

)

(

Figure 34. 2-Pole Low-Pass Sallen-Key Filter

circuit layout considerations

To achieve the levels of high performance of the TLV276x, follow proper printed-circuit board design techniques.

A general set of guidelines is given in the following.

Ground planes—It is highly recommended that a ground plane be used on the board to provide all

components with a low inductive ground connection. However, in the areas of the amplifier inputs and

output, the ground plane can be removed to minimize the stray capacitance.

Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic

capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers

depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal

of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply

terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less

effective. The designer should strive for distances of less than 0.1 inches between the device power

terminals and the ceramic capacitors.

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ꢁ

ꢚ

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ꢀ

ꢁ

ꢛ

ꢂ

ꢃ

ꢀ

ꢄ

ꢅ

ꢋ

ꢛ

ꢌ

ꢍ

ꢁ

ꢐ

ꢒ

ꢓ

ꢏ

ꢔ

ꢏ

ꢁ

ꢀꢑ

ꢚ

ꢖ

ꢜ

ꢑ

ꢀ

ꢖ

ꢛ

ꢀ

ꢑ

ꢖ

ꢍ

ꢀ

ꢏ

ꢑ

ꢚ

ꢍ

ꢁ

ꢖ

ꢁ

ꢏ

ꢀ

ꢞ

ꢀ

SLOS326E − JUNE 2000 − REVISED JANUARY 2005

APPLICATION INFORMATION

circuit layout considerations (continued)

Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins

will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board

is the best implementation.

Short trace runs/compact part placements—Optimum high performance is achieved when stray series

inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,

thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of

the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at

the input of the amplifier.

Surface-mount passive components—Using surface-mount passive components is recommended for high

performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of

surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small

size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray

inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be

kept as short as possible.

shutdown function

Three members of the TLV276x family (TLV2760/3/5) have a shutdown terminal for conserving battery life in

portable applications. When the shutdown terminal is pulled low, the supply current is reduced to 10 nA/channel,

the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the

shutdown terminal must be pulled high. The shutdown terminal should never be left floating. If the shutdown

feature is not desired, directly tie the shutdown terminal to the positive rail. The shutdown terminal threshold

is always referenced to the GND terminal of the device. Therefore, when operating the device with split supply

voltages (e.g. 1.8 V), the shutdown terminal needs to be pulled to the negative rail, not the system ground,

to disable the operational amplifier.

The amplifier is powered with a single 2.4-V supply and configured as a noninverting configuration with a unity

gain. Turnon and turnoff times are defined as the interval between application of the logic signal to the shutdown

pin and the point at which the supply current has reached half its final value. The times for the single, dual, and

quad are listed in the data tables.

general power dissipation considerations

For a given θ , the maximum power dissipation is shown in Figure 35 and is calculated by the following formula:

* T

ǒ ^MAXǓ

Where:

= Maximum power dissipation of TLV276x IC (watts)

= Absolute maximum junction temperature (150°C)

= Free-ambient air temperature (°C)

MAX

= θ + θ

JC CA

= Thermal coefficient from junction to case

= Thermal coefficient from case to ambient air (°C/W)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢌꢍꢎ ꢏ ꢁꢐ ꢑ ꢌ ꢈ ꢒꢓ ꢂ ꢎ ꢏꢔꢕꢑ ꢖ ꢑꢗ ꢘꢕ ꢕꢍꢏ ꢁ ꢙꢀꢑ ꢙꢕꢍꢏ ꢁ ꢏꢚ ꢖꢛꢀꢜ ꢑ ꢛ ꢀꢖ ꢛꢀ

ꢑ ꢖꢘꢕ ꢍꢀ ꢏꢑ ꢚꢍꢁ ꢍꢎ ꢖꢁ ꢏꢌ ꢏꢘ ꢕꢝ ꢗ ꢏꢀ ꢞ ꢝꢞꢛ ꢀꢟ ꢑ ꢗꢚ

SLOS326E − JUNE 2000 − REVISED JANUARY 2005

APPLICATION INFORMATION

general power dissipation considerations (continued)

MAXIMUM POWER DISSIPATION

FREE-AIR TEMPERATURE

1.75

1.5

= 150°C

PDIP Package

Low-K Test PCB

= 104°C/W

MSOP Package

Low-K Test PCB

SOIC Package

Low-K Test PCB

= 260°C/W

1.25

= 176°C/W

0.75

0.5

SOT-23 Package

Low-K Test PCB

0.25

= 324°C/W

−55−40 −25 −10

20 35 50 65 80 95 110 125

− Free-Air Temperature − °C

NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.

Figure 35. Maximum Power Dissipation vs Free-Air Temperature

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS326E − JUNE 2000 − REVISED JANUARY 2005

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim Parts Release 9.1, the model generation

software used with Microsim PSpice. The Boyle macromodel (see Note 4) and subcircuit in Figure 36 are

generated using TLV276x typical electrical and operating characteristics at T = 25°C. Using this information,

output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

Maximum positive output voltage swing

Maximum negative output voltage swing

Slew rate

Unity-gain frequency

Common-mode rejection ratio

Phase margin

Quiescent power dissipation

Input bias current

DC output resistance

AC output resistance

Short-circuit output current limit

Open-loop voltage amplification

NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

−

egnd

rd1

rd2

rss

ro2

css

vlim

−

IN+

IN−

−

ro1

gcm

ioff

OUT

dlp

dln

−

iss

vlp

hlim

vln

−

GND

+ 54

*DEVICE=amp_tlv276x_highVdd,OPAMP,NJF,INT

11 12 16.272E−6

10 99 6.8698E−9

dc 1.3371E−6

vlim 1K

* amp_tlv_276x_highVdd operational amplifier ”macromodel”

gcm

iss

* subcircuit updated using Model Editor release 9.1 on 05/15/00

* at 14:40 Model Editor is an OrCAD product.

hlim

rd1

rd2

ro1

ro2

rss

vlim

vlp

vln

.model

.model dy

.model jx1

.model jx2

.ends

10 jx1

* connections:

non-inverting input

| inverting input

10 jx2

100.00E3

61.456E3

| | positive power supply

| | | negative power supply

| | | | output

| | | | |

.subckt amp_tlv276x_highVdd 1 2 3 4 5

150.51E3

149.58E6

dc 0

12 457.48E−15

5.0000E−12

dc .78905

dc 0

dc 14.200

css

99 1.1431E−12

53 dy

dlp

dln

egnd

91 dx

90 dx

D(Is=800.00E−18)

D(Is=800.00E−18 Rs=1m Cjo=10p)

poly(2) (3,0) (4,0) 0 .5 .5

NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)

99 poly(5) vb vc ve vlp vln 0

176.02E6 −1E3 1E3 180E6

−180E6

Figure 36. Boyle Macromodel and Subcircuit

PSpice and Parts are trademarks of MicroSim Corporation.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jul-2013

PACKAGING INFORMATION

Orderable Device

TLV2760ID

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

ACTIVE

SOIC

SOT-23

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

T2760I

TLV2760IDBVR

TLV2760IDBVRG4

TLV2760IDBVT

TLV2760IDBVTG4

TLV2760IDG4

TLV2760IP

ACTIVE

DBV

3000

250

Green (RoHS

& no Sb/Br)

VANI

Green (RoHS

& no Sb/Br)

VANI

Green (RoHS

& no Sb/Br)

VANI

Green (RoHS

& no Sb/Br)

VANI

Green (RoHS

& no Sb/Br)

T2760I

T2761C

T2761I

VAXI

PDIP

Pb-Free

(RoHS)

TLV2760IPE4

TLV2761CD

PDIP

Pb-Free

(RoHS)

N / A for Pkg Type

SOIC

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

TLV2761CDG4

TLV2761ID

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

SOIC

Green (RoHS

& no Sb/Br)

-40 to 85

TLV2761IDBVR

TLV2761IDBVRG4

TLV2761IDBVT

TLV2761IDBVTG4

TLV2761IDG4

TLV2761IP

SOT-23

SOIC

DBV

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

VAXI

Green (RoHS

& no Sb/Br)

VAXI

Green (RoHS

& no Sb/Br)

VAXI

Green (RoHS

& no Sb/Br)

T2761I

PDIP

Pb-Free

(RoHS)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jul-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

TLV2761IPE4

TLV2762CD

ACTIVE

PDIP

SOIC

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

Level-1-260C-UNLIM

T2761I

ACTIVE

Green (RoHS

& no Sb/Br)

2762C

TLV2762CDG4

Green (RoHS

& no Sb/Br)

0 to 70

TLV2762CDGKT

TLV2762CDR

PREVIEW

ACTIVE

VSSOP

SOIC

DGK

250

TBD

Call TI

0 to 70

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

2762C

2762I

AJP

TLV2762CDRG4

TLV2762ID

ACTIVE

SOIC

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

-40 to 85

0 to 70

Green (RoHS

& no Sb/Br)

TLV2762IDG4

TLV2762IDGK

TLV2762IDGKG4

TLV2762IDGKR

TLV2762IDGKRG4

TLV2762IDR

SOIC

Green (RoHS

& no Sb/Br)

VSSOP

SOIC

DGK

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

AJP

2500

Green (RoHS

& no Sb/Br)

AJP

Green (RoHS

& no Sb/Br)

AJP

Green (RoHS

& no Sb/Br)

2762I

TLV2763C

AJR

TLV2762IDRG4

TLV2763CDR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

TLV2763CDRG4

TLV2763IDGS

TLV2763IDGSG4

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

VSSOP

DGS

Green (RoHS

& no Sb/Br)

-40 to 85

Green (RoHS

& no Sb/Br)

AJR

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jul-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

TLV2763IDGSR

TLV2763IDGSRG4

TLV2763IDR

ACTIVE

VSSOP

SOIC

DGS

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

AJR

ACTIVE

DGS

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLV2763I

TLV2764C

TLV2764I

2764I

TLV2763IDRG4

TLV2764CD

SOIC

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

TLV2764CDG4

TLV2764CDR

TLV2764CDRG4

TLV2764ID

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

SOIC

2500

Green (RoHS

& no Sb/Br)

0 to 70

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

SOIC

Green (RoHS

& no Sb/Br)

-40 to 85

TLV2764IDG4

TLV2764IDR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

TLV2764IDRG4

TLV2764IN

SOIC

Green (RoHS

& no Sb/Br)

PDIP

Pb-Free

(RoHS)

TLV2764INE4

TLV2764IPW

PDIP

Pb-Free

(RoHS)

N / A for Pkg Type

TSSOP

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

TLV2764IPWG4

TLV2764IPWR

TLV2764IPWRG4

Green (RoHS

& no Sb/Br)

2764I

2000

Green (RoHS

& no Sb/Br)

2764I

Green (RoHS

& no Sb/Br)

2764I

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jul-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

TLV2765CD

TLV2765CDG4

TLV2765CDR

TLV2765CDRG4

TLV2765ID

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLV2765C

ACTIVE

2500

Green (RoHS

& no Sb/Br)

0 to 70

TLV2765C

TLV2765I

2765I

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

SOIC

Green (RoHS

& no Sb/Br)

-40 to 85

TLV2765IDG4

TLV2765IDR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

TLV2765IDRG4

TLV2765IPW

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

TLV2765IPWG4

TLV2765IPWR

TLV2765IPWRG4

Green (RoHS

& no Sb/Br)

2765I

2000

Green (RoHS

& no Sb/Br)

2765I

Green (RoHS

& no Sb/Br)

2765I

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jul-2013

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 5

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Nov-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV2760IDBVR

TLV2760IDBVT

TLV2761IDBVR

TLV2761IDBVT

TLV2762CDR

TLV2762IDGKR

TLV2762IDR

SOT-23

SOIC

DBV

3000

250

180.0

330.0

9.0

3.15

6.4

5.3

6.4

6.5

5.3

6.5

6.9

6.5

6.9

3.2

5.2

3.4

5.2

9.0

3.4

9.0

5.6

10.3

5.6

1.4

2.1

1.4

2.1

1.4

2.1

1.6

2.1

1.6

4.0

8.0

9.0

8.0

3000

250

9.0

8.0

9.0

8.0

2500

2000

2500

2000

12.4

16.4

12.4

16.4

12.4

16.4

12.4

12.0

16.0

12.0

16.0

12.0

16.0

12.0

VSSOP

SOIC

DGK

TLV2763CDR

TLV2763IDGSR

TLV2763IDR

SOIC

VSSOP

SOIC

DGS

TLV2764CDR

TLV2764IDR

SOIC

TLV2764IPWR

TLV2765CDR

TLV2765IDR

TSSOP

SOIC

TLV2765IPWR

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Nov-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV2760IDBVR

TLV2760IDBVT

TLV2761IDBVR

TLV2761IDBVT

TLV2762CDR

TLV2762IDGKR

TLV2762IDR

SOT-23

SOIC

DBV

3000

250

182.0

340.5

364.0

358.0

340.5

367.0

358.0

366.0

367.0

333.2

367.0

333.2

367.0

182.0

338.1

364.0

335.0

338.1

367.0

335.0

364.0

367.0

345.9

367.0

345.9

367.0

20.0

20.6

27.0

35.0

20.6

38.0

35.0

50.0

38.0

28.6

35.0

28.6

35.0

3000

250

2500

2000

2500

2000

VSSOP

SOIC

DGK

TLV2763CDR

TLV2763IDGSR

TLV2763IDR

SOIC

VSSOP

SOIC

DGS

TLV2764CDR

TLV2764IDR

SOIC

TLV2764IPWR

TLV2765CDR

TLV2765IDR

TSSOP

SOIC

TLV2765IPWR

TSSOP

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV2762CDGKT [TI]

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