TLV27L1CDBV [TI]

OP-AMP, 7000uV OFFSET-MAX, 0.16MHz BAND WIDTH, PDSO5, GREEN, PLASTIC, SOT-23, 5 PIN;
TLV27L1CDBV
型号: TLV27L1CDBV
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

OP-AMP, 7000uV OFFSET-MAX, 0.16MHz BAND WIDTH, PDSO5, GREEN, PLASTIC, SOT-23, 5 PIN

放大器 光电二极管
文件: 总21页 (文件大小:789K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
FAMILY OF MICROPOWER RAIL-TO-RAIL OUTPUT  
OPERATIONAL AMPLIFIERS  
FEATURES  
DESCRIPTION  
D
D
D
D
D
D
D
D
BiMOS Rail-to-Rail Output  
The TLV27Lx single supply operational amplifiers  
Input Bias Current . . . 1 pA  
provide rail-to-rail output capability. The TLV27Lx takes  
the minimum operating supply voltage down to 2.7 V  
over the extended industrial temperature range, while  
adding the rail-to-rail output swing feature. The  
TLV27Lx also provides 160-kHz bandwidth from only  
7 μA. The maximum recommended supply voltage is  
16 V, which allows the devices to be operated from  
( 8-V supplies down to 1.35 V) two rechargeable cells.  
High Wide Bandwidth . . . 160 kHz  
High Slew Rate . . . 0.1 V/μs  
Supply Current . . . 7 μA (per channel)  
Input Noise Voltage . . . 89 nV/Hz  
Supply Voltage Range . . . 2.7 V to 16 V  
Specified Temperature Range  
− −40°C to 125°C . . . Industrial Grade  
0°C to 70°C . . . Commercial Grade  
Ultra-Small Packaging  
5 Pin SOT-23 (TLV27L1)  
The rail-to-rail outputs make the TLV27Lx good  
upgrades for the TLC27Lx family—offering more  
bandwidth at a lower quiescent current. The TLV27Lx  
offset voltage is equal to that of the TLC27LxA variant.  
Their cost effectiveness makes them a good alternative  
to the TLC/V225x, where offset and noise are not of  
premium importance.  
D
APPLICATIONS  
D
D
D
D
Portable Medical  
The TLV27L1/2 are available in the commercial  
temperature range to enable easy migration from the  
equivalent TLC27Lx. The TLV27L1 is not available with  
the power saving/performance boosting programmable  
pin 8.  
Power Monitoring  
Low Power Security Detection Systems  
Smoke Detectors  
The TLV27L1 is available in the small SOT-23 package  
—something the TLC27(L)1 was not—enabling  
performance boosting in a smaller package. The  
TLV27L2 is available in the 3mm x 5mm MSOP,  
providing PCB area savings over the 8-pin SOIC and  
8-pin TSSOP.  
SELECTION GUIDE  
V
[V]  
I /ch  
[μA]  
V
[V]  
V
[mV]  
I
GBW  
[MHz]  
SLEW RATE  
V , 1 kHz  
[nV/Hz]  
S
Q
ICR  
IO  
IB  
n
DEVICE  
[pA]  
[V/μs]  
TLV27Lx  
TLV238x  
TLC27Lx  
OPAx349  
OPAx347  
TLC225x  
2.7 to 16  
2.7 to 16  
4 to 16  
11  
0.2 to V +1.2  
5
60  
0.18  
0.18  
0.06  
0.06  
0.03  
0.02  
0.01  
0.02  
89  
S
10  
0.2 to V 0.2  
4.5  
60  
90  
S
17  
0.2 to V 1.5  
10/5/2  
10  
60  
0.085  
0.070  
0.35  
68  
S
1.8 to 5.5  
2.3 to 5.5  
2.7 to 16  
2
0.2 to V +0.2  
10  
300  
60  
S
34  
0.2 to V +0.2  
6
10  
S
62.5  
0 to V 1.5  
1.5/0.85  
60  
0.200  
19  
S
NOTE: All dc specs are maximums while ac specs are typicals.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
Copyright © 20012012, Texas Instruments Incorporated  
1
www.ti.com  
TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
PACKAGE/ORDERING INFORMATION  
SPECIFIED  
PACKAGE  
CODE  
PRODUCT  
PACKAGE  
SYMBOL  
TEMPERATURE  
RANGE  
ORDER NUMBER TRANSPORT MEDIA  
TLV27L1CD  
TLV27L1CDR  
TLV27L1CDBVR  
TLV27L1CDBVT  
TLV27L1ID  
Tube  
TLV27L1CD  
TLV27L1CDBV  
TLV27L1ID  
SOIC-8  
SOT-23  
SOIC-8  
SOT-23  
SOIC-8  
SOIC-8  
D
27V1C  
VBIC  
Tape and Reel  
0°C to 70°C  
DBV  
D
Tape and Reel  
Tube  
27V1I  
VBII  
TLV27L1IDR  
TLV27L1IDBVR  
TLV27L1IDBVT  
TLV27L2CD  
Tape and Reel  
40°C to 125°C  
TLV27L1IDBV  
TLV27L2CD  
TLV27L2ID  
DBV  
D
Tape and Reel  
Tube  
27V2C  
27V2I  
0°C to 70°C  
TLV27L2CDR  
TLV27L2ID  
Tape and Reel  
Tube  
D
40°C to 125°C  
TLV27L2IDR  
Tape and Reel  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†  
Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V  
S
Input voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
I
S
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
O
Differential input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
ID  
S
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
J
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C  
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 125°C  
stg  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: Relative to GND pin.  
DISSIPATION RATING TABLE  
PACKAGE  
θ
JC  
θ
JA  
T 25°C  
A
T = 85°C  
A
(°C/W)  
38.3  
55  
(°C/W)  
POWER RATING POWER RATING  
D (8)  
176  
710 mW  
385 mW  
425 mW  
370 mW  
201 mW  
221 mW  
DBV (5)  
DBV (6)  
324.1  
294.3  
55  
recommended operating conditions  
MIN  
1.35  
2.7  
MAX  
8
UNIT  
Dual supply  
Supply voltage, (V )  
V
V
S
Single supply  
16  
Input common-mode voltage range  
0.2 V 1.2  
S
C-suffix  
I-suffix  
0
70  
Operating free-air temperature, T  
°C  
A
40  
125  
2
www.ti.com  
TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 10 V (unless  
otherwise noted)  
dc performance  
PARAMETER  
TEST CONDITIONS  
T
A
MIN  
TYP  
MAX  
UNIT  
25°C  
Full range  
25°C  
0.5  
5
7
V
Input offset voltage  
Offset voltage drift  
mV  
V
= V /2,  
V
R
= V /2,  
= 50 Ω  
IO  
IC  
S
O
S
R = 100 kΩ,  
L
S
α
VIO  
1.1  
86  
μV/°C  
25°C  
71  
70  
80  
77  
77  
74  
V
R
= 0 V to V 1.2 V,  
= 50 Ω  
S
IC  
CMRR Common-mode rejection ratio  
dB  
dB  
S
Full range  
25°C  
100  
82  
V
V
= 2.7 V,  
5 V  
S
Full range  
25°C  
Large-signal differential voltage  
amplification  
V
=V /2,  
S
O(PP)  
A
VD  
R = 100 kΩ  
L
=
5 V  
S
Full range  
Full range is 40°C to 125°C for I suffix.  
input characteristics  
PARAMETER  
TEST CONDITIONS  
T
MIN  
TYP  
MAX  
60  
UNIT  
A
25°C  
70°C  
125°C  
25°C  
70°C  
125°C  
25°C  
1
100  
1000  
60  
I
I
Input offset current  
pA  
IO  
V
= V /2,  
V
O
= V /2,  
IC  
S
S
R = 100 kΩ,  
R
= 50 Ω  
L
S
1
200  
1000  
Input bias current  
pA  
IB  
r
Differential input resistance  
1000  
8
GΩ  
i(d)  
C
Common-mode input capacitance  
f = 1 kHz  
25°C  
pF  
IC  
power supply  
PARAMETER  
TEST CONDITIONS  
T
A
MIN  
TYP  
MAX  
11  
UNIT  
25°C  
Full range  
25°C  
7
I
Q
Quiescent current (per channel)  
V
= V /2  
μA  
S
O
16  
74  
70  
82  
V
V
= 2.7 V to 16 V,  
No load,  
S
PSRR  
Power supply rejection ratio (ΔV /ΔV  
)
IO  
dB  
S
= V /2 V  
Full range  
IC  
S
Full range is 40°C to 125°C for I suffix.  
3
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TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
electrical characteristics at recommended operating conditions, VS = 2.7 V, 5 V, and 5 V (unless  
otherwise noted) (continued)  
output characteristics  
PARAMETER  
TEST CONDITIONS  
T
A
MIN  
TYP  
MAX  
200  
220  
120  
200  
120  
150  
800  
900  
400  
500  
UNIT  
25°C  
Full range  
25°C  
160  
V
S
V
S
V
S
V
S
= 2.7 V  
= 5 V  
85  
50  
V
= V /2,  
= 100 μA  
IC  
S
I
OL  
Full range  
25°C  
V
O
Output voltage swing from rail  
=
5 V  
mV  
Full range  
25°C  
420  
200  
400  
= 5 V  
Full range  
25°C  
V
IC  
= V /2,  
S
I
OL  
= 500 μA  
V
V
=
5 V  
S
Full range  
25°C  
I
O
Output current  
V
O
= 0.5 V from rail  
= 2.7 V  
μA  
S
Full range is 40°C to 125°C for I suffix.  
dynamic performance  
PARAMETER  
Gain bandwidth product  
TEST CONDITIONS  
T
MIN  
TYP  
160  
0.06  
0.05  
0.8  
62  
MAX  
UNIT  
A
GBP  
SR  
R = 100 kΩ, C = 10 pF, f = 1 kHz  
25°C  
25°C  
kHz  
L
L
V
= 1 V, R = 100 kΩ,  
L
C = 50 pF  
O(pp)  
40°C  
125°C  
25°C  
Slew rate at unity gain  
V/μs  
L
φ
M
Phase margin  
R = 100 kΩ,  
C = 50 pF  
L
°
L
Rise  
Fall  
62  
V
= 1 V, A = 1,  
V
(STEP)pp  
t
s
Settling time (0.1%)  
25°C  
μs  
C = 50 pF,  
R = 100 kΩ  
L
44  
L
noise/distortion performance  
PARAMETER  
TEST CONDITIONS  
T
MIN  
TYP  
89  
MAX  
UNIT  
nV/Hz  
fA/Hz  
A
V
n
Equivalent input noise voltage  
Equivalent input noise current  
f = 1 kHz  
f = 1 kHz  
25°C  
25°C  
I
n
0.6  
4
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TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
TYPICAL CHARACTERISTICS  
Table of Graphs  
FIGURE  
1, 2, 3  
4
V
Input offset voltage  
vs Common-mode input voltage  
IO  
I /I  
IB IO  
Input bias and offset current  
High-level output voltage  
Low-level output voltage  
vs Free-air temperature  
vs High-level output current  
vs Low-level output current  
vs Supply voltage  
V
5, 7, 9  
6, 8, 10  
11  
OH  
OL  
V
I
Q
Quiescent current  
vs Free-air temperature  
12  
Supply voltage and supply current ramp up  
Differential voltage gain and phase shift  
Gain-bandwidth product  
13  
A
vs Frequency  
14  
VD  
GBP  
vs Free-air temperature  
vs Load capacitance  
vs Frequency  
15  
φ
m
Phase margin  
16  
CMRR Common-mode rejection ratio  
17  
PSRR  
Power supply rejection ratio  
Input referred noise voltage  
Slew rate  
vs Frequency  
18  
vs Frequency  
19  
SR  
vs Free-air temperature  
vs Frequency  
20  
V
O(PP)  
Peak-to-peak output voltage  
Inverting small-signal response  
Inverting large-signal response  
Crosstalk  
21  
22  
23  
vs Frequency  
24  
INPUT OFFSET VOLTAGE  
vs  
INPUT OFFSET VOLTAGE  
vs  
INPUT OFFSET VOLTAGE  
vs  
COMMON-MODE INPUT VOLTAGE  
COMMON-MODE INPUT VOLTAGE  
COMMON-MODE INPUT VOLTAGE  
2000  
2000  
2000  
1500  
1000  
500  
V
T
= 2.7 V  
= 25°C  
V
T
=
5 Vdc  
V
T
= 2.7 V  
= 25°C  
S
S
S
1500  
1500  
= 25°C  
A
A
A
1000  
500  
1000  
500  
0
0
500  
0
500  
1000  
500  
1000  
1000  
1500  
2000  
1500  
2000  
1500  
2000  
0
0.5  
1
1.5  
2
2.5  
3
5.2 3.6  
2  
0.4  
1.2  
2.8  
4.4  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
V
Common-Mode Input Voltage V  
V
Common-Mode Input Voltage V  
V
Common-Mode Input Voltage V  
IC  
IC  
IC  
Figure 2  
Figure 3  
Figure 1  
5
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TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
TYPICAL CHARACTERISTICS  
INPUT BIAS AND INPUT  
OFFSET CURRENT  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
FREE-AIR TEMPERATURE  
5
4
5
4
3
100  
90  
V
= 5 V  
V
= 5 V  
S
S
V
= 5 V  
= 2.5  
= 2.5  
S
125°C  
V
V
40°C  
IC  
O
3
80  
70  
60  
50  
40  
30  
20  
10  
0
0°C  
25°C  
25°C  
2
1
2
1
70°C  
25°C  
0
1  
2  
0
1  
2  
3  
4  
5  
0°C  
I
IB  
125°C  
40°C  
3  
I
IO  
4  
5  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
0
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15  
25  
45  
65  
85  
105  
125  
I
High-Level Output Current mA  
I
Low-Level Output Current mA  
T
A
Free-Air Temperature °C  
OH  
OL  
Figure 4  
Figure 5  
Figure 6  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
2.7  
2.4  
2.1  
1.8  
1.5  
1.2  
0.9  
0.6  
5
5
V
= 2.7 V  
V = 5 V  
S
S
V
= 5 V  
S
4.5  
4.5  
4
40°C  
125°C  
70°C  
40°C  
4
0°C  
0°C  
3.5  
3
3.5  
25°C  
70°C  
25°C  
25°C  
0°C  
3
70°C  
2.5  
2.5  
2
1.5  
1
2
1.5  
1
125°C  
125°C  
40°C  
0.3  
0
0.5  
0.5  
0
0
0
0.2  
0.4 0.6  
0.8  
1
1.2 1.4  
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
I High-Level Output Current mA  
OH  
I
Low-Level Output Current mA  
I
High-Level Output Current mA  
OL  
OH  
Figure 7  
Figure 8  
Figure 9  
QUIESCENT CURRENT  
vs  
FREE-AIR TEMPERATURE  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
QUIESCENT CURRENT  
vs  
SUPPLY VOLTAGE  
8
7
6
5
4
3
2
1
0
8
2.7  
16 V  
10 V  
V
= 2.7 V  
125°C  
70°C  
S
2.4  
2.1  
1.8  
1.5  
1.2  
7
6
5 V  
125°C  
70°C  
5
4
3
2
2.7 V  
25°C  
0°C  
40°C  
25°C  
0°C  
0.9  
0.6  
0.3  
0
40°C  
1
0
40 25 10  
5
20 35 50 65 80 95 110 125  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
0
2
4
6
8
10 12 14  
V Supply Voltage V  
S
16  
T
A
Free-Air Temperature °C  
I
Low-Level Output Current mA  
OL  
Figure 10  
Figure 11  
Figure 12  
6
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TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
TYPICAL CHARACTERISTICS  
DIFFERENTIAL VOLTAGE GAIN  
AND PHASE SHIFT  
vs  
SUPPLY VOLTAGE AND  
FREQUENCY  
SUPPLY CURRENT RAMP UP  
40  
15  
120  
100  
80  
V
= 5 V  
S
V
S
R
C
T
= 100 kΩ  
= 10 pF  
= 25°C  
L
L
10  
5
0°  
V
A
O
30°  
0
V
R
C
= 0 to 15 V,  
= 100 Ω,  
= 10 pF,  
= 25°C  
S
60  
60°  
90°  
L
L
40  
T
A
15  
10  
I
Q
20  
0
120°  
150°  
180°  
5
0
20  
0.1  
0
5
10  
15  
20  
25  
30  
1
10  
100  
1 k 10 k 100 k 1 M  
t Time ms  
f Frequency Hz  
Figure 14  
Figure 13  
COMMON-MODE REJECTION RATIO  
vs  
PHASE MARGIN  
vs  
LOAD CAPACITANCE  
GAIN-BANDWIDTH PRODUCT  
vs  
FREE-AIR TEMPERATURE  
FREQUENCY  
120  
80  
170  
160  
V
R
T
A
= 5 V  
= 100 kΩ  
= 25°C  
110  
S
V
T
A
= 5 V  
= 25°C  
S
70  
60  
50  
40  
30  
20  
10  
0
L
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
V
= 2.7 V  
S
150  
140  
130  
V
= 5 V  
S
120  
110  
100  
10  
100  
1 k  
10 k  
100 k  
1 M  
40 25 10 5 20 35 50 65 80 95 110 125  
10  
100  
1000  
f Frequency Hz  
C
Load Capacitance pF  
T
A
Free-Air Temperature °C  
L
Figure 15  
Figure 16  
Figure 17  
SLEW RATE  
vs  
FREE-AIR TEMPERATURE  
POWER SUPPLY REJECTION RATIO  
INPUT REFERRED NOISE VOLTAGE  
vs  
vs  
FREQUENCY  
FREQUENCY  
0.09  
0.08  
0.07  
0.06  
0.05  
100  
90  
250  
200  
150  
100  
V
= 5 V,  
S
V
= 2.5 V  
= 25°C  
S
SR+  
G = 2,  
= 100 kΩ  
T
A
80  
R
F
70  
SR−  
60  
50  
40  
30  
20  
0.04  
0.03  
0.02  
V = 5 V  
S
Gain = 1  
V
= 1  
O
50  
0
R
C
= 100 kΩ  
= 50 pF  
L
L
0.01  
0
10  
0
40 25 10 5 20 35 50 65 80 95 110 125  
10  
100  
1 k  
10 k  
100 k  
1 M  
1
10  
100  
1 k  
10 k  
100 k  
T
A
Free-air Temperature °C  
f Frequency Hz  
f Frequency Hz  
Figure 20  
Figure 18  
Figure 19  
7
www.ti.com  
TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
TYPICAL CHARACTERISTICS  
PEAK-TO-PEAK OUTPUT VOLTAGE  
vs  
INVERTING SMALL-SIGNAL  
RESPONSE  
FREQUENCY  
2
16  
V = 3 V  
I
PP  
1.5  
V
= 15 V  
S
14  
12  
10  
1
Gain = 1,  
R
C
= 100 kΩ,  
= 10 pF,  
= 5 V,  
L
L
0.5  
R
C
= 100 kΩ,  
= 10 pF,  
L
L
V
V
S
0
0.5  
1  
= 3 V  
,
O
PP  
THD+N <= 5%  
8
6
4
f = 1 kHz  
V
= 5 V  
S
1.5  
2  
V
= 3 V  
PP  
O
2
0
V
= 2.7 V  
S
100  
0
100 200 300 400 500 600 700  
10  
100  
1000  
1 k  
10 k  
t Time μs  
f Frequency Hz  
Figure 22  
Figure 21  
CROSSTALK  
vs  
FREQUENCY  
INVERTING LARGE-SIGNAL  
RESPONSE  
0.06  
0.04  
0.02  
0
V
= 5 V  
S
R
C
= 2 kΩ  
= 10 pF  
= 25°C  
L
L
20  
V = 100 mV  
I
PP  
T
A
Gain = 1,  
40  
60  
Channel 1 to 2  
R
C
= 100 kΩ,  
= 10 pF,  
L
L
V
V
= 5 V,  
= 100 mV  
S
0
,
O
PP  
80  
f = 1 kHz  
0.02  
0.04  
0.06  
100  
120  
140  
V
= 100 mV  
PP  
O
100  
0
100 200 300 400 500 600 700  
10  
100  
1 k  
10 k  
100 k  
t Time μs  
f Frequency Hz  
Figure 23  
Figure 24  
8
www.ti.com  
TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
APPLICATION INFORMATION  
offset voltage  
The output offset voltage (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times the  
OO  
IO  
IB  
corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:  
R
F
I
IB  
R
G
+
R
R
F
F
V
I
V
+ V  
1 ) ǒ Ǔ " I  
R
1 ) ǒ Ǔ " I  
R
V
O
ǒ Ǔ ǒ Ǔ  
OO  
IO  
IB)  
S
IB–  
F
R
R
+
G
G
R
S
I
IB+  
Figure 25. Output Offset Voltage Model  
general configurations  
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The  
simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 26).  
R
R
F
G
V
R
R
O
F
1
ǒ1 ) sR1C1Ǔ  
+
+
ǒ
1 )  
Ǔ
V
I
G
V
DD  
/2  
1
V
O
f
+
–3dB  
V
I
2pR1C1  
R1  
C1  
Figure 26. Single-Pole Low-Pass Filter  
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task.  
For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure  
to do this can result in phase shift of the amplifier.  
C1  
R1 = R2 = R  
C1 = C2 = C  
Q = Peaking Factor  
(Butterworth Q = 0.707)  
+
_
V
I
1
R1  
R2  
f
+
–3dB  
2pRC  
C2  
R
F
R
=
G
1
Q
R
F
2  
)
(
R
G
V
DD  
/2  
Figure 27. 2-Pole Low-Pass Sallen-Key Filter  
9
www.ti.com  
TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
APPLICATION INFORMATION  
circuit layout considerations  
To achieve the levels of high performance of the TLV27Lx, follow proper printed-circuit board design techniques. A  
general set of guidelines is given in the following.  
D
Ground planes—It is highly recommended that a ground plane be used on the board to provide all  
components with a low inductive ground connection. However, in the areas of the amplifier inputs and  
output, the ground plane can be removed to minimize the stray capacitance.  
D
Proper power supply decoupling—Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic  
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers  
depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal  
of every amplifier. In addition, the 0.1-μF capacitor should be placed as close as possible to the supply  
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less  
effective. The designer should strive for distances of less than 0.1 inches between the device power  
terminals and the ceramic capacitors.  
D
D
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins  
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board  
is the best implementation.  
Short trace runs/compact part placements—Optimum high performance is achieved when stray series  
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,  
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of  
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at  
the input of the amplifier.  
D
Surface-mount passive components—Using surface-mount passive components is recommended for high  
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of  
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small  
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray  
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be  
kept as short as possible.  
10  
www.ti.com  
TLV27L1  
TLV27L2  
SLOS378B SEPTEMBER 2001 REVISED MARCH 2012  
APPLICATION INFORMATION  
general power dissipation considerations  
For a given θ , the maximum power dissipation is shown in Figure 28 and is calculated by the following formula:  
JA  
T
–T  
MAX  
A
P
+
ǒ Ǔ  
D
q
JA  
Where:  
P
D
= Maximum power dissipation of TLV27Lx IC (watts)  
T
T
= Absolute maximum junction temperature (150°C)  
MAX  
= Free-ambient air temperature (°C)  
= θ + θ  
A
θ
JA  
JC  
JC  
CA  
CA  
θ
θ
= Thermal coefficient from junction to case  
= Thermal coefficient from case to ambient air (°C/W)  
MAXIMUM POWER DISSIPATION  
vs  
FREE-AIR TEMPERATURE  
2
T
J
= 150°C  
PDIP Package  
Low-K Test PCB  
1.75  
1.5  
1.25  
1
θ
JA  
= 104°C/W  
MSOP Package  
Low-K Test PCB  
SOIC Package  
Low-K Test PCB  
θ
JA  
= 260°C/W  
θ
JA  
= 176°C/W  
0.75  
0.5  
SOT-23 Package  
Low-K Test PCB  
0.25  
0
θ
JA  
= 324°C/W  
5540 25 10  
5
20 35 50 65 80 95 110 125  
T
A
Free-Air Temperature °C  
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.  
Figure 28. Maximum Power Dissipation vs Free-Air Temperature  
TLV27L1  
D PACKAGE  
(TOP VIEW)  
TLV27L2  
D PACKAGE  
(TOP VIEW)  
TLV27L1  
DBV PACKAGE  
(TOP VIEW)  
NC  
IN  
IN+  
NC  
1OUT  
1IN−  
1IN+  
GND  
VDD  
1
2
3
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
5
4
V
DD  
OUT  
GND  
VDD  
OUT  
NC  
2OUT  
2IN−  
2IN+  
GND  
IN−  
IN+  
NC No internal connection  
11  
www.ti.com  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
TLV27L1CD  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
0 to 70  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
D
8
5
5
5
5
8
8
5
5
5
5
8
8
8
8
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
27V1C  
TLV27L1CDBVR  
TLV27L1CDBVRG4  
TLV27L1CDBVT  
TLV27L1CDBVTG4  
TLV27L1CDG4  
TLV27L1ID  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DBV  
DBV  
DBV  
DBV  
D
3000  
3000  
250  
250  
75  
Green (RoHS  
& no Sb/Br)  
0 to 70  
VBIC  
VBIC  
VBIC  
VBIC  
27V1C  
27V1I  
VBII  
Green (RoHS  
& no Sb/Br)  
0 to 70  
Green (RoHS  
& no Sb/Br)  
0 to 70  
Green (RoHS  
& no Sb/Br)  
0 to 70  
Green (RoHS  
& no Sb/Br)  
0 to 70  
SOIC  
D
75  
Green (RoHS  
& no Sb/Br)  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
TLV27L1IDBVR  
TLV27L1IDBVRG4  
TLV27L1IDBVT  
TLV27L1IDBVTG4  
TLV27L1IDG4  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
DBV  
DBV  
D
3000  
3000  
250  
250  
75  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
VBII  
Green (RoHS  
& no Sb/Br)  
VBII  
Green (RoHS  
& no Sb/Br)  
VBII  
Green (RoHS  
& no Sb/Br)  
27V1I  
27V1I  
27V1I  
BAC  
TLV27L1IDR  
SOIC  
D
2500  
2500  
80  
Green (RoHS  
& no Sb/Br)  
TLV27L1IDRG4  
TLV27L2CDGK  
TLV27L2CDGKG4  
TLV27L2CDGKR  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
VSSOP  
VSSOP  
VSSOP  
DGK  
DGK  
DGK  
Green (RoHS  
& no Sb/Br)  
80  
Green (RoHS  
& no Sb/Br)  
BAC  
2500  
Green (RoHS  
& no Sb/Br)  
BAC  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
TLV27L2CDGKRG4  
TLV27L2CDR  
ACTIVE  
VSSOP  
SOIC  
DGK  
8
8
8
8
8
8
8
8
8
8
8
2500  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
BAC  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
2500  
2500  
75  
Green (RoHS  
& no Sb/Br)  
0 to 70  
0 to 70  
27V2C  
27V2C  
27V2I  
27V2I  
BAD  
TLV27L2CDRG4  
TLV27L2ID  
SOIC  
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
-40 to 125  
-40 to 125  
TLV27L2IDG4  
TLV27L2IDGK  
TLV27L2IDGKG4  
TLV27L2IDGKR  
TLV27L2IDGKRG4  
TLV27L2IDR  
SOIC  
D
75  
Green (RoHS  
& no Sb/Br)  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
DGK  
D
80  
Green (RoHS  
& no Sb/Br)  
80  
Green (RoHS  
& no Sb/Br)  
BAD  
2500  
2500  
2500  
2500  
Green (RoHS  
& no Sb/Br)  
BAD  
Green (RoHS  
& no Sb/Br)  
BAD  
Green (RoHS  
& no Sb/Br)  
-40 to 125  
-40 to 125  
27V2I  
27V2I  
TLV27L2IDRG4  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TLV27L1CDBVR  
TLV27L1CDBVT  
TLV27L1IDBVR  
TLV27L1IDBVT  
TLV27L1IDR  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
DBV  
DBV  
D
5
5
5
5
8
8
8
8
8
8
8
3000  
250  
180.0  
180.0  
180.0  
180.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
9.0  
9.0  
3.15  
3.15  
3.15  
3.15  
6.4  
3.2  
3.2  
3.2  
3.2  
5.2  
3.4  
3.4  
5.2  
3.4  
3.4  
5.2  
1.4  
1.4  
1.4  
1.4  
2.1  
1.4  
1.4  
2.1  
1.4  
1.4  
2.1  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q3  
Q3  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
3000  
250  
9.0  
8.0  
9.0  
8.0  
2500  
2500  
2500  
2500  
2500  
2500  
2500  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
TLV27L2CDGKR  
TLV27L2CDGKR  
TLV27L2CDR  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
5.3  
5.3  
6.4  
TLV27L2IDGKR  
TLV27L2IDGKR  
TLV27L2IDR  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
5.3  
5.3  
6.4  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TLV27L1CDBVR  
TLV27L1CDBVT  
TLV27L1IDBVR  
TLV27L1IDBVT  
TLV27L1IDR  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
DBV  
DBV  
D
5
5
5
5
8
8
8
8
8
8
8
3000  
250  
182.0  
182.0  
182.0  
182.0  
340.5  
358.0  
364.0  
340.5  
358.0  
364.0  
340.5  
182.0  
182.0  
182.0  
182.0  
338.1  
335.0  
364.0  
338.1  
335.0  
364.0  
338.1  
20.0  
20.0  
20.0  
20.0  
20.6  
35.0  
27.0  
20.6  
35.0  
27.0  
20.6  
3000  
250  
2500  
2500  
2500  
2500  
2500  
2500  
2500  
TLV27L2CDGKR  
TLV27L2CDGKR  
TLV27L2CDR  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
TLV27L2IDGKR  
TLV27L2IDGKR  
TLV27L2IDR  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
Pack Materials-Page 2  
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