TLV320AIC3256_12 [TI]
Ultra Low Power Stereo Audio Codec With Embedded miniDSP; 超低功耗立体声音频编解码器嵌入式miniDSP
| 型号： | TLV320AIC3256_12 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Ultra Low Power Stereo Audio Codec With Embedded miniDSP |
| 文件： | 总44页 (文件大小：1013K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV320AIC3256
www.ti.com
SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Ultra Low Power Stereo Audio Codec With Embedded miniDSP
Check for Samples: TLV320AIC3256
1
FEATURES
•
Future 3.5mm x 3.3mm 42-ball WCSP
2
•
Stereo Audio DAC with 100dB SNR
APPLICATIONS
•
5.0mW Stereo 48ksps
•
•
•
•
•
•
•
•
Portable Navigation Devices (PND)
Portable Media Player (PMP)
Mobile Handsets
Communication
Portable Computing
Acoustic Echo Cancellation (AEC)
Active Noise Cancellation (ANC)
Advanced DSP algorithms
DAC-to-Ground-Centered Headphone Playback
•
•
•
•
•
•
Stereo Audio ADC with 93dB SNR
5.2mW Stereo 48ksps ADC Record
PowerTune™
Extensive Signal Processing Options
Embedded miniDSP
Six Single-Ended or 3 Fully-Differential Analog
Inputs
•
•
•
•
•
•
•
Stereo Analog and Digital Microphone Inputs
Ground-Centered Stereo Headphone Outputs
Very Low-Noise PGA
DESCRIPTION
The TLV320AIC3256 (sometimes referred to as the
AIC3256) is a flexible, low-power, low-voltage stereo
audio codec with programmable inputs and outputs,
PowerTune capabilities, fully-programmable miniDSP,
fixed predefined and parameterizable signal
processing blocks, integrated PLL, and flexible digital
interfaces.
Low Power Analog Bypass Mode
Programmable Microphone Bias
Programmable PLL
5mm x 5mm 40-pin QFN Package
IN1_L
IN2_L
IN3_L
AGC
DRC
Vol. Ctrl
-6...+14dB
0…+47.5 dB
+
+
ADC
Signal
Proc.
DAC
Signal
Proc.
HPL
LOL
LOR
+
+
+
+
Left
ADC
Left
DAC
tpl
*
*
1dB steps
-6...+29dB
Gain Adj.
0.5 dB
steps
-30...0 dB
1dB steps
-6...+29dB
Data
Interface
miniDSP
miniDSP
-30...0 dB
1dB steps
-6...+14dB
0…
+47.5 dB
Gain Adj.
+
+
ADC
Signal
Proc.
DAC
Signal
Proc.
Right
ADC
Right
DAC
tpr
*
*
HPR
IN3_R
IN2_R
IN1_R
0.5 dB steps
AGC
DRC
1dB steps
Vol. Ctrl
GND_Sense
SPI_Select
Reset
SPI / I2C
Control Block
Dig Inter
Mic rupt
Sec.
I2S I/F
Primary
I2S Interface
PLL
VNEG
Fly_N
Fly_P
Charge
Pump
MicBias
MicDet
Mic
Bias
Supplies
Pin Muxing/ Clock Routing
Ref
Ref
Figure 1. Simplified Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerTune is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TLV320AIC3256
SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The TLV320AIC3256 features two fully-programmable miniDSP cores that support application-specific algorithms
in the record and/or the playback path of the device. The miniDSP cores are fully software controlled. Target
miniDSP algorithms, such as active noise cancellation, acoustic echo cancellation or advanced DSP filtering are
loaded into the device after power-up.
Extensive register-based control of power, input/output channel configuration, gains, effects, pin-multiplexing and
clocks is included, allowing the device to be precisely targeted to its application. The device can cover operations
from 8kHz mono voice playback to audio stereo 192kHz DAC playback, making it ideal for portable
battery-powered audio and telephony applications.
The record path of the TLV320AIC3256 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations covering single-ended and differential setups, as well as
floating or mixing input signals. It also includes a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. Digital signal processing blocks can remove audible noise that may be introduced by
mechanical coupling, e.g. optical zooming in a digital camera.
The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC
and analog input signals as well as programmable volume controls. The playback path contains two high-power
output drivers which eliminate the need for ac coupling capacitors. A built in charge pump generates the negative
supply for the ground centered high powered output drivers. The high-power outputs can be configured in
multiple ways, including stereo and mono BTL.
The device can be programmed to various power-performance trade-offs. Mobile applications frequently have
multiple use cases requiring very low power operation while being used in a mobile environment. When used in a
docked environment power consumption typically is less of a concern, while minimizing noise is important. The
TLV320AIC3256 addresses both cases.
The device offers single supply operation from 1.5V-1.95V. Digital I/O voltages are supported in the range of
1.1V-3.6V.
The required internal clock of the TLV320AIC3256 can be derived from multiple sources, including the MCLK pin,
the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived
from the MCLK pin, the BCLK or GPIO pins. Although using the PLL ensures the availability of a suitable clock
signal, it is not recommended for the lowest power settings. The PLL is highly programmable and can accept
available input clocks in the range of 512kHz to 50MHz.
The device is available in the 5mm × 5mm, 40-pin QFN package. A 3.5mm × 3.3mm 42-ball WCSP will soon be
available.
2
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Product Folder Link(s): TLV320AIC3256
TLV320AIC3256
www.ti.com
SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Package and Signal Descriptions
Packaging/Ordering Information
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
OPERATING
TEMPERATURE
RANGE
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
TLV320AIC3256
QFN
RSB
YZF
–40°C to 85°C
TLV320AIC3256IRSBT
TLV320AIC3256IRSBR
TLV320AIC3256IYZFT
TLV320AIC3256IYZFR
Tape and Reel, 250
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 3000
TLV320AIC3256(1)
WCSP
–40°C to 85°C
(1) Preview information
Pin Assignments
IOVss
DVdd (40)
SCLK/MFP3
SCL/SSZ
SDA/MOSI
MISO/MFP4
SPI_SELECT
IN1_L
DVdd_CP
FLY_P
DVss_CP
FLY_N
VNEG
MICDET
HPR
IN1_R
DRVDD_HP
HPL
IN2_L
IN2_R
Figure 2. QFN (RSB) Package, Bottom View
Figure 3. WCSP (YZF) Package, Bottom View
(Preview)
Table 1. Ball Layout, YZF Package, Bottom View (Preview)
G
F
AVdd
HPL
AVdd
DRVdd_HP
MICDET
FLY_N
FLY_P
DVss
LOL
LOR
MICBIAS
IN3_R
AVss
MISO
SCLK
BCLK
DOUT
4
REF
IN3_L
AVss
NC
IN2_R
IN2_L
E
D
C
B
A
HPR
GND_SENSE
DVss_CP
SDA/MOSI
GPIO
IN1_R
VNEG
DVdd_CP
DVdd
DVss
1
IN1_L
RESET
IOVss
DIN
SPI_SELECT
SCL/SS
IOVdd
MCLK
WCLK
2
3
5
6
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TLV320AIC3256
SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
www.ti.com
Table 2. TERMINAL FUNCTIONS
5x5mm
40-PIN QFN
WCSP
(YZF)
NAME
TYPE
DESCRIPTION
(RSB) PIN BALL NO.
NO.
(Preview)
1
B2
A1
C5
B3
DVss
GND Digital ground. Device substrate.(1)
GND Digital ground(1)
2
DVss
3
RESET
GPIO
I
Hardware reset
Primary
4
I/O
General purpose digital IO
Secondary
CLKOUT output
MFP5
INT1 output
INT2 output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output
5
6
7
8
A2
B4
A3
A5
MCLK
BCLK
WCLK
DIN
I
Master clock input
I/O
I/O
I
Audio serial data bus (primary) bit clock
Audio serial data bus (primary) word clock
Primary function
Audio serial data bus data input
Secondary function
MFP1
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) word clock input
Digital Microphone Input
Clock Input
General Purpose Input
9
A4
DOUT
MFP2
O
Primary
Audio serial data bus data output
Secondary
General purpose output
Clock output
INT1 output
INT2 output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
10
11
12
A6
B5
C4
IOVdd
IOVss
SCLK
PWR Supply for IO buffers. 1.1V to 3.6V
GND Ground for IO buffers.
I
Primary (SPI_Select = 1)
SPI serial clock
MFP3
Secondary: (SPI_Select = 0)
Digital microphone input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC/common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General purpose input
13
14
15
B6
C3
D4
SCL
SS
I
I2C interface serial clock (SPI_Select = 0)
SPI interface mode chip-select signal (SPI_Select = 1)
I2C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
SDA
MOSI
I/O
O
MISO
Primary (SPI_Select = 1)
(1) The DVss pins are not connected within the device: Must be connected on the PC board.
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Table 2. TERMINAL FUNCTIONS (continued)
5x5mm
40-PIN QFN
WCSP
(YZF)
NAME
TYPE
DESCRIPTION
(RSB) PIN BALL NO.
NO.
(Preview)
Serial data output
MFP4
Secondary (SPI_Select = 0)
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Digital microphone clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
16
17
C6
D6
SPI_SELECT
IN1_L
I
I
Control mode select pin ( 1 = SPI, 0 = I2C )
Multifunction analog input,
Single-ended configuration: MIC 1 or Line 1 left
Differential configuration: MIC or Line right, negative
18
19
20
E6
F6
G6
IN1_R
IN2_L
IN2_R
I
I
I
Multifunction analog input,
Single-ended configuration: MIC 1 or Line 1 right
Differential configuration: MIC or Line right, positive
Multifunction analog input,
Single-ended configuration: MIC 2 or Line 2 right
Differential configuration: MIC or Line left, positive
Multifunction analog input,
Single-ended configuration: MIC 2 or Line 2 right
Differential configuration: MIC or Line left, negative
21
22
23
24
E4, E5
G5
AVss
GND Analog Ground
REF
O
O
I
Reference voltage output for filtering
G4
MICBIAS
IN3_L
Microphone bias voltage output
F5
Multifunction analog input,
Single-ended configuration: MIC3 or Line 3 left,
Differential configuration: MIC or Line left, positive,
Differential configuration: MIC or Line right, negative
25
F4
IN3_R
I
Multifunction analog input,
Single-ended configuration: MIC3 or Line 3 right,
Differential configuration: MIC or Line left, negative,
Differential configuration: MIC or Line right, positive
26
27
G3
F3
LOL
O
O
I
Left line output
LOR
Right line output
28
E3
GND_SENSE
AVdd
External ground reference for headphone interface –0.5V to 0.5V
29, 30
31
G2, G1
F1
PWR Analog voltage supply 1.5V–1.95V(2)
HPL
O
Left headphone output
32
F2
DRVdd_HP
PWR Power supply for headphone output stage
Ground-centered circuit configuration, 1.5V to 1.95V
Unipolar circuit configuration, 1.5V to 3.6V
33
34
35
E1
E2
D1
HPR
O
I
Right headphone output
Microphone detection
MICDET
VNEG
PWR Negative supply for headphones. –1.8V to 0V
Input when charge pump is disabled,
Filtering output when charge pump is enabled
36
37
D2
D3
FLY_N
PWR Negative terminal for charge-pump flying capacitor
GND Charge pump ground
DVss_CP
(2) The AVdd pins are not connected within the device: Must be connected on the PC board.
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Table 2. TERMINAL FUNCTIONS (continued)
5x5mm
40-PIN QFN
WCSP
(YZF)
NAME
TYPE
DESCRIPTION
(RSB) PIN BALL NO.
NO.
(Preview)
38
C2
C1
B1
FLY_P
DVdd_CP
DVdd
PWR Positive terminal for charge pump flying capacitor
PWR Charge Pump supply; recommended to connect to DVdd
PWR Digital voltage supply 1.26V – 1.95V
39
40
6
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 2.2
UNIT
V
AVdd to AVss
DVdd to DVss
–0.3 to 2.2
V
IOVDD to IOVSS
–0.3 to 3.9
V
Digital Input voltage
Analog input voltage
Operating temperature range
Storage temperature range
Junction temperature (TJ Max)
IOVSS to IOVDD + 0.3
AVSS to AVdd + 0.3
–40 to 85
V
V
°C
°C
°C
W
–55 to 150
105
QFN package (RSB)
Power dissipation
(TJ Max – TA)/ qJA
35
qJA Thermal impedance
Power dissipation
C/W
W
WCSP package (YZF)
(TJ Max – TA)/ qJA
50
qJA Thermal impedance
C/W
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM
MAX UNIT
AVdd
Power Supply Voltage Range
Power Supply Voltage Range
PLL Input Frequency
Referenced to AVss(1)
Referenced to IOVSS(1)
Referenced to DVss(1)
Referenced to DVss(1)
1.5
1.1
1.8
1.95
3.6
V
IOVDD
DVdd(2)
1.26
1.26
1.5
1.8
1.8
1.8
1.95
1.95
1.95
3.6
DVDD_CP
DRVDD_HP
V
Referenced
to AVss(1)
Ground-centered config
Unipolar config
1.5
Clock divider uses fractional divide
10
20
MHz
(D > 0), P=1, DVdd ≥ 1.65V (Refer to table in
SLAU306, Maximum TLV320AIC3256 Clock
Frequencies)
Clock divider uses integer divide
0.512
20
MHz
MHz
(D = 0), P=1, DVdd ≥ 1.65V (Refer to table in
SLAU306, Maximum TLV320AIC3256 Clock
Frequencies)
MCLK
Master Clock Frequency
MCLK; Master Clock Frequency; DVdd
1.65V
≥
50
25
MCLK; Master Clock Frequency; DVdd
1.26V
≥
SCL
SCL Clock Frequency
400
kHz
kΩ
Ω
LOL, LOR
HPL, HPR
Stereo line output load resistance
0.6
10
16
Stereo headphone output load
resistance
Single-ended configuration
Differential configuration
14.4
Headphone output load resistance
Digital output load capacitance
Operating Temperature Range
24.4
32
10
Ω
CLout
pF
°C
TOPR
–40
85
(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2V max, for any combination of ground signals.
(2) At DVdd values lower than 1.65V, the PLL does not function. Please see table in SLAU306, Maximum TLV320AIC3256 Clock
Frequencies for details on maximum clock frequencies.
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
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Electrical Characteristics, ADC
At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge
pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC (1) (2) (CM = 0.9V)
Input signal level (for 0dB output) Single-ended, CM = 0.9V
0.5
VRMS
1kHz sine wave input
Single-ended Configuration
IN1R to Right ADC and IN1L to Left ADC,
Rin = 20K, fs = 48kHz,
Device Setup
AOSR = 128, MCLK = 256*fs,
PLL Disabled; AGC = OFF,
Channel Gain = 0dB,
Processing Block = PRB_R1,
Power Tune = PTM_R4
Inputs ac-shorted to ground
80
93
93
Signal-to-noise ratio,
A-weighted(1) (2)
SNR
DR
dB
IN2R, IN3R routed to Right ADC and ac-shorted to ground
IN2L, IN3L routed to Left ADC and ac-shorted to ground
Dynamic range A-weighted(1) (2) –60dB full-scale, 1-kHz input signal
93
–84
–84
dB
dB
–3 dB full-scale, 1-kHz input signal
–70
THD+ Total Harmonic Distortion plus
Noise
IN2R,IN3R routed to Right ADC
IN2L, IN3L routed to Left ADC
–3dB full-scale, 1-kHz input signal
N
AUDIO ADC (CM=0.75V)
Input signal level (for 0dB output) Single-ended, CM=0.75V, AVdd = 1.5V
0.375
VRMS
1kHz sine wave input
Single-ended Configuration
INR, IN2R, IN3R routed to Right ADC
INL, IN2L, IN3L routed to Left ADC
Rin = 20K, fs = 48kHz,
AOSR=128, MCLK = 256* fs,
Device Setup
PLL Disabled, AGC = OFF,
Channel Gain = 0dB,
Processing Block = PRB_R1
Power Tune = PTM_R4
SNR
DR
Signal-to-noise ratio, A-weighted Inputs ac-shorted to ground
90
dB
(1) (2)
Dynamic range A-weighted(1) (2) –60dB full-scale, 1-kHz input signal
90
dB
dB
THD+ Total Harmonic Distortion plus
Noise
–3dB full-scale, 1-kHz input signal
–81
N
(1) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
8
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Electrical Characteristics, ADC (continued)
At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge
pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC (Gain=40dB)
Input signal level (for 0dB output) Differential Input, CM=0.9V, Channel Gain=40dB
10
mVRMS
1kHz sine wave input
Differential configuration
IN1L and IN1R routed to Right ADC
IN2L and IN2R routed to Left ADC
Device Setup
Rin =10K, fs =48kHz, AOSR=128
MCLK = 256* fs PLL Disabled
AGC = OFF
Processing Block = PRB_R1,
Power Tune = PTM_R4
ICN
Idle-Channel Noise,
A-weighted(3) (4)
Inputs ac-shorted to ground, input referred noise
2.8
0.1
mVRMS
AUDIO ADC
1kHz sine wave input
dB
Single-ended configuration
Rin = 20K fs = 48kHz, AOSR=128,
MCLK = 256* fs, PLL Disabled
AGC = OFF, Channel Gain=0dB
Processing Block = PRB_R1,
Power Tune = PTM_R4, CM=0.9V
Gain Error
1kHz sine wave input at -3dBFS
Single-ended configuration
IN1L routed to Left ADC
IN1R routed to Right ADC, Rin = 20K
AGC = OFF, AOSR = 128,
109
108
dB
dB
Input Channel Separation
Input Pin Crosstalk
Channel Gain=0dB, CM=0.9V
1kHz sine wave input at –3dBFS on IN2L, IN2L internally
not routed.
IN1L routed to Left ADC
ac-coupled to ground
1kHz sine wave input at –3dBFS on IN2R,
IN2R internally not routed.
IN1R routed to Right ADC
ac-coupled to ground
Single-ended configuration Rin = 20K,
AOSR=128 Channel, Gain=0dB, CM=0.9V
217Hz, 100mVpp signal on AVdd,
Single-ended configuration, Rin=20K,
Channel Gain=0dB; CM=0.9V
55
dB
PSRR
Single-Ended, Rin = 10K, PGA gain set to 0dB
Single-Ended, Rin = 10K, PGA gain set to 47.5dB
Single-Ended, Rin = 20K, PGA gain set to 0dB
Single-Ended, Rin = 20K, PGA gain set to 47.5dB
Single-Ended, Rin = 40K, PGA gain set to 0dB
Single-Ended, Rin = 40K, PGA gain set to 47.5dB
1-kHz tone
0
47.5
–6
dB
dB
dB
dB
dB
dB
dB
ADC programmable gain
amplifier gain
41.5
–12
35.5
0.5
ADC programmable gain
amplifier step size
(3) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(4) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Bypass Outputs
At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge
pump disabled unless otherwise noted.
PARAMETER
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Load = 16Ω (single-ended), 50pF;
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input and Output CM=0.9V;
Device Setup
Headphone Output on DRVdd_HP Supply;
IN1L routed to HPL and IN1R routed to HPR;
Channel Gain=0dB
Gain Error
Noise, A-weighted(1)
0.8
3.3
dB
Idle Channel, IN1L and IN1R ac-shorted to
ground
mVRMS
THD
Total Harmonic Distortion
446mVrms, 1-kHz input signal
–81
dB
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Load = 10KOhm (single-ended), 50pF;
Input and Output CM=0.9V;
Device Setup
LINE Output on DRVdd_HP Supply;
IN1L, IN1R routed to line out
Channel Gain = 0dB
Gain Error Gain Error
0.8
6.7
dB
Idle Channel,
mVRMS
IN1L and IN1R ac-shorted to ground
Noise, A-weighted(1)
Channel Gain=40dB,
3
mVRMS
Input Signal (0dB) = 5mVrms
Inputs ac-shorted to ground, Input Referred
(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
10
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Electrical Characteristics, Microphone Interface
At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge
pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICROPHONE BIAS
Bias voltage
Bias voltage CM=0.9V, DRVdd_HP = 1.8V
Micbias Mode 0, Connect to AVdd or
DRVdd_HP
1.5
V
Micbias Mode 3, Connect to AVdd
Micbias Mode 3, Connect to DRVdd_HP
CM=0.75V, DRVdd_HP = 1.8V
AVdd
V
V
DRVdd_HP
Micbias Mode 0, Connect to AVdd or
DRVdd_HP
1.23
1.43
V
V
Micbias Mode 1, Connect to AVdd or
DRVdd_HP
Micbias Mode 3, Connect to AVdd
AVdd
V
V
Micbias Mode 3, Connect to DRVdd_HP
DRVdd_HP
MICROPHONE BIAS
Bias voltage
Bias voltage CM=0.9V, DRVdd_HP = 3.3V
Micbias Mode 0, Connect to DRVdd_HP
Micbias Mode 1, Connect to DRVdd_HP
Micbias Mode 2, Connect to DRVdd_HP
Micbias Mode 3, Connect to DRVdd_HP
CM=0.75V, DRVdd_HP = 3.3V
1.5
1.7
V
V
V
V
2.5
DRVdd_HP
Micbias Mode 0, Connect to DRVdd_HP
Micbias Mode 1, Connect to DRVdd_HP
Micbias Mode 2, Connect to DRVdd_HP
Micbias Mode 3, Connect to DRVdd_HP
1.23
1.43
V
V
V
V
2.1
DRVdd_HP
9.5
Output Noise
CM=0.9V, Micbias Mode 2, A-weighted, 20Hz
to 20kHz bandwidth,
mVRMS
Current load = 0mA.
Current Sourcing
Inline Resistance
Micbias Mode 2, Connect to DRVdd_HP
Micbias Mode 3, Connect to AVdd
Micbias Mode 3, Connect to DRVdd_HP
3
131
89
mA
Ω
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Electrical Characteristics, Audio DAC Outputs
At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge
pump disabled unless otherwise noted.
PARAMETER
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT (CM=0.9V)
Load = 10 kΩ (single-ended), 56pF
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Line Output on AVdd Supply
Input & Output CM=0.9V
Device Setup
DOSR = 128, MCLK=256* fs,
Channel Gain = 0dB, word length = 16 bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB)
Signal-to-noise ratio A-weighted(1) (2)
0.5
100
100
VRMS
dB
SNR
DR
All zeros fed to DAC input
87
(1) (2)
Dynamic range, A-weighted
–60dB 1kHz input full-scale signal, Word
length=20 bits
dB
THD+N Total Harmonic Distortion plus Noise
DAC Gain Error
–3dB full-scale, 1-kHz input signal
0 dB, 1kHz input full scale signal
Mute
–81
0.5
–70
dB
dB
dB
dB
DAC Mute Attenuation
121
108
DAC channel separation
–1 dB, 1kHz signal, between left and right HP
out
100mVpp, 1kHz signal applied to AVdd
100mVpp, 217Hz signal applied to AVdd
72
80
dB
dB
DAC PSRR
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT (CM=0.75V)
Load = 10 kΩ (single-ended), 56pF
Line Output on AVdd Supply
Input & Output CM=0.75V; AVdd=1.5V
DOSR = 128
Device Setup
MCLK=256* fs
Channel Gain = 0dB
word length = 20-bits
Processing Block = PRB_P1
Power Tune = PTM_P4
Full scale output voltage (0dB)
Signal-to-noise ratio, A-weighted
0.375
99
VRMS
dB
(1) (2)
SNR
DR
All zeros fed to DAC input
(1) (2)
Dynamic range, A-weighted
–60dB 1 kHz input full-scale signal
–1 dB full-scale, 1-kHz input signal
98
dB
THD+N Total Harmonic Distortion plus Noise
–77
dB
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (GROUND-CENTERED CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 56pF
Input CM=0.9V, Output CM=0V
DOSR = 128,
MCLK=256* fs, Channel Gain=0dB
word length = 16 bits;
Device Setup
Processing Block = PRB_P1
Power Tune = PTM_P3
FS1
Full scale output voltage (for THD ≤
0.65
VRMS
–40dB)
SNR
DR
Signal-to-noise ratio, A-weighted(1) (2)
All zeros fed to DAC input
85
95
93
dB
dB
(1) (2)
Dynamic range, A-weighted
–60dB 1kHz input full-scale signal, Word
Length = 20 bits, Power Tune = PTM_P4
THD+N Total Harmonic Distortion plus Noise
500mVRMS output (corresponds to FS1 –
2.3dB),
–70
–55
dB
1-kHz input signal
(1) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
12
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Electrical Characteristics, Audio DAC Outputs (continued)
At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge
pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
500mVRMS output, 1kHz input full scale signal
Mute
MIN
TYP
MAX
UNIT
DAC Gain Error
0.5
dB
DAC Mute Attenuation
DAC channel separation
118
102
dB
–3dB, 1kHz signal, between left and right HP
out
dB
100mVpp, 1kHz signal applied to AVdd
100mVpp, 217Hz signal applied to AVdd
THD ≤ –40dB
66
77
dB
dB
DAC PSRR
Power Delivered
26.5
mW
FS2
Full scale output voltage (for THD ≤
–40dB)
Load = 32Ω
0.85
V
SNR
Signal-to-noise ratio, A-weighted(1) (2)
All zeros fed to DAC input, Load = 32Ω
THD ≤ –40dB, Load = 32Ω
96
dB
Power Delivered
22.5
mW
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 56pF,
Headphone Output on AVdd Supply,
Input & Output CM=0.9V
Device Setup
DOSR = 128, MCLK=256* fs,
Channel Gain = 0dB
Processing Block = PRB_P1,
Power Tune = PTM_P3
Full scale output voltage (0dB)
Signal-to-noise ratio, A-weighted(3) (4)
0.5
100
100
–83
VRMS
dB
SNR
DR
All zeros fed to DAC input
87
(3) (4)
Dynamic range, A-weighted
-60dB 1 kHz input full-scale signal
–3dB full-scale, 1-kHz input signal
dB
THD+N Total Harmonic Distortion plus Noise
–70
dB
(3) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(4) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Misc.
At 25°C, AVdd, DVdd, IOVdd,DVdd_CP, DRVdd_HP = 1.8V, fs (Audio) = 48kHz, Cref = 1µF on REF PIN, PLL and Charge
pump disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
CMMode = 0 (0.9V)
0.9
0.75
1.1
Reference Voltage Settings
Reference Noise
V
CMMode = 1 (0.75V)
CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth,
mVRMS
Cref = 1mF
Decoupling Capacitor
Bias Current
1
mF
mA
120
miniDSP(1)
Maximum miniDSP clock frequency - ADC
Maximum miniDSP clock frequency - DAC
DVdd = 1.65V
DVdd = 1.65V
58.9
58.9
MHz
MHz
Shutdown Current
Device Setup
I(total)
DVdd is provided externally, no clocks supplied, no
digital activity, register values are retained
Sum of all supply currents, all supplies at 1.8V
<10
mA
(1) The miniDSP clock speed is specified by design and not tested in production.
Electrical Characteristics, Logic Levels
At 25°C, AVdd, DVdd, IOVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP
CMOS
MAX
UNIT
LOGIC FAMILY
VIH
Logic Level
IIH = 5 mA, IOVDD > 1.6V
0.7 × IOVDD
0.9 × IOVDD
IOVDD
V
V
IIH = 5mA, 1.2V ≤ IOVDD <1.6V
IIH = 5mA, IOVDD < 1.2V
IIL = 5 mA, IOVDD > 1.6V
IIL = 5mA, 1.2V ≤ IOVDD <1.6V
IIL = 5mA, IOVDD < 1.2V
IOH = 2 TTL loads
V
VIL
–0.3
0.3 × IOVDD
0.1 × IOVDD
0
V
V
V
VOH
VOL
0.8 × IOVDD
V
IOL = 2 TTL loads
0.1 × IOVDD
V
Capacitive Load
10
pF
14
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Interface Timing
Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
All specifications at 25°C, DVdd = 1.8V
WCLK
t (WS)
d
BCLK
t (DO-BCLK)
d
t (DO-WS)
d
DOUT
t (DI)
t (DI)
S
h
DIN
I2S/LJF Timing in Master Mode
Figure 4. I2S/LJF/RJF Timing in Master Mode
Table 3. I2S/LJF/RJF Timing in Master Mode (see Figure 4)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
MAX
MIN
MAX
td(WS)
WCLK delay
30
20
22
20
20
20
ns
ns
ns
ns
ns
ns
ns
td (DO-WS)
WCLK to DOUT delay (For LJF Mode only)
td (DO-BCLK)
BCLK to DOUT delay
DIN setup
ts(DI)
th(DI)
tr
8
8
8
8
DIN hold
Rise time
24
24
12
12
tf
Fall time
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WCLK
th(WS)
ts(WS)
tL(BCLK)
td(DO-WS)
tH(BCLK)
td(DO-BCLK)
BCLK
DOUT
DIN
th(DI)
ts(DI)
Figure 5. I2S/LJF/RJF Timing in Slave Mode
Table 4. I2S/LJF/RJF Timing in Slave Mode (see Figure 5)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
35
35
8
MAX
MIN
35
35
8
MAX
tH (BCLK)
tL (BCLK)
ts (WS)
th (WS)
td (DO-WS)
td (DO-BCLK)
ts(DI)
BCLK high period
ns
BCLK low period
WCLK setup
WCLK hold
8
8
WCLK to DOUT delay (For LJF mode only)
20
22
20
22
BCLK to DOUT delay
DIN setup
8
8
8
8
th(DI)
DIN hold
tr
Rise time
4
4
4
4
tf
Fall time
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Typical DSP Timing Characteristics
All specifications at 25°C, DVdd = 1.8V
WCLK
t (WS)
d
t (WS)
d
BCLK
DOUT
DIN
t (DO-BCLK)
d
t (DI)
h
t (DI)
s
Figure 6. DSP Timing in Master Mode
Table 5. DSP Timing in Master Mode (see Figure 6)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
MAX
MIN
MAX
td (WS)
WCLK delay
30
22
20
20
ns
ns
ns
ns
ns
ns
td (DO-BCLK)
BCLK to DOUT delay
DIN setup
ts(DI)
th(DI)
tr
8
8
8
8
DIN hold
Rise time
24
24
12
12
tf
Fall time
WCLK
t (ws)
h
t (ws)
t (ws)
h
s
t (ws)
h
t (BCLK)
L
BCLK
DOUT
DIN
t
(BCLK)
H
t (DO-BCLK)
d
t (DI)
h
t (DI)
s
Figure 7. DSP Timing in Slave Mode
Table 6. DSP Timing in Slave Mode (see Figure 7)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
35
35
8
MAX
MIN
35
35
8
MAX
tH (BCLK)
tL (BCLK)
ts(WS)
BCLK high period
BCLK low period
WCLK setup
WCLK hold
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(WS)
8
8
td (DO-BCLK)
BCLK to DOUT delay
DIN setup
22
22
ts(DI)
th(DI)
tr
8
8
8
8
DIN hold
Rise time
4
4
4
4
tf
Fall time
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I2C Interface Timing
Figure 8. I2C Interface Timing
Table 7. I2C Interface Timing
PARAMETER
TEST CONDITION
Standard-Mode
Fast-Mode
MIN TYP
UNITS
MIN
0
TYP
MAX
MAX
fSCL
SCL clock frequency
100
0
400
kHz
tHD;STA Hold time (repeated) START
condition. After this period, the first
clock pulse is generated.
4.0
0.8
ms
tLOW
tHIGH
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
1.3
0.6
0.8
ms
ms
ms
tSU;STA Setup time for a repeated START
condition
tHD;DAT Data hold time: For I2C bus
devices
0
3.45
0
0.9
ms
tSU;DAT Data set-up time
250
100
ns
ns
ns
ms
ms
tr
tf
SDA and SCL Rise Time
SDA and SCL Fall Time
1000 20+0.1Cb
300
300
300 20+0.1Cb
tSU;STO Set-up time for STOP condition
4.0
4.7
0.8
1.3
tBUF
Bus free time between a STOP
and START condition
Cb
Capacitive load for each bus line
400
400
pF
18
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
SPI Interface Timing
SS
t
td
tLag
t
tLead
sck
tf
tr
SCLK
MISO
tsckl
tsckh
tv
tdis
MSB OUT
thi
BIT 6 . . . 1
LSB OUT
t
a
tsu
MOSI
MSB IN
BIT 6 . . . 1
LSB IN
Figure 9. SPI Interface Timing Diagram
Timing Requirements (See Figure 9)
At 25°C, DVdd = 1.8V
Table 8. SPI Interface Timing
PARAMETER
TEST CONDITION
IOVDD=1.8V
IOVDD=3.3V
MIN TYP
UNITS
MIN
100
50
TYP MAX
MAX
tsck
tsckh
tsckl
tlead
tlag
td
SCLK Period(1)
50
25
25
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse width High
SCLK Pulse width Low
Enable Lead Time
50
30
Enable Lag Time
30
Sequential Transfer Delay
Slave DOUT access time
Slave DOUT disable time
DIN data setup time
DIN data hold time
40
ta
40
40
20
20
tdis
tsu
15
15
10
10
thi
tv;DOUT DOUT data valid time
25
4
18
4
tr
tf
SCLK Rise Time
SCLK Fall Time
4
4
(1) These parameters are based on characterization and are not tested in production.
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Typical Characteristics
Device Power Consumption
Device power consumption largely depends on PowerTune configuration. For information on device power
consumption, see the TLV320AIC3256 Application Reference Guide, literature number SLAU306.
Typical Performance
ADC SNR
vs
TOTAL HARMONIC DISTORTION GCHP CONFIGURATION
vs
CHANNEL GAIN
HEADPHONE OUTPUT POWER
100
95
90
85
80
75
70
65
60
0
R
= 10 kW, Differential
IN
-10
R
= 20 kW, Differential
IN
-20
-30
R
= 10 kW, Single Ended
IN
32W
-40
16W
R
= 20 kW, Single Ended
IN
-50
-60
-70
-80
55
50
-20
0
20
Channel Gain - dB
40
60
0
10
20
30
40
50
Headphone Output Power mW
Figure 10.
Figure 11.
TOTAL HARMONIC DISTORTION UNIPOLAR
CONFIGURATION
TOTAL HARMONIC DISTORTION
vs
vs
HEADPHONE OUTPUT POWER
HEADPHONE OUTPUT POWER
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
-60
-70
CM = 0.9 V,
32 W BTL Load
CM = 0.9 V,
= 32 W
CM = 1.65 V,
R = 32 W
L
R
= 16 W
R
L
L
GCHP Mode
DRVDD_HP = 1.8V
CM = 0.9 V
Unipolar Mode
DRVDD_HP = 3.3V
CM = 1.65 V
CM = 1.65 V,
= 16 W
R
L
-80
-90
-80
-90
0
50
100
150
200
0
20
40
60
80
Headphone Output Power - mW
Headphone Output Power - mW
Figure 12.
Figure 13.
20
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HEADPHONE SNR AND OUTPUT POWER
vs
OUTPUT COMMON MODE SETTING
105
100
95
60
50
SNR
90
40
30
20
10
0
85
80
Output Power
75
70
65
60
0
0.75
0.9
1.25
Output Common Mode Setting
1.5
1.65
Figure 14.
FFT
DAC PLAYBACK TO HEADPHONE FFT @ -1dBFS
(UNIPOLAR MODE)
SINGLE ENDED LINE INPUT TO ADC FFT @ -1dBr
vs
vs
FREQUENCY
FREQUENCY
0
-20
0
-20
DAC
ADC
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
-160
0
5000
10000
15000
20000
0
5000
10000
15000
20000
f - Frequency - Hz
f - Frequency - Hz
Figure 15.
Figure 16.
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DAC PLAYBACK TO HEADPHONE FFT @ -1dBFS
(GROUND-CENTERED MODE)
DAC PLAYBACK TO LINE-OUT FFT @ -1dBFS
vs
vs
FREQUENCY
FREQUENCY
0
0
-20
DAC
DAC
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5000
10000
15000
20000
0
5000
10000
15000
20000
f - Frequency - Hz
f - Frequency - Hz
Figure 17.
Figure 18.
LINE INPUT TO HEADPHONE FFT @ 446mVrms
(UNIPOLAR MODE)
LINE INPUT TO LINE-OUT FFT @ 446mVrms (PGA MODE)
vs
vs
FREQUENCY
FREQUENCY
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-140
-120
-140
0
5000
10000
15000
20000
0
5000
10000
15000
20000
f - Frequency - Hz
f - Frequency - Hz
Figure 19.
Figure 20.
22
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Typical Circuit Configuration
Host Processor
DOUT
Reset MCLK
SCL
SDA
BCLK WCLK DIN
0.1u
0.1u
1K
SPI_Select
MICBIAS
LOL
LOR
1k 1k 2.7k
4700p
TPA2012
Class D Amp
0.1u
0.1u
1K
0.1uF
4700p
IN1_R
IN1_L
MFP3/SCLK
MFP4/MISO
MFP5/GPIO
IOVDD
0.1uF
0.1uF
0.1uF
TLV320AIC3256
1.1...3.6V
IN2_L
AVDD
1.8...1.95V
IN2_R
MICDET
AVDD
DVDD
1k
1k
DVDD_CP
DRVDD_HP
FLY_P
10 uF
0.1uF
IN3_R
2.2 uF
X7R
IN3_L
FLY_N
GND_Sense
DVSS_
HPR
HPL
REF
AVSS
IOVSS
CP
DVSS
DVSS
VNEG
Headset_Mic
Earjack
Headset_Spkr_R
Headset_Spkr_L
Headset_Gnd
microphone
and headset
speakers
2.2 uF
X7R
1uF
Figure 21. Typical Circuit Configuration
APPLICATION OVERVIEW
The TLV320AIC3256 offers a wide range of configuration options. Figure 1 shows the basic functional blocks of
the device.
Device Connections
Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are Reset and the SPI_Select pin, which are HW control pins. Depending on the state of
SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Multifunction Pins.
Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
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Multifunction Pins
Table 9 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Table 9. Multifunction Pin Assignments
1
2
3
4
5
6
7
8
Pin Function
MCLK
BCLK
WCLK
DIN
MFP1
DOUT
MFP2
DMDIN/
MFP3/
SCLK
DMCLK/
MFP4/
MISO
GPIO
MFP5
A
B
C
D
E
F
PLL Input
S(1)
S(1) ,D(4)
S(2)
S(2)
S(2),D
E(5)
E
S(3)
S(3)
Codec Clock Input
I2S BCLK input
I2S BCLK output
I2S WCLK input
I2S WCLK output
E, D
E
G
H
I
I2S ADC word clock input
I2S ADC WCLK out
I2S DIN
E
E
E
E
E
E, D
J
I2S DOUT
E, D
E
K
K
K
L
General Purpose Output I
General Purpose Output II
General Purpose Output III
General Purpose Input I
General Purpose Input II
General Purpose Input III
INT1 output
E
E
L
E
L
E
E
E
E
E
E
M
N
Q
R
S
T
E
E
E
E
INT2 output
Secondary I2S BCLK input
Secondary I2S WCLK in
Secondary I2S DIN
Secondary I2S DOUT
Secondary I2S BCLK OUT
Secondary I2S WCLK OUT
Aux Clock Output
E
E
E
E
E
E
E
U
V
X
E
E
E
E
E
E
(1) S(1): The MCLK pin can be used to drive the PLL and Codec Clock inputs simultaneously
(2) S(2): The BCLK pin can be used to drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously
(3) S(3): The GPIO/MFP5 pin can be used to drive the PLL and Codec Clock inputs simultaneously
(4) D: Default Function
(5) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if GPIO/MFP5 has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)
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Analog Audio I/O
The analog I/O path of the TLV320AIC3256 features a large set of options for signal conditioning as well as
signal routing:
•
•
•
•
•
•
•
•
6 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration
2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
2 mixer amplifiers for analog bypass
2 low power analog bypass channels
Mute function
Channel-to-channel phase adjustment
Fast charge of ac-coupling capacitors
Anti thump
Analog Low Power Bypass
The TLV320AIC3256 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC
resources are required for such operation; this supports low-power operation during analog-bypass mode.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1_L to the
left headphone amplifier (HPL) and IN1_R to HPR.
ADC Bypass Using Mixer Amplifiers
In addition to the low-power bypass mode, there is a bypass mode that uses the programmable gain amplifiers of
the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified
and routed to the line or headphone outputs, fully bypassing the ADC and DAC.
To enable this mode, the mixer amplifiers are powered on via software command.
Headphone Output
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in
single-ended DC-coupled headphone configurations. An integral charge pump generates the negative supply
required to operate the headphone drivers in dc-coupled mode, where the common mode of the output signal is
made equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers
in dc-coupled (ground centered mode) eliminates the need for large dc-blocking capacitors.
HPL
HPR
GND_SENSE
Figure 22. TLV320AIC3256 Ground-Centered Headphone Output
Alternatively the headphone amplifier can also be operated in a unipolar circuit configuration using DC blocking
capacitors.
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Line Outputs
Line Out Amplifier Overview
The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in
the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the
analog input common-mode setting, or 1.65V. With output common-mode setting of 1.65V and DRVdd_HP
supply at 3.3V the line-level drivers can drive up to 1Vrms output signal. The line-level drivers can drive out a
mixed combination of DAC signal and attenuated ADC PGA signal. Signal mixing is register-programmable.
ADC
The TLV320AIC3256 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable
oversampling ratio, followed by a digital decimation filter. The ADC supports sampling rates from 8kHz to
192kHz. In order to provide optimal system power management, the stereo recording path can be powered up
one channel at a time, to support the case where only mono record capability is required.
The ADC path of the TLV320AIC3256 features a large set of options for signal conditioning as well as signal
routing:
•
•
•
•
•
•
•
•
2 ADCs
6 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration
2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
2 mixer amplifiers for analog bypass
2 low power analog bypass channels
Fine gain adjust of digital channels with 0.1 dB step size
Digital volume control with a range of -12 to +20dB
Mute function
In addition to the standard set of ADC features the TLV320AIC3256 also offers the following special functions:
•
•
•
•
Channel-to-channel phase adjustment
Fast charge of ac-coupling capacitors
Anti thump
Adaptive filter mode
ADC Processing
The TLV320AIC3256 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be
chosen from three different types, depending on the required frequency response, group delay and sampling
rate.
ADC Processing Blocks
The TLV320AIC3256 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy to balance power conservation
and signal-processing flexibility. Less signal-processing capability reduces the power consumed by the device.
Table 10 gives an overview of the available processing blocks of the ADC channel and their properties. The
Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
•
•
•
First-order IIR
Scalable number of biquad filters
Variable-tap FIR filter
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The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low-group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column
(RC) gives an approximate indication of power consumption.
Table 10. ADC Processing Blocks
Processing
Blocks
Channel
Decimation
Filter
1st Order
IIR Available
Number
BiQuads
FIR
Required
AOSR Value
Resource
Class
PRB_R1(1)
PRB_R2
PRB_R3
PRB_R4
PRB_R5
PRB_R6
PRB_R7
PRB_R8
PRB_R9
PRB_R10
PRB_R11
PRB_R12
PRB_R13
PRB_R14
PRB_R15
PRB_R16
PRB_R17
PRB_R18
Stereo
Stereo
Stereo
Right
A
A
A
A
A
A
B
B
B
B
B
B
C
C
C
C
C
C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0
5
0
0
5
0
0
3
0
0
3
0
0
5
0
0
5
0
No
No
128,64
128,64
128,64
128,64
128,64
128,64
64
6
8
8
3
4
4
3
4
4
2
2
2
3
4
4
2
2
2
25-Tap
No
Right
No
Right
25-Tap
No
Stereo
Stereo
Stereo
Right
No
64
20-Tap
No
64
64
Right
No
64
Right
20-Tap
No
64
Stereo
Stereo
Stereo
Right
32
No
32
25-Tap
No
32
32
Right
No
32
Right
25-Tap
32
(1) Default
For more detailed information see the Application Reference Guide, SLAU306
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DAC
The TLV320AIC3256 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter.
The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling
and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal
images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize
power dissipation and performance, the TLV320AIC3256 allows the system designer to program the
oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling
ratios for lower input data rates and lower oversampling ratios for higher input data rates.
The TLV320AIC3256 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320AIC3256 features many options for signal conditioning and signal routing:
•
2 headphone amplifiers
–
–
–
Ground-centered, bipolar operation or unipolar operation
Usable in single-ended or differential mode
Analog volume setting with a range of -6 to +14 dB
•
2 line-out amplifiers
–
–
Usable in single-ended or differential mode
Analog volume setting with a range of -6 to +29 dB
•
•
•
Digital volume control with a range of -63.5 to +24dB
Mute function
Dynamic range compression (DRC)
In addition to the standard set of DAC features the TLV320AIC3256 also offers the following special features:
•
•
•
Built in sine wave generation (beep generator)
Digital auto mute
Adaptive filter mode
DAC Processing Blocks — Overview
The TLV320AIC3256 implements signal processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy balancing power conservation
and signal processing flexibility. Less signal processing capability will result in less power consumed by the
device. Table 11 gives an overview over all available processing blocks of the DAC channel and their properties.
The Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
•
•
•
•
First-order IIR
Scalable number of biquad filters
3D – Effect
Beep Generator
The processing blocks are tuned for typical cases and can achieve high image rejection or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients. The Resource Class Column (RC)
gives an approximate indication of power consumption.
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Table 11. Overview – DAC Predefined Processing Blocks
Processing
Interpolation
Filter
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
Resource
Class
Block No.
PRB_P1(1)
PRB_P2
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
A
A
A
Stereo
Stereo
Stereo
Left
No
Yes
Yes
No
3
6
6
3
6
6
0
4
4
6
6
0
4
4
6
6
0
4
4
0
4
4
2
5
5
No
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
8
12
10
4
PRB_P3
PRB_P4
No
PRB_P5
Left
Yes
Yes
Yes
No
Yes
No
6
PRB_P6
Left
6
PRB_P7
Stereo
Stereo
Stereo
Stereo
Stereo
Left
No
6
PRB_P8
Yes
No
8
PRB_P9
No
8
PRB_P10
PRB_P11
PRB_P12
PRB_P13
PRB_P14
PRB_P15
PRB_P16
PRB_P17
PRB_P18
PRB_P19
PRB_P20
PRB_P21
PRB_P22
PRB_P23
PRB_P24
PRB_P25
Yes
Yes
Yes
No
Yes
No
10
8
No
3
Left
Yes
No
4
Left
No
4
Left
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
6
Left
4
Stereo
Stereo
Stereo
Left
No
3
Yes
No
6
4
No
2
Left
Yes
No
3
Left
2
Stereo
Stereo
Stereo
No
8
Yes
Yes
Yes
Yes
12
12
(1) Default
For more detailed information see the Application Reference Guide, SLAU306
Digital Audio I/O Interface
Audio data is transferred between the host processor and the TLV320AIC3256 via the digital audio data serial
interface, or audio bus. The audio bus on this device is very flexible, including left or right-justified data options,
support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation,
very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple
devices within a system directly.
The audio bus of the TLV320AIC3256 can be configured for left or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard PCM interfaces is supported within the TDM mode. These modes
are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27,
D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or Slave mode,
for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a
frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock
corresponds to the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various
word-lengths as well as to support the case when multiple TLV320AIC3256s may share the same audio bus.
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The TLV320AIC3256 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0,
Register 28.
The TLV320AIC3256 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen. This can be configured via Page 0, Register 29, D(3).
The TLV320AIC3256 further includes programmability (Page 0, Register 27, D0) to place the DOUT line into a
hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with
the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3256, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,
or when word-clock or bit-clocks are used in the system as general-purpose clocks.
Clock Generation and PLL
The TLV320AIC3256 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the
miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference
clocks on MCLK BCLK or GPIO, the TLV320AIC3256 also provides the option of using the on-chip PLL which
supports a wide range of fractional multiplication values to generate the required clocks. Starting from
CODEC_CLKIN the TLV320AIC3256 provides several programmable clock dividers to help achieve a variety of
sampling rates for ADC, DAC and clocks for the miniDSP .
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3256.
For more detailed information see the Application Reference Guide, SLAU306
Control Interfaces
The TLV320AIC3256 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low.
It is not recommended to change the state of SPI_SELECT during device operation.
I2C Control
The TLV320AIC3256 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
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SPI Control
In the SPI control mode, the TLV320AIC3256 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3256) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the Application Reference Guide, SLAU306
Power Supply
The device has an integrated charge pump. Using the device in ground-centered headphone configuration, it can
be conveniently supplied from a single 1.5V to 1.95V rail. It has separate power domains for digital IO, digital
core, analog core, charge-pump input and headphone drive, all of which can be connected together and be
supplied from one source. For improved power efficiency, the digital core voltage can range from 1.26V to 1.95V.
The IO voltage can be supplied in the range of 1.1V to 3.6V.
For more detailed information see the TLV320AIC3256Application Reference Guide, SLAU306
Device Special Functions
The following special functions are available to support advanced system requirements:
•
•
•
Headset detection
Interrupt generation
Flexible pin multiplexing
For more detailed information see the Application Reference Guide, SLAU306
Register Map Summary
Table 12. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO. REG. NO.
PAGE NO. REG. NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09-0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Page Select Register
1
Software Reset Register
2
Reserved Register
3
Reserved Register
4
Clock Setting Register 1, Multiplexers
Clock Setting Register 2, PLL P&R Values
Clock Setting Register 3, PLL J Values
Clock Setting Register 4, PLL D Values (MSB)
Clock Setting Register 5, PLL D Values (LSB)
Reserved Register
5
6
7
8
9-10
11
12
13
14
15
16
17
Clock Setting Register 6, NDAC Values
Clock Setting Register 7, MDAC Values
DAC OSR Setting Register 1, MSB Value
DAC OSR Setting Register 2, LSB Value
miniDSP_D Instruction Control Register 1
miniDSP_D Instruction Control Register 2
miniDSP_D Interpolation Factor Setting Register
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Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO. REG. NO.
PAGE NO. REG. NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39-41
42
43
44
45
46
47
48
49
50-51
52
53
54
55
56
57-59
60
61
62
63
64
65
66
67
68
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27-0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32-0x33
0x34
0x35
0x36
0x37
0x38
0x39-0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
Clock Setting Register 8, NADC Values
Clock Setting Register 9, MADC Values
ADC Oversampling (AOSR) Register
miniDSP_A Instruction Control Register 1
miniDSP_A Instruction Control Register 2
miniDSP_A Decimation Factor Setting Register
Reserved Register
Clock Setting Register 10, Multiplexers
Clock Setting Register 11, CLKOUT M divider value
Audio Interface Setting Register 1
Audio Interface Setting Register 2, Data offset setting
Audio Interface Setting Register 3
Clock Setting Register 12, BCLK N Divider
Audio Interface Setting Register 4, Secondary Audio Interface
Audio Interface Setting Register 5
Audio Interface Setting Register 6
Digital Interface Misc. Setting Register
Reserved Register
ADC Flag Register
DAC Flag Register 1
DAC Flag Register 2
Reserved Register
Sticky Flag Register 1
Interrupt Flag Register 1
Sticky Flag Register 2
Sticky Flag Register 3
Interrupt Flag Register 2
Interrupt Flag Register 3
INT1 Interrupt Control Register
INT2 Interrupt Control Register
Reserved Register
GPIO/MFP5 Control Register
DOUT/MFP2 Function Control Register
DIN/MFP1 Function Control Register
MISO/MFP4 Function Control Register
SCLK/MFP3 Function Control Register
Reserved Registers
DAC Signal Processing Block Control Register
ADC Signal Processing Block Control Register
miniDSP_A and miniDSP_D Configuration Register
DAC Channel Setup Register 1
DAC Channel Setup Register 2
Left DAC Channel Digital Volume Control Register
Right DAC Channel Digital Volume Control Register
Headset Detection Configuration Register
DRC Control Register 1
32
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Product Folder Link(s): TLV320AIC3256
TLV320AIC3256
www.ti.com
SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Table 12. Summary of Register Map (continued)
Decimal
PAGE NO. REG. NO.
Hex
DESCRIPTION
PAGE NO. REG. NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
69
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
DRC Control Register 2
DRC Control Register 3
Beep Generator Register 1
Beep Generator Register 2
Beep Generator Register 3
Beep Generator Register 4
Beep Generator Register 5
Beep Generator Register 6
Beep Generator Register 7
Beep Generator Register 8
Beep Generator Register 9
Reserved Register
70
71
72
73
74
75
76
77
78
79
80
81
ADC Channel Setup Register
82
ADC Fine Gain Adjust Register
83
Left ADC Channel Volume Control Register
Right ADC Channel Volume Control Register
ADC Phase Adjust Register
84
85
86
Left Channel AGC Control Register 1
Left Channel AGC Control Register 2
Left Channel AGC Control Register 3
Left Channel AGC Control Register 4
Left Channel AGC Control Register 5
Left Channel AGC Control Register 6
Left Channel AGC Control Register 7
Left Channel AGC Control Register 8
Right Channel AGC Control Register 1
Right Channel AGC Control Register 2
Right Channel AGC Control Register 3
Right Channel AGC Control Register 4
Right Channel AGC Control Register 5
Right Channel AGC Control Register 6
Right Channel AGC Control Register 7
Right Channel AGC Control Register 8
DC Measurement Register 1
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110-127
0
DC Measurement Register 2
Left Channel DC Measurement Output Register 1
Left Channel DC Measurement Output Register 2
Left Channel DC Measurement Output Register 3
Right Channel DC Measurement Output Register 1
Right Channel DC Measurement Output Register 2
Right Channel DC Measurement Output Register 3
0x6E-0x7F Reserved Register
0x00
0x01
0x02
0x03
Page Select Register
1
Power Configuration Register 1
Power Configuration Register 2
Playback Configuration Register 1
2
3
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TLV320AIC3256
SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
www.ti.com
Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO. REG. NO.
PAGE NO. REG. NO.
1
4
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x1A-0x22
0x1A-0x22
0x1A-0x22
0x2C
0x2C
0x2C
0x04
Playback Configuration Register 2
Reserved Register
1
5-8
9
0x05-0x08
0x09
1
Output Driver Power Control Register
Common Mode Control Register
1
10
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1
11
Over Current Protection Configuration Register
HPL Routing Selection Register
1
12
1
13
HPR Routing Selection Register
1
14
LOL Routing Selection Register
1
15
LOR Routing Selection Register
1
16
0x10
HPL Driver Gain Setting Register
1
17
0x11
HPR Driver Gain Setting Register
1
18
0x12
LOL Driver Gain Setting Register
1
19
0x13
LOR Driver Gain Setting Register
1
20
0x14
Headphone Driver Startup Control Register
Reserved Register
1
21
0x15
1
22
0x16
IN1L to HPL Volume Control Register
IN1R to HPR Volume Control Register
Mixer Amplifier Left Volume Control Register
Mixer Amplifier Right Volume Control Register
Reserved Register
1
23
0x17
1
24
0x18
1
25
0x19
1
26-50
51
0x1A-0x32
0x33
1
MICBIAS Configuration Register
1
52
0x34
Left MICPGA Positive Terminal Input Routing Configuration Register
Reserved Register
1
53
0x35
1
54
0x36
Left MICPGA Negative Terminal Input Routing Configuration Register
Right MICPGA Positive Terminal Input Routing Configuration Register
Reserved Register
1
55
0x37
1
56
0x38
1
57
0x39
Right MICPGA Negative Terminal Input Routing Configuration Register
Floating Input Configuration Register
Left MICPGA Volume Control Register
Right MICPGA Volume Control Register
ADC Power Tune Configuration Register
ADC Analog Volume Control Flag Register
DAC Analog Gain Control Flag Register
Reserved Register
1
58
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
1
59
1
60
1
61
1
62
1
63
1
64-70
71
0x40-0x46
0x47
1
Analog Input Quick Charging Configuration Register
Reserved Register
1
72-122
123
124
125
126-127
0
0x48-0x7A
0x7B
0x7C
0x7D
1
Reference Power-up Configuration Register
Charge Pump Control
1
1
Headphone Driver Configuration
1
0x7E-0x7F Reserved Register
26-34
26-34
26-34
44
0x00
Page Select Register
1-7
8-127
0
0x01-0x07
0x08-0x7F
0x00
Reserved.
ADC Coefficients Buffer-B C(0:255)
Page Select Register
44
1
0x01
DAC Adaptive Filter Configuration Register
Reserved
44
2-7
0x02-0x07
34
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Product Folder Link(s): TLV320AIC3256
TLV320AIC3256
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
Table 12. Summary of Register Map (continued)
Decimal
PAGE NO. REG. NO.
Hex
DESCRIPTION
PAGE NO. REG. NO.
44
8-127
0
0x2C
0x08-0x7F
DAC Coefficients Buffer-A C(0:29)
Page Select Register
Reserved.
45-52
0x2D-0x34 0x00
45-52
1-7
0x2D-0x34 0x01-0x07
0x2D-0x34 0x08-0x7F
45-52
8-127
0
DAC Coefficients Buffer-A C(30:255)
Page Select Register
Reserved.
62-70
0x3E-0x46
0x3E-0x46
0x3E-0x46
0x50-0x72
0x50-0x72
0x50-0x72
0x00
62-70
1-7
0x01-0x07
0x08-0x7F
0x00
62-70
8-127
0
DAC Coefficients Buffer-B C(0:255)
Page Select Register
Reserved.
80-114
80-114
80-114
152-186
152-186
152-186
1-7
0x01-0x07
0x08-0x7F
8-127
0
miniDSP_A Instructions
Page Select Register
Reserved.
0x98-0xBA 0x00
1-7
0x98-0xBA 0x01-0x07
0x98-0xBA 0x08-0x7F
8-127
miniDSP_D Instructions
Additional Package Data, YZK Package
Table 13.
Dim
Value
Unit
X max:
X min:
3499.00
3439.00
3229.00
3239.00
µm
Y max:
Y min:
Notes:
Step X:3509.00 x Y:3309.00 µm
Step -40µm + 30 µm=max
Step -40µm – 30 µm=min
µm
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SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010
www.ti.com
REVISION HISTORY
Changes from Revision initial (December 2010) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed "mV" to "mVRMS" for Input signal level units ....................................................................................................... 9
Changed Gain Error value from 0.7 to 0.8 ......................................................................................................................... 10
Changed Gain Error value from 0.5 to 0.8 ......................................................................................................................... 10
Changed Noise, Idle Channel value from 6.9 to 6.7 ........................................................................................................... 10
Changed Bias voltage, Micbias Mode 0 value from 1.25 to 1.23 ....................................................................................... 11
Changed Bias voltage, Micbias Mode 0 value from 1.25 to 1.23 ....................................................................................... 11
Changed DAC Gain Error value from 0.4 to 0.5 ................................................................................................................. 12
Changed DAC Gain Error value from 0.1 to 0.5 ................................................................................................................. 13
Changed DAC channel separation condition from –1dB to –3dB ...................................................................................... 13
Changed 10µF to 1µF in Reference Noise conditions statement ....................................................................................... 14
Deleted min value from Decoupling Capacitor, changed typ value from 10 to 1µF ........................................................... 14
Moved value from typ to min .............................................................................................................................................. 14
Moved value from typ to min .............................................................................................................................................. 14
Changed WCLK delay min from 14 to 30ns ....................................................................................................................... 15
36
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV320AIC3256IRSBR
TLV320AIC3256IRSBT
ACTIVE
ACTIVE
WQFN
WQFN
RSB
RSB
40
40
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV320AIC3256IRSBR
TLV320AIC3256IRSBT
WQFN
WQFN
RSB
RSB
40
40
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV320AIC3256IRSBR
TLV320AIC3256IRSBT
WQFN
WQFN
RSB
RSB
40
40
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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