TLV320AIC3262_15 [TI]
Ultralow Power Stereo Audio Codec;
| 型号： | TLV320AIC3262_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Ultralow Power Stereo Audio Codec |
| 文件： | 总65页 (文件大小：1259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV320AIC3262
www.ti.com
SLAS679 –DECEMBER 2011
Ultra Low Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Stereo
Class-D Speaker Amplifier
Check for Samples: TLV320AIC3262
1
FEATURES
•
Three Independent Digital Audio Serial
Interfaces
2
•
Stereo Audio DAC with 101dB SNR
2.7mW Stereo 48kHz DAC Playback
Stereo Audio ADC with 93dB SNR
5.6mW Stereo 48kHz ADC Record
8-192kHz Playback and Record
30mW DirectPathTM Headphone Driver
Eliminates Large Output DC-Blocking
Capacitors
–
TDM and mono PCM support on all Audio
Serial Interfaces
•
•
•
•
•
–
8-channel Input and Output on Audio Serial
Interface 1
•
Programmable PLL, plus Low-Frequency
Clocking
•
•
•
Programmable 12-Bit SAR ADC
SPI and I2C Control Interfaces
•
•
128mW Differential Receiver Output Driver
Stereo Class-D Speaker Drivers
4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP
(YZF) Package
–
–
1.7 W (8Ω , 5.5V, 10% THDN)
1.4 W (8Ω , 5.5V, 1% THDN)
AIC3262
APPLICATIONS
•
•
•
•
Stereo Line Outputs
•
•
•
•
•
•
•
•
•
•
•
Mobile Handsets
PowerTune™ - Adjusts Power vs. SNR
Extensive Signal Processing Options
Tablets/eBooks
Portable Navigation Devices (PND)
Portable Media Player (PMP)
Portable Gaming Systems
Portable Computing
Eight Single-Ended or 4 Fully-Differential
Analog Inputs
•
•
•
•
Stereo Digital and Analog Microphone Inputs
Low Power Analog Bypass Mode
Acoustic Echo Cancellation (AEC)
Active Noise Cancellation (ANC)
Noise Suppression (NS)
Speaker Protection
Asynchronous Sample Rate Conversion
Fully-programmable Enhanced miniDSP with
PurePathTM Studio Support
–
Extensive Algorithm Support for Voice and
Audio Applications
Advanced DSP algorithms
Three
Audio Buses
SAR
ADC
CP
8 SE /
4 Diff
Inputs
Receiver
DAC
ADC
ADC
Two
miniDSP
Engines
Mixer
Level
Control
Outputs
1.4 W
DAC
Stereo
Speaker
(Class-D)
ASRC
Mixer
PGA
2
I C/SPI Bus
PLL
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerTune is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TLV320AIC3262
SLAS679 –DECEMBER 2011
www.ti.com
DESCRIPTION
The TLV320AIC3262 (also referred to as the AIC3262) is a flexible, highly-integrated, low-power, low-voltage
stereo audio codec. The AIC3262 features digital microphone inputs and programmable outputs, PowerTune
capabilities, enhanced fully-programmable miniDSP, predefined and parameterizable signal processing blocks,
integrated PLL, and flexible audio interfaces. Extensive register-based control of power, input and output channel
configuration, gains, effects, pin-multiplexing and clocks are included, allowing the device to be precisely targeted
to its application.
LOL
-78...0dB
-6...29dB
(1-dB Steps)
Int.
Ref.
VREF_SAR
VBAT
VBAT
IN1L
RECP
RECM
IN1L/AUX1
IN1R/AUX2
TEMP
-78...0dB
SAR
ADC
LOR
TEMP
SENSOR
-78...0dB
6...30dB
(6-dB Steps)
IN1R
-78...0dB
-6dB
SPKLP
SPKLM
-12, -6, 0dB
LOL
SPR_IN
-78...0dB
–12, –6, 0dB
IN1L/AUX1
IN2L
–12, –6, 0dB
–12, –6, 0dB
–6 dB
-6...14dB
Vol. Ctrl.
AGC
DRC
)
(1-dB Steps
IN3L
ADC
Signal
Proc.
DAC
Signal
Proc.
HPL
Left
ADC
Left
DAC
+
–
tPL
IN4L
-78...0dB
0ꢀ47.5dB
(0.5-dB Steps)
Gain Adj.
–36...0dB
MAL
LOL
miniDSP
miniDSP
Dig Mixer
Volume
Audio
Interface
ASRC
Dig Mixer
Volume
HPVSS_SENSE
–36...0dB
MAR
LOR
HPR
0ꢀ47.5dB
(0.5-dB Steps)
Gain Adj.
-78...0dB
ADC
Signal
Proc.
DAC
Signal
Proc.
Right
ADC
Right–
DAC
–6 dB
tPR
IN4R
IN3R
+
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
Vol. Ctrl.
-12, -6, 0dB
-6...14dB
AGC
DRC
IN2R
)
(1-dB Steps
-78...0dB
IN1R/AUX2
LOR
-6dB
SPR_IN
SPKRP
SPKRM
Low Freq
Clocking
6...30dB
(6-dB Steps)
SPI_SELECT
RESET
SPI / I2C
Control Block
Digital Interrupt
Mic. Ctrl
Tertiary
Audio IF
Secondary
Audio IF
Primary
Audio Interface
PLL
MICDET
Detection
MICBIAS
Mic
Bias
Charge
Pump
MICBIAS_EXT
Supplies
Pin Muxing / Clock Routing
VREF_AUDIO
Ref
B0395-04
Figure 1. Simplified Block Diagram
2
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SLAS679 –DECEMBER 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The TLV320AIC3262 features two fully-programmable miniDSP cores that support application-specific algorithms
in the record and/or the playback path of the device. The miniDSP cores are fully software programmable.
Targeted miniDSP algorithms, such as active noise cancellation, acoustic echo cancellation or advanced DSP
filtering are loaded into the device after power-up.
Combined with the advanced PowerTune technology, the device can execute operations from 8kHz mono voice
playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC3262 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations which cover single-ended and differential setups, as well as
floating or mixing input signals. It also provides a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. One application of the digital signal processing blocks is removable of audible noise
that may be introduced by mechanical coupling, e.g. optical zooming in a digital camera. The record path can
also be configured as a stereo digital microphone Pulse Density Modulation (PDM) interface typically used at
64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects; headphone, line, receiver, and Class-D
speaker outputs; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The
playback path contains two high-power DirectPathTM headphone output drivers which eliminate the need for ac
coupling capacitors. A built in charge pump generates the negative supply for the ground centered headphone
drivers. These headphone output drivers can be configured in multiple ways, including stereo, and mono BTL. In
addition, playback audio can be routed to integrated stereo Class-D speaker drivers or a differential receiver
amplifier.
The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-
off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used
in a mobile environment. When used in a docked environment power consumption typically is less of a concern
while lowest possible noise is important. With PowerTune the TLV320AIC3262 can address both cases.
The required internal clock of the TLV320AIC3262 can be derived from multiple sources, including the MCLK1
pin, the MCLK2 pin, the BCLK1 pin, the BCLK2 pin, several general purpose I/O pins or the output of the internal
PLL, where the input to the PLL again can be derived from similar pins. Although using the internal fractional PLL
ensures the availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is
highly programmable and can accept available input clocks in the range of 512kHz to 50MHz. To enable even
lower clock frequencies, an integrated low-frequency clock multiplier can also be used as an input to the PLL.
The TLV320AIC3262 has a 12-bit SAR ADC converter that supports system voltage measurements. These
system voltage measurements can be sourced from three dedicated analog inputs (IN1L/AUX1, IN1R/AUX2, or
VBAT pins), or, alternatively, an on-chip temperature sensor that can be read by the SAR ADC.
The TLV320AIC3262 also features three full Digital Audio Serial Interfaces, each supporting I2S, DSP/TDM, RJF,
LJF, and mono PCM formats. This enables three simultaneous digital playback and record paths to three
independent digital audio buses or chips. Additionally, the general purpose interrupt pins can be used to connect
to a fourth digital audio bus, allowing the end system to easily switch in this fourth audio bus to one of the three
Digital Audio Serial Interfaces.
The device is available in the 4.81 mm x 4.81 mm x 0.625 mm 81-Ball WCSP (YZF) Package.
Copyright © 2011, Texas Instruments Incorporated
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SLAS679 –DECEMBER 2011
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Package and Signal Descriptions
Packaging/Ordering Information
OPERATING
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE
TLV320AIC3262IYZFT
TLV320AIC3262IYZFR
Tape and Reel, 250
Tape and Reel, 3000
TLV320AIC3262
WCSP-81
YZF
–40°C to 85°C
Pin Assignments
space
space
J
DVDD
GPIO1
DOUT3
DOUT2
GPI1
IOVSS
DVDD
WCLK1
DIN1
H
IOVDD
GPIO2
RESET
BCLK3
GPO1
DIN3
SDA
SCL
IOVDD
DIN2
DOUT1
BCLK2
BCLK1
MCLK1
SPI_SELECT
G
MCLK2
WCLK3
WCLK2
AVDD_18
F
VBAT
IOVSS
SPK_V
GPI4
GPI2
GPI3
DVSS
IN2R
IN3L
IN2L
IN3R
E
SPKRP
DVSS
AVSS2
AVSS3
AVSS1
AVSS
VREF
_AUDIO
HPVSS
_SENSE
VREF_SAR
AVDD1_18
RECP
D
C
SRVDD
SPKRM
SLVSS
SRVSS
SPKLM
SLVDD
LOR
IN4R
IN1R/AUX2
MICBIAS
IN1L/AUX1
MICBIAS
_EXT
AVDD4_18
AVDD2_18
LOL
IN4L
HVDD_18
B
A
CPFCP
CPVSS
HPL
RECM
MICDET
CPVDD_18
RECVDD_33
AVDD3_33
SPKLP
AVSS4
CPFCM
VNEG
HPR
RECVSS
9
8
7
6
5
4
3
2
1
P0044-07
Figure 2. WCSP-81 (YZF) Package Ball Assignments, Top View
4
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TLV320AIC3262
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SLAS679 –DECEMBER 2011
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package
WCSP (YZF)
BALL
NAME
I/O/P DESCRIPTION
LOCATION
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
AVDD3_33
RECVSS
RECVDD_33
HPR
P
P
3.3V Power Supply for Micbias
Receiver Driver Ground
P
3.3V Power Supply for Receiver Driver
Right Headphone Output
O
I/O
I/O
P
VNEG
Charge Pump Negative Supply
Charge Pump Flying Capacitor M terminal
Power Supply Input for Charge Pump
Analog Ground for Class-D
CPFCM
CPVDD_18
AVSS4
P
SPKLP
O
I/O
O
O
P
Left Channel P side Class-D Output
Headset Detection Pin
MICDET
RECP
Receiver Driver P side Output
Receiver Driver M side Output
Headphone Amp Power Supply
Left Headphone Output
RECM
HVDD_18
HPL
O
P
CPVSS
Charge Pump Ground
CPFCP
I/O
P
Charge Pump Flying Capacitor P Terminal
Left Channel Class-D Output Stage Power Supply
Left Channel Class-D Output Stage Ground
Analog Input 4 Left
SLVDD
SLVSS
P
IN4L
I
AVDD1_18
MICBIAS_EXT
MICBIAS
AVDD2_18
LOL
P
1.8V Analog Power Supply
O
O
P
Output Bias Voltage for Headset Microphone.
Output Bias Voltage for Microphone to be used for on-board Microphones
1.8V Analog Power Supply
O
P
Left Line Output
AVDD4_18
SPKLM
1.8V Analog Power Supply for Class-D
Left Channel M side Class-D Output
Right Channel M side Class-D Output
Analog Reference Filter Output
O
O
O
SPKRM
VREF_AUDIO
SAR ADC Voltage Reference Input or Internal SAR ADC Voltage Reference Bypass
Capacitor Pin
D2
VREF_SAR
I/O
Analog Input 1 Left, Auxiliary 1 Input to SAR ADC
(Special Function: Left Channel High Impedance Input for Capacitive Sensor
Measurement)
D3
IN1L/AUX1
I
Analog Input 1 Right, Auxiliary 2 Input to SAR ADC
(Special Function: Right Channel High Impedance Input for Capacitive Sensor
Measurement)
D4
IN1R/AUX2
I
D5
D6
D7
D8
D9
E1
E2
E3
E4
E5
E6
E7
IN4R
HPVSS_SENSE
LOR
I
I
Analog Input 4 Right
Headphone Ground Sense Terminal
Right Line Output
O
P
P
I
SRVSS
SRVDD
IN3R
Right Channel Class-D Output Stage Ground
Right Channel Class-D Output Stage Power Supply
Analog Input 3 Right
IN3L
I
Analog Input 3 Left
AVSS
P
P
P
P
P
Analog Ground
AVSS1
AVSS3
AVSS2
DVSS
Analog Ground
Analog Ground
Analog Ground
Digital Ground
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Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL
NAME
I/O/P DESCRIPTION
LOCATION
E8
E9
F1
F2
F3
F4
SPK_V
SPKRP
IN2L
P
O
I
Class-D Output Stage Power Supply (Connect to SRVDD through a Resistor)
Right Channel P side Class-D Output
Analog Input 2 Left
IN2R
I
Analog Input 2 Right
AVDD_18
DVSS
P
P
1.8V Analog Power Supply
Digital Ground
Multi Function Digital Input 3
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
F5
F6
F7
GPI3
GPI2
GPI4
I
I
I
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Secondary: (SPI_SELECT = 0)
I2C Address Bit 1 (I2C_ADDR0, LSB)
Multi Function Digital Input 2
Primary:
General Purpose Input
Secondary:
Audio Serial Data Bus 1 Data Input
Audio Serial Data Bus 1 Data Input (L2/R2 or L3/R3 or L4/R4)
Digital Microphone Data Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Multi Function Digital Input 4
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Secondary: (SPI_SELECT = 0)
I2C Address Bit 2 (I2C_ADDR1, MSB)
Digital I/O Buffer Ground
F8
F9
G1
IOVSS
VBAT
P
I
Battery Monitor Voltage Input
Master Clock Input 1
Primary:
MCLK1
I
Audio Serial Data Bus 2 Bit Clock
Secondary:
Audio Serial Data Bus 1 Data Input (L3/R3)
Audio Serial Data Bus 1 Data Output (L3/R3)
General Purpose Input
General Purpose Output
General CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
G2
BCLK2
I/O
INT1 Output
INT2 Output
General Clock Input
Low-Frequency Clock Input
6
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Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL
NAME
I/O/P DESCRIPTION
LOCATION
Primary:
Audio Serial Data Bus 2 Data Input
Secondary:
Digital Microphone Data Input
G3
DIN2
I
Audio Serial Data Bus 1 Data Input (L2/R2)
General Purpose Input
Low-Frequency Clock Input
Primary:
Audio Serial Data Bus 2 Word Clock
Secondary:
Audio Serial Data Bus 1 Data Input (L4/R4)
Audio Serial Data Bus 1 Data Output (L4/R4)
General Purpose Input
General Purpose Output
CLKOUT Output
G4
WCLK2
I/O
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Low-Frequency Clock Input
Primary:
Audio Serial Data Bus 3 Word Clock
Secondary:
G5
G6
WCLK3
I/O
General Purpose Output
General Purpose Input
Audio Serial Data Bus 1 Data Out (L4/R4)
Low-Frequency Clock Input
Primary:
Audio Serial Data Bus 3 Data Input
DIN3
I
Secondary:
Audio Serial Data Bus 1 Data Input (L3/R3)
Control Interface Select
G7
G8
SPI_SELECT
RESET
I
I
SPI_SELECT = ‘1’: SPI Interface selected
SPI_SELECT = ‘0’: I2C Interface selected
Active Low Reset
Master Clock 2
Primary:
Clock Input
G9
H1
MCLK2
BCLK1
I
Secondary:
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L3/R3 or L4/R4)
Low-Frequency Clock Input
Primary:
Audio Serial Data Bus 1 Bit Clock
Secondary:
I/O
General Clock Input
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Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL
NAME
I/O/P DESCRIPTION
LOCATION
Primary:
Audio Serial Data Bus 1 Data Output
Secondary:
Audio Serial Data Bus 1 Data Output (L1/R1)
H2
DOUT1
O
General Purpose Output
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
H3
H4
IOVDD
SCL
P
Digital I/O Buffer Supply
I2C Interface Serial Clock (SPI_SELECT = 0)
SPI interface mode chip-select signal (SPI_SELECT = 1)
I/O
I2C interface mode serial data input (SPI_SELECT = 0)
SPI interface mode serial data input (SPI_SELECT = 1)
H5
SDA
I/O
Multifunction Digital Output 1
Primary: (SPI_SELECT = 1)
Serial Data Output
Secondary: (SPI_SELECT = 0)
General Purpose Output
CLKOUT Output
H6
GPO1
O
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L2/R2 or L3/R3 or L4/R4)
Primary:
Audio Serial Data Bus 3 Bit Clock
Secondary:
H7
BCLK3
I/O
General Purpose Input
General Purpose Output
Low-Frequency Clock Input
Audio Serial Data Bus 1 Data Output (L3/R3)
Multi Function Digital IO 2
Outputs:
General Purpose Output
ADC MOD Clock Output For Digital Microphone
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L2/R2 or L3/R3 or L4/R4)
Audio Serial Data Bus 1 Bit Clock Output
ADC Word Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
H8
GPIO2
I/O
ADC Bit Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Inputs:
General Purpose Input
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L2/R2 or L3/R3 or L4/R4)
Audio Serial Data Bus 1 Bit Clock Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
8
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SLAS679 –DECEMBER 2011
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL
NAME
I/O/P DESCRIPTION
LOCATION
H9
IOVDD
P
I
Digital I/O Buffer Supply
Primary:
Audio Serial Data Bus 1 Data Input
Secondary:
Audio Serial Data Bus 1 Data Input (L1/R1)
J1
DIN1
General Clock Input
Digital Microphone Data Input
Primary:
Audio Serial Data Bus 1 Word Clock
J2
WCLK1
I/O
Secondary:
Low-Frequency Clock Input
General CLKOUT Output
1.8V Digital Power Supply
J3
J4
DVDD
IOVSS
P
P
Digital I/O Buffer Ground
Multifunction Digital Input 1
Primary: (SPI_SELECT = 1)
SPI Serial Clock
Secondary: (SPI_SELECT = 0)
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L2/R2 or L3/R3 or L4/R4)
General Clock Input
J5
GPI1
I
Low-Frequency Clock Input
General Purpose Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Primary:
Audio Serial Data Bus 2 Data Output
Secondary:
General Purpose Output
ADC MOD Clock Output
SAR ADC Interrupt
J6
DOUT2
O
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L2/R2)
Primary:
Audio Serial Data Bus 3 Data Output
Secondary:
General Purpose Output
J7
DOUT3
O
Audio Serial Data Bus 1 Data Output (L2/R2 or L3/R3)
Audio Serial Data Bus 1 Word Clock Output
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Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
WCSP (YZF)
BALL
NAME
I/O/P DESCRIPTION
LOCATION
Multi Function Digital IO 1
Outputs:
General Purpose Output
ADC MOD Clock Output
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Data Output (L3/R3 or L4/R4)
Audio Serial Data Bus 1 Word Clock Output
ADC Word Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
J8
GPIO1
I/O
ADC Bit Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Inputs:
General Purpose Input
Digital Microphone Data Input
Audio Serial Data Bus 1 Data Input (L3/R3 or L4/R4)
Audio Serial Data Bus 1 Word Clock Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
J9
DVDD
P
1.8V Digital Power Supply
10
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Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
V
AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18 to AVSS1, AVSS2, AVSS4, AVSS respectively(2)
–0.3 to 2.2
–0.3 to 3.9
–0.3 to 2.2
–0.3 to 3.9
–0.3 to 2.2
–0.3 to 2.2
–0.3 to 6.0
AVDD3_33 to AVSS3 and RECVDD_33 to RECVSS
DVDD to DVSS
V
V
IOVDD to IOVSS
V
HVDD_18 to AVSS
V
CPVDD_18 to CPVSS
SLVDD to SLVSS, SRVDD to SRVSS, SPK_V to SRVSS(3)
V
V
Digital Input voltage to ground
IOVSS – 0.3 to IOVDD +
0.3
V
Analog input voltage to ground
AVSS – 0.3 to AVDDx_18
+ 0.3
V
VBAT
–0.3 to 6
V
°C
Operating temperature range
Storage temperature range
Junction temperature (TJ Max)
Power dissipation
–40 to 85
–55 to 125
°C
105
°C
(TJ Max – TA)/ θJA
W
θJA Junction-to-ambient thermal resistance
39.1
0.1
°C/W
θJCtop Junction-to-case (top) thermal resistance
θJB Junction-to-board thermal resistance
WCSP-81 package
(YZF)
12.0
0.7
PsiJT Junction-to-top characterization parameter
PsiJB Junction-to-board characterization parameter
11.5
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) It's recommended to keep all AVDDx_18 supplies within ± 50 mV of each other.
(3) It's recommended to keep SLVDD, SRVDD, and SPK_V supplies within ± 50 mV of each other.
Recommended Operating Conditions
MIN NOM
MAX UNIT
AVDD1_18,
AVDD2_18,
AVDD4_18,
AVDD_18
Power Supply Voltage Range Referenced to AVSS1, AVSS2, AVSS4, AVSS
respectively(1) It is recommended to connect each
1.5
1.8
1.95
V
of these supplies to a single supply rail.
AVDD3_33 ,
RECVDD_33
Referenced to AVSS3 and RECVSS respectively
1.65(2)
3.3
3.6
IOVDD
Referenced to IOVSS(1)
Referenced to DVSS(1)
1.1
1.26
3.6
1.95
1.95
1.95
DVDD(3)
CPVDD_18
HVDD_18
1.8
1.8
1.8
(1)
Power Supply Voltage Range Referenced to CPVSS
1.26
1.5(2)
V
V
Referenced to AVSS(1)
Ground-centered
Configuration
Unipolar
Configuration
1.65(2)
2.7
3.6
5.5
SLVDD(1)
Power Supply Voltage Range Referenced to SLVSS(1)
(1) All grounds on board are tied together, so they should not differ in voltage by more than 0.1V max, for any combination of ground
signals. AVDDx_18 are within +/- 0.05 V of each other. SLVDD, SRVDD, and SPK_V are within +/- 0.05 V of each other.
(2) Minimum voltage for HVDD_18 and RECVDD_33 should be greater than or equal to AVDD2_18. Minimum voltage for AVDD3_33
should be greater than or equal to AVDD1_18 and AVDD2_18.
(3) At DVDD values lower than 1.65V, the PLL does not function. Please see table in SLAU309, Maximum TLV320AIC3262 Clock
Frequencies for details on maximum clock frequencies.
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MAX UNIT
Recommended Operating Conditions (continued)
MIN NOM
SRVDD(1)
SPK_V(1)
Power Supply Voltage Range Referenced to SRVSS(1)
Power Supply Voltage Range Referenced to SRVSS(1)
2.7
2.7
5.5
5.5
V
V
V
VREF_SAR
External voltage reference for Referenced to AVSS
SAR
1.8 AVDDx_18
PLL Input Frequency(4)
Clock divider uses fractional divide
10
20 MHz
20 MHz
(D > 0), P=1, PLL_CLKIN_DIV=1, DVDD ≥ 1.65V
(Refer to table in SLAU309, Maximum
TLV320AIC3262 Clock Frequencies)
Clock divider uses integer divide
0.512
(D = 0), P=1, PLL_CLKIN_DIV=1, DVDD ≥ 1.65V
(Refer to table in SLAU309, Maximum
TLV320AIC3262 Clock Frequencies)
MCLK
Master Clock Frequency
SCL Clock Frequency
MCLK; Master Clock Frequency; IOVDD ≥ 1.65V
MCLK; Master Clock Frequency; IOVDD ≥ 1.1V
50 MHz
33
SCL
400 kHz
kΩ
LOL, LOR
Stereo line output load
resistance
0.6
14.4
7.2
10
16
8
HPL, HPR
Stereo headphone output load Single-ended configuration
resistance
Ω
Ω
SPKLP-
SPKLM,
SPKRP-
SPKRM
Speaker output load
resistance
Differential
RECP-RECM Receiver output resistance
Differential
24.4
32
10
Ω
CIN
Charge pump input capacitor
(CPVDD to CPVSS terminals)
µF
CO
Charge pump output capacitor Type X7R
(VNEG terminal)
2.2
2.2
µF
µF
CF
Charge pump flying capacitor Type X7R
(CPFCP to CPFCM terminals)
TOPR
Operating Temperature Range
–40
85
°C
(4) The PLL Input Frequency refers to clock frequency after PLL_CLKIN_DIV divider. Frequencies higher than 20MHz can be sent as an
input to this PLL_CLKIN_DIV and reduced in frequency prior to input to the PLL.
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Electrical Characteristics, SAR ADC
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
SAR ADC Inputs
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog
Input
Input voltage range
0
VREF_SAR
V
(1)
Input impedance
IN1L/AUX1 or IN1R/AUX2 Selected
1 ÷ (f×CSAR_IN
)
kΩ
pF
µA
V
Input capacitance, CSAR_IN
Input leakage current
VBAT Input voltage range
25
1
Battery
Input
2.2
5.5
VBAT Input impedance
VBAT Input capacitance
VBAT Input leakage current
5
25
1
kΩ
pF
µA
VBAT (Battery measurement) selected
SAR ADC Conversion
Resolution
Programmable: 8-bit, 10-bit, 12-bit
12-bit resolution
8
12
Bits
Bits
LSB
No missing codes
Integral linearity
11
±1
IN1L/
AUX1
12-bit resolution, SAR ADC clock =
Internal Oscillator Clock, Conversion
clock = Internal Oscillator / 4, External
Reference = 1.8V(2)
Offset error
Gain error
Noise
±1
0.07
±1
LSB
%
DC voltage applied to IN1L/AUX1 = 1 V,
SAR ADC clock = Internal Oscillator
Clock, Conversion clock = Internal
Oscillator / 4, External Reference =
1.8V(3)(2)
LSB
VBAT
Accuracy
Offset error
Gain error
Noise
12-bit resolution, SAR ADC clock =
Internal Oscillator Clock, Conversion
clock = Internal Oscillator / 4, Internal
Reference = 1.25V
2
±2
%
LSB
%
1.5
DC voltage applied to VBAT = 3.6 V, 12-
bit resolution, SAR ADC clock = Internal
Oscillator Clock, Conversion clock =
Internal Oscillator / 4, Internal Reference
= 1.25V
±0.5
LSB
Conversion Rate
Normal conversion operation
12-bit resolution, SAR ADC clock = 12
MHz External Clock, Conversion clock =
External Clock / 4, External Reference =
1.8V(2). With Fast SPI reading of data.
119
250
kHz
kHz
High-speed conversion
operation
8-bit resolution,SAR ADC clock = 12
MHz External Clock, Internal Conversion
clock = External Clock (Conversion
accuracy is reduced.), External
Reference = 1.8V(2). With Fast SPI
reading of data.
Voltage Reference - VREF_SAR
Voltage range
Internal VREF_SAR
External VREF_SAR
CM=0.9V, Cref = 1μF
1.25±0.05
V
V
1.25
AVDDx_18
Reference Noise
32
1
μVRMS
μF
Decoupling Capacitor
(1) SAR input impedance is dependent on the sampling frequency (f designated in Hz), and the sampling capacitor is CSAR_IN = 25pF.
(2) When utilizing External SAR reference, this external reference should be restricted VEXT_SAR_REF≤AVDD_18 and AVDD2_18.
(3) Noise from external reference voltage is excluded from this measurement.
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Electrical Characteristics, ADC
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(1) (2)
AUDIO ADC (CM = 0.9V)
Input signal level (0dB)
Single-ended, CM = 0.9V
0.5
VRMS
1kHz sine wave input, Single-ended Configuration
IN2R to Right ADC and IN2L to Left ADC, Rin = 20kΩ, fs = 48kHz,
AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF,
Channel Gain = 0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4
Device Setup
Inputs ac-shorted to ground
85
93
93
IN1R, IN3R, IN4R each exclusively routed in separate tests to Right
ADC and ac-shorted to ground
Signal-to-noise ratio, A-
weighted(1) (2)
SNR
DR
dB
dB
IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
ADC and ac-shorted to ground
Dynamic range A-
weighted(1) (2)
–60dB full-scale, 1-kHz input signal
93
–3 dB full-scale, 1-kHz input signal
–87
–87
–70
dB
IN1R,IN3R, IN4R each exclusively routed in separate tests to Right
ADC
Total Harmonic
Distortion plus Noise
THD+N
IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
ADC
–3dB full-scale, 1-kHz input signal
1kHz sine wave input at -3dBFS, Single-ended configuration
Rin = 20K fs = 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled
AGC = OFF, Channel Gain=0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4, CM=0.9V
0.1
dB
Gain Error
1kHz sine wave input at -3dBFS, Single-ended configuration
IN1L routed to Left ADC, IN1R routed to Right ADC, Rin = 20K
AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V
110
116
dB
dB
Input Channel
Separation
1kHz sine wave input at –3dBFS on IN2L, IN2L internally not routed.
IN1L routed to Left ADC, ac-coupled to ground
Input Pin Crosstalk
1kHz sine wave input at –3dBFS on IN2R, IN2R internally not
routed.
IN1R routed to Right ADC, ac-coupled to ground
Single-ended configuration Rin = 20kΩ, AOSR=128 Channel
Gain=0dB, CM=0.9V
217Hz, 100mVpp signal on AVDD_18, AVDDx_18
Single-ended configuration, Rin=20kΩ, Channel Gain=0dB;
CM=0.9V
59
dB
PSRR
(1) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with pre-analyzer 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, ADC (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO ADC (CM = 0.75V)
Input signal level (0dB)
Single-ended, CM=0.75V, AVDD_18, AVDDx_18 = 1.5V
0.375
VRMS
1kHz sine wave input, Single-ended Configuration
IN2R to Right ADC and IN2L to Left ADC, Rin = 20K, fs = 48kHz,
AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF,
Channel Gain = 0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4
Device Setup
SNR
DR
Signal-to-noise ratio, A- Inputs ac-shorted to ground
91
91
dB
dB
(3) (4)
weighted
IN1R, IN3R, IN4R each exclusively routed in separate tests to Right
ADC and ac-shorted to ground
IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
ADC and ac-shorted to ground
Dynamic range A-
weighted(3) (4)
–60dB full-scale, 1-kHz input signal
91
dB
dB
THD+N Total Harmonic
Distortion plus Noise
–3dB full-scale, 1-kHz input signal
–85
(3) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(4) All performance measurements done with pre-analyzer 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, ADC (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO ADC (Differential Input, CM = 0.9V)
Input signal level (0dB)
Differential, CM=0.9V, AVDD_18, AVDDx_18 = 1.8V
1
VRMS
1kHz sine wave input, Differential Configuration
IN1L, IN1R Routed to Right ADC, IN2L, IN2R Routed to Left ADC
Rin = 20kΩ, fs = 48kHz, AOSR=128, MCLK = 256* fs,
PLL Disabled, AGC = OFF, Channel Gain = 0dB,
Processing Block = PRB_R1, Power Tune = PTM_R4
Device Setup
SNR
DR
Signal-to-noise ratio, A- Inputs ac-shorted to ground
weighted
94
94
dB
dB
dB
dB
(5) (6)
Dynamic range A-
weighted(5) (6)
–60dB full-scale, 1-kHz input signal
–3dB full-scale, 1-kHz input signal
THD+N Total Harmonic
Distortion plus Noise
–88
0.1
1kHz sine wave input at -3dBFS, Differential configuration
Rin = 20kΩ, fs = 48kHz, AOSR=128, MCLK = 256* fs, PLL Disabled
AGC = OFF, Channel Gain=0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4, CM=0.9V
Gain Error
1kHz sine wave input at -3dBFS, Differential configuration
IN1L/IN1R differential signal routed to Right ADC,
IN2L/IN2R differential signal routed to Left ADC, Rin = 20kΩ
AGC = OFF, AOSR = 128, Channel Gain=0dB, CM=0.9V
107
109
dB
dB
Input Channel
Separation
1kHz sine wave input at –3dBFS on IN2L/IN2R, IN2L/IN2R internally
not routed.
Input Pin Crosstalk
IN1L/IN1R differentially routed to Right ADC, ac-coupled to ground
1kHz sine wave input at –3dBFS on IN2L/IN2R, IN2L/IN2R internally
not routed.
IN3L/IN3R differentially routed to Left ADC, ac-coupled to ground
Differential configuration Rin = 20kΩ, AOSR=128 Channel Gain=0dB,
CM=0.9V
217Hz, 100mVpp signal on AVDD_18, AVDDx_18
Differential configuration, Rin=20K, Channel Gain=0dB; CM=0.9V
59
dB
PSRR
AUDIO ADC
IN1 - IN3, Single-Ended, Rin = 10K, PGA gain set to 0dB
IN1 - IN3, Single-Ended, Rin = 10K, PGA gain set to 47.5dB
IN1 - IN3, Single-Ended, Rin = 20K, PGA gain set to 0dB
IN1 - IN3, Single-Ended, Rin = 20K, PGA gain set to 47.5dB
IN1 - IN3, Single-Ended, Rin = 40K, PGA gain set to 0dB
IN1 - IN3, Single-Ended, Rin = 40K, PGA gain set to 47.5dB
IN4, Single-Ended, Rin = 20K, PGA gain set to 0dB
0
47.5
–6
dB
dB
dB
dB
dB
dB
dB
dB
dB
41.5
–12
35.5
–6
ADC programmable gain
amplifier gain
IN4, Single-Ended, Rin = 20K, PGA gain set to 47.5dB
41.5
0.5
ADC programmable gain 1-kHz tone
amplifier step size
(5) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(6) All performance measurements done with pre-analyzer 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Bypass Outputs
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO RECEIVER AMPLIFIER, DIRECT MODE
Load = 32Ω (differential), 56pF;
Input CM=0.9V; Output CM=1.65V;
IN1L routed to RECP and IN1R routed to
RECM;
Device Setup
Channel Gain=0dB
Full scale differential input voltage (0dB)
Gain Error
Noise, A-weighted(1)
1
0.5
13
VRMS
dB
707mVrms (-3dBFS), 1-kHz input signal
Idle Channel, IN1L and IN1R ac-shorted to
ground
μVRMS
THD+N Total Harmonic Distortion plus Noise
707mVrms (-3dBFS), 1-kHz input signal
–88
dB
ANALOG BYPASS TO HEADPHONE AMPLIFIER, PGA MODE
Load = 16Ω (single-ended), 56pF; HVDD_18
= 3.3V
Input CM=0.9V; Output CM=1.65V
Device Setup
IN1L routed to ADCPGA_L, ADCPGA_L
routed through MAL to HPL; and IN1R routed
to ADCPGA_R, ADCPGA_R routed through
MAR to HPR; Rin = 20K; Channel Gain = 0dB
Full scale input voltage (0dB)
Gain Error
Noise, A-weighted(1)
0.5
–1.2
6
VRMS
dB
446mVrms (-1dBFS), 1-kHz input signal
Idle Channel, IN1L and IN1R ac-shorted to
ground
μVRMS
THD+N Total Harmonic Distortion plus Noise
446mVrms (-1dBFS), 1-kHz input signal
–81
dB
ANALOG BYPASS TO HEADPHONE AMPLIFIER (GROUND-CENTERED CIRCUIT CONFIGURATION), PGA MODE
Load = 16Ω (single-ended), 56pF;
Input CM=0.9V;
IN1L routed to ADCPGA_L, ADCPGA_L
Device Setup
routed through MAL to HPL; and IN1R routed
to ADCPGA_R, ADCPGA_R routed through
MAR to HPR; Rin = 20K; Channel Gain = 0dB
Full scale input voltage (0dB)
Gain Error
Noise, A-weighted(1)
0.5
–1.0
11
VRMS
dB
446mVrms (-1dBFS), 1-kHz input signal
Idle Channel, IN1L and IN1R ac-shorted to
ground
μVRMS
THD+N Total Harmonic Distortion plus Noise
446mVrms (-1dBFS), 1-kHz input signal
–67
dB
(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Bypass Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Load = 10KOhm (single-ended), 56pF;
Input and Output CM=0.9V;
IN1L routed to ADCPGA_L and IN1R routed
to ADCPGA_R; Rin = 20k
Device Setup
ADCPGA_L routed through MAL to LOL and
ADCPGA_R routed through MAR to LOR;
Channel Gain = 0dB
Full scale input voltage (0dB)
Gain Error
0.5
–0.7
6
VRMS
dB
446mVrms (-1dBFS), 1-kHz input signal
Idle Channel,
μVRMS
IN1L and IN1R ac-shorted to ground
(2)
Noise, A-weighted
Channel Gain=40dB,
3
μVRMS
Inputs ac-shorted to ground, Input Referred
ANALOG BYPASS TO LINE-OUT AMPLIFIER, DIRECT MODE
Load = 10KOhm (single-ended), 56pF;
Input and Output CM=0.9V;
IN1L routed to LOL and IN1R routed to LOR;
Channel Gain = 0dB
Device Setup
Full scale input voltage (0dB)
Gain Error
0.5
–0.3
3
VRMS
dB
446mVrms (-1dBFS), 1-kHz input signal
Idle Channel,
IN1L and IN1R ac-shorted to ground
μVRMS
Noise, A-weighted(2)
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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SLAS679 –DECEMBER 2011
Electrical Characteristics, Microphone Interface
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
MICROPHONE BIAS (MICBIAS or MICBIAS_EXT)
Bias voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
CM=0.9V, AVDD3_33 = 1.8V
Micbias Mode 0
1.63
V
V
Micbias Mode 3
AVDD3_33
CM=0.75V, AVDD3_33 = 1.8V
Micbias Mode 0
1.36
V
V
Micbias Mode 3
AVDD3_33
MICROPHONE BIAS (MICBIAS or MICBIAS_EXT)
Bias voltage
CM=0.9V, AVDD3_33 = 3.3V
Micbias Mode 0
1.63
2.36
V
V
V
V
Micbias Mode 1
Micbias Mode 2
2.91
Micbias Mode 3
AVDD3_33
CM=0.75V, AVDD3_33 = 3.3V
Micbias Mode 0
1.36
1.97
V
Micbias Mode 1
V
V
Micbias Mode 2
2.42
Micbias Mode 3
AVDD3_33
26
V
Output Noise
CM=0.9V, Micbias Mode 2, A-weighted, 20Hz
to 20kHz bandwidth,
Current load = 0mA.
μVRMS
184
nV/√Hz
Current Sourcing
Micbias Mode 0 (CM=0.9V)(1)
3
7
mA
mA
Micbias Mode 1 or Micbias Mode 2
(CM=0.9V)(2)
Inline Resistance
Micbias Mode 3
63.6
Ω
(1) To provide 3mA, Micbias Mode 0 voltage yields typical voltage of 1.60V for Common Mode of 0.9V.
(2) To provide 7mA, Micbias Mode 1 voltage yields typical voltage of 2.31V, and Micbias Mode 2 voltage yields typical voltage of 2.86V for
Common Mode of 0.9V.
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Electrical Characteristics, Audio DAC Outputs
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Load = 10 kΩ (single-ended), 56pF
Input & Output CM=0.9V
DOSR = 128, MCLK=256* fs,
Channel Gain = 0dB,
Device Setup
Processing Block = PRB_P1,
Power Tune = PTM_P4
Full scale output voltage (0dB)
Signal-to-noise ratio A-weighted(1) (2) All zeros fed to DAC input
0.5
101
101
VRMS
dB
SNR
DR
85
(1) (2)
Dynamic range, A-weighted
–60dB 1kHz input full-scale signal, Word length=20
dB
bits
THD+N
Total Harmonic Distortion plus Noise
DAC Gain Error
–3dB full-scale, 1-kHz input signal
–3dB full-scale, 1-kHz input signal
Mute
–88
0.1
119
108
71
dB
dB
dB
dB
dB
DAC Mute Attenuation
DAC channel separation
–1 dB, 1kHz signal, between left and right Line out
100mVpp, 1kHz signal applied to AVDD_18,
AVDDx_18
DAC PSRR
100mVpp, 217Hz signal applied to AVDD_18,
AVDDx_18
71
dB
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Load = 10 kΩ (single-ended), 56pF
Input & Output CM=0.75V; AVDD_18, AVDDx_18,
HVDD_18=1.5V
DOSR = 128
MCLK=256* fs
Device Setup
Channel Gain = 0dB
Processing Block = PRB_P1
Power Tune = PTM_P4
Full scale output voltage (0dB)
0.375
99
VRMS
dB
(1)
SNR
DR
Signal-to-noise ratio, A-weighted
All zeros fed to DAC input
(2)
–60dB 1 kHz input full-scale signal, Word length=20
bits
99
dB
dB
(1) (2)
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
–3 dB full-scale, 1-kHz input signal
–88
(1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Audio DAC Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO DAC – MONO DIFFERENTIAL LINE OUTPUT
Load = 10 kΩ (differential), 56pF
Input & Output CM=0.9V, LOL signal routed to LOR
amplifier
DOSR = 128, MCLK=256* fs,
Device Setup
Channel Gain = 0dB,
Processing Block = PRB_P1,
Power Tune = PTM_P4
Full scale output voltage (0dB)
Signal-to-noise ratio A-weighted(3) (4) All zeros fed to DAC input
1
101
101
–86
0.1
97
VRMS
dB
SNR
DR
(3) (4)
Dynamic range, A-weighted
Total Harmonic Distortion plus Noise
DAC Gain Error
–60dB 1kHz input full-scale signal,
–3dB full-scale, 1-kHz input signal
–3dB full-scale, 1-kHz input signal
Mute
dB
THD+N
dB
dB
DAC Mute Attenuation
dB
100mVpp, 1kHz signal applied to AVDD_18,
AVDDx_18
62
dB
DAC PSRR
100mVpp, 217Hz signal applied to AVDD_18,
AVDDx_18
63
dB
(3) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(4) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Audio DAC Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (GROUND-CENTERED CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 56pF,
Input CM=0.9V;
DOSR = 128, MCLK=256* fs,
Device Setup
Channel Gain = 0dB,
Processing Block = PRB_P1,
Power Tune = PTM_P3,
Headphone Output Strength=100%
Output 1 Output voltage
0.5
94
VRMS
dB
(5)
SNR
Signal-to-noise ratio, A-weighted
All zeros fed to DAC input
80
(6)
(5) (6)
DR
Dynamic range, A-weighted
–60dB 1 kHz input full-scale signal
–3dB full-scale, 1-kHz input signal
–3dB, 1kHz input full scale signal
Mute
93
–71
–0.2
92
dB
THD+N
Total Harmonic Distortion plus Noise
DAC Gain Error
–55
dB
dB
dB
dB
dB
DAC Mute Attenuation
DAC channel separation
–3dB, 1kHz signal, between left and right HP out
83
100mVpp, 1kHz signal applied to AVDD_18,
AVDD1x_18
55
DAC PSRR
100mVpp, 217Hz signal applied to AVDD_18,
AVDD1x_18
55
15
dB
Power Delivered
THDN ≤ -40dB, Load = 16Ω
mW
Output 2 Output voltage
SNR
Load = 16Ω (single-ended), Channel Gain = 5dB
Signal-to-noise ratio, A-weighted(5) (6) All zeros fed to DAC input, Load = 16Ω
0.8
96
24
VRMS
dB
Power Delivered
THDN ≤ -40dB, Load = 16Ω
mW
Output 3 Output voltage
SNR
Load = 32Ω (single-ended), Channel Gain = 5dB
Signal-to-noise ratio, A-weighted(5) (6) All zeros fed to DAC input, Load = 32Ω
0.9
97
22
VRMS
dB
Power Delivered THDN ≤ -40dB, Load = 32Ω
mW
(5) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(6) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Audio DAC Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 56pF
Input & Output CM=0.9V, DOSR = 128,
MCLK=256* fs, Channel Gain=0dB
Processing Block = PRB_P1
Device Setup
Power Tune = PTM_P4
Headphone Output Control = 100%
Full scale output voltage (0dB)
Signal-to-noise ratio, A-weighted(7) (8) All zeros fed to DAC input
0.5
100
100
VRMS
dB
SNR
DR
(7) (8)
Dynamic range, A-weighted
–60dB 1kHz input full-scale signal, Power Tune =
dB
PTM_P4
THD+N
Total Harmonic Distortion plus Noise
DAC Gain Error
–3dB full-scale, 1-kHz input signal
–3dB, 1kHz input full scale signal
Mute
–79
–0.2
119
88
dB
dB
dB
dB
dB
DAC Mute Attenuation
DAC channel separation
–1dB, 1kHz signal, between left and right HP out
100mVpp, 1kHz signal applied to AVDD_18,
AVDD1x_18
64
DAC PSRR
100mVpp, 217Hz signal applied to AVDD_18,
AVDD1x_18
70
15
dB
RL=16Ω
Power Delivered
THDN ≤ -40dB, Input CM=0.9V,
Output CM=0.9V
mW
(7) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(8) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Audio DAC Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 56pF,
Input & Output CM=0.75V; AVDD_18, AVDDx_18,
HVDD_18=1.5V,
DOSR = 128, MCLK=256* fs,
Channel Gain = 0dB,
Device Setup
Processing Block = PRB_P1,
Power Tune = PTM_P4
Headphone Output Control = 100%
Full scale output voltage (0dB)
0.375
99
VRMS
dB
SNR
Signal-to-noise ratio, A-weighted(9)
All zeros fed to DAC input
(10)
(9) (10)
DR
Dynamic range, A-weighted
-60dB 1 kHz input full-scale signal
–3dB full-scale, 1-kHz input signal
99
dB
dB
THD+N
Total Harmonic Distortion plus Noise
–77
AUDIO DAC – MONO DIFFERENTIAL RECEIVER OUTPUT
Load = 32 Ω (differential), 56pF,
Output CM=1.65V,
AVDDx_18=1.8V, DOSR = 128
MCLK=256* fs, Left DAC routed to LOL to RECP,
LOL signal routed to LOR to RECM, Channel
(Receiver Driver) Gain = 6dB for full scale output
signal,
Device Setup
Processing Block = PRB_P4,
Power Tune = PTM_P4
Full scale output voltage (0dB)
2
VRMS
dB
SNR
Signal-to-noise ratio, A-weighted(9)
All zeros fed to DAC input
90
99
(10)
(9) (10)
DR
Dynamic range, A-weighted
–60dB 1kHz input full-scale signal
–3dB full-scale, 1-kHz input signal
97
–81
56
dB
dB
dB
THD+N
Total Harmonic Distortion plus Noise
100mVpp, 1kHz signal applied to AVDD_18,
AVDD1x_18
DAC PSRR
100mVpp, 217Hz signal applied to AVDD_18,
AVDD1x_18
58
dB
RL=32Ω
117
mW
Power Delivered
THDN ≤ -40dB, Input CM=0.9V,
Output CM=1.65V
(9) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(10) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Class-D Outputs
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
2.67
91
MAX
UNIT
VRMS
dB
DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8Ω (Differential), 56pF+33µH
SLVDD=SRVDD=3.6, BTL measurement, DAC input
= 0dBFS, class-D gain = 12dB, THD+N ≤ –20dB,
Output voltage
CM=0.9V
SLVDD=SRVDD=3.6V, BTL measurement, class-D
gain = 6dB, measured as idle-channel noise, A-
weighted (with respect to full-scale output value of 2
Vrms)(1) (2), CM=0.9V
SNR
Signal-to-noise ratio
SLVDD=SRVDD=3.6V, BTL measurement, DAC input
= 0dBFS, class-D gain = 6dB, CM=0.9V
THD
Total harmonic distortion
–66
–66
67
dB
dB
dB
Total harmonic distortion SLVDD=SRVDD=3.6V, BTL measurement, DAC input
THD+N
+ noise
= 0dBFS, class-D gain = 6dB, CM=0.9V
SLVDD=SRVDD=3.6V, BTL measurement, ripple on
SPKVDD = 200 mVp-p at 1 kHz, CM=0.9V
Power-supply rejection
ratio
PSRR
SLVDD=SRVDD=3.6V, BTL measurement, ripple on
SPKVDD = 200 mVp-p at 217 Hz, CM=0.9V
67
102
dB
dB
Mute attenuation
Analog Mute Only
SLVDD = SRVDD =
3.6 V
0.72
THD+N = 10%, f = 1 kHz,
SLVDD = SRVDD =
Class-D Gain = 12 dB, CM =
4.2 V
1.00
1.70
0.58
0.80
1.37
0.9 V, RL = 8 Ω
SLVDD = SRVDD =
5.5 V
PO
Maximum output power
W
SLVDD = SRVDD =
3.6 V
THD+N = 1%, f = 1 kHz,
SLVDD = SRVDD =
Class-D Gain = 12 dB, CM =
4.2 V
0.9 V, RL = 8 Ω
SLVDD = SRVDD =
5.5 V
DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 Ω (Differential), 56pF+33µH
SLVDD=SRVDD=5.0V, BTL measurement, DAC input
Output voltage
= 0dBFS, class-D gain = 12dB, THD+N ≤ –20dB,
CM=0.9V
3.46
91
VRMS
SLVDD=SRVDD=5.0V, BTL measurement, class-D
gain = 6dB, measured as idle-channel noise, A-
weighted (with respect to full-scale output value of 2
Vrms)(1) (2) , CM=0.9V
SNR
Signal-to-noise ratio
SLVDD=SRVDD=5.0V, BTL measurement, DAC input
= 0dBFS, class-D gain = 6dB, CM=0.9V
THD
Total harmonic distortion
–70
–70
67
Total harmonic distortion SLVDD=SRVDD=5.0V, BTL measurement, DAC input
THD+N
+ noise
= 0dBFS, class-D gain = 6dB, CM=0.9V
SLVDD=SRVDD=5.0V, BTL measurement, ripple on
SPKVDD = 200mVp-p at 1kHz, CM=0.9V
Power-supply rejection
ratio
PSRR
SLVDD=SRVDD=5.0V, BTL measurement, ripple on
SPKVDD = 200 mVp-p at 217 Hz, CM=0.9V
67
Mute attenuation
Analog Mute Only
102
dB
W
THD+N = 10%, f = 1 kHz,
SLVDD = SRVDD =
Class-D Gain = 12 dB, CM =
5.0 V
PO
Maximum output power
1.41
0.9 V, RL = 8 Ω
(1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Misc.
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE - VREF_AUDIO
CMMode = 0 (0.9V)
0.9
0.75
1.2
Reference Voltage Settings
Reference Noise
V
CMMode = 1 (0.75V)
CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth,
μVRMS
Cref = 1μF
Decoupling Capacitor
Bias Current
1
μF
μA
99
miniDSP(1)
miniDSP clock frequency - ADC
miniDSP clock frequency - DAC
miniDSP clock frequency - ADC
miniDSP clock frequency - DAC
miniDSP clock frequency - ADC
miniDSP clock frequency - DAC
DVDD = 1.26V
DVDD = 1.26V
DVDD = 1.65V
DVDD = 1.65V
DVDD = 1.71V
DVDD = 1.71V
37.5
33.0
59.5
55.0
62.5
58.0
MHz
MHz
MHz
MHz
MHz
MHz
Shutdown Power
Coarse AVdd supply turned off, All External analog
supplies powered and set available, No external
digital input is toggled, register values are retained.
Device Setup
P(total)(2)
Sum of all supply currents, all supplies at 1.8 V
except for SLVDD = SRVDD = SPK_V = 3.6 V and
RECVDD_33 = AVDD3_33 = 3.3 V
9.8
μW
I(DVDD)
I(IOVDD)
2.6
0.15
1.15
μA
μA
μA
I(AVDD1_18, AVDD2_18, AVDD4_18,
AVDD_18, HVDD_18, CPVDD_18)
I(RECVDD_33, AVDD3_33)
I(SLVDD, SRVDD, SPK_V)
0.15
0.5
μA
μA
(1) miniDSP clock speed is specified by design and not tested in production.
(2) For further details on playback and recording power consumption, refer to Powertune section in SLAU309.
Electrical Characteristics, Logic Levels
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD, IOVDD = 1.8V; AVDD3_33, RECVDD_33 = 3.3V; SLVDD,
SRVDD, SPK_V = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 16 bits; Cext = 1μF on VREF_SAR and VREF_AUDIO pins;
PLL disabled unless otherwise noted.
PARAMETER
LOGIC FAMILY
TEST CONDITIONS
MIN
TYP
CMOS
MAX
UNIT
VIH
Logic Level
IIH = 5 μA, IOVDD > 1.65V
0.7 × IOVDD
0.9 × IOVDD
IOVDD
V
V
IIH = 5μA, 1.2V ≤ IOVDD <1.65V
IIH = 5μA, IOVDD < 1.2V
V
VIL
IIL = 5 μA, IOVDD > 1.65V
–0.3
0.3 × IOVDD
0.1 × IOVDD
0
V
IIL = 5μA, 1.2V ≤ IOVDD <1.65V
IIL = 5μA, IOVDD < 1.2V
V
V
VOH
IOH = 3mA load, IOVDD > 1.65V
IOH = 1mA load, IOVDD < 1.65V
IOL = 3mA load, IOVDD > 1.65V
IOL = 1mA load, IOVDD < 1.65V
0.8 × IOVDD
0.8 × IOVDD
V
V
VOL
0.1 × IOVDD
0.1 × IOVDD
V
V
Capacitive Load
10
pF
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Interface Timing
Note: All timing specifications are measured at characterization but not tested at final test. The audio serial interface timing
specifications are applied to Audio Serial Interface #1, Audio Serial Interface #2 and Audio Serial Interface #3.
Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
WCLK represents WCLK1 pin for Audio Serial Interface #1, WCLK2 pin for Audio Serial Interface #2, and WCLK3 pin for
Audio Serial Interface #3. BCLK represents BCLK1 pin for Audio Serial Interface #1, BCLK2 pin for Audio Serial Interface #2,
and BCLK3 pin for Audio Serial Interface #3. DOUT represents DOUT1 pin for Audio Serial Interface #1, DOUT2 pin for
Audio Serial Interface #2, and DOUT3 pin for Audio Serial Interface #3. DIN represents DIN1 pin for Audio Serial Interface #1,
DIN2 pin for Audio Serial Interface #2, and DIN3 pin for Audio Serial Interface #3. Specifications are at 25° C with DVDD =
1.8V and IOVDD = 1.8 V.
WCLK
t (WS)
d
BCLK
t (DO-BCLK)
d
t (DO-WS)
d
DOUT
t (DI)
t (DI)
h
S
DIN
I2S/LJF Timing in Master Mode
Figure 3. I2S/LJF/RJF Timing in Master Mode
Table 2. I2S/LJF/RJF Timing in Master Mode (see Figure 3)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
MAX
MIN
MAX
td(WS)
WCLK delay
22
22
22
20
20
20
ns
ns
ns
ns
ns
ns
ns
td (DO-WS)
WCLK to DOUT delay (For LJF Mode only)
BCLK to DOUT delay
DIN setup
td (DO-BCLK)
ts(DI)
th(DI)
tr
4
4
4
4
DIN hold
BCLK Rise time
10
10
8
8
tf
BCLK Fall time
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WCLK
BCLK
DOUT
DIN
th(WS)
ts(WS)
tL(BCLK)
td(DO-WS)
tH(BCLK)
td(DO-BCLK)
th(DI)
ts(DI)
Figure 4. I2S/LJF/RJF Timing in Slave Mode
Table 3. I2S/LJF/RJF Timing in Slave Mode (see Figure 4)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
30
30
4
MAX
MIN
30
30
4
MAX
tH (BCLK)
tL (BCLK)
ts (WS)
th (WS)
td (DO-WS)
td (DO-BCLK)
ts(DI)
BCLK high period
ns
BCLK low period
WCLK setup
WCLK hold
4
4
WCLK to DOUT delay (For LJF mode only)
BCLK to DOUT delay
DIN setup
22
22
20
20
4
4
4
4
th(DI)
DIN hold
tr
BCLK Rise time
5
5
4
4
tf
BCLK Fall time
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Typical DSP Timing Characteristics
Specifications are at 25° C with DVDD = 1.8 V.
WCLK
t (WS)
d
t (WS)
d
BCLK
DOUT
DIN
t (DO-BCLK)
d
t (DI)
t (DI)
h
s
Figure 5. DSP/Mono PCM Timing in Master Mode
Table 4. DSP/Mono PCM Timing in Master Mode (see Figure 5)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
MAX
MIN
MAX
20
td (WS)
WCLK delay
22
22
ns
ns
ns
ns
ns
ns
td (DO-BCLK)
BCLK to DOUT delay
DIN setup
20
ts(DI)
th(DI)
tr
4
4
4
4
DIN hold
BCLK Rise time
BCLK Fall time
10
10
8
8
tf
WCLK
t (ws)
h
t (ws)
t (ws)
h
s
t (ws)
h
t (BCLK)
L
BCLK
DOUT
DIN
t
(BCLK)
H
t (DO-BCLK)
d
t (DI)
h
t (DI)
s
Figure 6. DSP/Mono PCM Timing in Slave Mode
Table 5. DSP/Mono PCM Timing in Slave Mode (see Figure 6)
PARAMETER
IOVDD=1.8V
IOVDD=3.3V
UNITS
MIN
30
30
4
MAX
MIN
30
30
4
MAX
tH (BCLK)
tL (BCLK)
ts(WS)
BCLK high period
BCLK low period
WCLK setup
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(WS)
WCLK hold
4
4
td (DO-BCLK)
BCLK to DOUT delay
DIN setup
22
20
ts(DI)
th(DI)
tr
5
5
5
5
DIN hold
BCLK Rise time
BCLK Fall time
5
5
4
4
tf
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I2C Interface Timing
Figure 7. I2C Interface Timing Diagram
Table 6. I2C Interface Timing (see Figure 7)
PARAMETER
TEST CONDITION
Standard-Mode
Fast-Mode
MIN TYP
UNITS
MIN
0
TYP
MAX
MAX
fSCL
SCL clock frequency
100
0
400
kHz
tHD;STA Hold time (repeated) START
condition. After this period, the first
clock pulse is generated.
4.0
0.8
μs
tLOW
tHIGH
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
1.3
0.6
0.8
μs
μs
μs
tSU;STA Setup time for a repeated START
condition
tHD;DAT Data hold time: For I2C bus
devices
0
3.45
0
0.9
μs
tSU;DAT Data set-up time
250
100
ns
ns
ns
μs
μs
tr
tf
SDA and SCL Rise Time
SDA and SCL Fall Time
1000 20+0.1Cb
300
300
300 20+0.1Cb
tSU;STO Set-up time for STOP condition
4.0
4.7
0.8
1.3
tBUF
Bus free time between a STOP
and START condition
Cb
Capacitive load for each bus line
400
400
pF
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SPI Interface Timing
SS = SCL pin, SCLK = GPI1 pin, MISO = GPO1 pin, and MOSI = SDA pin. Specifications are at 25° C with DVDD = 1.8 V.
SS
t
td
tLag
t
tLead
sck
tf
tr
SCLK
MISO
tsckl
tsckh
tv
tdis
MSB OUT
thi
BIT 6 . . . 1
LSB OUT
t
a
tsu
MOSI
MSB IN
BIT 6 . . . 1
LSB IN
Figure 8. SPI Interface Timing Diagram
Timing Requirements (See Figure 8)
Specifications are at 25° C with DVDD = 1.8 V.
Table 7. SPI Interface Timing
PARAMETER
SCLK Period(1)
TEST CONDITION
IOVDD=1.8V
MIN TYP MAX
IOVDD=3.3V
MIN TYP
UNITS
MAX
tsck
50
25
25
25
25
25
40
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsckh
tsckl
tlead
ttrail
SCLK Pulse width High
SCLK Pulse width Low
Enable Lead Time
Enable Trail Time
td;seqxfr Sequential Transfer Delay
ta
Slave DOUT (MISO) access time
Slave DOUT (MISO) disable time
DIN (MOSI) data setup time
DIN (MOSI) data hold time
25
25
20
20
tdis
tsu
8
8
8
8
th;DIN
tv;DOUT DOUT (MISO) data valid time
20
4
14
4
tr
tf
SCLK Rise Time
SCLK Fall Time
4
4
(1) These parameters are based on characterization and are not tested in production.
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Typical Characteristics
Device Power Consumption
Device power consumption largely depends on PowerTune configuration. For information on device power
consumption, see the TLV320AIC3262 Application Reference Guide, literature number SLAU309.
Typical Performance
Audio ADC Performance
ADC SNR
vs
ADC SINGLE ENDED INPUT TO ADC FFT @ -3dBr
CHANNEL GAIN
Input-Referred
vs
FREQUENCY
0
Rin = 10k, DE
Rin = 20k, DE
Rin = 40k, DE
110
105
100
95
−20
−40
−60
Rin = 10k, SE
Rin = 20k, SE
−80
−100
−120
−140
90
Rin = 40k, SE
85
−10
0
10
20
30
40
50
0.02
0.1
1
10
20
Channel Gain (dB)
Frequency (kHz)
G001
G002
Figure 9.
Figure 10.
ADC DIFFERENTIAL INPUT TO ADC FFT @ -3dBr
vs
FREQUENCY
0
−20
−40
−60
−80
−100
−120
−140
0.02
0.1
1
10
20
Frequency (kHz)
G003
Figure 11.
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Audio DAC Performance
DAC TO HEADPHONE OUTPUT (GCHP) FFT AMPLITUDE
DAC TO LINE OUTPUT FFT AMPLITUDE @ -3dBFS
@ -3dBFS
vs
vs
FREQUENCY
10kΩ Load
FREQUENCY
16Ω Load
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0.02
0.1
1
10
20
0.02
0.1
1
10
20
Frequency (kHz)
Frequency (kHz)
G004
G005
Figure 12.
Figure 13.
DAC TO HEADPHONE OUTPUT (GCHP) FFT AMPLITUDE
@ -3dBFS
DAC TO DIFFERENTIAL RECEIVER OUTPUT FFT
AMPLITUDE @ -3dBFS
vs
vs
FREQUENCY
32Ω Load
FREQUENCY
32Ω Load
0
0
−20
−40
−20
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0.02
0.1
1
10
20
0.02
0.1
1
10
20
Frequency (kHz)
Frequency (kHz)
G013
G006
Figure 14.
Figure 15.
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TOTAL HARMONIC DISTORTION+NOISE
TOTAL HARMONIC DISTORTION+NOISE
vs
vs
HEADPHONE (GCHP) OUTPUT POWER
9dB Gain
DIFFERENTIAL RECEIVER OUTPUT POWER
32Ω Load
0
−10
−20
−30
−40
−50
−60
−70
−80
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
CM=0.75v,32Ohm,
HVDD=CPVDD=1.5V
CM=0.75V,
RECVDD=1.65V RECVDD=1.8V
CM=0.9V,
CM=0.75v,16Ohm,
HVDD=CPVDD=1.5V
CM=1.25V,
RECVDD=2.5V
CM=0.9v,32Ohm,
HVDD=CPVDD=1.8V
CM=1.5V,
RECVDD=3V
CM=0.9v,16Ohm,
HVDD=CPVDD=1.8V
CM=1.65V,
RECVDD=3.3V
0
10
20
30
40
50
60
70
0
20
40
60
80
100 120 140 160 180
Output Power (mW)
Output Power (mW)
G007
G008
Figure 16.
Figure 17.
DIFFERENTIAL RECEIVER SNR AND OUTPUT POWER
vs
OUTPUT COMMON MODE SETTING
32Ω Load
120
150
110
100
90
125
SNR
100
75
80
Output Power
50
25
0
70
60
0.8
1.0
1.2
1.4
1.6
Output Common Mode Setting (V)
G009
Figure 18.
Class-D Driver Performance
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
Different Gain Settings, 8Ω Load,
Different SLVDD/SRVDD/SPK_V Supplies, 8Ω Load, 12dB
SLVDD=SRVDD=SPK_V=3.6V
Gain
0
−10
−20
−30
−40
−50
−60
−70
−80
0
2.7V
3.6V
4.2V
5.0V 5.5v
−10
−20
−30
−40
−50
−60
−70
−80
12dB
18dB
24dB
30
6dB
0
200
400
600
800
1000
1200
0
200 400 600 800 1000 1200 1400 1600 1800
Output Power (mW)
Output Power (mW)
G010
G011
Figure 19.
Figure 20.
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MICBIAS Performance
MICBIAS MODE 2, CM = 0.9V, AVDD3_33 OP STAGE
vs
MICBIAS LOAD CURRENT
3
2.95
2.9
2.85
2.8
0
1
2
3
4
5
6
7
Micbias Load (mA)
G012
Figure 21.
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Application Overview
Typical Circuit Configuration
Figure 22 shows a typical circuit configuration for a system utilizing TLV320AIC3262. Note that while this circuit
configuration shows all three Audio Serial Interfaces connected to a single Host Processor, it is also quite
common for these Audio Serial Interfaces to connect to separate devices (e.g. Host Processor on Audio Serial
Interface #1, and modems and/or Bluetooth devices on the other audio serial interfaces).
Note: VBAT is used for System
voltage measurement. Battery
HOST PROCESSOR
SVDD
Audio
Audio
Audio
Interface #1
Interface #2
Interface #3
1 F
1 F
1 F
LOL
VREF_SAR
Lineout
1 F
VREF_AUDIO
LOR
1 F
+1.8VA
10 F
F
CPVDD_18
0.1
1 F
1 F
1 F
1 F
1 F
1 F
1 F
Analog_In1
Analog_In2
Analog_In3
Analog_In4
Analog_In5
Analog_In6
Analog_In7
IN1R/AUX2
IN2L
CPVSS
CPFCP
2.2 F
X7R Type
CPFCM
VNEG
IN2R
2.2 F
X7R Type
IN3L
32
RECP
RECM
IN3R
Receiver
MICDET
IN4R
2.2k
0.1
MICBIAS_EXT
F
IN4L
IN1L/AUX1
HPL
MICBIAS
To Internal
Mic
HPR
Headset
+3.3VA
AVDD3_33
HPVSS_SENSE
1
F
0.1 F
AGND at Connector
8
AVSS3
SPKLP
SPKLM
RECVSS
RECVDD_33
1 F
8
SPKRP
SPKRM
0.1 F
+3.3VA
2
+1.8VD
0.1
SVDD
F
0.1
F
10 F
0.1
F
10 F
10
F 0.1 F
F
0.1
F
0.1
F
0.1 F
0.1
F
0.1
1
F
10
F
10
F
0.1
F
S0441-02
+1.8VD
+1.8VA
Figure 22. Typical Circuit Configuration
Device Connections
Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
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The fixed-function pins are hardware-control pins RESET and SPI_SELECT pin. Depending on the state of
SPI_SELECT, four pins SCL, SDA, GPO1, and GPI1 are configured for either I2C or SPI protocol. Only in I2C
mode, GPI3 and GPI4 provide four possible I2C addresses for the TLV320AIC3262.
Other digital IO pins can be configured for various functions via register control.
Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
The possible analog routings of analog input pins to ADCs and output amplifiers as well as the routing from
DACs to output amplifiers can be seen in the Analog Routing Diagram.
Multifunction Pins
Table 8 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 9 pins (MCLK1, MCLK2, BCLK1, DIN1, BCLK2, GPIO1, GPIO2, GPI1, GPI2).
Table 8. Multifunction Pin Assignments for Pins MCLK1, MCLK2, WCLK1, BCLK1, DIN1, DOUT1, WCLK2,
BCLK2, DIN2, and DOUT2
1
2
3
4
5
6
7
8
9
10
Pin Function
MCLK1 MCLK2 WCLK1 BCLK1
DIN1
DOUT1
WCLK2
BCLK2
DIN2
DOUT2
A
B
C
D
E
F
INT1 Output
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
INT2 Output
SAR ADC Interrupt
CLOCKOUT Output
ADC_MOD_CLOCK Output
E
E
Single DOUT for ASI1 (All
Channels)
E, D
F
F
G
Single DOUT for ASI2
Single DOUT for ASI3
E, D
Multiple DOUTs for ASI1 (L1,
R1)
E
G
G
G
I
Multiple DOUTs for ASI1 (L2,
R2)
E
E
Multiple DOUTs for ASI1 (L3,
R3)
E
E
Multiple DOUTs for ASI1 (L4,
R4)
E
E
General Purpose Output (via
Reg)
E(1)
F
Single DIN for ASI1 (All
Channels)
E, D(2)
F
F
H
Single DIN for ASI2
Single DIN for ASI3
E, D
Multiple DINs for ASI1 (L1,
R1)
E
H
H
H
J
Multiple DINs for ASI1 (L2,
R2)
E
Multiple DINs for ASI1 (L3,
R3)
E
E
E
E
Multiple DINs for ASI1 (L4,
R4)
E
Digital Mic Data
E
E
(1) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if DOUT1 has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)
(2) D: Default Function
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Table 8. Multifunction Pin Assignments for Pins MCLK1, MCLK2, WCLK1, BCLK1, DIN1, DOUT1, WCLK2,
BCLK2, DIN2, and DOUT2 (continued)
1
2
3
4
5
DIN1
S
6
7
8
BCLK2
S(4)
S(4)
S(4)
S
9
10
Pin Function
MCLK1 MCLK2 WCLK1 BCLK1
DOUT1
WCLK2
DIN2
DOUT2
K
L
Input to PLL_CLKIN
Input to ADC_CLKIN
Input to DAC_CLKIN
Input to CDIV_CLKIN
Input to LFR_CLKIN
Input to HF_CLK
S(3), D
S(3), D
S(3), D
S(3), D
S(3), D
S(3)
S
S
S
S
S
S(4)
S(4)
S(4)
S
M
N
O
P
Q
R
S
E
S
S
E
S
S
Input to REF_1MHz_CLK
S(3)
General Purpose Input (via
Reg)
E
E
E
S
ISR Interrupt for miniDSP
(via Reg)
T
WCLK Output for ASI1
WCLK Input for ASI1
BCLK Output for ASI1
BCLK Input for ASI1
WCLK Output for ASI2
WCLK Input for ASI2
BCLK Output for ASI2
E
U
V
W
X
Y
Z
S, D
E
S(4), D
E
S, D
E
AA BCLK Input for ASI2
BB WCLK Output for ASI3
CC WCLK Input for ASI3
DD BCLK Output for ASI3
EE BCLK Input for ASI3
S(4), D
(3) S(3): The MCLK1 pin could be chosen to drive the PLL, ADC Clock, DAC Clock, CDIV Clock, LFR Clock, HF Clock, and
REF_1MHz_CLK inputs simultaneously
(4) S(4): The BCLK1 or BCLK2 pins could be chosen to drive the PLL, ADC Clock, DAC Clock, and audio interface bit clock inputs
simultaneously
Table 9. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1,
GPI1, GPI2, GPI3, and GPI4
11
12
13
14
15
16
17
18
19
20
21
Pin Function
WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2
GPO1/
GPI1/
GPI2 GPI3(2) GPI4(2)
MISO(1)
SCLK(1)
A
B
C
D
E
INT1 Output
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
INT2 Output
SAR ADC Interrupt
CLOCKOUT Output
ADC_MOD_CLOCK
Output
F
Single DOUT for ASI1
(All Channels)
E
F
F
G
Single DOUT for ASI2
Single DOUT for ASI3
E, D
Multiple DOUTs for
ASI1 (L1, R1)
(1) GPO1 and GPI1 can only be utilized for functions defined in this table when part utilizes I2C for control. In SPI mode, these pins serve
as the MISO and SCLK, respectively.
(2) GPI3 and GPI4 can only be utilized for functions defined in this table when part utilizes SPI for control. In I2C mode, these pins serve as
I2C address pins.
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Table 9. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1,
GPI1, GPI2, GPI3, and GPI4 (continued)
11
12
13
14
15
16
17
18
19
20
21
Pin Function
WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2
GPO1/
GPI1/
GPI2 GPI3(2) GPI4(2)
MISO(1)
SCLK(1)
G
G
G
I
Multiple DOUTs for
ASI1 (L2, R2)
E
E
E
E
E
E
E
E
E
E
Multiple DOUTs for
ASI1 (L3, R3)
E
E
E
E
E
Multiple DOUTs for
ASI1 (L4, R4)
E
General Purpose
Output (via Reg)
E(3)
E
F
Single DIN for ASI1
(All Channels)
E
F
F
H
Single DIN for ASI2
Single DIN for ASI3
E, D
Multiple DINs for ASI1
(L1, R1)
H
H
H
Multiple DINs for ASI1
(L2, R2)
E
E
E
E
E
E
E
E
E
Multiple DINs for ASI1
(L3, R3)
E
E
E
Multiple DINs for ASI1
(L4, R4)
J
Digital Mic Data
E
E
E
S(4)
S(4)
S(4)
S
E
S(4)
S(4)
S(4)
S
K
L
Input to PLL_CLKIN
Input to ADC_CLKIN
Input to DAC_CLKIN
Input to CDIV_CLKIN
Input to LFR_CLKIN
Input to HF_CLK
S(4)
S(4)
S(4)
S(4)
S(4)
S(4)
M
N
O
P
Q
S
E
S
E
S
S
S
S
Input to
REF_1MHz_CLK
R
S
General Purpose Input
(via Reg)
E
E
E
E
E
E
E
E
ISR Interrupt for
miniDSP (via Reg)
T
WCLK Output for ASI1
WCLK Input for ASI1
BCLK Output for ASI1
BCLK Input for ASI1
WCLK Output for ASI2
WCLK Input for ASI2
BCLK Output for ASI2
E
E
E
U
V
W
X
Y
Z
E
E
AA BCLK Input for ASI2
BB WCLK Output for ASI3
CC WCLK Input for ASI3
DD BCLK Output for ASI3
EE BCLK Input for ASI3
E
S, D(5)
E
S, D
(3) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if WCLK3 has been
allocated for General Purpose Output, it cannot be used as the ASI3 WCLK output at the same time)
(4) S(4): The GPIO1, GPIO2, GPI1, or GPI2 pins could be chosen to drive the PLL, ADC Clock, and DAC Clock inputs simultaneously
(5) D: Default Function
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Table 9. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1,
GPI1, GPI2, GPI3, and GPI4 (continued)
11
12
13
14
15
16
17
18
19
20
21
Pin Function
WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2
GPO1/
GPI1/
GPI2 GPI3(2) GPI4(2)
MISO(1)
SCLK(1)
FF ADC BCLK Input for
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
ASI1
GG ADC WCLK Input for
E
ASI1
HH ADC BCLK Output for
ASI1
II
ADC WCLK Output for
ASI1
JJ ADC BCLK Input for
E
E
E
E
E
E
E
E
ASI2
KK ADC WCLK Input for
ASI2
LL ADC BCLK Output for
ASI2
MM ADC WCLK Output for
ASI2
NN ADC BCLK Input for
E
E
E
E
E
E
E
E
ASI3
OO ADC WCLK Input for
ASI3
PP ADC BCLK Output for
ASI3
QQ ADC WCLK Output for
ASI3
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Analog Audio I/O
P1_R45_D1=Power
P1_R48_D[6:4]=Gain
-12, -6, 0dB
SPKLP
P1_R23_D[4:3]
MAL
LOL
P1_R45_D7
Class-D
IN1L-B
Speaker Amp L
6, 12, 18, 24, 30
dB
P1_R46_D[6:0]
SPKLM
IN1L
IN1L
P1_R45_D2
SPR_IN
10/20/40K
20K
P1_R52_D[7:6]
P1_R52_D[5:4]
-78dB to 0dB
P1_R46_D[6:0]
P1_R17_D3=Power
P1_R45_D0=Power
P1_R48_D[2:0]=Gain
IN2L
-78dB to 0dB
P1_R47_D[6:0]
10/20/40K
IN1L
SPKRP
MAL
P1_R47_D[6:0]
Mixer Amp
Left
LOR
MAR
P1_R17_D5
P1_R18_D[5:0]
Class-D
IN3L
IN4L
10/20/40K
P1_R52_D[3:2]
SPR_IN
Speaker Amp R
6, 12, 18, 24,
30 dB
SPKRM
P1_R45_D6
-36dB to 0dB
P1_R18_D[5:0]
20K
P1_R53_D5
0 to +47.5 dB
P1_R59
10/20/40K
P
P1_R52_D[1:0]
IN1R
IN2R
IN3R
IN4R
P
P1_R27_D1=Power
P1_R31_D[5:0]=Gain
Mic PGA
Left
Left DAC
Left ADC
10/20/40K
10/20/40K
20K
P1_R54_D[5:4]
P1_R54_D[3:2]
P1_R53_D4
M
P1_R27_D7
P1_R27_D5
MAL
M
HPL
Headphone
Amplifier Left
-6dB to14dB
LDACP
LOL-B1
P1_R28_D[6:0]
Left Channel Input Options:
-78dB to 0dB
P1_R28_D[6:0]
Single Ended: IN1L or IN2L or IN3L or IN1R or IN4L
10/20/40K
10/20/40K
P1_R54_D[7:6]
P1_R54_D[1:0]
Differential: IN2L (P) and IN2R (M) or IN3L (P) and IN3R (M)
or IN4L (P) and IN4R (M)
P1_R23_D7
P1_R23_D[4:3]
P1_R22_D1=Power
Lineout
MAL
IN1L-B
LOL
Note (For All Inputs to Mic PGA):
Amplifier
Left
CM2L
P1_R22_D7
P1_R22_D5
LDACM
RDACP
PGA Input = 0 dB for Singled Ended Input with RIN = 10K
PGA Input = +6 dB for Differential Input with RIN= 10K
PGA Input = -6 dB for Singled Ended Input with RIN= 20K
PGA Input = 0 dB for Differential Input with RIN= 20K
PGA Input = -12 dB for Singled Ended Input with RIN= 40K
PGA Input = -6 dB for Differential Input with RIN= 40K
CM1L
CM1R
CM2R
CM
-78dB to 0dB
P1_R36_D[6:0]
P1_R40_D[5:0]=Gain RECP
P1_R40_D7=Power RECP
10/20/40K
-78dB to 0dB
P1_R38_D[6:0]
P1_R57_D[1:0]
P1_R57_D[7:6]
RECP
P1_R36_D[6:0]
LOL-B2
1
P1_R38_D[6:0]
IN1L
Receiver
Amplifier
-6db to +29dB
10/20/40K
20K
Right Channel Input Options:
P1_R39_D[6:0]
P1_R37_D[6:0]
IN1R
RECM
2
LOR-B2
-78dB to 0dB
Single Ended: IN1R or IN2R or IN3R or IN2L or IN4R
P1_R39_D[6:0]
P1_R41_D[5:0]=Gain RECM
P1_R40_D6=Power RECM
P1_R56_D4
IN4L
-78dB to 0dB
P1_R37_D[6:0]
Differential: IN1R (P) and IN1L (M) or IN3R (P) and IN3L (M)
or IN4R (P) and IN4L (M)
10/20/40K
10/20/40K
10/20/40K
P1_R57_D[3:2]
P1_R57_D[5:4]
P1_R55_D[1:0]
P1_R56_D5
IN3L
IN1L
IN2L
0 to +47.5 dB
P1_R60
P1_R22_D0=Power
P1_R22_D2
LOL
RDACM
M
P
P1_R22_D6
M
LOR
Lineout
Amplifier
Right
Mic PGA
Right
Right DAC
Right ADC
P1_R23_D6
MAR
P
P1_R23_D[1:0]
IN1R-B
IN4R
IN3R
20K
P1_R19_D[5:0]
-36d to 0dB
-78dB to 0dB
P1_R29_D[6:0]
10/20/40K
10/20/40K
10/20/40K
P1_R17_D2=Power
P1_R55_D[3:2]
P1_R55_D[5:4]
P1_R55_D[7:6]
P1_R19_D[5:0]
MAR
P1_R27_D0=Power
P1_R32_D[5:0]=Gain
Mixer Amp
P1_R17_D4
IN2R
IN1R
Right
P1_R29_D[6:0]
LOR-B1
LDACM
RDACP
MAR
IN1R
HPR
P1_R27_D2
P1_R27_D4
P1_R27_D6
Headphone
Amplifier Right
-6dB to +14dB
20K
IN1R
-12, -6, 0dB
P1_R23_D[1:0]
IN1R-B
Figure 23. Analog Routing Diagram
For more detailed information see the TLV320AIC3262 Application Reference Guide, SLAU309.
Analog Low Power Bypass
The TLV320AIC3262 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC
resources are required for such operation; this supports low-power operation during analog-bypass mode. In
analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1L to the left
lineout amplifier (LOL) and IN1R to LOR. Additionally, line-level signals can be routed directly from these analog
inputs to the differential receiver amplifier, which outputs on RECP and RECM.
ADC Bypass Using Mixer Amplifiers
In addition to the low-power bypass mode, there is a bypass mode that uses the programmable gain amplifiers of
the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified
and routed to the line, speaker, or headphone outputs, fully bypassing the ADC and DAC. To enable this mode,
the mixer amplifiers are powered on via software command.
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Headphone Outputs
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in single-
ended DC-coupled headphone configurations. An integral charge pump generates the negative supply required
to operate the headphone drivers in dc-coupled mode, where the common mode of the output signal is made
equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers in dc-
coupled (ground centered mode) eliminates the need for large dc-blocking capacitors.
HPL
HPR
HPVSS_SENSE
Figure 24. TLV320AIC3262 Ground-Centered Headphone Output
Alternatively the headphone amplifier can also be operated in a unipolar circuit configuration using DC blocking
capacitors.
Stereo Line Outputs
The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in
the range of 600Ω to 10kΩ. The output common mode of line level drivers can be configured to equal the analog
input common-mode setting, either 0.75V or 0.9V. The line-level drivers can drive out a mixed combination of
DAC signal and attenuated ADC PGA signal, and signal mixing is register-programmable.
Differential Receiver Output
The differential receiver amplifier output spans the RECP and RECM pins and can drive a 32Ω receiver driver.
With output common-mode setting of 1.65V and RECVDD_33 supply at 3.3V, the receiver driver can drive up to
a 1Vrms output signal. With the RECVDD_33 supply at 3.3V, the receiver driver can deliver greater than 128mW
into a 32Ω BTL load. If desired, the RECVDD_33 supply can be set to 1.8V, at which the driver can deliver about
40mW into the 32Ω BTL load.
Stereo Class-D Speaker Outputs
The integrated Class-D stereo speaker drivers (SPKLP/SPKLN and SPKRP/SPKRN) are capable of driving two
8Ω differential loads. The speaker drivers can be powered directly from the power supply (2.7V to 5.5V) on the
SLVDD and SRVDD pins, however the voltage (including spike voltage) must be limited below the Absolute
Maximum Voltage of 6.0V.
The speaker drivers are capable of supplying 750 mW per channel at 10% THD+N with a 3.6-V power supply
and 1.46W per channel at 10% THD+N with a 5.0V power supply. Separate left and right channels can be sent
to each Class-D driver through the Lineout signal path, or from the mixer amplifiers in the ADC bypass. If only
one speaker is being utilized for playback, the analog mixer before the Left Speaker amplifier can sum the left
and right audio signals for monophonic playback.
ADC / Digital Microphone Interface
The TLV320AIC3262 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable
oversampling ratio, followed by a digital decimation filter and a programmable miniDSP. The ADC supports
sampling rates from 8kHz to 192kHz. In order to provide optimal system power management, the stereo
recording path can be powered up one channel at a time, to support the case where only mono record capability
is required.
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The ADC path of the TLV320AIC3262 features a large set of options for signal conditioning as well as signal
routing:
•
•
•
•
•
•
•
•
•
2 ADCs
8 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration
2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
2 mixer amplifiers for analog bypass
2 low power analog bypass channels
Fine gain adjust of digital channels with 0.1 dB step size
Digital volume control with a range of -12 to +20dB
Mute function
Automatic gain control (AGC)
In addition to the standard set of ADC features the TLV320AIC3262 also offers the following special functions:
•
•
•
•
•
•
Built in microphone biases
Stereo digital microphone interface
Channel-to-channel phase adjustment
Fast charge of ac-coupling capacitors
Anti thump
Adaptive filter mode
ADC Processing Blocks — Overview
The TLV320AIC3262 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the sigma-delta modulator to generate digital data at Nyquist sampling rate with high dynamic range. The
decimation filter can be chosen from three different types, depending on the required frequency response, group
delay and sampling rate.
ADC Processing Blocks
The TLV320AIC3262 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy to balance power conservation
and signal-processing flexibility. Decreasing the use of signal-processing capabilities reduces the power
consumed by the device. Table 10 gives an overview of the available processing blocks of the ADC channel and
their properties. The Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
•
•
•
•
First-order IIR
Scalable number of biquad filters
Variable-tap FIR filter
AGC
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low-group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first order IIR, BiQuad and FIR filters have fully user programmable coefficients.
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Table 10. ADC Processing Blocks
Processing
Blocks
Channel
Decimation
Filter
1st Order
IIR Available
Number
BiQuads
FIR
Required AOSR
Value
Resource
Class
PRB_R1(1)
PRB_R2
PRB_R3
PRB_R4
PRB_R5
PRB_R6
PRB_R7
PRB_R8
PRB_R9
PRB_R10
PRB_R11
PRB_R12
PRB_R13
PRB_R14
PRB_R15
PRB_R16
PRB_R17
PRB_R18
Stereo
Stereo
Stereo
Left
A
A
A
A
A
A
B
B
B
B
B
B
C
C
C
C
C
C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0
5
0
0
5
0
0
3
0
0
3
0
0
5
0
0
5
0
No
No
128,64,32,16,8,4
128,64,32,16,8,4
128,64,32,16,8,4
128,64,32,16,8,4
128,64,32,16,8,4
128,64,32,16,8,4
64,32,16,8,4,2
64,32,16,8,4,2
64,32,16,8,4,2
64,32,16,8,4,2
64,32,16,8,4,2
64,32,16,8,4,2
32,16,8,4,2,1
7
8
8
4
4
4
3
4
4
2
2
2
3
4
4
2
2
2
25-Tap
No
Left
No
Left
25-Tap
No
Stereo
Stereo
Stereo
Left
No
17-Tap
No
Left
No
Left
17-Tap
No
Stereo
Stereo
Stereo
Left
No
32,16,8,4,2,1
25-Tap
No
32,16,8,4,2,1
32,16,8,4,2,1
Left
No
32,16,8,4,2,1
Left
25-Tap
32,16,8,4,2,1
(1) Default
For more detailed information see the Application Reference Guide, SLAU309.
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DAC
The TLV320AIC3262 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter.
The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling
and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal
images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize
power dissipation and performance, the TLV320AIC3262 allows the system designer to program the
oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling
ratios for lower input data rates and lower oversampling ratios for higher input data rates.
The TLV320AIC3262 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320AIC3262 features many options for signal conditioning and signal routing:
•
2 headphone amplifiers
–
–
Usable in single-ended stereo or differential mono mode
Analog volume setting with a range of -6 to +14 dB
•
•
2 line-out amplifiers
Usable in single-ended stereo or differential mono mode
2 Class-D speaker amplifiers
–
–
–
Usable in stereo differential mode
Analog volume control with a settings of +6, +12, +18, +24, and +30 dB
•
1 Receiver amplifier
–
–
Usable in mono differential mode
Analog volume setting with a range of -6 to +29 dB
•
•
•
Digital volume control with a range of -63.5 to +24dB
Mute function
Dynamic range compression (DRC)
In addition to the standard set of DAC features the TLV320AIC3262 also offers the following special features:
•
•
•
•
Built in sine wave generation (beep generator)
Digital auto mute
Adaptive filter mode
Asynchronous Sample Rate Conversion
DAC Processing Blocks — Overview
The TLV320AIC3262 implements signal processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
The choice between these processing blocks is part of the PowerTune strategy balancing power conservation
and signal processing flexibility. Less signal processing capability will result in less power consumed by the
device. The Table 11 gives an overview over all available processing blocks of the DAC channel and their
properties. The Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
•
•
•
•
First-order IIR
Scalable number of biquad filters
3D – Effect
Beep Generator
The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients.
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RC Class
Table 11. Overview – DAC Predefined Processing Blocks
Processing
Block No.
Interpolation
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
Filter
PRB_P1(1)
A
Stereo
Stereo
Stereo
Left
No
Yes
Yes
No
3
6
6
3
6
6
0
4
4
6
6
0
4
4
6
6
0
4
4
0
4
4
2
5
5
0
No
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
No
8
12
10
4
PRB_P2
A
PRB_P3
A
PRB_P4
A
No
PRB_P5
A
Left
Yes
Yes
Yes
No
Yes
No
6
PRB_P6
A
Left
5
PRB_P7
B
Stereo
Stereo
Stereo
Stereo
Stereo
Left
No
5
PRB_P8
B
Yes
No
9
PRB_P9
B
No
7
PRB_P10
PRB_P11
PRB_P12
PRB_P13
PRB_P14
PRB_P15
PRB_P16
PRB_P17
PRB_P18
PRB_P19
PRB_P20
PRB_P21
PRB_P22
PRB_P23
PRB_P24
PRB_P25
PRB_P26
B
Yes
Yes
Yes
No
Yes
No
9
B
7
B
No
3
B
Left
Yes
No
4
B
Left
No
4
B
Left
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
5
B
Left
4
C
C
C
C
C
C
A
Stereo
Stereo
Stereo
Left
No
3
Yes
No
6
4
No
2
Left
Yes
No
3
Left
2
Stereo
Stereo
Stereo
Stereo
No
8
A
Yes
Yes
No
Yes
Yes
No
12
13
1
A
D
(1) Default
For more detailed information see the Application Reference Guide, SLAU309.
Powertune
The TLV320AIC3262 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance,
or to an operating point between the two extremes to best fit the application. The TLV320AIC3262 PowerTune
modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback
(DAC) path.
For more detailed information see the Application Reference Guide, SLAU309.
Clock Generation and PLL
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3262.
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The TLV320AIC3262 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require source reference clocks, and
these clocks can be from a single source or from two separate sources. They can be provided on a variety of
device pins such as MCLKx, BCLK1, BCLK2, GPI1, GPI2, or GPIOx pins. The clocks, ADC_CLKIN and
DAC_CLKIN, can then be routed through highly-flexible clock dividers to generate the various clocks required for
ADC, DAC and the miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be
generated from the reference clocks on MCLKx, BCLK1, BCLK2, or GPIOx, the codec also provides the option of
using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required
clocks. The ADC_CLKIN and DAC_CLKIN can then be routed through highly-flexible clock dividers to generate
the various clocks required for ADC, DAC and the miniDSP sections.
For more detailed information see the Application Reference Guide, SLAU309.
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Interfaces
www.ti.com
Control Interfaces
The TLV320AIC3262 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low.
It is not recommended to change the state of SPI_SELECT during device operation.
I2C Control
The TLV320AIC3262 supports the I2C control protocol, and will respond by default (GPI3 and GPI4 grounded) to
the 7-bit I2C address of 0011000. With the two I2C address pins, GPI3 and GPI4, the device can be configured to
respond to one of four 7-bit I2C addresses, 0011000, 0011001, 0011010, or 0011011. The full 8-bit I2C address
can be calculated as:
8-Bit I2C Address = "00110" + GPI4 + GPI3 + R/W
E.g. to write to the TLV320AIC3262 with GPI4 = 1 and GPI3 = 0 the 8-Bit I2C Address is "00110" + GPI4 + GPI3
+ R/W = "00110100" = 0x34
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
SPI Control
In the SPI control mode, the TLV320AIC3262 uses the pins SCL as SS, GPI1 as SCLK, GPO1 as MISO, SDA as
MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0) and
clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The SPI port allows full-duplex,
synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The
SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates
transmissions. The SPI slave devices (such as the TLV320AIC3262) depend on a master to start and
synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master
begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the
byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.
For more detailed information see the Application Reference Guide, SLAU309.
Digital Audio Interfaces
The TLV320AIC3262 features three digital audio data serial interfaces, or audio buses. These three interfaces
can be run simultaneously, thereby enabling reception and transmission of digital audio from/to three separate
devices. A common example of this scenario would be individual connections to an application processor, a
communication baseband processor, and a Bluetooth chipset. By utilizing the TLV320AIC3262 as the center of
the audio processing in a portable audio system, mixing of voice and music audio is greatly simplified. In
addition, the miniDSP can be utilized to greatly enhance the portable device experience by providing advanced
audio processing to both communication and media audio streams simultaneously. In addition to the three
simultaneous digital audio interfaces, a fourth set of digital audio pins can be muxed into Audio Serial Interface
#1. In other words, four separate 4-wire digital audio buses can be connected to the TLV320AIC3262, with up to
three of these 4-wire buses receiving and sending digital audio data.
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Audio Serial Interfaces
AUDIO SERIAL INTERFACE #1
AUDIO SERIAL INTERFACE #2
AUDIO SERIAL INTERFACE #3
WCLK
BCLK
DIN
DOUT
WCLK
BCLK
DIN
DOUT
WCLK
BCLK
DIN
DOUT
Figure 25. Typical Multiple Connections to Three Audio Serial Interfaces
Each audio bus on the TLV320AIC3262 is very flexible, including left or right-justified data options, support for
I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible
master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a
system directly.
Each of the three audio buses of the TLV320AIC3262 can be configured for left or right-justified, I2S, DSP, or
TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the
TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition,
the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible
connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may
be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the
maximum of the selected ADC and DAC sampling frequencies. When configuring an audio interface for six-wire
mode, the ADC and DAC paths can operate based on separate word clocks.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider. The number
of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support
the case when multiple TLV320AIC3262s may share the same audio bus. When configuring an audio interface
for six-wire mode, the ADC and DAC paths can operate based on separate bit clocks.
The TLV320AIC3262 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks.
The TLV320AIC3262 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen.
The TLV320AIC3262 further includes programmability to 3-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on
a single audio serial data bus. When the audio serial data bus is powered down while configured in master
mode, the pins associated with the interface are put into a 3-state output condition.
By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3262, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,
or when word-clock or bit-clocks are used in the system as general-purpose clocks.
For more detailed information see the Application Reference Guide, SLAU309.
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miniDSP
The TLV320AIC3262 features two fully programmable miniDSP cores. The first miniDSP core is tightly coupled
to the ADC, the second miniDSP core is tightly coupled to the DAC. The algorithms for the miniDSP must be
loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the
ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each
miniDSP can run up to 1145 instructions on every audio sample at a 48kHz sample rate. The two cores can run
fully synchronized and can exchange data. The TLV320AIC3262 features the ability to process a multitude of
algorithms simultaneously. For example, the miniDSPs enable simultaneous noise cancellation, acoustic echo
cancellation, sidetone, equalization filtering, dynamic range compression, conversation recording, user-interface
sound mixing, and other voice enhancement processing at voice-band sampling rates (e.g. 8kHz) and high-
defintion voice sampling rates (e.g. 16kHz). The TLV320AIC3262 miniDSPs also enable advanced DSP sound
enhancement algorithms for an enhanced media experience on a portable audio device.
Software
Software development for the TLV320AIC3262 is supported through TI's comprehensive PurePath Studio
Development Environment. A powerful, easy-to-use tool designed specifically to simplify software development
on the TLV320AIC3xxx miniDSP audio platform. The Graphical Development Environment consists of a library of
common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected
together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse.
For more detailed information see the Application Reference Guide, SLAU309.
Asynchronous Sample Rate Conversion (ASRC)
For playing back audio/speech signals at various sampling rates, AIC3262 provides an efficient asynchronous
sampling rate conversion with the combination of a dedicated ASRC coefficient calculator and the DAC miniDSP
engine. The coefficient calculator estimates the audio/speech data input rate versus the DAC playback rate and
feeds the calculated coefficients to the miniDSP, with which it converts the audio/speech data to the DAC
playback rate. The whole process can be configured automatically without the need of any input sampling rate
related information. The input sampling rates as well as the DAC playback rate are not limited to the typical
audio/speech sampling rates. A reliable and efficient handshaking is involved between the miniDSP software and
the coefficient calculator. For detailed information, please refer to the AIC3262 software programming manual.
For more detailed information see the Application Reference Guide, SLAU309.
Power Supply
The TLV320AIC3262 integrates a large amount of digital and analog functionality, and each of these blocks can
be powered separately to enable the system to select appropriate power supplies for desired performance and
power consumption. The device has separate power domains for digital IO, digital core, analog core, analog
input, receiver driver, charge-pump input, headphone driver, and speaker drivers. If desired, all of the supplies
(except for the supplies for speaker drivers, which can directly connect to the battery) can be connected together
and be supplied from one source in the range of 1.65 to 1.95V. Individually, the IOVDD voltage can be supplied
in the range of 1.1V to 3.6V. For improved power efficiency, the digital core power supply can range from 1.26V
to 1.95V. The analog core voltages (AVDD1_18, AVDD2_18, AVDD4_18, and AVDD_18) can range from 1.5V to
1.95V. The microphone bias (AVDD3_33) and receiver driver supply (RECVDD_33) voltages can range from
1.65V to 3.6V. The charge-pump input voltage (CPVDD_18) can range from 1.26V to 1.95V, and the headphone
driver supply (HVDD_18) voltage can range from 1.5V to 1.95V. The speaker driver voltages (SLVDD, SRVDD,
and SPK_V) can range from 2.7V to 5.5V.
For more detailed information see the Application Reference Guide, SLAU309.
Device Special Functions
The following special functions are available to support advanced system requirements:
•
•
•
•
SAR ADC
Headset detection
Interrupt generation
Flexible pin multiplexing
For more detailed information see the Application Reference Guide, SLAU309.
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SLAS679 –DECEMBER 2011
Register Map Summary
Table 12. Summary of Register Map
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
Page Select Register
Software Reset Register
Reserved Registers
1
2-3
0x02-
0x03
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Clock Control Register 1, Clock Input Multiplexers
Clock Control Register 2, PLL Input Multiplexer
Clock Control Register 3, PLL P and R Values
Clock Control Register 4, PLL J Value
5
6
7
8
Clock Control Register 5, PLL D Values (MSB)
Clock Control Register 6, PLL D Values (LSB)
Clock Control Register 7, PLL_CLKIN Divider
Clock Control Register 8, NDAC Divider Values
Clock Control Register 9, MDAC Divider Values
DAC OSR Control Register 1, MSB Value
DAC OSR Control Register 2, LSB Value
Reserved Registers
9
10
11
12
13
14
15-17
0x0F-
0x11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33-35
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
Clock Control Register 10, NADC Values
Clock Control Register 11, MADC Values
ADC Oversampling (AOSR) Register
CLKOUT MUX
Clock Control Register 12, CLKOUT M Divider Value
Timer clock
Low Frequency Clock Generation Control
High Frequency Clock Generation Control 1
High Frequency Clock Generation Control 2
High Frequency Clock Generation Control 3
High Frequency Clock Generation Control 4
High Frequency Clock Trim Control 1
High Frequency Clock Trim Control 2
High Frequency Clock Trim Control 3
High Frequency Clock Trim Control 4
Reserved Registers
0x21-
0x23
0
0
0
0
0
0
0
0
36
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x24
0x25
0x26
ADC Flag Register
DAC Flag Register
DAC Flag Register
Reserved Registers
37
38
39-41
0x27-
0x29
0
0
0
0
0
0
0
0
0
0
0
0
42
43
44
45
46
47
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
Sticky Flag Register 1
Interrupt Flag Register 1
Sticky Flag Register 2
Sticky Flag Register 3
Interrupt Flag Register 2
Interrupt Flag Register 3
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Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0
0
0
48
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x30
0x31
0x32
0x33
INT1 Interrupt Control
INT2 Interrupt Control
SAR Control 1
49
50
51
Interrupt Format Control Register
Reserved Registers
52-59
0x34-
0x3B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
DAC Processing Block and miniDSP Power Control
ADC Processing Block Control
Reserved Register
Primary DAC Power and Soft-Stepping Control
Primary DAC Master Volume Configuration
Primary DAC Left Volume Control Setting
Primary DAC Right Volume Control Setting
Headset Detection
DRC Control Register 1
DRC Control Register 2
DRC Control Register 3
Beep Generator Register 1
Beep Generator Register 2
Beep Generator Register 3
Beep Generator Register 4
Beep Generator Register 5
Beep Sin(x) MSB
Beep Sin(x) LSB
Beep Cos(x) MSB
Beep Cos(x) LSB
Reserved Register
ADC Channel Power Control
ADC Fine Gain Volume Control
Left ADC Volume Control
Right ADC Volume Control
ADC Phase Control
Left AGC Control 1
Left AGC Control 2
Left AGC Control 3
Left AGC Attack Time
Left AGC Decay Time
Left AGC Noise Debounce
Left AGC Signal Debounce
Left AGC Gain
Right AGC Control 1
Right AGC Control 2
Right AGC Control 3
Right AGC Attack Time
Right AGC Decay Time
Right AGC Noise Debounce
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Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
100
101
102
103
104
105
106
107
108
109
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
Right AGC Signal Debounce
Right AGC Gain
ADC DC Measurement Control Register 1
ADC DC Measurement Control Register 2
Left Channel DC Measurement Output Register 1 (MSB Byte)
Left Channel DC Measurement Output Register 2 (Middle Byte)
Left Channel DC Measurement Output Register 3 (LSB Byte)
Right Channel DC Measurement Output Register 1 (MSB Byte)
Right Channel DC Measurement Output Register 2 (Middle Byte)
Right Channel DC Measurement Output Register 3 (LSB Byte)
Reserved Registers
110-114 0x00
0x6E-
0x72
0
0
0
0
115
0x00
0x00
0x00
0x73
I2C Interface Miscellaneous Control
Reserved Registers
116-118 0x00
0x74-
0x76
0
0
0
0
0
0
0
0
119
120
121
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x77
0x78
0x79
miniDSP Control Register 1, Register Access Control
miniDSP Control Register 2, Register Access Control
miniDSP Control Register 3, Register Access Control
Reserved Registers
122-126 0x00
0x7A-
0x7E
0
0
0
0
0
0
0
0
1
1
1
1
1
1
127
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x7F
0x00
0x01
0x02
0x03
0x04
Book Selection Register
Page Select Register
1
Power Configuration Register
Reserved Register
2
3
Left DAC PowerTune Configuration Register
Right DAC PowerTune Configuration Register
Reserved Registers
4
5-7
0x05-
0x07
0
0
0
0
0
0
1
1
1
1
1
1
8
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x08
0x09
0x0A
0x0B
0x0C
Common Mode Register
9
Headphone Output Driver Control
Receiver Output Driver Control
Headphone Output Driver De-pop Control
Receiver Output Driver De-Pop Control
Reserved Registers
10
11
12
13-16
0x0D-
0x10
0
0
0
0
1
1
1
1
17
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x11
0x12
0x13
Mixer Amplifier Control
18
Left ADC PGA to Left Mixer Amplifier (MAL) Volume Control
Right ADC PGA to Right Mixer Amplifier (MAR) Volume Control
Reserved Registers
19
20-21
0x14-
0x15
0
0
0
1
1
1
22
0x00
0x00
0x00
0x01
0x01
0x01
0x16
0x17
Lineout Amplifier Control 1
Lineout Amplifier Control 2
Reserved
23
24-26
0x18-
0x1A
0
0
0
0
1
1
1
1
27
28
29
30
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x1B
0x1C
0x1D
0x1E
Headphone Amplifier Control 1
Headphone Amplifier Control 2
Headphone Amplifier Control 3
Reserved Register
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Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
31
32
33
34
35
36
37
38
39
40
41
42
43-44
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
HPL Driver Volume Control
HPR Driver Volume Control
Charge Pump Control 1
Charge Pump Control 2
Charge Pump Control 3
Receiver Amplifier Control 1
Receiver Amplifier Control 2
Receiver Amplifier Control 3
Receiver Amplifier Control 4
Receiver Amplifier Control 5
Receiver Amplifier Control 6
Receiver Amplifier Control 7
Reserved Registers
0x2B-
0x2C
0
0
0
0
0
1
1
1
1
1
45
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x2D
0x2E
0x2F
0x30
Speaker Amplifier Control 1
Speaker Amplifier Control 2
Speaker Amplifier Control 3
Speaker Amplifier Volume Controls
Reserved Registers
46
47
48
49-50
0x31-
0x32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
51
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
Microphone Bias Control
52
Input Select 1 for Left Microphone PGA P-Terminal
Input Select 2 for Left Microphone PGA P-Terminal
Input Select for Left Microphone PGA M-Terminal
Input Select 1 for Right Microphone PGA P-Terminal
Input Select 2 for Right Microphone PGA P-Terminal
Input Select for Right Microphone PGA M-Terminal
Input Common Mode Control
53
54
55
56
57
58
59
Left Microphone PGA Control
60
Right Microphone PGA Control
61
ADC PowerTune Configuration Register
ADC Analog PGA Gain Flag Register
DAC Analog Gain Flags Register 1
62
63
64
DAC Analog Gain Flags Register 2
65
Analog Bypass Gain Flags Register
Driver Power-Up Flags Register
66
67-118
0x43-
0x76
Reserved Registers
0
0
0
0
0
1
1
1
1
1
119
120
121
122
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x77
0x78
0x79
0x7A
Headset Detection Tuning Register 1
Headset Detection Tuning Register 2
Microphone PGA Power-Up Control Register
Reference Powerup Delay Register
Reserved Registers
123-127 0x00
0x7B-
0x7F
0
0
0
3
3
3
0
1
2
0x00
0x00
0x00
0x03
0x03
0x03
0x00
0x01
0x02
Page Select Register
Reserved Register
Primary SAR ADC Control
54
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SLAS679 –DECEMBER 2011
Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
3
3
3
0x00
0x00
0x03
0x03
0x03
Primary SAR ADC Conversion Mode
Reserved Registers
4-5
0x04-
0x05
0
0
3
3
6
0x00
0x00
0x03
0x03
0x06
SAR Reference Control
Reserved Registers
7-8
0x07-
0x08
0
0
0
3
3
3
9
0x00
0x00
0x00
0x03
0x03
0x03
0x09
0x0A
SAR ADC Flags Register 1
SAR ADC Flags Register 2
Reserved Registers
10
11-12
0x0B-
0x0C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34-53
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
SAR ADC Buffer Mode Control
Reserved Register
Scan Mode Timer Control
Reserved Register
SAR ADC Clock Control
SAR ADC Buffer Mode Data Read Control
SAR ADC Measurement Control
Reserved Register
SAR ADC Measurement Threshold Flags
IN1L Max Threshold Check Control 1
IN1L Max Threshold Check Control 2
IN1L Min Threshold Check Control 1
IN1L Min Threshold Check Control 2
IN1R Max Threshold Check Control 1
IN1R Max Threshold Check Control 2
IN1R Min Threshold Check Control 1
IN1R Min Threshold Check Control 2
TEMP Max Threshold Check Control 1
TEMP Max Threshold Check Control 2
TEMP Min Threshold Check Control 1
TEMP Min Threshold Check Control 2
Reserved Registers
0x22-
0x35
0
0
0
0
0
0
0
3
3
3
3
3
3
3
54
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x36
0x37
0x38
0x39
0x3A
0x3B
IN1L Measurement Data (MSB)
IN1L Measurement Data (LSB)
IN1R Measurement Data (MSB)
IN1R Measurement Data (LSB)
VBAT Measurement Data (MSB)
VBAT Measurement Data (LSB)
Reserved Registers
55
56
57
58
59
60-65
0x3C-
0x41
0
0
0
0
0
3
3
3
3
3
66
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x42
0x43
0x44
0x45
TEMP1 Measurement Data (MSB)
TEMP1 Measurement Data (LSB)
TEMP2 Measurement Data (MSB)
TEMP2 Measurement Data (LSB)
Reserved Registers
67
68
69
70-127
0x46-
0x7F
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Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
Page Select Register
1
Audio Serial Interface 1, Audio Bus Format Control Register
Audio Serial Interface 1, Left Ch_Offset_1 Control Register
2
3
Audio Serial Interface 1, Right Ch_Offset_2 Control Register
Audio Serial Interface 1, Channel Setup Register
Audio Serial Interface 1, Multi-Channel Setup Register 1
Audio Serial Interface 1, Multi-Channel Setup Register 2
Audio Serial Interface 1, ADC Input Control
4
5
6
7
8
Audio Serial Interface 1, DAC Output Control
9
Audio Serial Interface 1, Control Register 9, ADC Slot Tristate Control
Audio Serial Interface 1, WCLK and BCLK Control Register
Audio Serial Interface 1, Bit Clock N Divider Input Control
Audio Serial Interface 1, Bit Clock N Divider
10
11
12
13
14
15
16
17
18
19-22
Audio Serial Interface 1, Word Clock N Divider
Audio Serial Interface 1, BCLK and WCLK Output
Audio Serial Interface 1, Data Output
Audio Serial Interface 1, ADC WCLK and BCLK Control
Audio Serial Interface 2, Audio Bus Format Control Register
Audio Serial Interface 2, Data Offset Control Register
Reserved Registers
0x13-
0x16
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
23
24
25
26
27
28
29
30
31
32
33
34
35-38
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
Audio Serial Interface 2, ADC Input Control
Audio Serial Interface 2, DAC Output Control
Reserved Register
Audio Serial Interface 2, WCLK and BCLK Control Register
Audio Serial Interface 2, Bit Clock N Divider Input Control
Audio Serial Interface 2, Bit Clock N Divider
Audio Serial Interface 2, Word Clock N Divider
Audio Serial Interface 2, BCLK and WCLK Output
Audio Serial Interface 2, Data Output
Audio Serial Interface 2, ADC WCLK and BCLK Control
Audio Serial Interface 3, Audio Bus Format Control Register
Audio Serial Interface 3, Data Offset Control Register
Reserved Registers
0x23-
0x26
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
39
40
41
42
43
44
45
46
47
48
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
Audio Serial Interface 3, ADC Input Control
Audio Serial Interface 3, DAC Output Control
Reserved Register
Audio Serial Interface 3, WCLK and BCLK Control Register
Audio Serial Interface 3, Bit Clock N Divider Input Control
Audio Serial Interface 3, Bit Clock N Divider
Audio Serial Interface 3, Word Clock N Divider
Audio Serial Interface 3, BCLK and WCLK Output
Audio Serial Interface 3, Data Output
Audio Serial Interface 3, ADC WCLK and BCLK Control
56
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TLV320AIC3262
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SLAS679 –DECEMBER 2011
Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
4
49-64
0x00
0x04
0x31-
0x40
Reserved Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
65
66
67
68
69
70
71
72
73
74
75
76
77-81
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
WCLK1 (Input/Output) Pin Control
Reserved Register
DOUT1 (Output) Pin Control
DIN1 (Input) Pin Control
WCLK2 (Input/Output) Pin Control
BCLK2 (Input/Output) Pin Control
DOUT2 (Output) Pin Control
DIN2 (Input) Pin Control
WCLK3 (Input/Output) Pin Control
BCLK3 (Input/Output) Pin Control
DOUT3 (Output) Pin Control
DIN3 (Input) Pin Control
0x4D-
0x51
Reserved Registers
0
0
4
4
82
0x00
0x00
0x04
0x04
0x52
MCLK2 (Input) Pin Control
Reserved Registers
83-85
0x53-
0x55
0
0
0
4
4
4
86
0x00
0x00
0x00
0x04
0x04
0x04
0x56
0x57
GPIO1 (Input/Output) Pin Control
GPIO2 (Input/Output) Pin Control
Reserved Registers
87
88-90
0x58-
0x5A
0
0
0
4
4
4
91
0x00
0x00
0x00
0x04
0x04
0x04
0x5B
0x5C
GPI1 (Input) Pin Control
GPI2 (Input) Pin Control
Reserved Registers
92
93-95
0x5D-
0x5F
0
0
4
4
96
0x00
0x00
0x04
0x04
0x60
GPO1 (Output) Pin Control
Reserved Registers
97-100
0x61-
0x64
0
0
4
4
101
0x00
0x04
0x04
0x65
Digital Microphone Input Pin Control
Reserved Registers
102-117 0x00
0x66-
0x75
0
0
0
4
4
4
118
119
0x00
0x00
0x04
0x04
0x04
0x76
0x77
miniDSP Data Port Control
Digital Audio Engine Synchronization Control
Reserved Registers
120-127 0x00
0x78-
0x7F
0
0
0
0
252
252
252
252
0
0x00
0x00
0x00
0x00
0xFC
0xFC
0xFC
0xFC
0x00
0x01
0x02
Page Select Register
1
SAR Buffer Mode Data (MSB) and Buffer Flags
SAR Buffer Mode Data (LSB)
Reserved Registers
2
3-127
0x03-
0x7F
20
20
0
0
0
0x14
0x14
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-126
0x01-
0x7E
20
20
0
127
0
0x14
0x14
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-26
0x01-
0x1A
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SLAS679 –DECEMBER 2011
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Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
20
1-26
1-7
0x14
0x01-
0x1A
0x01-
0x07
Reserved Registers
20
1-26
8-127
0x14
0x01-
0x1A
0x08-
0x7F
ADC Fixed Coefficients C(0:767)
40
40
40
0
0
0
0
0x28
0x28
0x28
0x00
0x00
0x00
0x00
0x01
Page Select Register
1
ADC Adaptive CRAM Configuration Register
Reserved Registers
2-126
0x02-
0x7E
40
40
0
127
0
0x28
0x28
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-17
0x01-
0x11
40
40
1-17
1-17
1-7
0x28
0x28
0x01-
0x11
0x01-
0x07
Reserved Registers
8-127
0x01-
0x11
0x08-
0x7F
ADC Adaptive Coefficients C(0:509)
40
40
18
18
0
0x28
0x28
0x12
0x12
0x00
Page Select Register
Reserved Registers
1-7
0x01-
0x07
40
40
18
18
8-15
0x28
0x28
0x12
0x12
0x08-
0x0F
ADC Adaptive Coefficients C(510:511)
Reserved Registers
16-127
0x10-
0x7F
60
60
0
0
0
0x3C
0x3C
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-126
0x01-
0x7E
60
60
0
127
0
0x3C
0x3C
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-35
0x01-
0x23
60
60
1-35
1-35
1-7
0x3C
0x3C
0x01-
0x23
0x01-
0x07
Reserved Registers
8-127
0x01-
0x23
0x08-
0x7F
DAC Fixed Coefficients C(0:1023)
80
80
80
0
0
0
0
0x50
0x50
0x50
0x00
0x00
0x00
0x00
0x01
Page Select Register
1
DAC Adaptive Coefficient Bank #1 Configuration Register
Reserved Registers
2-126
0x02-
0x7E
80
80
0
127
0
0x50
0x50
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-17
0x01-
0x11
80
80
1-17
1-17
1-7
0x50
0x50
0x01-
0x11
0x01-
0x07
Reserved Registers
8-127
0x01-
0x11
0x08-
0x7F
DAC Adaptive Coefficient Bank #1 C(0:509)
80
80
18
18
0
0x50
0x50
0x12
0x12
0x00
Page Select Register
Reserved Registers
1-7
0x01-
0x07
80
80
18
18
8-15
0x50
0x50
0x12
0x12
0x08-
0x0F
DAC Adaptive Coefficient Bank #1 C(510:511)
Reserved Registers
16-127
0x10-
0x7F
82
82
0
0
0
1
0x52
0x52
0x00
0x00
0x00
0x01
Page Select Register
DAC Adaptive Coefficient Bank #2 Configuration Register
58
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TLV320AIC3262
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SLAS679 –DECEMBER 2011
Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
82
0
2-126
0x52
0x00
0x02-
0x7E
Reserved Registers
82
82
0
127
0
0x52
0x52
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-17
0x01-
0x11
82
82
1-17
1-17
1-7
0x52
0x52
0x01-
0x11
0x01-
0x07
Reserved Registers
8-127
0x01-
0x11
0x08-
0x7F
DAC Adaptive Coefficient Bank #2 C(0:509)
82
82
18
18
0
0x52
0x52
0x12
0x12
0x00
Page Select Register
Reserved Registers
1-7
0x01-
0x07
82
82
18
18
8-15
0x52
0x52
0x12
0x12
0x08-
0x0F
DAC Adaptive Coefficient Bank #2 C(510:511)
Reserved Registers
16-127
0x10-
0x7F
100
100
0
0
0
0x64
0x64
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-47
0x01-
0x2F
100
100
100
100
0
0
0
0
48
0x64
0x64
0x64
0x64
0x00
0x00
0x00
0x00
0x30
0x31
0x32
ADC miniDSP_A Instruction Control Register 1
ADC miniDSP_A Instruction Control Register 2
ADC miniDSP_A Decimation Ratio Control Register
Reserved Registers
49
50
51-56
0x33-
0x38
100
100
100
0
0
0
57
0x64
0x64
0x64
0x00
0x00
0x00
0x39
0x3A
ADC miniDSP_A Instruction Control Register 3
ADC miniDSP_A ISR Interrupt Control
Reserved Registers
58
59-126
0x3B-
0x7E
100
100
0
127
0
0x64
0x64
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-52
0x01-
0x34
100
100
1-52
1-52
1-7
0x64
0x64
0x01-
0x34
0x01-
0x07
Reserved Registers
8-127
0x01-
0x34
0x08-
0x7F
miniDSP_A Instructions
120
120
0
0
0
0x78
0x78
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-47
0x01-
0x2F
120
120
120
120
0
0
0
0
48
0x78
0x78
0x78
0x78
0x00
0x00
0x00
0x00
0x30
0x31
0x32
DAC miniDSP_D Instruction Control Register 1
DAC miniDSP_D Instruction Control Register 2
DAC miniDSP_D Interpolation Factor Control Register
Reserved Registers
49
50
51-56
0x33-
0x38
120
120
120
0
0
0
57
0x78
0x78
0x78
0x00
0x00
0x00
0x39
0x3A
DAC miniDSP_D Instruction Control Register 3
DAC miniDSP_D ISR Interrupt Control
Reserved Registers
58
59-126
0x3B-
0x7E
120
120
0
127
0
0x78
0x78
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-103
0x01-
0x67
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
59
Product Folder Link(s): TLV320AIC3262
TLV320AIC3262
SLAS679 –DECEMBER 2011
www.ti.com
Table 12. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
120
1-103
1-7
0x78
0x01-
0x67
0x01-
0x07
Reserved Registers
120
1-103
8-127
0x78
0x01-
0x67
0x08-
0x7F
miniDSP_D Instructions
60
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3262
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV320AIC3262IYZFR
TLV320AIC3262IYZFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YZF
YZF
81
81
2500
250
Green (RoHS
& no Sb/Br)
SNAGCU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV320AIC3262IYZFR DSBGA
TLV320AIC3262IYZFT DSBGA
YZF
YZF
81
81
2500
250
330.0
330.0
12.4
12.8
5.04
5.04
5.07
5.07
0.75
0.75
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV320AIC3262IYZFR
TLV320AIC3262IYZFT
DSBGA
DSBGA
YZF
YZF
81
81
2500
250
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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