TLV320AIC3268IRGCR [TI]
TLV320AIC3268 超低功耗立体声音频编解码器 | RGC | 64 | -40 to 85;
| 型号： | TLV320AIC3268IRGCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV320AIC3268 超低功耗立体声音频编解码器 | RGC | 64 | -40 to 85 商用集成电路 编解码器 |
| 文件： | 总265页 (文件大小：5451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
TLV320AIC3268 低功率立体声音频编解码器，具有 105dB 数模转换器 (DAC)，DirectPath 头戴
式耳机和 D 类扬声器放大器以及集成 miniDSP
1 特性
2 应用范围
1
•
立体声音频 DAC 到差分线路输出的 105dB 信噪比
(SNR)
•
•
•
低功率便携式音频器件
消费类音频器件
信息娱乐系统
•
到音频模数转换器 (ADC) 立体声线路输入的 95 dB
SNR
•
•
•
•
8-192kHz 回放和录制
3 说明
24 mW DirectPathTM 头戴式耳机驱动器的输出功率
121 mW 差分接收器输出驱动器的输出功率
D 类扬声器，此扬声器具有
TLV320AIC3268 (AIC3268) 为用户提供一个集成的方
法以实现具备多数字和模拟音频流的音频系统，将其作
为输入源和多输出器件（诸如高功率音频放大器）。
集成的 miniDSP 使得用户能够通过定制音频流信号处
理来使他们的产品与众不同。 这款器件的低功耗使其
成为电池供电运行系统或者运行在受限功耗环境中的系
统的理想选择。
–
–
1.45 W (8Ω，5V，10% THDN)
1.15 W (8Ω，5V，1% THDN)
•
•
•
•
•
•
差分或单端立体声线路输出
AIC3268 是一款集成型、低功率、低压立体声音频编
解码器，并且特有 4 个数字麦克风输入，以及可编程
输出、预先定义且可参数化的数字处理块和一个集成
PLL。 所包含的大范围基于寄存器的功率、输入和输
出通道配置、增益、效应、端子复用以及时钟控制使得
此器件能够精准的针对其目标应用。
8 个单端或 4 个全差分模拟输入
模拟麦克风输入，和多达 4 个同时数字麦克风通道
大范围的信号处理选项
完全可编程增强型 miniDSP
3 个具有单独 I/O 电源电压的独立数字音频串行接
AIC3268 支持 8kHz 声音到 192kHz 立体声音乐的大
范围应用，从而使其成为多种低功率电池供电运行以及
消费类音频应用的理想选择。
口
–
所有音频串行接口 (ASI) 上支持时分复用
(TDM) 和单声道脉冲编码调制 (PCM)
–
ASI 1 上的 8 通道输入和输出
器件信息
•
•
•
可编程锁相环 (PLL)，以及低频计时
可编程 12 位逐次逼近 (SAR) ADC
SPI 和 I2C 控制接口
器件名称
封装
封装尺寸
TLV320AIC3268
VQFN (64)
9mm x 9mm
AIC3268
BIAS
PLL
CHARGE PUMP
4 简化图
Digital
Input
Amplifier
I2
In
S
S
2
ADC
DAC
I
Out
S
BT
M
U
X
I2
In
Audio
Processing
Digital
Input
Amplifier
CD
2
ADC
DAC
I
S
Out
I2
In
S
S/PDIF
Rx
SPI/I2C
ASI-1
ASI-2
ASI-3
SAR
ADC
Analog
Input
Amplifier
REF
TERMINAL MUX
Analog
Out
Analog
In
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLAS953
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化图 ...................................................................... 1
修订历史记录 ........................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 Handling Ratings....................................................... 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 8
7.5 Electrical Characteristics, SAR ADC........................ 9
7.6 Electrical Characteristics, ADC................................ 9
7.7 Electrical Characteristics, Bypass Outputs ............ 12
7.8 Electrical Characteristics, Microphone Interface.... 13
7.9 Electrical Characteristics, Audio DAC Outputs...... 14
7.10 Electrical Characteristics, Class-D Outputs ......... 17
7.11 Electrical Characteristics, Misc. ........................... 18
7.12 Electrical Characteristics, Logic Levels, IOVDDx 21
7.13 Interface Timing .................................................... 22
7.14 Typical Characteristics.......................................... 26
8
9
Detailed Description ............................................ 34
8.1 Overview ................................................................. 34
8.2 Functional Block Diagram ....................................... 35
8.3 Feature Description................................................. 36
8.4 Device Functional Modes...................................... 120
8.5 Programming......................................................... 121
8.6 Register Maps....................................................... 121
Applications and Implementation .................... 243
9.1 Application Information.......................................... 243
9.2 Typical Applications .............................................. 243
9.3 Initialization Setup................................................. 247
10 Power Supply Recommendations ................... 251
11 Layout................................................................. 252
11.1 Layout Guidelines ............................................... 252
11.2 Layout Example .................................................. 253
12 器件和文档支持 ................................................... 254
12.1 社区资源.............................................................. 254
12.2 Trademarks......................................................... 254
12.3 Electrostatic Discharge Caution.......................... 254
12.4 Glossary.............................................................. 254
13 机械封装和可订购信息 ........................................ 255
5 修订历史记录
Changes from Revision Initial Release (January 2014) to Revision A
Page
•
•
已更改生产数据文档状态 ........................................................................................................................................................ 1
已转换为全新的数据表格式..................................................................................................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
6 Terminal Configuration and Functions
space
space
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVDD4_18 49
SPKP 50
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MICBIAS_VDD
MICDET
AVDD1_18
IN4L
SVDD 51
SPKM 52
SPK_V 53
VBAT 54
IN4R
VREF_SAR
VREF_AUDIO
IN1L_AUX1
IN1R_AUX2
IN3L
DVDD_18 55
DVSS 56
VSS
DVSS 57
DOUT2 58
BCLK2 59
GPIO4 60
DVDD_18 61
IOVDD2_33 62
DIN2 63
IN3R
IN2R
IN2L
AVDD_18
MCLK
WCLK2 64
BCLK1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 1. QFN-64(RGC) Package Terminal Assignments (Top View)
Terminal Functions – 64 Terminal QFN (RGC) Package
QFN (RGC)
TERMINAL
NUMBER
POWER
DOMAIN
NAME
I,O,IO,P
DESCRIPTION
Multi Function Digital IO 3
See Table 47
1
2
GPIO3
IO
P
IOVDD2
IOVDD1
IOVDD1_33
Digital I/O Buffer Supply 1 (Not internally connected to terminal no. 10)
Multi Function Digital Output 1
Primary: (SPI_SELECT = 1)
3
MISO_GPO1
O
IOVDD1
SPI Serial Data Output
Secondary: (SPI_SELECT = 0)
See Table 46
Copyright © 2014, Texas Instruments Incorporated
3
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Terminal Functions – 64 Terminal QFN (RGC) Package (continued)
QFN (RGC)
TERMINAL
NUMBER
POWER
DOMAIN
NAME
I,O,IO,P
DESCRIPTION
Control Interface Select
4
SPI_SELECT
I
IOVDD1
SPI_SELECT = '1' : SPI interface selected
SPI_SELECT = '0' : I2C interface selected
Primary: (SPI_SELECT = '1')
SPI interface mode serial data input
Secondary: (SPI_SELECT = '0')
I2C interface mode serial data
Multi Function Digital IO 5
See Table 47
5
6
7
SDA_MOSI
GPIO5
IO
IO
I
IOVDD1
IOVDD1
IOVDD1
Primary: (SPI_SELECT = '1')
SPI Serial Clock
I2C_ADDR_SCLK
Secondary: (SPI_SELECT = '0')
I2C Address Bit (I2C_ADDR)
Primary: (SPI_SELECT = '1')
SPI Chip Select
8
SCL_SSZ
IO
IOVDD1
Secondary: (SPI_SELECT = '0')
I2C Clock
9
DVDD_18
IOVDD1_33
RESET
P
P
I
Digital
1.8V Digital Power Supply (Not internally connected to terminal no. 55)
10
11
IOVDD1
Digital IO Buffer Supply 1 (Not internally connected to terminal no. 2)
Active Low Reset
Primary:
Audio Serial Data Bus 1 Word Clock
Secondary:
12
13
14
WCLK1
GPIO2
DOUT1
IO
IO
O
IOVDD1
IOVDD1
IOVDD1
See Table 46
Multi Function Digital IO 2
See Table 47
Primary:
Audio Serial Data Bus 1 Data Output
Secondary:
See Table 46
Primary:
Audio Serial Data Bus 1 Data Input
Secondary:
15
16
17
DIN1
GPIO1
BCLK1
I
IOVDD1
IOVDD1
IOVDD1
See Table 46
Multi Function Digital IO 1
See Table 47
IO
IO
Primary:
Audio Serial Data Bus 1 Bit Clock
Secondary:
See Table 46
18
19
20
21
22
23
MCLK
AVDD_18
IN2L
I
P
I
IOVDD1
Analog
Analog
Analog
Analog
Analog
Master Clock Input
1.8V Analog Power Supply
Analog Input 2 Left
Analog Input 2 Right
Analog Input 3 Right
Analog Input 3 Left
IN2R
I
IN3R
I
IN3L
I
4
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Terminal Functions – 64 Terminal QFN (RGC) Package (continued)
QFN (RGC)
TERMINAL
NUMBER
POWER
DOMAIN
NAME
I,O,IO,P
DESCRIPTION
Analog Input 1 Right
Auxilliary 2 Input to SAR ADC
(Special Function: Right Channel High Impedance Input for Capacitive Sensor
Measurement)
24
25
IN1R_AUX2
I
Analog
Analog
Analog Input 1 Left
Auxilliary 1 Input to SAR ADC
(Special Function: Left Channel High Impedance Input for Capacitive Sensor
Measurement)
IN1L_AUX1
I
26
27
VREF_AUDIO
VREF_SAR
I
Analog
Analog
Analog Reference Voltage Filter Output
SAR ADC Voltage Reference Input or SAR ADC Internal Voltage Reference
Bypass Capacitor Terminal
IO
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
IN4R
IN4L
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Speaker
Speaker
Speaker
Analog Input 4 Right
I
Analog Input 4 Left
AVDD1_18
MICDET
MICBIAS_VDD
MICBIAS_EXT
MICBIAS
RECP
P
1.8V Analog Power Supply
IO
P
Headset Detection Terminal
Power Supply for Micbias
O
O
O
P
Output Bias Voltage for Headset Microphone
Output Bias Voltage for on-board Microphones
Receiver Driver P side Output
3.3V Power Supply for Receiver Driver
Receiver Driver M side Output
1.8V Analog Power Supply
RECVDD_33
RECM
O
P
AVDD2_18
HPR
O
P
Right Headphone Output
HVDD_18
HPL
Headphone Amplifier Power Supply
Left Headphone Output
O
I
HPVSS_SENSE
VNEG
Headphone Ground Sense Terminal
Charge Pump Negative Supply
Charge Pump Flying Capacitor M Terminal
Charge Pump Flying Capacitor P Terminal
Power Supply Input for Charge Pump
Left Line Output
IO
IO
IO
P
CPFCM
CPFCP
CPVDD_18
LOL
O
O
P
LOR
Right Line Output
AVDD4_18
SPKP
1.8V Analog Power Supply for Speaker Amplifier
P side Speaker Amplifier Output
Speaker Amplifier Output Stage Power Supply
M side Speaker Amplifier Output
O
P
SVDD
SPKM
O
Speaker Amplifier Output Stage Power Supply (Connect to SVDD through a
resistor)
53
SPK_V
P
Speaker
54
55
56
57
VBAT
DVDD_18
DVSS
I
Speaker
Digital
Digital
Digital
Battery Monitor Voltage Input
P
P
P
1.8V Digital Power Supply (Not internally connected to terminal no. 9 and 61)
Digital Ground (Not internally connected to terminal no. 57 and Thermal Pad)
DVSS
Digital Ground (Not internally connected to terminal no. 56 and Thermal Pad)
Primary:
Audio Serial Data Bus 2 Data Output
Secondary:
58
DOUT2
O
IOVDD2
See Table 47
Copyright © 2014, Texas Instruments Incorporated
5
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Terminal Functions – 64 Terminal QFN (RGC) Package (continued)
QFN (RGC)
TERMINAL
NUMBER
POWER
DOMAIN
NAME
I,O,IO,P
DESCRIPTION
Primary:
Audio Serial Bus 2 Bit Clock
59
BCLK2
GPIO4
IO
IO
IOVDD2
IOVDD2
Secondary:
See Table 47
Multi Function Digital IO 4
See Table 47
60
61
62
DVDD_18
P
P
Digital
1.8V Digital Power Supply (Not internally connected to terminal no. 55)
IOVDD2_33
IOVDD2
Digital IO Buffer Supply 2
Primary:
Audio Serial Data Bus 2 Data Input
Secondary:
63
64
DIN2
I
IOVDD2
See Table 47
Primary:
Audio Serial Data Bus 2 Word Clock
Secondary:
WCLK2
VSS
IO
P
IOVDD2
Ground
See Table 47
THERMAL
PAD
Internal Device Ground
6
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 2.2
UNIT
V
AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18 to VSS respectively(2)
RECVDD_33 to VSS
–0.3 to 3.9
V
DVDD_18 to VSS
–0.3 to 2.2
V
IOVDD1_33, IOVDD2_33 to VSS
HVDD_18 to VSS
–0.3 to 3.9
V
–0.3 to 2.2
V
CPVDD_18 to VSS
–0.3 to 2.2
V
SVDD, SPK_V, MICBIAS_VDD to VSS(3)
–0.3 to 6.0
V
Digital Input voltage to VSS
VSS – 0.3 to IOVDDx + 0.3
VSS – 0.3 to AVDDx_18 + 0.3
–0.3 to 6
V
Analog input voltage to VSS
VBAT to VSS
V
V
Junction temperature (TJ Max)
QFN-64 package (RGC) Power dissipation
115
°C
W
(TJ Max – TA) / θJA
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) It's recommended to keep all AVDDx_18 supplies within ±50 mV of each other.
(3) It's recommended to keep SVDD and SPK_V supplies within ±50 mV of each other.
7.2 Handling Ratings
MIN
MAX
125
UNIT
Tstg
Storage temperature range
–55
°C
HBM
CDM
2000
500
ESD
V
7.3 Recommended Operating Conditions
MIN NOM
1.5(2)
1.8
MAX UNIT
AVDD1_18,
AVDD2_18,
AVDD4_18,
AVDD_18
Power Supply Voltage Range Referenced to VSS respectively(1) It is
1.95
V
recommended to connect each of these supplies
to a single supply rail.
RECVDD_33
Referenced to VSS
Referenced to VSS
1.65(3)
1.1
3.3
3.6
3.6
IOVDD1_33,
IOVDD2_33
DVDD_18
CPVDD_18
HVDD_18
SVDD(1)
Power Supply Voltage Range Referenced to VSS
1.26(4)
1.26
1.5(3)
2.7
1.8
1.8
1.8
1.95
1.95
1.95
5.5
Power Supply Voltage Range Referenced to VSS
V
Referenced to VSS
Power Supply Voltage Range Referenced to VSS(1)
Power Supply Voltage Range Referenced to VSS(1)
V
V
V
SPK_V(1)
2.7
5.5
MICBIAS_VD Power Supply Voltage Range Referenced to VSS
D
2.7
5.5
VREF_SAR
External voltage reference for Referenced to VSS
SAR
1.8 AVDDx_18
V
(1) AVDDx_18 are within ±0.05 V of each other. SVDD and SPK_V are within ±0.05 V of each other.
(2) For optimal performance with CM=0.9V, min AVDDx_18 = 1.8V.
(3) Minimum voltage for HVDD_18 and RECVDD_33 should be greater than or equal to AVDDx_18.
(4) At DVDD_18 values lower than 1.65V, the PLL and SAR ADC do not function.
Copyright © 2014, Texas Instruments Incorporated
7
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Recommended Operating Conditions (continued)
MIN NOM
MAX UNIT
PLL Input Frequency(5)
Clock divider uses fractional divide
10
20 MHz
(D > 0), P=1, PLL_CLKIN_DIV=1, DVDD_18 ≥
1.65V
Clock divider uses integer divide
(D = 0), P=1, PLL_CLKIN_DIV=1, DVDD_18 ≥
1.65V
0.512
20 MHz
MCLK
Master Clock Frequency
SCL Clock Frequency
MCLK; Master Clock Frequency; IOVDD1_33 ≥
1.65V
50 MHz
33
MCLK; Master Clock Frequency; IOVDD1_33 ≥
1.1V
SCL
400 kHz
LOL, LOR
Stereo line output load
resistance
0.6
10
16
8
kΩ
HPL, HPR
Stereo headphone output load Single-ended configuration
resistance
14.4
7.2
Ω
Ω
SPKP-SPKM Speaker output load
resistance
Differential
RECP-RECM Receiver output resistance
Differential
24.4
32
10
Ω
CIN
Charge pump input capacitor
(CPVDD to CPVSS terminals)
µF
CO
Charge pump output capacitor Type X7R
(VNEG terminal)
2.2
2.2
µF
µF
CF
Charge pump flying capacitor Type X7R
(CPFCP to CPFCM terminals)
TOPR
Operating Temperature Range
–40
85
°C
(5) The PLL Input Frequency refers to clock frequency after PLL_CLKIN_DIV divider. Frequencies higher than 20MHz can be sent as an
input to this PLL_CLKIN_DIV and reduced in frequency prior to input to the PLL.
7.4 Thermal Information
TLV320AIC3268
THERMAL METRIC(1)
UNIT
RGC TERMINALS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
19.8
5.3
2.9
0.1
2.8
0.3
θJCtop
θJB
°C/W
ψJT
ψJB
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
8
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
7.5 Electrical Characteristics, SAR ADC
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
SAR ADC Inputs
Analog Input Input voltage range
Input capacitance, CSAR_IN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IN1L/AUX1 or IN1R/AUX2 Selected
0
VREF_SAR
V
25
1
pF
µA
V
Input leakage current
Battery Input VBAT Input voltage range
VBAT Input impedance
2.2
8
5.5
12
VBAT (Battery measurement) selected(1)
VBAT (Battery measurement) not selected
5
1
kΩ
µA
VBAT Input leakage current
SAR ADC Conversion
Resolution
Programmable: 8-bit, 10-bit, 12-bit
Bits
LSB
LSB
LSB
%
12-bit
12-bit
8-bit
Integral Linearity
Differential Linearity
Offset error
±0.7
±0.7
0.7
IN1L/AUX1 routed to SAR ADC, 12-bit
resolution, SAR ADC clock = Internal
Oscillator Clock, Conversion Clock =
Internal Oscillator / 4, External Reference =
1.8V(2)
Gain error
±0.01
±0.7
±0.7
0.5
Integral Linearity
Differential Linearity
Offset error
LSB
LSB
LSB
%
IN1L/AUX1 routed to SAR ADC, 12-bit
resolution, SAR ADC clock = 12MHz
External Clock, Conversion Clock =
External Clock / 4, External Reference =
1.8V(2)
Gain error
-0.01
±0.04
±0.04
±0.5
0.2
Integral Linearity
Differential Linearity
Offset error
LSB
LSB
LSB
%
IN1L/AUX1 routed to SAR ADC, 8-bit
resolution, SAR ADC clock = 12MHz
External Clock, Conversion Clock =
External Clock, External Reference =
1.8V(2)
Gain error
Battery
Measurement
Accuracy
VBAT is routed to SAR ADC, 12-bit
resolution, SAR ADC clock = Internal
Oscillator Clock, Conversion Clock =
Internal Oscillator / 4, Internal Reference =
1.25V
-1
%
Offset error
Gain error
±2.1
-0.8
LSB
%
Voltage Reference - VREF_SAR
Voltage range
Internal VREF_SAR
External VREF_SAR
1.25±0.05
V
V
1.25
1
AVDDx_18
Decoupling Capacitor
μF
(1) When VBAT is not being sampled/converted. When VBAT is being sampled, effective input impedance to GND is 5.24kΩ.
(2) When utilizing External SAR reference, this external reference should be restricted VEXT_SAR_REF≤AVDD_18 and AVDD2_18.
7.6 Electrical Characteristics, ADC
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
AUDIO ADC (Single Ended)
Input signal level (0dB)
TEST CONDITIONS
MIN
TYP
MAX UNIT
CM = 0.9V
0.5
VRMS
CM = 0.75V
0.375
1kHz sine wave input, Single-ended Configuration
IN2R to Right ADC and IN2L to Left ADC, Rin = 20kΩ, fs = 48kHz,
AOSR = 128, MCLK = 256*fs, AGC = OFF,
Channel Gain = 0dB, Processing Block = PRB_R1,
Power Tune = PTM_R4
Device Setup
Copyright © 2014, Texas Instruments Incorporated
9
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Electrical Characteristics, ADC (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
Inputs ac-shorted to ground
MIN
TYP
94
MAX UNIT
85
IN1R, IN3R, IN4R each exclusively routed in separate tests to Right
ADC and ac-shorted to ground
94
IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
Signal-to-noise ratio, A- ADC and ac-shorted to ground
SNR
dB
weighted(1) (2)
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC and ac-shorted to ground
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC and ac-shorted to ground
CM=0.75V, AVDD_18,AVDDx_18=1.5V
92
94
92
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC
–60dBr full-scale input
Dynamic range A-
weighted(1) (2)
DR
dB
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC
–60dBr full-scale input, CM=0.75V, AVDD_18,AVDDx_18=1.5V
–3 dBr full-scale signal
-88
-88
-75
IN1R, IN3R, IN4R each exclusively routed in separate tests to Right
ADC
IN1L, IN3L, IN4L each exclusively routed in separate tests to Left
ADC
Total Harmonic
Distortion plus Noise
THD+N
–3dBr full-scale signal
dB
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC
-85
±0.1
-0.1
–3dBr full-scale signal, CM=0.75V, AVDD_18,AVDDx_18=1.5V
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC
-3dBr full-scale signal
Gain Error
dB
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC
-3dBr full-scale signal, CM=0.75V, AVDD_18, AVDDx_18=1.5V
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC and ac shorted to ground
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC and ac shorted to ground
-1518
-1766
Output Offset
LSB
dB
IN1R, IN2R, IN3R, IN4R each exclusively routed in separate tests to
Right ADC and ac shorted to ground
IN1L, IN2L, IN3L, IN4L each exclusively routed in separate tests to
Left ADC and ac shorted to ground
CM=0.75V, AVDD_18, AVDDx_18=1.5V
Inter Channel Gain Error -3dBr full scale signal
Mismatch
± 0.1
(1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with pre-analyzer 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
10
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Electrical Characteristics, ADC (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Inrter Channel
Separation
-3dBr full scale signal
110
dB
-3dBr full scale signal on IN2L and IN2R, IN2L and IN2R not
104
dB
Input Terminal Crosstalk internally routed. IN1L routed to Left ADC and ac-coupled to ground,
IN1R routed to Right ADC and ac-coupled to ground
217Hz, 100mVpp signal on AVDD_18, AVDDx_18, HPVDD_18,
CPVDD_18, IOVDDx_18, DVDD_18
59
59
Power Supply Rejection
Ratio
PSRR
dB
1kHz, 100mVpp signal on AVDD_18, AVDDx_18, HPVDD_18,
CPVDD_18, IOVDDx_18, DVDD_18
IN1L, IN1R, IN2L, IN2R, IN3L, IN3R inputs, Rin=10kΩ
All Inputs, Rin=20K
0
-6
47.5
ADC Analog
Programmable Gain
Amplifier, Gain Range
41.5
35.5
dB
dB
IN1L, IN1R, IN2L, IN2R, IN3L, IN3R inputs, Rin=40kΩ
-12
ADC Analog
Programmable Gain
Amplifier, Gain Step Size
0.5
AUDIO ADC (Differential)
CM=0.9V
1.0
Input signal level (0dB)
VRMS
CM=0.75V
0.75
1kHz sine wave input, Differential Configuration
IN1L, IN1R routed to Right ADC and IN2L, IN2R routed to Left ADC
Rin = 20kΩ, fs = 48kHz, CM=0.9V
AOSR = 128, MCLK = 256*fs, AGC = OFF,
Channel Gain = 0dB, Processing Block = PRB_R1, Power Tune =
PTM_R4
Device Setup
SNR
DR
Signal-to-noise ratio, A- Inputs ac-shorted to ground
87
95
92
(3) (4)
weighted
dB
Inputs ac-shorted to ground, CM=0.75V, AVDD_18,
AVDDx_18=1.5V
Dynamic range A-
weighted(3) (4)
–60dBr full scale signal
95
92
dB
dB
dB
dB
–60dBr full scale signal, CM=0.75V, AVDD_18,AVDDx_18=1.5V
–3dBr full scale
THD+N Total Harmonic
Distortion plus Noise
–89
-76
–3dBr full scale, CM=0.75V, AVDD_18, AVDDx_18=1.5V
–3dBr full scale
-85
Gain Error
±0.02
±0.1
0.1
–3dBr full scale, CM=0.75V, AVDD_18, AVDDx_18=1.5V
Inter Channel Gain Error –3dBr full scale
Mismatch
–3dBr full scale, CM=0.75V, AVDD_18, AVDDx_18=1.5V
0.2
Output Offset
Inputs ac-shorted to ground
-2053
-2198
LSB
Inputs ac-shorted to ground, CM=0.75V, AVDD_18,
AVDDx_18=1.5V
Inter Channel Seperation -3dBr full scale signal
111
117
dB
dB
Input Terminal Crosstalk -3dBr input on IN2L, IN2R. IN2L, IN2R internally not routed.IN1L,
IN1R differentially routed to Right ADC ac-shorted to ground. -3dBr
on IN2L, IN2R. IN2L,IN2R internally not routed.IN3L, IN3R
differentially routed to Left ADC ac-shorted to ground.
PSRR
Power Supply Rejection 217Hz, 100mVpp signal on AVDD_18, AVDDx_18, HPVDD_18,
53
53
Ratio
CPVDD_18, IOVDDx_18, DVDD_18
dB
1kHz, 100mVpp signal on AVDD_18, AVDDx_18, HPVDD_18,
CPVDD_18, IOVDDx_18, DVDD_18
(3) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(4) All performance measurements done with pre-analyzer 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a
filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
Copyright © 2014, Texas Instruments Incorporated
11
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Electrical Characteristics, ADC (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CMRR Common Mode
Rejection Ratio
IN1L, IN1R shorted together and routed to Right ADC. IN2L, IN2R
shorted together and routed to Left ADC. 350mVrms signal on
shorted pairs
68
dB
ADC Analog
Programmable Gain
Amplifier, Gain Range
All Inputs, Rin=10kΩ
All Inputs, Rin=20kΩ
All Inputs, Rin=40kΩ
6
0
53.5
47.5
41.5
dB
dB
-6
ADC Analog
Programmable Gain
Amplifier, Gain Step Size
0.5
7.7 Electrical Characteristics, Bypass Outputs
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO RECEIVER AMPLIFIER, DIRECT MODE
Load = 32Ω (differential), 56pF
Output CM=1.65V
Device Setup
IN1L routed to RECP and IN1R routed to
RECM
Channel Gain=0dB, 1kHz input signal
Full scale differential input voltage
(0dBr)
1
VRMS
Voltage Gain
Gain Error
Noise, A-weighted(1)
1
–0.6
12
V/V
dB
-3dBr input signal
IN1L and IN1R ac-shorted to ground
-3dBr input signal
μVRMS
dB
THD+N Total Harmonic Distortion plus Noise
-90
ANALOG BYPASS TO HEADPHONE AMPLIFIER (GROUND-CENTERED CIRCUIT CONFIGURATION), PGA MODE
Load = 16Ω (single-ended), 1nF
IN1L routed to ADCPGA_L, ADCPGA_L
routed through MAL to HPL and IN1R routed
to ADCPGA_R, ADCPGA_R routed through
Device Setup
MAR to HPR
Rin = 20K, Channel Gain = 0dB
Full scale input voltage (0dBr)
Voltage Gain
0.5
1
VRMS
V/V
Gain Error
Noise, A-weighted(1)
-3dBr input signal
-0.8
10.3
-71
dB
IN1L and IN1R ac-shorted to ground
-3dBr input signal
μVRMS
dB
THD+N Total Harmonic Distortion plus Noise
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Load = 10KΩ (single-ended), 56pF
Output CM=0.9V
IN1L routed to ADCPGA_L, ADCPGA_L
routed through MAL to LOL and IN1R routed
to ADCPGA_R, ADCPGA_R routed through
MAR to LOR
Device Setup
Rin = 20K, Channel Gain = 0dB
Full scale input voltage (0dBr)
0.5
VRMS
(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
12
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Electrical Characteristics, Bypass Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
Voltage Gain
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
V/V
Gain Error
-1dBr input signal
–0.9
6
dB
(2)
Noise, A-weighted
IN1L and IN1R ac-shorted to ground
-3dBr input signal
μVRMS
dB
THD+N Total Harmonic Distortion plus Noise
-87
ANALOG BYPASS TO LINE-OUT AMPLIFIER, DIRECT MODE
Load = 10KΩ (single-ended), 56pF
Output CM=0.9V
IN1L routed to LOL and IN1R routed to LOR
Channel Gain = 0dB
Device Setup
Full scale input voltage (0dBr)
Voltage Gain
0.5
1
VRMS
V/V
Gain Error
Noise, A-weighted(2)
-3dBr input signal
-0.4
3
dB
IN1L and IN1R ac-shorted to ground
-3dBr input signal
μVRMS
dB
THD+N Total Harmonic Distortion plus Noise
-95
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
7.8 Electrical Characteristics, Microphone Interface
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
MICROPHONE BIAS (MICBIAS or MICBIAS_EXT)
Bias voltage
Micbias Mode 0, No Load Current
Micbias Mode 1, Load Current = 8mA
Micbias Mode 4, No Load Current(1)
Micbias Mode 5, No Load Current(1)
1.8
2.0
V
1.85
2.15
V
V
V
V
2.9
3.0
Micbias Mode 0, No Load Current, CM=0.75V,
AVDD_18, AVDDx_18=1.5V
1.50
Micbias Mode 1, No Load Current, CM=0.75V,
AVDD_18, AVDDx_18=1.5V
1.7
2.4
2.5
6.4
V
V
V
Micbias Mode 4, No Load Current, CM=0.75V,
AVDD_18, AVDDx_18=1.5V
Micbias Mode 5, No Load Current, CM=0.75V,
AVDD_18, AVDDx_18=1.5V
Output Noise
Micbias Mode 1, A-weighted, 20Hz to 20kHz
bandwidth,
μVRMS
Current load = 0mA.
Current Sourcing
Micbias Mode 0, 1, 4, or 5
8
mA
(1) With Common Mode voltage of 0.9V, the MICBIAS_VDD voltage must be at minimum 3.05V to utilize Micbias Mode 4, and minimum of
3.2V to utilize Micbias Mode 5. With Common Mode voltage of 0.75V, the corresponding MICBIAS_VDD voltage must be minimum of
2.65V and 2.75V respectively.
Copyright © 2014, Texas Instruments Incorporated
13
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Electrical Characteristics, Microphone Interface (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
217Hz, 100mVpp signal on AVDD_18,
AVDDx_18, HVDD_18, CPVDD_18, DVDD_18,
IOVDDx_33, Micbias Mode 1
51
dB
217Hz, 100mVpp signal on MICBIAS_VDD,
CM=0.9V, Micbias Mode 1
93
51
88
dB
dB
dB
PSRR Power Supply Rejection Ratio(2)
1kHz, 100mVpp signal on AVDDx_18,
DVDD_18, IOVDDx, CM=0.9V, Micbias Mode 1
1kHz, 100mVpp signal on MICBIAS_VDD,
CM=0.9V, Micbias Mode 1
(2) PSRR is specified as 20*log10(Vsup/Vout), where Vsup is the signal applied on the power supply and Vout is the measured analog output.
For ADC, Vout is given as equivalent analog input signal which produces the same level of digital output signal.
7.9 Electrical Characteristics, Audio DAC Outputs
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT
Load = 10kΩ (single-ended), 56pF
CM=0.9V
DOSR = 128, MCLK=256* fs
Channel Gain = 0dB
Device Setup
Processing Block = PRB_P1, Power Tune =
PTM_P4
Full scale output voltage (0dBr)
0.5
0.375
102
VRMS
CM = 0.75V, AVDD_18, AVDDx_18 = 1.5V
Signal-to-noise ratio A-weighted(1) (2) All zeros fed to DAC input
88
SNR
DR
dB
dB
All zeros fed to DAC input, CM=0.75V,
AVDD_18,AVDDx_18=1.5V
–60dBFS input signal
99
(1) (2)
Dynamic range, A-weighted
102
99
–60dBFS input signal, CM=0.75V,
AVDD_18,AVDDx_18=1.5V
Total Harmonic Distortion plus Noise
DAC Gain Error
–3dBFS input signal
–93
-91
-72
dB
THD+N
–3dBFS input signal, CM=0.75V,
AVDD_18,AVDDx_18=1.5V
–3dBFS input signal
±0.01
0.1
dB
dB
–3dBFS input signal, CM=0.75V,
AVDD_18,AVDDx_18=1.5V
Inter Channel Gain Mismatch
–3dBFS input signal
± 0.0
±0.0
–3dBFS input signal, CM=0.75V,
AVDD_18,AVDDx_18=1.5V
DAC Mute Attenuation
DAC channel separation
Digital Volume Control is Muted
126
114
dB
dB
–3dBFS, 1kHz signal, between left and right Line
out
(1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
14
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Electrical Characteristics, Audio DAC Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
217Hz, 100mVpp signal applied to AVDD_18,
AVDDx_18,
74
dB
HVDD_18,CPVDD_18,IOVDDx_33,DVDD_18
PSRR
RL
Power Supply Rejection Ratio(3)
1kHz, 100mVpp signal applied to AVDD_18,
AVDDx_18,HVDD_18,CPVDD_18,IOVDDx_33,DVD
D_18
73
10
dB
Output Resistive Load(4)
Resistance to ground
9
kΩ
AUDIO DAC – STEREO DIFFERENTIAL LINE OUTPUT
Load = 10kΩ (differential), 56pF between
RECP,RECMM and LOL,LOR
Left DAC routed directly to RECP,RECM, Right
DAC routed to LOL,LOR
Output CM=0.9V
DOSR = 128, MCLK=256* fs
Channel Gain = 0dB
Device Setup
Processing Block = PRB_P1, Power Tune =
PTM_P4
RECVDD_33, AVDD_18, AVDDx_18=1.8V
Full scale output voltage (0dBr)
1
VRMS
CM = 0.75V, AVDD_18, AVDDx_18,
RECVDD_33=1.5V
0.75
Signal-to-noise ratio A-weighted(1) (2) All zeros fed to DAC input
92
105
103
SNR
DR
dB
All zeros fed to DAC input, CM=0.75V,
AVDD_18, AVDDx_18, RECVDD_33=1.5V
–60dBFS input signal
(5) (6)
Dynamic range, A-weighted
105
102
dB
–60dBFS input full-scale signal, CM=0.75V,
AVDD_18, AVDDx_18, RECVDD_33=1.5V
Total Harmonic Distortion plus Noise
DAC Gain Error
–3dBFS input signal
-94
-92
-75
dB
THD+N
–3dBFS input signal, CM=0.75V,
AVDD_18, AVDDx_18, RECVDD_33=1.5V
–3dBFS input signal
±0.03
±0.04
dB
–3dBFS input signal, CM=0.75V,
AVDD_18, AVDDx_18, RECVDD_33=1.5V
Inter Channel Gain Mismatch
Output Offset
-3dBFS input signal
0.0
±0.5
±0.4
dB
All zero's fed to DAC Input
mV
All zero's fed to DAC Input, CM=0.75V
AVDD_18, AVDDx_18, RECVDD_33=1.5V
DAC Mute Attenuation
Digital Volume Control is Muted
126
93
dB
dB
PSRR
217kHz, 100mVpp signal applied to AVDD_18,
AVDDx_18, RECVDD_33, HVDD_18, CPVDD_18,
IOVDDx_33, DVDD_18
Power Supply Rejection Ratio(7)
1kHz, 100mVpp signal applied to AVDD_18,
AVDDx_18, RECVDD_33, HVDD_18, CPVDD_18,
IOVDDx_33, DVDD_18
92
dB
(3) PSRR is specified as 20*log10(Vsup/Vout), where Vsup is the signal applied on the power supply and Vout is the measured analog output.
For ADC, Vout is given as equivalent analog input signal which produces the same level of digital output signal.
(4) Minimum resistive load and Maximum capacitive load are specified by design.
(5) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(6) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(7) PSRR is specified as 20*log10(Vsup/Vout), where Vsup is the signal applied on the power supply and Vout is the measured analog output.
For ADC, Vout is given as equivalent analog input signal which produces the same level of digital output signal.
Copyright © 2014, Texas Instruments Incorporated
15
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www.ti.com.cn
Electrical Characteristics, Audio DAC Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RL
Output Resistive Load(8)
Resistance between LOL , LOR and RECP, RECM
9
10
kΩ
AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (GROUND-CENTERED CIRCUIT CONFIGURATION)
Load = 16Ω (single-ended), 1nF
DOSR = 128, MCLK=256* fs
Channel Gain = 0dB
Processing Block = PRB_P1, Power Tune =
Device Setup
PTM_P3
Headphone Output Strength=100%
Full-scale Output voltage (0dBr)
0.5
VRMS
CM=0.75V,
0.375
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18=1.5V
(9)
Signal-to-noise ratio, A-weighted
All zeros fed to DAC input
88
94
93
(10)
All zeros fed to DAC input
SNR
DR
dB
CM=0.75V,
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18=1.5V
(9) (10)
Dynamic range, A-weighted
–60dBFS input signal
95
94
–60dBFS input signal
CM=0.75V,
dB
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18=1.5V
Total Harmonic Distortion plus Noise
DAC Gain Error
–3dBFS input signal
-69
-71
-60
dB
–3dBFS input signal
CM=0.75V,
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18=1.5V
THD+N
–3dBFS input signal
±0.1
0.2
–3dBFS input signal
CM=0.75V,
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18=1.5V
dB
dB
Inter Channel Gain Mismatch
–3dBFS input signal
±0.1
±0.1
–3dBFS input signal
CM=0.75V,
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18=1.5V
DAC Mute Attenuation
DAC channel separation
Output Offset
Analog Volume Control is Muted
Between HPL, HPR at –3dBFS input signal
All zeros fed to DAC
139
80
dB
dB
mV
dB
±0.1
67
217Hz, 100mVpp signal applied to
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,IOVDD
x_33,DVDD_18
PSRR
Power Supply Rejection Ration(11)
1kHz, 100mVpp signal applied to
AVDD_18,AVDDx_18,HVDD_18,CPVDD_18,IOVDD
x_33,DVDD_18
70
dB
THD+N=0.1%
17
24
8
THD+N=1%, Headphone Gain=5dB
THD+N=0.1%, RL=32Ω
Power Delivered
mW
THD+N=1%, Headphone Gain=5dB, RL=32Ω
21
(8) Minimum resistive load and Maximum capacitive load are specified by design.
(9) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(10) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(11) PSRR is specified as 20*log10(Vsup/Vout), where Vsup is the signal applied on the power supply and Vout is the measured analog output.
For ADC, Vout is given as equivalent analog input signal which produces the same level of digital output signal.
16
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Electrical Characteristics, Audio DAC Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
Output Load(12)
AUDIO DAC – MONO DIFFERENTIAL RECEIVER OUTPUT
Load = 32Ω (differential), 56pF
TEST CONDITIONS
MIN
14.4
TYP
MAX UNIT
RL
Resistive Load to ground
16
Ω
Output CM=1.65V
DOSR = 128, MCLK=256* fs
Left DAC routed to RECP, RECM, Channel
(Receiver Driver) Gain = 6dB for full scale output
signal
Device Setup
Processing Block = PRB_P4, Power Tune =
PTM_P4
Full scale output voltage (0dBr)
2
VRMS
dB
Signal-to-noise ratio, A-weighted(13)
All zeros fed to DAC input
90
102
SNR
(14)
(13) (14)
DR
Dynamic range, A-weighted
–60dBFS input signal
–3dBFS input signal
103
-91
62
dB
THD+N
Total Harmonic Distortion plus Noise
Power Supply Rejection Ratio(11)
-70
dB
dB
217Hz, 100mVpp signal applied to AVDD_18,
AVDD1x_18,HVDD_18,
CPVDD_18,IOVDDx_33,DVDD_18
PSRR
1kHz, 100mVpp 217Hz signal applied to AVDD_18,
AVDD1x_18,HVDD_18,
59
CPVDD_18,IOVDDx_33,DVDD_18
1kHz, 100mVpp signal applied on RECVDD_33
All zero's fed to DAC, Offset Correction Enabled
THD+N ≤ 0.1%
89
±0.5
72
Output Offset
mV
Power Delivered
mW
THD+N ≤ 1%
121
mW
(12) Minimum resistive load and Maximum capacitive load are specified by design.
(13) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20Hz to 20kHz bandwidth using an audio analyzer.
(14) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
7.10 Electrical Characteristics, Class-D Outputs
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8Ω (Differential), 33µH
BTL Load = 8Ω, 33µH between SPKP and SPKM
Device Setup
Lineout routed to Class-D
PRB_P1, PTM_P4, DOSR=128, MCLK=256*FS
0dBFS input signal, Class-D gain=12dB, THD+N ≤
–20dB
2.7
3.5
Output voltage
VRMS
SVDD=5.0V
0dBFS input signal, Class-D gain=12dB, THD+N ≤
–20dB
Class-D gain=6dB(1)
45
46
140
Idle Channel Noise
µVRMS
SVDD=5.0V
Class-D gain=6dB(1)
(1) All performance measurements done with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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Electrical Characteristics, Class-D Outputs (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
-3dBFS input signal, Class-D gain=6dB
All zero's fed to DAC, Class-D gain=6dB
MIN
TYP
MAX
UNIT
Total harmonic distortion
+ noise
THD+N
PSRR
-68
dB
Output Offset
±12.1
64
mV
dB
217Hz, 200 mVp-p signal on SVDD, Class-D
gain=6dB
Power-supply rejection
ratio(2)
1kHz, 200 mVp-p signal on SVDD, Class-D gain=6dB
Analog Mute Only
64
104
dB
dB
Mute attenuation
SVDD = 3.6 V
0.65
0.81
1.15
0.74
1.02
1.45
THD+N = 1%, f = 1 kHz,
Class-D gain = 12 dB
SVDD = 4.2 V
SVDD = 5.0 V
SVDD = 3.6 V
PO
Maximum output power
W
THD+N = 10%, f = 1 kHz,
Class-D gain = 12 dB
SVDD = 4.2 V
SVDD = 5.0 V
Over Temperature
>104
20
C
C
Protection Trip Point(3)
Over Temperature
Protection Hysterisis(3)
Over Current Trip
Threshold(4)
>850
mA
(2) PSRR is specified as 20*log10(Vsup/Vout), where Vsup is the signal applied on the power supply and Vout is the measured analog output.
For ADC, Vout is given as equivalent analog input signal which produces the same level of digital output signal.
(3) Over Temperature and Over Current Protection parameters are indicative values from design. Over Temperature trip point can be very
heavily influenced by thermal properties of the actual PCB.
(4) Over Temperature and Over Current Protection parameters are indicative values from design. Over Temperature trip point can be very
heavily influenced by thermal properties of the actual PCB.
7.11 Electrical Characteristics, Misc.
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE - VREF_AUDIO
CMMode = 0 (0.9V)
0.9
0.75
1
Reference Voltage Settings
V
CMMode = 1 (0.75V)
Decoupling Capacitor
Bias Current
μF
μA
Reference forcefully powered on.
101
miniDSP
miniDSP clock frequency - ADC
DVDD_18 = 1.26V
DVDD_18 = 1.65V
DVDD_18 = 1.71V
DVDD_18 = 1.26V
DVDD_18 = 1.65V
DVDD_18 = 1.71V
37.5
63
MHz
MHz
69
miniDSP clock frequency - DAC
35.0
59.0
62.5
Shutdown Power
Coarse AVdd supply turned off, All External
analog supplies powered and set available,
No external digital input is toggled, register
values are retained.
Device Setup
18
Copyright © 2014, Texas Instruments Incorporated
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Electrical Characteristics, Misc. (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
P(total)
Sum of all supply currents, all supplies at 1.8
V except for SVDD = SPK_V =
MICBIAS_VDD = 3.6 V and RECVDD_33 =
3.3 V
1.4
μW
I(DVDD_18)
0.02
0.17
0.13
μA
μA
μA
I(IOVDD1_33, IOVDD2_33)
I(AVDD1_18, AVDD2_18, AVDD4_18,
AVDD_18, HVDD_18, CPVDD_18)
I(RECVDD_33)
0.01
0.22
μA
μA
I(SVDD, SPK_V, MICBIAS_VDD)
Active Power
Device Setup
fS=48ksps, PLL disabled, Device is I2S slave,
Stereo ADC record, AGC disabled
PTM_R4,PRB_P1
I(DVDD_18)
4
28
mA
µA
I(IOVDD1_18,IOVDD2_18)
I(AVDD1_18, AVDD2_18,
AVDD4_18,AVDD_18, HVDD_18,
CPVDD_18)
6.9
mA
I(RECVDD_33)
0
µA
µA
I(SVDD, SPK_V,MICBIAS_VDD)
Device Setup
0.2
fS=8ksps, PLL disabled, Device is I2S slave,
Stereo ADC record, AGC disabled
PTM_R4,PRB_P1
I(DVDD_18)
0.9
5
mA
µA
I(IOVDD1_18,IOVDD2_18)
I(AVDD1_18, AVDD2_18,
AVDD4_18,AVDD_18, HVDD_18,
CPVDD_18)
6.7
mA
I(RECVDD_33)
0
µA
µA
I(SVDD, SPK_V,MICBIAS_VDD)
Device Setup
0.2
fS=48ksps, PLL disabled; Device is I2S slave
Stereo DAC Playback on Stereo Single-ended
Lineout;
PTM_P4; PRB_P1;
All zeros on I2S input; DAC Modualtor
excited;
Input CM=0.9V
I(DVDD_18)
4.8
6
mA
µA
I(IOVDD1_18,IOVDD2_18)
I(AVDD1_18, AVDD2_18,
AVDD4_18,AVDD_18, HVDD_18,
CPVDD_18)
1.9
mA
I(RECVDD_33)
0
µA
µA
(SVDD, SPK_V,MICBIAS_VDD)
Device Setup
0.2
fS=48ksps, PLL disabled; Device is I2S slave
Stereo DAC Playback on Stereo Differential
Lineout;
PTM_P4; PRB_P1;
All zeros on I2S input; DAC Modualtor
excited;
Input CM=0.9V
I(DVDD_18)
5.3
mA
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Electrical Characteristics, Misc. (continued)
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
7
MAX
UNIT
µA
I(IOVDD1_18,IOVDD2_18)
I(AVDD1_18, AVDD2_18,
AVDD4_18,AVDD_18, HVDD_18,
CPVDD_18)
2.3
mA
I(RECVDD_33)
2
mA
µA
I(SVDD, SPK_V,MICBIAS_VDD)
Device Setup
0.2
fS=48ksps, PLL disabled; Device is I2S slave
Stereo DAC Playback on Headphones
(Ground Centered Mode);
PTM_P4; PRB_P1;
All zeros on I2S input; DAC Modualtor
excited;
Input CM=0.9V
I(DVDD_18)
5.2
6
mA
µA
I(IOVDD1_18,IOVDD2_18)
I(AVDD1_18, AVDD2_18,
AVDD4_18,AVDD_18, HVDD_18,
CPVDD_18)
6.4
mA
I(RECVDD_33)
0
µA
µA
I(SVDD, SPK_V,MICBIAS_VDD)
Device Setup
0.2
fS=48ksps, PLL disabled; Device is I2S slave
Mono DAC Playback on Speaker Amp ;
PTM_P4; PRB_P1;
All zeros on I2S input; DAC Modualtor
excited;
Input CM=0.9V
I(DVDD_18)
3.3
5
mA
µA
I(IOVDD1_18,IOVDD2_18)
I(AVDD1_18, AVDD2_18,
AVDD4_18,AVDD_18, HVDD_18,
CPVDD_18)
1.9
mA
I(RECVDD_33)
0
µA
I(SVDD, SPK_V,MICBIAS_VDD)
Device Setup
6.7
mA
fS=48ksps, PLL disabled; Device is I2S slave
Mono DAC Playback on Receiver Amp ;
PTM_P4; PRB_P1;
All zeros on I2S input; DAC Modualtor
excited;
Input CM=0.9V, Receiver Amp Output
CM=1.65V
I(DVDD_18)
3.1
6
mA
µA
I(IOVDD1_18,IOVDD2_18)
I(AVDD1_18, AVDD2_18,
AVDD4_18,AVDD_18, HVDD_18,
CPVDD_18)
1.4
mA
I(RECVDD_33)
2.3
0.2
mA
µA
I(SVDD, SPK_V,MICBIAS_VDD)
20
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
7.12 Electrical Characteristics, Logic Levels, IOVDDx
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V; SVDD,
SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on VREF_SAR and
VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
PARAMETER
Digital IO (When SPI_SELECT = '1', all terminals, When SPI_SELECT = '0', all terminals except SCL, SDA)
LOGIC FAMILY CMOS
VIH Logic Level
TEST CONDITIONS
MIN
TYP
MAX UNIT
IIH = 5 μA, IOVDDx_33 > 1.65V
IIH = 5μA, 1.2V ≤ IOVDDx_33 <1.65V
IIH = 5μA, IOVDDx_33 < 1.2V
0.7 × IOVDDx_33
0.9 × IOVDDx_33
IOVDDx_33
–0.3
V
V
V
VIL
IIL = 5 μA, IOVDDx_33 > 1.65V
0.3 × IOVDDx_33
V
V
IIL = 5μA, 1.2V ≤ IOVDDx_33 <1.65V
IIL = 5μA, IOVDDx_33 < 1.2V
0.1 × IOVDDx_33
0
V
VOH
IOH = 3mA load, IOVDDx_33 > 1.65V
IOH = 1mA load, IOVDDx_33 < 1.65V
IOL = 3mA load, IOVDDx_33 > 1.65V
IOL = 1mA load, IOVDDx_33 < 1.65V
0.8 × IOVDDx_33
0.8 × IOVDDx_33
V
V
VOL
0.2 × IOVDDx_33
0.2 × IOVDDx_33
V
V
Capacitive Load
10
pF
Digital IO (SCL, SDA when SPI_SELECT = '0')
LOGIC FAMILY
OPEN
DRAIN
VIH
VIL
0.7 × IOVDD1_33
–0.3
V
V
V
V
0.3 × IOVDD1_33
0.4
VOL
IOL = 3mA load, IOVDD1_33 > 2V
IOL = 2mA load, IOVDD1_33 ≤ 2V
0.2 × IOVDD1_33
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7.13 Interface Timing
Note: All timing specifications are measured at characterization but not tested at final test. The audio serial interface timing
specifications are applied to Audio Serial Interface 1, Audio Serial Interface 2 and Audio Serial Interface 3.
7.13.1 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
WCLK represents WCLK1 terminal for Audio Serial Interface 1, WCLK2 terminal for Audio Serial Interface 2 and Word Clock
for Audio Serial Interface 3. BCLK represents BCLK1 terminal for Audio Serial Interface 1, BCLK2 for Audio Serial Interface 2
and Bit Clock for Audio Serial Interface 3. DOUT represents DOUT1 terminal for Audio Serial Interface 1, DOUT2 for Audio
Serial Interface 2 and Data Out for Audio Serial Interface 3. DIN represents DIN1 terminal for Audio Serial Interface 1, DIN2
for Audio Serial Interface 2 and Data In for Audio Serial Interface 3. Specifications are at 25° C with DVDD_18 = 1.8V.
WCLK
t
d(WS)
BCLK
t
d(DO-BCLK)
t
d(DO-WS)
DOUT
t
t
h(DI)
S(DI)
DIN
Figure 2. I2S,LJF,RJF Timing in Master Mode
Table 1. I2S,LJF,RJF Timing in Master Mode (see Figure 2)
PARAMETER
IOVDDx=1.8V
IOVDDx=3.3V
UNIT
MIN
MAX
MIN
MAX
td(WS)
WCLK delay
23
28
25
17
23
19
ns
ns
ns
ns
ns
ns
ns
td (DO-WS)
WCLK to DOUT delay (For LJF Mode only)
BCLK to DOUT delay
DIN setup
td (DO-BCLK)
ts(DI)
th(DI)
tr
7
5
8
5
DIN hold
BCLK Rise time
7
5
6
tf
BCLK Fall time
10
22
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
WCLK
th(WS)
ts(WS)
tL(BCLK)
td(DO-WS)
tH(BCLK)
td(DO-BCLK)
BCLK
DOUT
DIN
th(DI)
ts(DI)
Figure 3. I2S,LJF,RJF Timing in Slave Mode
Table 2. I2S,LJF,RJF Timing in Slave Mode (see Figure 3)
PARAMETER
IOVDDx=1.8V
IOVDDx=3.3V
UNIT
MIN
34
34
7
MAX
MIN
30
30
7
MAX
tH (BCLK)
tL (BCLK)
ts (WS)
BCLK high period
ns
BCLK low period
WCLK setup
th (WS)
WCLK hold
5
5
td (DO-WS)
WCLK to DOUT delay (For LJF mode only)
BCLK to DOUT delay
DIN setup
28
26
24
21
td (DO-BCLK)
ts(DI)
th(DI)
tr
5
5
5
5
DIN hold
BCLK Rise time
BCLK Fall time
5
5
4
4
tf
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7.13.2 Typical DSP Timing Characteristics
Specifications are at 25° C with DVDD_18 = 1.8 V.
WCLK
th(WS)
ts(WS)
tL(BCLK)
td(DO-WS)
tH(BCLK)
td(DO-BCLK)
BCLK
DOUT
DIN
th(DI)
ts(DI)
Figure 4. DSP,Mono PCM Timing in Master Mode
Table 3. DSP,Mono PCM Timing in Master Mode (see Figure 4)
PARAMETER
IOVDDx=1.8V
IOVDDx=3.3V
UNIT
MIN
MAX
MIN
MAX
td (WS)
WCLK delay
22
25
17
19
ns
ns
ns
ns
ns
ns
td (DO-BCLK)
BCLK to DOUT delay
DIN setup
ts(DI)
th(DI)
tr
5
5
5
5
DIN hold
BCLK Rise time
BCLK Fall time
7
5
6
tf
10
WCLK
t
t
h(ws)
t
h(ws)
t
s(ws)
h(ws)
t
BCLK
DOUT
DIN
L(BCLK)
t
H(BCLK)
t
d(DO-BCLK)
t
t
h(DI)
s(DI)
Figure 5. DSP/Mono PCM Timing in Slave Mode
Table 4. DSP,Mono PCM Timing in Slave Mode (see Figure 5)
PARAMETER
IOVDDx=1.8V
IOVDDx=3.3V
UNIT
MIN
31
31
6
MAX
MIN
25
25
6
MAX
tH (BCLK)
tL (BCLK)
ts(WS)
BCLK high period
BCLK low period
WCLK setup
ns
ns
ns
ns
th(WS)
WCLK hold
5
5
td (DO-BCLK)
BCLK to DOUT delay
DIN setup
26
20
ns
ns
ns
ns
ns
ts(DI)
th(DI)
tr
5
5
5
5
DIN hold
BCLK Rise time
BCLK Fall time
5
5
4
4
tf
24
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7.13.3 I2C Interface Timing
Figure 6. I2C Interface Timing Diagram
Table 5. I2C Interface Timing (see Figure 6)
PARAMETER
Standard-Mode
Fast-Mode
UNIT
MIN
0
MAX
MIN
0
MAX
fSCL
SCL clock frequency
100
400
kHz
tHD;STA
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
4.0
0.8
μs
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time: For I2C bus devices
Data set-up time
4.7
4.0
4.7
0
1.3
0.6
0.8
0
μs
μs
μs
μs
ns
ns
ns
μs
μs
3.45
0.9
250
100
SDA and SCL Rise Time
1000
300
20 + 0.1Cb
300
300
tf
SDA and SCL Fall Time
20 + 0.1Cb
0.8
tSU;STO
tBUF
Set-up time for STOP condition
4.0
4.7
Bus free time between a STOP and START
condition
1.3
Cb
Capacitive load for each bus line
400
400
pF
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7.13.4 SPI Interface Timing
SS = SCL terminal, SCLK = I2C_ADDR_SCLK terminal, MISO = GPO1 terminal, and MOSI = SDA terminal. Specifications
are at 25° C with DVDD_18 = 1.8V.
SS
t
td
tLag
t
tLead
sck
tf
tr
SCLK
MISO
tsckl
tsckh
tv(DOUT)
tdis
MSB OUT
th(DIN)
BIT 6 . . . 1
LSB OUT
t
a
tsu
MOSI
MSB IN
BIT 6 . . . 1
LSB IN
Figure 7. SPI Interface Timing Diagram
Table 6. SPI Interface Timing
PARAMETER
IOVDD1=1.8V
IOVDD1=3.3V
UNIT
MIN
48
24
24
24
24
20
MAX
MIN
40
20
20
20
20
20
MAX
tsck
tsckh
tsckl
tlead
tlag
SCLK Period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse width High
SCLK Pulse width Low
SS Lead Time
SS Lag Time
td;seqxfr
ta
Sequential Transfer Delay
Slave DOUT (MISO) access time
Slave DOUT (MISO) disable time
DIN (MOSI) data setup time
DIN (MOSI) data hold time
DOUT (MISO) data valid time
SCLK Rise Time
19
20
13
13
tdis
tsu
8
9
7
7
th;DIN
tv;DOUT
tr
19
4
15
4
tf
SCLK Fall Time
4
4
7.14 Typical Characteristics
TA = 25°C; AVDD_18, AVDDx_18, HVDD_18, CPVDD_18, DVDD_18, IOVDDx_33 = 1.8V; RECVDD_33 = 3.3V;
SVDD, SPK_V, MICBIAS_VDD = 3.6V; fS (Audio) = 48kHz; Audio Word Length = 20 bits; Cext = 1μF on
VREF_SAR and VREF_AUDIO terminals; PLL disabled, Device CM = 0.9V unless otherwise noted.
26
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Typical Characteristics (continued)
7.14.1 SAR ADC Performance
1.0
1.0
0.8
0.5
0.5
0.3
0.0
0.0
±0.3
±0.5
±0.8
±1.0
±0.5
±1.0
0
1024
2048
3072
0
1024
2048
3072
ADC Output Code
ADC Output Code
C002
C001
12-bit resolution
12-bit resolution
Internal Oscillator divide by 4
External Reference
Internal Oscillator divide by 4
External Reference
Figure 8. SAR ADC, DNL versus Output Code
Figure 9. SAR ADC, INL versus Output Code
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
±0.1
±0.2
±0.3
±0.4
±0.5
±0.1
±0.2
±0.3
±0.4
±0.5
0
64
128
192
0
64
128
192
ADC Output Code
ADC Output Code
C004
C003
8-bit resolution
8-bit resolution
12MHz External Conversion Clock
External Reference
12MHz External Conversion Clock
External Reference
Figure 10. SAR ADC, DNL versus Output Code
Figure 11. SAR ADC, INL versus Output Code
2.0
1.5
1.0
0.5
0.0
±0.5
±1.0
±1.5
±2.0
2.2
3.2
4.2
5.2
VBAT (V)
C005
12-bit resolution
Internal Oscillator Clock Divider by 4
Interal Reference
Figure 12. Battery Measurement, Accuracy versus VBAT Input Voltage
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Typical Characteristics (continued)
7.14.2 Audio ADC Performance
0
±20
±10
±30
±50
±40
±70
±90
±60
±110
±130
±150
±80
±100
20
200
2000
20000
±70
±60
±50
±40
±30
±20
±10
0
Frequency (Hz)
Input Amplitude (dBr)
C009
C007
Differential Input
Rin=20kΩ
CM=0.9V
Differential Input
Rin=20kΩ
CM=0.9V
Channel Gain=0dB
Input Amplitude=-3dBr
Channel Gain=0dB
Figure 13. Audio ADC, Output Amplitude versus
Frequency
Figure 14. Audio ADC, Total Harmonic Distortion + Noise
versus Input Amplitude
0
±10
±30
±50
±20
±40
±70
±90
±60
±110
±130
±150
±80
±100
20
200
2000
20000
C006
±70
±60
±50
±40
±30
±20
±10
0
Frequency (Hz)
Input Amplitude (dBr)
C008
Single-ended Input
Channel Gain=0dB
Rin=20kΩ
CM=0.9V
Single-ended Input
Channel Gain=0dB
Rin=20kΩ
CM=0.9V
Input Amplitude=-3dBr
Figure 15. Audio ADC, Output Amplitude versus
Frequency
Figure 16. Audio ADC, Total Harmonic Distortion + Noise
versus Input Amplitude
100
95
90
85
80
75
Diff, Rin 10K
Diff, Rin 20K
Diff, Rin 40K
SE, Rin 10K
70
65
60
55
SE, Rin 20K
SE, Rin 40K
±12 ±6
0
6
12 18 24 30 36 42 48
Channel Gain (dB)
C010
Differential and Single-ended Inputs
Rin=10kΩ
20kΩ and 40kΩ
CM=0.9V
Figure 17. Audio ADC, Output SNR versus Channel Gain (Analog)
28
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Typical Characteristics (continued)
7.14.3 MICBIAS Performance
3.10
2.70
2.30
1.90
Mode 5
Mode 4
Mode 0
Mode 1
1.50
0
1
2
3
4
5
6
7
8
Load Current (mA)
C011
MICBIAS_VDD at 200mV above programmed output voltage
CM=0.9V
Figure 18. Micbias, Output Voltage versus Load Current
7.14.4 Audio DAC to Line Out Performance
0
±20
±10
±30
±50
±40
±70
±90
±60
±110
±130
±150
±80
±100
20
200
2000
Frequency (Hz)
20000
±70
±60
±50
±40
±30
±20
±10
0
Input Amplitude (dBFS)
C012
C013
Differential Line Out
RECVDD_33=1.8V
Rload=10kΩ
Input Amplitude=-3dBFS
CM=0.9V
Differential Line Out
RECVDD_33=1.8V
Rload=10kΩ
CM=0.9V
Figure 19. DAC Playback on Line Out Amplifier, Output
Amplitude versus Frequency
Figure 20. DAC Playback on Line Out Amplifier, Total
Harmonic Distortion + Noise versus Input Amplitude
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Typical Characteristics (continued)
±10
±30
±10
±30
±50
±50
±70
±90
±70
±110
±130
±150
±90
±110
20
200
2000
20000
20
200
2000
20000
Frequency (Hz)
Frequency (Hz)
C014
C015
Differential Line Out
RECVDD_33=1.8V
Rload=10kΩ
CM=0.9V
Single-ended Line Out
Input Amplitude=-3dBFS
Rload=10kΩ
CM=0.9V
Input Amplitude=-3dBFS
Figure 21. DAC Playback on Line Out Amplifier, Total
Harmonic Distortion + Noise versus Input Frequency
Figure 22. DAC Playback on Line Out Amplifier, Output
Amplitiude versus Frequency
0
±20
±40
±60
±80
±10
±30
±50
±70
±90
±100
±110
±70
±60
±50
±40
±30
±20
±10
0
20
200
2000
20000
Input Amplitude (dBFS)
Frequency (Hz)
C017
C016
Single-ended Line Out
Rload=10kΩ
CM=0.9V
Single-ended Line Out
Input Amplitude=-3dBFS
Rload=10kΩ
CM=0.9V
Figure 23. DAC Playback on Line Out Amplifier, Total
Harmonic Distortion + Noise versus Input Amplitude
Figure 24. DAC Playback on Line Out Amplifier, Total
Harmonic Distortion + Noise versus Input Frequency
30
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Typical Characteristics (continued)
7.14.5 Audio DAC to Headphone Performance
±10
±30
±10
±30
±50
±50
±70
±70
±90
±90
±110
±130
±150
±110
±130
±150
20
200
2000
20000
20
200
2000
20000
Frequency (Hz)
Frequency (Hz)
C018
C019
Input Amplitude=-60dBFS
Rload=16Ω
Input Amplitude=-60dBFS
Rload=32Ω
Figure 25. DAC Playback on Headphone Amplifier, Output
Amplitude versus Frequency
Figure 26. DAC Playback on Headphone Amplifier, Output
Amplitude versus Frequency
0
CM=0.75V, R=16ꢀꢁGain=5dB
±10
±30
CM=0.9V, R=16ꢀꢁGain=5dB
±20
CM=0.75V, R=32ꢀꢁGain=5dB
CM=0.9V, R=32ꢀꢁGain=5dB
±40
±60
±50
±70
±80
±90
±110
±100
20
200
2000
Frequency (Hz)
20000
0.0
0.1
1.0
10.0
100.0
Output Power (mW)
C020
C021
Headphone Gain=5dB
Rload=16Ω and 32Ω
Headphone Gain=0dB
Device CM=0.9V
Rload=16Ω
Device CM=0.75V and 0.9V
Input Amplitude=-3dBFS
Figure 27. DAC Playback on Headphone Amplifier, Total
Harmonic Distortion + Noise versus Output Power
Figure 28. DAC Playback on Headphone Amplifier, Total
Harmonic Distortion + Noise versus Input Frequency
±10
±30
±50
±70
±90
±110
20
200
2000
Frequency (Hz)
20000
C022
Headphone Gain=0dB
Device CM=0.9V
Rload=32Ω
Input Amplitude=-3dBFS
Figure 29. DAC Playback on Headphone Amplifier, Total Harmonic Distortion + Noise versus Input Frequency
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Typical Characteristics (continued)
7.14.6 Audio DAC to Receiver Performance
±10
±30
±10
±30
±50
±50
±70
±90
±70
±110
±130
±150
±90
±110
0.1
1.0
10.0
100.0
20
200
2000
Frequency (Hz)
20000
Output Power (mW)
C023
C024
Receiver Gain=6dB
Device CM=0.9V
Output CM=1.65V
Rload=32Ω
Receiver Gain=6dB
Device CM=0.9V
Output CM=1.65V
Rload=32Ω
Input Amplitude=-3dBFS
Figure 30. DAC Playback on Receiver Amplifier, Output
Amplitude versus Input Frequency
Figure 31. DAC Playback on Receiver Amplifier, Total
Harmonic Distortion + Noise versus Output Power
±10
±30
±50
±70
±90
±110
20
200
2000
Frequency (Hz)
20000
C025
Receiver Gain=6dB
Device CM=0.9V
Output CM=1.65V
Rload=32Ω
Input Amplitude=-3dBFS
Figure 32. DAC Playback on Receiver Amplifier, Total Harmonic Distortion + Noise versus Input Frequency
32
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Typical Characteristics (continued)
7.14.7 Class-D Driver Performance
0
±20
±10
±30
±50
±40
SVDD = 5.5V
±70
±90
±60
SVDD = 5.0V
SVDD = 4.2V
±110
±130
±150
±80
SVDD = 3.6V
SVDD = 2.7V
±100
20
200
2000
20000
0.1
0.6
1.1
1.6
2.1
Frequency (Hz)
Output Power (W)
C026
C027
Input Amplitude=-3dBFS
Speaker Gain=6dB
Rload=8Ω
Speaker Gain=12dB
Rload=8Ω
SVDD=2.7V, 3.6V, 4.2V, 5.0V and 5.5V
Figure 33. DAC Playback on Speaker Amplifier, Output
Amplitude versus Frequency
Figure 34. DAC Playback on Speaker Amplifier, Total
Harmonic Distortion + Noise versus Output Power
±10
±30
91
81
71
61
51
±50
±70
SVDD=2.7V
SVDD=3.6V
SVDD=4.2V
±90
41
31
21
±110
±130
±150
SVDD=5.0V
11
SVDD=5.5V
1.00
1
0.01
20
200
2000
20000
0.10
Output Power (W)
Frequency (Hz)
C029
C028
Speaker Gain=6dB
Rload=8Ω
SVDD=2.7V, 3.6V, 4.2V, 5.0V and 5.5V
Rload=8Ω
Input Amplitude=-3dBFS
Figure 36. DAC Playback on Speaker Amplifier, Total
Harmonic Distortion versus Input Frequency
Figure 35. DAC Playback on Speaker Amplifier, Efficiency
versus Output Power
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8 Detailed Description
8.1 Overview
The TLV320AIC3268 (AIC3268) is a flexible, highly-integrated, low-power, low-voltage stereo audio codec. The
AIC3268 features four digital microphone inputs, plus programmable outputs, PowerTune capabilities, enhanced
fully-programmable miniDSP, predefined and parameterizable signal processing blocks, integrated PLL, and
flexible digital audio interfaces. Extensive register-based control of power, input and output channel configuration,
gains, effects, terminal-multiplexing and clocks are included, allowing the device to be precisely targeted to its
application.
The record path of the TLV320AIC3268 covers operations from 8kHz mono to 192kHz stereo recording, and
contains programmable input channel configurations which cover single-ended and differential setups, as well as
floating or mixing input signals. It also provides a digitally-controlled stereo microphone preamplifier and
integrated microphone bias. The record path can also be configured for up to two stereo (that is up to 4)
simultaneous digital microphone Pulse Density Modulation (PDM) interfaces typically used at 64Fs or 128Fs.
The playback path offers signal processing blocks for filtering and effects; headphone, line, receiver, and Class-D
speaker output; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The
playback path contains two high-power DirectPathTM headphone output drivers which eliminate the need for ac
coupling capacitors. A built in charge pump generates the negative supply for the ground centered headphone
drivers. These headphone output drivers can be configured in multiple ways, including stereo, and mono BTL.
The playback path also features stereo lineout drivers, which can be configured either for single-ended operation
or differential output operation for high performance systems. In addition, playback audio can be routed to an
integrated Class-D speaker driver or a differential receiver amplifier.
The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-
off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used
in a mobile environment. When used in a docked environment power consumption typically is less of a concern
while lowest possible noise is important. With PowerTune the TLV320AIC3268 can address both cases.
The required internal clock of the TLV320AIC3268 can be derived from multiple sources, including the MCLK
terminal, the BCLK1 terminal, the BCLK2 terminal, several general purpose IO terminals or the output of the
internal PLL, where the input to the PLL again can be derived from similar terminals. Although using the internal
fractional PLL ensures the availability of a suitable clock signal, it is not recommended for the lowest power
settings. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to
50MHz. To enable even lower clock frequencies, an integrated low-frequency clock multiplier can also be used
as an input to the PLL.
The TLV320AIC3268 has a 12-bit SAR ADC converter that supports system voltage measurements. These
system voltage measurements can be sourced from three dedicated analog inputs (IN1L/AUX1, IN1R/AUX2 or
VBAT terminals), or, alternatively, an on-chip temperature sensor that can be read by the SAR ADC.
The device also features three full Digital Audio Serial Interfaces, each supporting I2S, DSP/TDM, RJF, LJF, and
mono PCM formats. This enables three simultaneous digital playback and record paths to three independent
digital audio buses or chips. Each of the Digital Audio Serial Interfaces can be run using separate power voltages
to enable easy integration with separate chips with different IO voltages.
The device is available in the 9mm x 9mm x 0,9mm 64-terminal QFN package.
34
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8.2 Functional Block Diagram
LOL
-6...29 dB
-78...0dB
(1-dB Steps)
Int.
Ref.
VREF_SAR
IN1L
RECP
VBAT
VBAT
-78...0dB
IN1L/AUX1
IN1R/AUX2
RECM
SAR
ADC
LOR
-78...0dB
6...30dB
(6-dB Steps)
TEMP
TEMP
SENSOR
IN1R
-78...0dB
-6dB
SPKP
SPKM
-12, -6, 0dB
LOL
RIGHT _
CH_IN
-78...0dB
LOR
–12, –6, 0dB
IN1L_AUX1
IN2L
–12, –6, 0dB
–12, –6, 0dB
-6...14dB
(1-dB Steps)
-78... 0dB
Vol. Ctrl.
AGC
IN3L
ADC
Signal
Proc .
DAC
Signal
Proc.
HPL
–6 dB
Left
ADC
Left
+
tPL
IN4L
–
DAC
-78...0dB
0…47.5dB
(0.5-dB Steps )
Gain Adj.
–36...0dB
MAL
LOL
miniDSP
miniDSP
Dig Mixer
Volume
Audio
HPVSS_SENSE
Dig Mixer
Volume
Interface
–36...0dB
MAR
LOR
HPR
0…47.5dB
(0.5-dB Steps )
Gain Adj.
-78...0dB
ADC
Signal
Proc .
DAC
Signal
Proc.
Right
ADC
Right –
DAC +
–6 dB
tPR
IN4R
IN3R
–12, –6, 0dB
–12, –6, 0dB
–12, –6, 0dB
Vol.Ctrl.
-6...14dB
(1-dB Steps
AGC
IN2R
)
-12, -6,0dB
IN1R_AUX2
-6dB
Low Freq
Clocking
SPI_SELECT
RESET
2
Digital Interrupt
Ctrl
SPI / I C
Control Block
PLL
ASI-3
ASI-2
ASI-1
Mic. (x4)
MICDET
Detection
MICBIAS
Mic
Bias
Charge
Pump
MICBIAS_EXT
Supplies
Terminal Muxing / Clock Routing
VREF_AUDIO
Ref
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8.3 Feature Description
8.3.1 Analog Audio I/O
P1_R45_D1=Power
P1_R48_D[6:4]=Gain
-12, -6, 0dB
SPKP
P1_R23_D[4:3]
MAL
LOL
P1_R45_D7
Class-D
Speaker Amp L
6, 12, 18, 24, 30
dB
IN1L-B
P1_R46_D[6:0]
SPKM
IN1L
IN1L
P1_R45_D2
RIGHT_CH_IN
10/20/40K
P1_R52_D[7:6]
20K
-78dB to 0dB
P1_R46_D[6:0]
P1_R17_D3=Power
IN2L
-78dB to 0dB
P1_R47_D[6:0]
10/20/40K
P1_R52_D[5:4]
IN1L
MAL
P1_R47_D[6:0]
Mixer Amp
LOR
MAR
P1_R17_D5
P1_R18_D[5:0]
Left
IN3L
10/20/40K
P1_R52_D[3:2]
P1_R45_D6
-36dB to 0dB
P1_R18_D[5:0]
IN4L
20K
P1_R53_D5
0 to +47.5 dB
P1_R59
10/20/40K
P
P1_R52_D[1:0]
IN1R
IN2R
IN3R
IN4R
P
P1_R27_D1=Power
P1_R31_D[5:0]=Gain
Mic PGA
Left
Left DAC
Left ADC
10/20/40K
10/20/40K
20K
P1_R54_D[5:4]
P1_R54_D[3:2]
P1_R53_D4
M
P1_R27_D7
P1_R27_D5
MAL
M
HPL
Headphone
Amplifier Left
-6dB to14dB
LDACP
LOL-B1
P1_R28_D[6:0]
Left Channel Input Options:
-78dB to 0dB
P1_R28_D[6:0]
Single Ended: IN1L or IN2L or IN3L or IN1R or IN4L
10/20/40K
10/20/40K
P1_R54_D[7:6]
P1_R54_D[1:0]
Differential: IN2L (P) and IN2R (M) or IN3L (P) and IN3R (M)
or IN4L (P) and IN4R (M)
P1_R23_D7
P1_R23_D[4:3]
P1_R22_D1=Power
MAL
IN1L-B
LOL
Lineout
Amplifier
Left
Note (For All Inputs to Mic PGA):
CM2L
P1_R22_D7
P1_R22_D5
LDACM
RDACP
PGA Input = 0 dB for Singled Ended Input with RIN = 10K
PGA Input = +6 dB for Differential Input with RIN= 10K
PGA Input = -6 dB for Singled Ended Input with RIN= 20K
PGA Input = 0 dB for Differential Input with RIN= 20K
PGA Input = -12 dB for Singled Ended Input with RIN= 40K
PGA Input = -6 dB for Differential Input with RIN= 40K
CM1L
CM1R
CM2R
CM
-78dB to 0dB
P1_R36_D[6:0]
P1_R40_D[5:0]=Gain RECP
P1_R40_D7=Power RECP
-78dB to 0dB
P1_R38_D[6:0]
P1_R36_D[6:0]
10/20/40K
LOL-B2
P1_R57_D[1:0]
P1_R57_D[7:6]
RECP
P1_R38_D[6:0]
IN1L
1
Receiver
Amplifier
-6db to +29dB
LDACP
LDACM
IN1R
P1_R42_D6
P1_R42_D5
10/20/40K
20K
Right Channel Input Options:
RECM
P1_R39_D[6:0]
P1_R37_D[6:0]
2
Single Ended: IN1R or IN2R or IN3R or IN2L or IN4R
LOR-B2
-78dB to 0dB
P1_R56_D4
IN4L
P1_R41_D[5:0]=Gain RECM
P1_R40_D6=Power RECM
P1_R39_D[6:0]
Differential: IN1R (P) and IN1L (M) or IN3R (P) and IN3L (M)
or IN4R (P) and IN4L (M)
-78dB to 0dB
P1_R37_D[6:0]
10/20/40K
10/20/40K
10/20/40K
P1_R57_D[3:2]
P1_R57_D[5:4]
P1_R55_D[1:0]
P1_R56_D5
IN3L
IN1L
IN2L
0 to +47.5 dB
P1_R60
P1_R22_D0=Power
P1_R22_D2
LOL
M
P
P1_R22_D6
M
RDACM
LOR
Lineout
Amplifier
Right
Mic PGA
Right
Right DAC
Right ADC
P1_R23_D6
MAR
P
P1_R23_D[1:0]
IN1R-B
IN4R
IN3R
20K
P1_R19_D[5:0]
-36d to 0dB
-78dB to 0dB
P1_R29_D[6:0]
10/20/40K
10/20/40K
10/20/40K
P1_R17_D2=Power
P1_R55_D[3:2]
P1_R55_D[5:4]
P1_R55_D[7:6]
P1_R19_D[5:0]
MAR
P1_R27_D0=Power
P1_R32_D[5:0]=Gain
Mixer Amp
P1_R17_D4
IN2R
IN1R
Right
P1_R29_D[6:0]
LOR-B1
LDACM
RDACP
MAR
IN1R
HPR
P1_R27_D2
P1_R27_D4
P1_R27_D6
Headphone
Amplifier Right
-6dB to +14dB
20K
IN1R
-12, -6, 0dB
P1_R23_D[1:0]
IN1R-B
Figure 37. Analog Routing Diagram
8.3.1.1 Analog Low Power Bypass
The TLV320AIC3268 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input terminal to an amplifier driving an analog output terminal. Neither the ADC nor the
DAC resources are required for such operation; this supports low-power operation during analog-bypass mode.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1L to the left
lineout amplifier (LOL) and IN1R to LOR. Additionally, line-level signals can be routed directly from these analog
inputs to the amplifier.
8.3.1.2 Headphone Outputs
The stereo headphone drivers on terminals HPL and HPR can drive loads with impedances down to 16Ω in
single-ended DC-coupled headphone configurations. An integral charge pump generates the negative supply
required to operate the headphone drivers in dc-coupled mode, where the common mode of the output signal is
made equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers
in dc-coupled (ground centered mode) eliminates the need for large dc-blocking capacitors.
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HPL
HPR
HPVSS_SENSE
Figure 38. TLV320AIC3268 Ground-Centered Headphone Output
8.3.1.2.1 Using the Headphone Amplifier
The headphone drivers are capable of driving a mixed combination of DAC signal, left and right ADC PGA signal,
and LOL and LOR output signals by configuring B0_P1_R27-R29. The ADC PGA signals can be attenuated up
to 36dB before routing to headphone drivers by configuring B0_P1_R18 and B0_P1_R19. The line-output signals
can be attenuated up to 78dB before routing to headphone drivers by configuring B0_P1_R28 and B0_P1_R29.
The level of the DAC signal can be controlled using the digital volume control of the DAC by configuring
B0_P0_R64-R66. To control the output-voltage swing of headphone drivers, the headphone driver volume
control provides a range of –6.0dB to +14.0dB in steps of 1dB. These can be configured by programming
B0_P1_R27, B0_P1_R31, and B0_P1_R32. In addition, finer volume controls are also available when routing
LOL or LOR to the headphone drivers by controlling B0_P1_R27-R28. These level controls are not meant to be
used as dynamic volume control, but more to set output levels during initial device configuration. Register
B0_P1_R9_D[6:5] allows the headphone output stage to be scaled to tradeoff power delivered vs quiescent
(1)
power consumption.
8.3.1.2.2 Ground-Centered Headphone Amplifier Configuration
Among the other advantages of the ground-centered connection is inherent freedom from turn-on transients that
can cause audible pops, sometimes at uncomfortable volumes.
(1) If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute.
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8.3.1.2.2.1 Circuit Topology
The power supply hook up scheme for the ground centered configuration is shown in HVDD_18 terminal supplies
the positive side of the headphone amplifier. CPVDD_18 terminal supplies the charge pump which in turn
supplies the negative side of the headphone amplifier. Two capacitors are required for the charge pump circuit to
work. These capacitors should be X7R rated.
1.5...1.95V
CPVDD
CPVDD_18
HVDD_18
-6...+14dB
HPL
1dB steps
-6...+14dB
HPR
1dB steps
HPVSS_SENSE
VNEG
CPFCM
2.2 uF
X7R
2.2 uF
X7R
Charge
Pump
CPFCP
CPVSS
Figure 39. Ground-Centered Headphone Connections
8.3.1.2.2.2 Charge Pump Setup and Operation
The built in charge pump draws charge from the CPVDD_18 supply, and by switching the external capacitor
between CPFCP and CPFCM, generates the negative voltage on VNEG terminal. The charge-pump circuit uses
the principles of switched-capacitor charge conservation to generate the VNEG supply in a very efficient fashion.
To turn on the charge pump circuit when headphone drivers are powered, program B0_P1_R35_D[1:0] to "'00".
When the charge pump circuit is disabled, VNEG acts as a ground terminal, allowing unipolar configuration of the
headphone amps. By default, the charge pump is disabled. The switching rate of the charge pump can be
controlled by B0_P1_R33. Because the charge pump can demand significant inrush currents from the supply, it
is important to have a capacitor connected in close proximity to the CPVDD_18 and CPVSS terminals of the
device. At 500kHz clock rate this requires approximately a 10μF capacitor. The ESR and ESL of the capacitor
must be low to allow fast switching currents.
The ground-centered mode of operation is enabled by configuring B0_P1_R31_D7 to "1". Note that the HPL and
HPR gain settings are ganged in Ground-Cetered Mode of operation (B0_P1_R32_D7 = "1"). The HPL and HPR
gain settings cannot be ganged if using the Stereo Unipolar Configuration.
8.3.1.2.2.3 Output Power Optimization
The device can be optimized for a specific output-power range. The charge pump and the headphone driver
circuitry can be reduced in power so less overall power is consumed. The headphone driver power can be
programmed in B0_P1_R9. The control of charge pump switching current is programmed in B0_P1_R34_D[4:2].
8.3.1.2.2.4 Offset Correction and Start-Up
The TLV320AIC3268 offers an offset-correction scheme that is based on calibration during power up. This
scheme minimizes the differences in DC voltage between HPVSS_SENSE and HPL/HPR outputs.
The offset calibration happens after the headphones are powered up in ground-centered configuration. All other
headphone configurations like signal routings, gain settings and mute removal must be configured before
headphone powerup. Any change in these settings while the headphones are powered up may result in
additional offsets and are best avoided.
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The offset-calibration block has a few programmable parameters that the user must control. The user can either
choose to calibrate the offset only for the selected input routing or all input configurations. The calibration data is
stored in internal memory until the next hardware reset or until AVDDx power is removed.
Programming B0_P1_R34_D[1:0] as "10" causes the offset to be calibrated for the selected input mode.
Programming B0_P1_R34_D[1:0] as “11” causes the offset to be calibrated for all possible configurations. All
related blocks must be powered while doing offset correction.
Programming B0_P1_R34_D[1:0] as “00” (default) disables the offset correction block. While the offset is being
calibrated, no signal should be applied to the headphone amplifier, that is the DAC should be kept muted and
analog bypass routing should be kept at the highest attenuation.
8.3.1.3 Stereo Line Outputs
The TLV320AIC3268 features stereo line level drivers which can be configured in either fully differential
configuration (RECP, RECM and LOL, LOR) or single-ended configuration (LOL and LOR).The stereo line level
drivers can drive a wide range of line level resistive impedances in the range of 600Ω to 10kΩ. The output
common mode of line level drivers can be configured to equal the analog input common-mode setting, either
0.75V or 0.9V. The line-level drivers can drive out a mixed combination of DAC signal and attenuated ADC PGA
signal, and signal mixing is register-programmable.
8.3.1.3.1 Line Out Amplifier Configurations
The TLV320AIC3268 can support stereo differential lineout as shown in Figure 40 for stereo DAC playback.
RECP
B0_P1_R42_D[6]=’1'
LDACP
LEFT
DAC AFIR
LDACM
RECM
B0_P1_R42_D[5]=’1'
LOL
B0_P1_R22_D[5]=’1'
RDACP
RIGHT
DAC AFIR
RDACM
LOR
B0_P1_R22_D[6]=’1'
Figure 40. Stereo Differential Line-out
In this mode, the output common-mode setting of the receiver amplifier should be kept the same as the input
common mode by programming B0_P1_R8_D[1:0]="00". Also, in this mode the receiver driver gain should be
kept at 0dB by programming B0_P1_R40_D[5:0] and B0_P1_R41_D[5:0] as "000000". The RECVDD_33 supply
should be connected to the AVDDx_18 power rails for symmetricity.
The TLV320AIC3268 can also support stereo single-ended line outputs as shown in Figure 41 for stereo DAC
playback.
Signal mixing can be configured by programming B0_P1_R22 and B0_P1_R23. To route the output of Left DAC
and Right DAC for stereo single-ended output, as shown in Figure 41, LDACM can be routed to LOL driver by
setting B0_P1_R22_D7 = ‘1’, and RDACM can be routed to LOR driver by setting B0_P1_R22_D6 = ‘1’.
Alternatively, stereo single-ended signals can also be routed through the mixer amplifiers by configuring
B0_P1_R23_D[7:6]. For lowest-power operation, stereo single-ended signals can also be routed in direct
terminal bypass with possible gains of 0dB, -6dB, or -12dB by configuring B0_P1_R23_D[4:3] and
B0_P1_R23_D[1:0]. While each of these two bypass cases could be used in a stereo single-ended configuration,
a mono differential input signal could also be used.
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The output of the stereo line out drivers can also be routed to the stereo headphone drivers, with 0dB to -72dB
gain controls in steps of 0.5dB on each headphone channel. This enables the DAC output or bypass signals to
be simultaneously played back to the stereo headphone drivers as well as stereo line- level drivers. This routing
and volume control is achieved in B0_P1_R28 and B0_P1_R29.
LDACM,
MAL, or
IN1L-B
LOL
RDACM,
MAR, or
IN1R-B
LOR
Figure 41. Stereo Single-Ended Line-out
Additionally, the two line-level drivers can be configured to act as a mono differential line level driver by routing
the output of LOL to LOR (B0_P1_R22_D2 = ‘1’). This differential signal takes either LDACM, MAL, or IN1L-B as
a single-ended mono signal and creates a differential mono output signal on LOL and LOR.
LDACM,
MAL, or
IN1L-B
LOL
Output +
Output -
LOR
LOL
Figure 42. Single Channel Input to Differential Line-out
8.3.1.4 Differential Receiver Output
The differential receiver amplifier output spans the RECP and RECM terminals and can drive a 32Ω receiver
driver. he receiver driver can drive up to a 1Vrms output signal.
The differential receiver driver is capable of driving a mixed combination of DAC signal through the Line Out
amplifiers and the line-bypass from analog input IN1L and IN1R. Routing and volume level setting of the IN1L
and IN1R input signals to the Positive and Negative driver is controlled by B0_P1_R38 and B0_P1_R39
respectively. These two registers enable fine tuning of the inputs to the receiver driver by allowing up to 78dB of
attenuation. A single volume control can be utilized for both inputs by setting B0_P1_R39_D7. Routing and
volume level setting of the LOL and LOR signals to the positive and negative inputs of the differential receiver
driver is controlled by B0_P1_R36 and B0_P1_R37 respectively. These two registers enable fine tuning of the
separate positive and negative differential signals by allowing up to 78dB of attenuation. A single volume control
can be utilized for both inputs by setting B0_P1_R37_D7. Routing of LDACP and LDACM signals to the Positive
and Negative driver is controlled by B0_P1_R42_D6 and B0_P1_R42_D5 respectively.
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
LOL
LDACP
IN1L
32Ω
RECP
RECM
LOR
LDACM
IN1R
Figure 43. Receiver Differential Output
The receiver driver can be powered on by writing 11 to B0_P1_R40_D[7:6]. The positive driver gain and muting
can be controlled by writing to B0_P1_R40_D[5:0], and the negative driver gain can be controlled by writing to
B0_P1_R41_D[5:0], with each amplifier providing -6dB to 29dB gains in steps of 1dB. A single volume control
can be utilized for the differential receiver output drivers by setting B0_P1_R41_D7 to '1'.
The TLV320AIC3268 has an overcurrent/short-circuit protection feature for the receiver drivers that is always
enabled to provide protection. If the output is shorted, this overcurrent condition either shuts down the output
stage (if B0_P1_R10_D0 = 1) or starts to limit the amount of current (if B0_P1_R10_D0 = 0). The default
condition for the receiver driver is current-limiting mode. In case of a short circuit, for automatic latching
shutdown, the output is disabled and a status flag is provided as read-only bits B0_P0_R44_D7 for RECP and on
B0_P0_R44_D6 for RECM.
The receiver driver also has an offset calibration for minimizing start-up transients. By default, this feature is
enabled at every power-up by setting B0_P1_R42_D[4:3] to '01'. The status of the offset calibration can be read
through the Receiver Offset Calibration Flag (B0_P1_R42_D7). Offset calibration should only be disabled if this
driver is utilized as a second single-ended headphone configuration (that is, should not be utilized in differential
configuration).
8.3.1.5 Class-D Speaker Outputs
The integrated Class-D speaker driver (SPKP, SPKN) is capable of driving an 8Ω differential load. The speaker
driver can be powered directly from the power supply (2.7V to 5.5V) on the SVDD terminal, however the voltage
(including spike voltage) must be limited below the Absolute Maximum Voltage of 6.0V.
The speaker driver capable of supplying 0.74 W at 10% THD+N with a 3.6-V power supply and 1.45 W at 10%
THD+N with a 5.0V power supply. Separate left and right channels can be sent to the Class-D driver through the
Lineout signal path, or from the mixer amplifiers in the ADC bypass. Additionally, the analog mixer before the
Speaker amplifier can sum the left and right audio signals for monophonic playback.
The speaker driver is capable of driving a mixed combination of DAC signal through the Line Out amplifiers and
the left and right ADC PGA signal. The ADC PGA signals can be routed to the speaker drivers by setting
B0_P1_R45_D7 (Left Mixer amplifier to Speaker) and B0_P1_R45_D6 (Right Mixer amplifier to Speaker), and
these signals can be attenuated up to 36dB before this routing to the speakers by configuring B0_P1_R18 and
B0_P1_R19. Routing and volume level setting of the LOL and LOR signals to the speaker driver is controlled by
B0_P1_R46 and B0_P1_R47 respectively. These two registers enable fine tuning of the separate stereo signals
by allowing up to 78dB of attenuation. To play the stereo DAC signals through the Line Out amplifiers to the
speaker, the DAC signals should be routed to the LOL/LOR drivers by setting B0_P1_R22_D[7:6]. The level of
these DAC signal can also be controlled using the digital volume control of the DAC signal (B0_P0_R65 and
B0_P0_R66).
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TLV320AIC3268
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8Ω
SPKP
SPKM
MAL
LOL
LOR
MAR
RIGHT_CH_IN
Figure 44. Speaker Output
The class-D speaker driver can be powered on by writing to B0_P1_R45_D1. The driver gain can be controlled
by writing to B0_P1_R48_D[6:4], and it can be muted by writing ‘000’ to these bits.
The TLV320AIC3268 has a short-circuit protection feature for the speaker driver that is always enabled to
provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current
limiting is not an available option for the higher-current speaker driver output stage.) In case of a short circuit, the
output is disabled and a status flag is provided as a read-only bit on B0_P0_R44_D7. If shutdown occurs due to
an overcurrent condition, then the device requires a reset to re-enable the output stage. Resetting can be done in
two ways. First, the device master reset can be used, which requires either toggling the RESET terminal or using
the software reset. If master reset is used, it resets all of the registers. Second, a dedicated speaker power-stage
reset can be used that keeps all of the other device settings. The speaker power-stage reset is done by setting
B0_P1_R45_D1. If the fault condition has been removed, then the device returns to normal operation. If the fault
is still present, then another shutdown occurs. Repeated resetting (more than three times) is not recommended,
as this could lead to overheating.
The TLV320AIC3268 has an overtemperature thermal-protection (OTP) feature for the speaker driver which is
always enabled to provide protection. If the device is overheated, then the output stops switching. When the
device cools down, the device resumes switching. An overtemperature status flag is provided as a read-only bit
on B0_P0_R45_D7, and this status flag can be routed to INT1 interrupt (B0_P0_R48_D1 = ‘1’) or INT2 interrupt
(B0_P0_R49_D1 = ‘1’). The OTP feature is for self-protection of the device. If die temperature can be controlled
at the system/board level, then overtemperature does not occur.
To minimize battery current leakage, the SVDD voltage levels should not be less than the AVDDx_18 voltage
levels.
8.3.2 ADC / Digital Microphone Interface
The TLV320AIC3268 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable
oversampling ratio, followed by a digital decimation filter and a programmable miniDSP. The ADC supports
sampling rates from 8kHz to 192kHz. In order to provide optimal system power management, the stereo
recording path can be powered up one channel at a time, to support the case where only mono record capability
is required.
The ADC path of the TLV320AIC3268 features a large set of options for signal conditioning as well as signal
routing:
•
•
•
•
•
•
•
•
2 ADCs
8 analog inputs which can be mixed or multiplexed in single-ended or differential configuration
2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
2 mixer amplifiers for analog bypass
2 low power analog bypass channels
Fine gain adjust of digital channels with 0.1 dB step size
Digital volume control with a range of -12 to +20dB
Mute function
42
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•
Automatic gain control (AGC)
In addition to the standard set of ADC features the TLV320AIC3268 also offers the following special functions:
•
•
Built in microphone biases
Four-channel digital microphone interface
–
–
–
Allows 4 total microphones
Up to 4 digital microphones
Up to 2 analog microphones
•
•
•
•
Channel-to-channel phase adjustment
Fast charge of ac-coupling capacitors
Anti thump
Adaptive coefficient update mode
8.3.2.1 ADC Signal Routing
As shown in Figure 37, the TLV320AIC3268 includes eight analog inputs which can be configured as either 4
stereo single-ended pairs or 4 fully-differential pairs. These terminals connect through series resistors and
switches to the virtual ground terminals of two fully-differential amplifiers (one per ADC/PGA channel). By turning
on only one set of switches per amplifier at a time, the inputs can be effectively multiplexed to each ADC PGA
channel. By turning on multiple sets of switches per amplifier at a time, audio sources can be mixed. The
TLV320AIC3268 supports the ability to mix up to five single-ended analog inputs or up to three fully-differential
analog inputs into each ADC PGA channel.
In most applications, high input impedance is desired for analog inputs. However when used in conjunction with
high gain as in the case of microphone inputs, the higher input impedance results in higher noise or lower
dynamic range. The TLV320AIC3268 allows the user the flexibility of choosing the input impedance from 10kΩ,
20kΩ and 40kΩ. When multiple inputs are mixed together, by choosing different input impedances, level
adjustment can be achieved. For example, if one input is selected with 10kΩ input impedance and the second
input is selected with 20kΩ input impedance, then the second input is attenuated by half as compared to the first
input. Note that this input level control is not intended to be a volume control, but instead used occasionally for
level setting. Also, note that this input-level configurability is available on IN1L, IN1R, IN2L, IN2R, IN3L, and
IN3R; for IN4L and IN4R, this input impedance is fixed at 20kΩ.
Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal amplifiers, resulting
in saturation and clipterminalg of the mixed output signal. Whenever mixing is being implemented, the system
designer is advised to take adequate precautions to avoid such a saturation from occurring. In general, the mixed
signal should not exceed 0dB.
Typically, voice or audio signal inputs are capacitively coupled to the device. This allows the device to
independently set the common mode of the input signals to values chosen by register control of B0_P1_R8_D2
to either 0.9V or 0.75V. The correct value maximizes the dynamic range across the entire analog supply range.
Failure to capacitively connect the input to the device can cause high offset due to mismatch in source common-
mode and device common-mode setting. In extreme cases it could also saturate the analog channel, causing
distortion.
8.3.2.1.1 High Impedance Input Mode
The TLV320AIC3268 supports a special high impedance input mode on terminals IN1L/AUX1 and IN1R/AUX2 to
enable interfacing with sensors having high output impedance. By programming B0_P1_R17_D[5] and
B0_P1_R17_D[4] to '1' IN1L/AUX1 and IN1R/AUX2 can be used in high impedance mode respectively. While
using this mode, IN1L/AUX1 and IN1R/AUX2 should not be routed to Left and Right ADC PGA's or
B0_P1_R52_D[7:6], B0_P1_R52_D[1:0], B0_P1_R55_D[7:6] and B0_P1_R57_D[5:4] should be programmed as
"00". While using this mode the signal should be externally biased around a common mode which is close to the
device common mode programmed via B0_P1_R8_D[2]. When using high impedance mode, routing of MAL and
MAR amplifiers to Speaker Amplifier and Lineout Drivers is not supported.
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8.3.2.2 ADC Gain Setting
Digital
Gain
Adjust
Frequency
Response
and Gain
Input
Selection
Digital
Volume
Control
Analog
Gain
Audio
Interface
Analog
In
ADC
Filtering
PGA
ADC
Fully
Programmable
Coefficients
0,-6,-12 dB
0...47.5 dB
Step = 0.5 dB
-12...20 dB 0…-0.4 dB
Step = 0.5 dB Step= 0.1 dB
When the gain of the ADC Channel is kept at 0dB and the common mode set to 0.75V, a single-ended input of
0.375VRMS results in a full-scale digital signal at the output of ADC channel. Similarly, when the gain is kept at
0dB, and common mode is set to 0.9V, a single-ended input of 0.5VRMS results in a full-scale digital signal at the
output of the ADC channel. However various block functions control the gain through the channel. The gain
applied by the PGA is described in Table 7. Additionally, the digital volume control adjusts the gain through the
channel as described in Digital Volume Control. A finer level of gain adjustment is possible and described in Fine
Digital Gain Adjustment. The decimation filters A, B and C along with the delta-sigma modulator contribute to a
DC gain of 1.0 through the channel.
8.3.2.2.1 Analog Programmable Gain Amplifier (PGA)
The TLV320AIC3268 features a built-in low-noise PGA for boosting low-level signals, such as direct microphone
inputs, to full-scale to achieve high SNR. This PGA can provide a gain in the range of 0dB to 47.5dB for single-
ended inputs or 6dB to 53.5dB for fully-differential inputs (gain calculated w.r.t. input impedance setting of 10kΩ,
20kΩ input impedance will result in 6dB lower and 40kΩ will result in 12dB lower gain). This gain can be user
controlled by writing to B0_P1_R59 and B0_P1_R60. In the AGC mode this gain can also be automatically
controlled by the built-in hardware AGC.
Table 7. Analog PGA vs Input Configuration
Book 0, Page 1, Register 59, D[6:0]
(B0_P1_R59_D[6:0])
Book 0, Page 1, Register 60, D[6:0]
B0_P1_R60_D[6:0]
EFFECTIVE GAIN APPLIED BY PGA
SINGLE-ENDED
DIFFERENTIAL
RIN = 10kΩ
RIN = 20kΩ RIN = 40kΩ
RIN = 10kΩ RIN = 20kΩ RIN = 40kΩ
000 0000
000 0001
000 0010
…
0 dB
–6 dB
-12 dB
–11.5 dB
–11.0 dB
…
6.0 dB
6.5 dB
7.0 dB
…
0 dB
–6.0 dB
-5.5 dB
–5.0 dB
…
0.5 dB
1.0 dB
…
–5.5 dB
–5.0 dB
…
0.5 dB
7.5 dB
…
101 1110
101 1111
47.0 dB
47.5 dB
41.0 dB
41.5 dB
35.0 dB
35.5 dB
53.0 dB
53.5 dB
47.0 dB
47.5 dB
41.0 dB
41.5 dB
The gain changes are implemented with an internal soft-stepterminalg algorithm that only changes the actual
volume level by one 0.5-dB step every one or two ADC output samples, depending on the register value (see
registers B0_P0_R81_D[1:0]). This soft-stepterminalg ensures that volume control changes occur smoothly with
no audible artifacts. On reset, the PGA gain defaults to a mute condition, and at power down, the PGA soft-steps
the volume to mute before shutting down. A read-only flag B0_P0_R36_D7 and B0_P0_R36_D3 is set whenever
the gain applied by the PGA equals the desired value set by the register. The soft-stepterminalg control can also
be disabled by programming B0_P0_R81_D[1:0].
8.3.2.2.2 Digital Volume Control
The TLV320AIC3268 also has a digital volume-control block with a range from -12dB to +20dB in steps of 0.5dB.
It is set by programming B0_P0_R83 and B0_P0_R84 respectively for left and right channels.
44
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Table 8. Digital Volume Control for ADC
Desired Gain (dB)
Left / Right Channel
B0_P0_R83 and B0_P0_R84,
D[6:0]
–12.0
–11.5
–11.0
..
110 1000
110 1001
110 1010
–0.5
0.0
111 1111
000 0000 (Default)
000 0001
+0.5
..
+19.5
+20.0
010 0111
010 1000
During volume control changes, the soft-stepterminalg feature is used to avoid audible artifacts. The soft-
stepterminalg rate can be set to either 1 or 2 gain steps per sample. Soft-stepterminalg can also be entirely
disabled. This soft-stepterminalg is configured via B0_P0_R81_D[1:0], and is common to soft-stepterminalg
control for the analog PGA. During power-down of an ADC channel, this volume control soft-steps down to -
12.0dB before powering down. Due to the soft-stepterminalg control, soon after changing the volume control
setting or powering down the ADC channel, the actual applied gain may be different from the one programmed
through the control register. The TLV320AIC3268 gives feedback to the user, through read-only flags
B0_P0_R36_D7 for Left Channel and B0_P0_R36_D3 for the right channel.
8.3.2.2.3 Fine Digital Gain Adjustment
Additionally, the gains in each of the channels is finely adjustable in steps of 0.1dB. This is useful when trying to
match the gain between channels. By programming B0_P0_R82, the gain can be adjusted from 0dB to -0.4dB in
steps of 0.1dB. This feature, in combination with the regular digital volume control allows the gains through the
left and right channels be matched in the range of -0.5dB to +0.5dB with a resolution of 0.1dB.
8.3.2.2.4 AGC
The TLV320AIC3268 includes Automatic Gain Control (AGC) for ADC recording. AGC can be used to maintain a
nominally-constant output level when recording speech. As opposed to manually setting the PGA gain, in the
AGC mode, the circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very
weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The
AGC algorithm has several programmable parameters, including target gain, attack and decay time constants,
noise threshold, and max PGA applicable, that allow the algorithm to be fine tuned for any particular application.
The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal)
as a measure of the nominal amplitude of the output signal. Since the gain can be changed at the sample
interval time, the AGC algorithm operates at the ADC sample rate.
1. Target Level represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TLV320AIC3268
allows programming of eight different target levels, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal.
Since the TLV320AIC3268 reacts to the signal absolute average and not to peak levels, it is recommended that the target level be set
with enough margin to avoid clipterminalg at the occurrence of loud sounds.
2. Attack Time sets how quickly the AGC circuitry reduces the PGA gain when the output signal level exceeds the target level due to
increase in input signal level. Wide range of attack time programmability is supported in terms of number of samples (that is, number of
ADC sample frequency clock cycles).
3. Decay Time sets how quickly the PGA gain is increased when the output signal level falls below the target level due to reduction in
input signal level. Wide range of decay time programmability is supported in terms of number of samples (that is, number of ADC
sample frequency clock cycles).
4. Gain Hysteresis is the hysteresis applied to the required gain calculated by the AGC function while changing its mode of operation from
attack to decay or vice-versa. For example, while attacking the input signal, if the current applied gain by the AGC is xdB, and suddenly
because of input level going down, the new calculated required gain is ydB, then this gain is applied provided y is greater than x by the
value set in Gain Hysteresis. This feature avoids the condition when the AGC function can fluctuate between a very narrow band of
gains leading to audible artifacts. The Gain Hysteresis can be adjusted or disabled by the user.
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5. Noise threshold sets the level below which if the input signal level falls, the AGC considers it as silence, and thus brings down the gain
to 0 dB in steps of 0.5 dB every FS and sets the noise threshold flag. The gain stays at 0 dB unless the input speech signal average
rises above the noise threshold setting. This ensures that noise is not 'gained up' in the absence of speech. Noise threshold level in the
AGC algorithm is programmable from -30dB to -90 dB of full-scale. When AGC Noise Threshold is set to –70dB, –80db, or –90dB, the
microphone input Max PGA applicable setting must be greater than or equal to 11.5dB, 21.5dB, or 31.5dB respectively. This operation
includes hysteresis and debounce to avoid the AGC gain from cycling between high gain and 0 dB when signals are near the noise
threshold level. When utilizing the AGC noise threshold, it is recommended to configure the 1st order IIR filter as a high-pass filter to
achieve best performance. The noise (or silence) detection feature can be entirely disabled by the user.
6. Max PGA applicable allows the designer to restrict the maximum gain applied by the AGC. This can be used for limiting PGA gain in
situations where environmental noise is greater than the programmed noise threshold. Microphone input Max PGA can be programmed
from 0 dB to 58 dB in steps of 0.5 dB.
7. Hysteresis, as the name suggests, sets a window around the Noise Threshold which must be exceeded to either detect that the
recorded signal is indeed noise or signal. If initially the energy of the recorded signal is greater than the Noise Threshold, then the AGC
recognizes it as noise only when the energy of the recorded signal falls below the Noise Threshold by a value given by Hysteresis.
Similarly, after the recorded signal is recognized as noise, for the AGC to recognize it as a signal, its energy must exceed the Noise
Threshold by a value given by the Hysteresis setting. In order to prevent the AGC from jumterminalg between noise and signal states,
(which can happen when the energy of recorded signal is very close to the Noise threshold) a non-zero hysteresis value should be
chosen. The Hysteresis feature can also be disabled.
8. Debounce Time (Noise and Signal) sets the hysteresis in time domain for noise detection. The AGC continuously calculates the
energy of the recorded signal. If the calculated energy is less than the set Noise Threshold, then the AGC does not increase the input
gain to achieve the Target Level. However, to handle audible artifacts which can occur when the energy of the input signal is very close
to the Noise Threshold, the AGC checks if the energy of the recorded signal is less than the Noise Threshold for a time greater than the
Noise Debounce Time. Similarly the AGC starts increasing the input-signal gain to reach the Target Level when the calculated energy of
the input signal is greater than the Noise Threshold. Again, to avoid audible artifacts when the input-signal energy is very close to Noise
Threshold, the energy of the input signal needs to continuously exceed the Noise Threshold value for the Signal Debounce Time. If the
debounce times are kept very small, then audible artifacts can result by rapid enabling and disabling the AGC function. At the same
time, if the Debounce time is kept too large, then the AGC may take time to respond to changes in levels of input signals with respect to
Noise Threshold. Both noise and signal debounce time can be disabled.
9. The AGC Noise Threshold Flag is a read-only flag indicating that the input signal has levels lower than the Noise Threshold, and thus
is detected as noise (or silence). In such a condition the AGC applies a gain of 0 dB.
10. Gain Applied by AGC is a ready-only register setting which gives a real-time feedback to the system on the gain applied by the AGC
to the recorded signal. This, along with the Target Setting, can be used to determine the input signal level. In a steady state situation
Target
Level
(dB)
=
Gain
Applied
by
AGC
(dB)
+
Input
Signal
Level
(dB)
When the AGC noise threshold flag is set, then the status of gain applied by AGC should be ignored.
11. The AGC Saturation Flag is a read-only flag indicating that the ADC output signal has not reached its Target Level. However, the AGC
is unable to increase the gain further because the required gain is higher than the Maximum Allowed PGA gain. Such a situation can
happen when the input signal has very low energy and the Noise Threshold is also set very low. When the AGC noise threshold flag is
set, the status of AGC saturation flag should be ignored.
12. The ADC Saturation Flag is a read-only flag indicating an overflow condition in the ADC channel. On overflow, the signal is clipped and
distortion results. This typically happens when the AGC Target Level is kept very high and the energy in the input signal increases faster
than the Attack Time.
13. An AGC low-pass filter is used to help find the average level of the input signal. This average level is compared to the programmed
detection levels in the AGC to provide the correct functionality. This low pass filter is in the form of a first-order IIR filter. Three 8-bit
registers are used to form the 24-bit digital coefficient as shown on the register map. In this way, a total of 9 registers are programmed
to form the 3 IIR coefficients. The transfer function of the filter implemented for signal level detection is given by
N0 + N1z-1
H(z) =
223 - D1z-1
(1)
Where:
Coefficient N0 can be programmed by writing into B40_P1_R12, B40_P1_R13, and B40_P1_R14.
Coefficient N1 can be programmed by writing into B40_P1_R16, B40_P1_R17, and B40_P1_R18.
Coefficient D1 can be programmed by writing into B40_P1_R20, B40_P1_R21, and B40_P1_R22.
N0, N1 and D1 are 24-bit 2’s complement numbers and their default values implement a low-pass filter with cut-off at
0.002735*ADC_FS .
See Table 9 for various AGC programming options. AGC can be used only if analog microphone input is routed to the ADC channel.
46
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Table 9. AGC Parameter Settings
Function
Control Register
Left ADC
Control Register
Right ADC
Bits
AGC enable
Book 0, Page 0, Register 86
(B0_P0_R86)
Book 0, Page 0, Register 94
(B0_P0_R94)
D7
Target Level
Book 0, Page 0, Register 86
(B0_P0_R86)
Book 0, Page 0, Register 94
(B0_P0_R94)
D[6:4]
Gain Hysteresis
Book 0, Page 0, Register 86
(B0_P0_R86)
Book 0, Page 0, Register 94
(B0_P0_R94)
D[1:0]
Hysteresis
Book 0, Page 0, Register 87
(B0_P0_R87)
Book 0, Page 0, Register 95
(B0_P0_R95)
D[7:6]
Noise threshold
Book 0, Page 0, Register 87
(B0_P0_R87)
Book 0, Page 0, Register 95
(B0_P0_R95)
D[5:1]
Max PGA applicable
Time constants (attack time)
Time constants(decay time)
Debounce time (Noise)
Debounce time (Signal)
Gain applied by AGC
AGC Noise Threshold Flag
Book 0, Page 0, Register 88
(B0_P0_R88)
Book 0, Page 0, Register 96
(B0_P0_R96)
D[6:0]
Book 0, Page 0, Register 89
(B0_P0_R89)
Book 0, Page 0, Register 97
(B0_P0_R97)
D[7:0]
Book 0, Page 0, Register 90
(B0_P0_R90)
Book 0, Page 0, Register 98
(B0_P0_R98)
D[7:0]
Book 0, Page 0, Register 91
(B0_P0_R91)
Book 0, Page 0, Register 99
(B0_P0_R99)
D[4:0]
Book 0, Page 0, Register 92
(B0_P0_R92)
Book 0, Page 0, Register 100
(B0_P0_R100)
D[3:0]
Book 0, Page 0, Register 93
(B0_P0_R93)
Book 0, Page 0, Register 101
(B0_P0_R101)
D[7:0] (Read Only)
D[6:5] (Read Only)
Book 0, Page 0, Register 45
(B0_P0_R45) (sticky flag),
Book 0, Page 0, Register 47
(B0_P0_R47) (non-sticky flag)
Book 0, Page 0, Register 45
(B0_P0_R45) (sticky flag),
Book 0, Page 0, Register 47
(B0_P0_R47) (non-sticky flag)
AGC Saturation flag
ADC Saturation flag
Book 0, Page 0, Register 36
(B0_P0_R36) (sticky flag)
Book 0, Page 0, Register 36
(B0_P0_R36) (sticky flag)
D5, D1 (Read Only)
D[3:2] (Read Only)
Book 0, Page 0, Register 42
(B0_P0_R42) (sticky flag),
Book 0, Page 0, Register 43
(B0_P0_R43) (non-sticky flag)
Book 0, Page 0, Register 42
(B0_P0_R42) (sticky flag),
Book 0, Page 0, Register 43
(B0_P0_R43) (non-sticky flag)
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Input
Signal
Output
Signal
Target
Level
AGC
Gain
Attack
Decay Time
Figure 45. AGC Characteristics
The TLV320AIC3268 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be
chosen from three different types, depending on the required frequency response, group delay and sampling
rate.
8.3.2.3 ADC Processing Blocks
The TLV320AIC3268 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
Table 10 gives an overview of the available processing blocks of the ADC channel and their properties. The
Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
•
•
First-order IIR
AGC
Additional signal processing functions are acheived by programming the miniDSP. For specific details on
available processing functions, please contact Texas Instruments.
The processing blocks are tuned for mono or stereo use cases and can achieve high anti-alias filtering. The
available first order IIR, has fully user programmable coefficients.
48
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Table 10. ADC Processing Blocks
Processing
Blocks
Channel
Decimation
Filter
1st Order
IIR Available
Number
BiQuads
FIR
Required AOSR
Value
Resource
Class
PRB_R1(1)
Stereo
Left
A
A
Yes
Yes
0
0
No
No
128,64,32,16,8,4
128,64,32,16,8,4
7
4
PRB_R4
(1) Default
8.3.2.4 ADC Processing Blocks – Details
8.3.2.4.1 1st order IIR, AGC, Filter A
From Delta-Sigma
AGC
Gain
st
1
Order
IIR
To Audio
Interface
Modulator or
Digital Microphone
Filter A
´
Compen
Sation
AGC
From
Digital Vol. Ctrl
To Analog PGA
Figure 46. Signal Chain for PRB_R1 and PRB_R4
8.3.2.5 User Programmable Filters
The built-in processing block in TLV320AIC3268 has a user programmable first order IIR filter. This filter can be
used for dc-blocking purposes. The user programmable coefficients allow the user to control the cut-off
frequency of the high pass filter.
The coefficients of these filters are each 24-bits wide, in two's-complement and occupy 3 consecutive 8-bit
registers in the register space. For default values please see Table 56.
8.3.2.5.1 1st Order IIR Section
The transfer function for the first order IIR Filter is given by
N0 + N1z-1
H(z) =
223 - D1z-1
(2)
The frequency response for the 1st order IIR Section with default coefficients is flat at a gain of 0dB. Details on
ADC coefficient default values are given in Table 56.
Table 11. ADC 1st order IIR Filter Coefficients
Filter
FIlter
ADC Coefficient Left
ADC Coefficient Right Channel
Coefficient Channel
N0
N1
D1
C4 (B40_P1_R24-R26)
C36 (B40_P2_R32-R34)
C37 (B40_P2_R36-R38)
C39 (B40_P2_R40-R42)
1st Order
IIR
C5 (B40_P1_R28-R30)
C6 (B40_P1_R32-R34)
8.3.2.6 Decimation Filter
The TLV320AIC3268 offers 3 different types of decimation filters. The integrated digital decimation filter removes
high-frequency content and down samples the audio data from an initial sampling rate of AOSR*fS to the final
output sampling rate of fS. The decimation filtering is achieved using a higher-order CIC filter followed by linear-
phase FIR filters. The decimation filter cannot be chosen by itself, it is implicitly set through the chosen
processing block.
The following subsections describe the properties of the available filters A, B and C.
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8.3.2.6.1 Decimation Filter A
This filter is intended for use at sampling rates up to 48kHz. When configuring this filter, the oversampling ratio of
the ADC can either be 128 or 64. For highest performance the oversampling ratio must be set to 128. Using
AOSR of 64 for sampling rates up to 48kHz, gives lower power consumption, but degrades the signal to noise
ratio (SNR).
Filter A can also be used for 96kHz at an AOSR of 64.
Table 12. ADC Decimation Filter A, Specification
Parameter
Condition
Value (Typical)
Units
AOSR = 128
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0…0.39 fS
0.55…64fS
0.062
–73
dB
dB
17/fS
0.062
0.05
0.05
Sec.
dB
Pass Band Ripple, 8 ksps
Pass Band Ripple, 44.1 ksps
Pass Band Ripple, 48 ksps
AOSR = 64
0…0.39 fS
0…0.39 fS
0…0.39 fS
dB
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0…0.39 fS
0.55…32fS
0.062
–73
dB
dB
Sec.
dB
dB
dB
dB
17/fS
0.062
0.05
0.05
0.1
Pass Band Ripple, 8 ksps
Pass Band Ripple, 44.1 ksps
Pass Band Ripple, 48 ksps
Pass Band Ripple, 96 ksps
0…0.39 fS
0…0.39 fS
0…0.39 fS
0…20kHz
ADC Channel Response for Decimation Filter A
(Red line corresponds to –73 dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency Normalized to fS
G013
Figure 47. ADC Decimation Filter A, Frequency Response
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8.3.2.6.2 Decimation Filter B
Filter B is intended to support sampling rates up to 96kHz at a oversampling ratio of 64.
Table 13. ADC Decimation Filter B, Specifications
Parameter
Condition
Value (Typical)
Units
AOSR = 64
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0…0.39fS
±0.077
–46
dB
dB
Sec.
dB
dB
dB
dB
0.60fS…32fS
11/fS
0.076
0.06
Pass Band Ripple, 8 ksps
Pass Band Ripple, 44.1 ksps
Pass Band Ripple, 48 ksps
Pass Band Ripple, 96 ksps
0…0.39fS
0…0.39fS
0…0.39fS
0…20kHz
0.06
0.11
ADC Channel Response for Decimation Filter B
(Red line corresponds to –44 dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency Normalized to fS
G014
Figure 48. ADC Decimation Filter B, Frequency Response
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8.3.2.6.3 Decimation Filter C
Filter type C along with AOSR of 32 is specially designed for 192ksps operation for the ADC. The pass band
which extends up to 0.11*fS ( corresponds to 21kHz), is suited for audio applications.
Table 14. ADC Decimation Filter C, Specifications
Parameter
Condition
0…0.11fS
Value (Typical)
±0.033
–60
Units
dB
Filter Gain from 0 to 0.11fS
Filter Gain from 0.28fS to 16fS
Filter Group Delay
0.28fS…16fS
dB
11/fS
Sec.
dB
Pass Band Ripple, 8 ksps
Pass Band Ripple, 44.1 ksps
Pass Band Ripple, 48 ksps
Pass Band Ripple, 96 ksps
Pass Band Ripple, 192 ksps
0…0.11fS
0…0.11fS
0…0.11fS
0…0.11fS
0…20kHz
0.033
0.033
dB
0.032
dB
0.032
dB
0.086
dB
ADC Channel Response for Decimation Filter C
(Red line corresponds to –60 dB)
0
–20
–40
–60
–80
–100
–120
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency Normalized to fS
G015
Figure 49. ADC Decimation Filter C, Frequency Response
8.3.2.7 ADC Data Interface
The decimation filter and signal processing block in the ADC channel passes 32-bit data words to the audio
serial interface once every cycle of Fs,ADC. During each cycle of Fs,ADC, a pair of data words ( for left and right
channel) are passed. The audio serial interface rounds the data to the required word length of the interface
before converting to serial data as per the different modes for audio serial interface.
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8.3.2.8 ADC Special Functions
8.3.2.8.1 Power Tune Modes
As a part of PowerTune strategy, the analog performance of ADC can be adjusted. As a consequence the power
consumption on AVDDx_18 supplies can be traded off with the speed of operation (ADC_MOD_CLK) and
performance.
The TLV320AIC3268 supports 4 different power tune modes for ADC, PTM_R1, PTM_R2, PTM_R3 and
PTM_R4, which can be set by programming B0_P1_R61_D[7:6]. The PTM_R4 is the default mode and gives the
best performance for ADC with AOSR=128 and ADC_FS up to 48ksps. At lower speeds of ADC_MOD_CLK (
AOSR*ADC_FS ) lower PTM modes can be used for the benefit of lower power consumption, for example for
AOSR=64 and ADC_FS=8ksps, PTM_R1 can be used. Using lower PTM modes for higher frequencies of
ADC_MOD_CLK can result in reduction of peak amplitude of analog inputs where the distortion performance
sets in. In general , PTM_R1 is recommended till ADC_MOD_CLK up to 0.768MHz, PTM_R2 for
ADC_MOD_CLK up to 1.536MHz and PTM_R3 for ADC_MOD_CLK up to 3.072MHz. In applications where
power consumption is not very critical, PTM_R4 is recommended to be used for best performance.
8.3.2.8.2 Microphone Bias
The TLV320AIC3268 has two built-in low noise Microphone Bias terminals for electret-condenser microphones:
MICBIAS and MICBIAS_EXT. Typically, MICBIAS is utilized for onboard microphones, while MICBIAS_EXT
provides a microphone bias for inserted headsets. Each bias amplifier can support up to 8mA of load current to
support multiple microphones. Each bias amplifier has been designed to provide a combination of high PSRR,
low noise and programmable bias voltages to allow the user to fine tune the biasing to specific microphone
combinations. To support a wide range of bias voltages, the bias amplifier can work off either a low analog
supply or the higher AVDD3_33 analog supply.To support a wide range of bias voltages, the MICBIAS and
MICBIAS_EXT voltage are generated through an onchip low-dropout regulator. Thus, programmed voltages
should be 300mV below MICBIAS_VDD.
Table 15. MICBIAS Voltage Control
MICBIAS Mode
B0_P1_R51_D[2:0]
B0_P1_R8_D2
Minimum
MICBIAS_VD
D Voltage
MICBIAS Output Voltage (without
load)
000
001
0 or 1
0 or 1
2.7V
2.7V
Grounded
Tristated (use only if external bias
utilized)
MICBIAS Mode 0
MICBIAS Mode 0
MICBIAS Mode 1
MICBIAS Mode 1
MICBIAS Mode 4
MICBIAS Mode 4
MICBIAS Mode 5
MICBIAS Mode 5
010
010
011
011
110
110
111
111
0
1
0
1
0
1
0
1
2.7V
2.7V
2.7V
2.7V
3.05V
2.7V
3.2V
2.7V
1.80V
1.50V
2.00V
1.67V
2.85V
2.37V
3.00V
2.50V
Table 16. MICBIAS_EXT Voltage Control
MICBIAS_EXT Mode
B0_P1_R51_D[6:4]
B0_P1_R8_D2
Minimum
MICBIAS_VD
D Voltage
MICBIAS Voltage (without load)
000
001
0 or 1
0 or 1
2.7V
2.7V
Grounded
Tristated (use only if external bias
utilized)
MICBIAS_EXT Mode 0
MICBIAS_EXT Mode 0
MICBIAS_EXT Mode 1
MICBIAS_EXT Mode 1
010
010
011
011
0
1
0
1
2.7V
2.7V
2.7V
2.7V
1.80V
1.50V
2.00V
1.67V
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Table 16. MICBIAS_EXT Voltage Control (continued)
MICBIAS_EXT Mode
B0_P1_R51_D[6:4]
B0_P1_R8_D2
Minimum
MICBIAS_VD
D Voltage
MICBIAS Voltage (without load)
MICBIAS_EXT Mode 4
MICBIAS_EXT Mode 4
MICBIAS_EXT Mode 5
MICBIAS_EXT Mode 5
110
110
111
111
0
1
0
1
3.05V
2.7V
3.2V
2.7V
2.85V
2.37V
3.00V
2.50V
8.3.2.8.3 Digital Microphone Function
In addition to supporting analog microphones, the TLV320AIC3268 also interfaces to digital microphones.
Σ-Δ
LEFT ADC
CIC FILTER
Σ-Δ
RIGHT ADC
CIC FILTER
Signal
Processing
Blocks
LEFT CIC2
FILTER
RIGHT CIC2
FILTER
DIG_MIC_IN2
ADC_MOD_CLK
DIG_MIC_IN1
DOUT2 MISO_GPO1
BCLK2
WCLK2
GPIO4 GPIO5
GPIO3
DIN2
GPIO1 GPIO2
DIN1
Figure 50. Digital Microphone in TLV320AIC3268
The TLV320AIC3268 outputs internal clock ADC_MOD_CLK on several digital IO terminals. This clock can act
as DigMic Clock. The generation of ADC_MOD_CLK is described in Figure 58. The digital microphone data can
be accepted on several terminals on both the rising edge as well as the falling edge of the DigMic Clock.
Table 17 describes the various ways in which digital microphone interface can be implemented using the several
terminal options available in TLV320AIC3268. The TLV320AIC3268 supports two stereo channels of digital
microphone. The stereo Digital Mic 1 channel can be muxed with the ADC modulator for analog inputs. The
54
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additional stereo Digital Mic 2 channel is seperately supported. Both these channels use the same DigMic Clock.
The Digital Mic 1 channel can be processed either by the built in processing available in PRB_Rx modes or be
custom processed in miniDSP. The Digital Mic 2 channel can be processed by using the miniDSP. Each data
line configured for digital microphone data can support either mono data or stereo data by using both edges of
DigMic Clock. Some of the common digital microphone features as listed in Table 17.
Table 17. Digital Microphone Features
Digital Microphone Feature
Digital Mic 1 enabled for Left ADC CIC Filter
Register
B0_P0_R81_D[5:4]=01
Digital Mic 1 enabled for Right ADC CIC Filter
Digital Mic 2 enabled for Left CIC2 Filter
B0_P0_R81_D[3:2]=01
B0_P0_R112_D[5:4]=01
B0_P0_R112_D[3:2]=01
B0_P4_R100_D[7]
Digital Mic 2 enabled for Right CIC2 Filter
Digital Mic 1 left channel data valid clock edge control
Digital Mic 1 right channel data valid clock edge control
Digital Mic 2 left channel data valid clock edge control
Digital Mic 2 right channel data valid clock edge control
Digital Mic 1 left channel data terminal selection
Digital Mic 1 right channel data terminal selection
Digital Mic 2 left channel data terminal selection
Digital Mic 2 right channel data terminal selection
B0_P4_R100_D[6]
B0_P4_R100_D[3]
B0_P4_R100_D[2]
B0_P4_R101_D[7:4]
B0_P4_R101_D[3:0]
B0_P4_R102_D[7:4]
B0_P4_R102_D[3:0]
Since the digital microphone signals do not pass through the ADC PGA block, the hardware AGC should not be
enabled while using digital microphone inputs for left and right ADC channels.
ADC_MOD_CLK
DIG_MIC_IN
RIGHT
RIGHT
LEFT
RIGHT
LEFT
LEFT
Figure 51. Timing Diagram for Digital Microphone Interface
The digital-microphone mode can be selectively enabled for only-left, only-right, or stereo channels. When the
digital microphone mode is enabled, the analog section of the ADC can be powered down and bypassed for
power efficiency. The AOSR value for the ADC channel must be configured to select the desired decimation ratio
to be achieved based on the external digital microphone properties.
Figure 52 is a typical circuit diagram showing one possibility for connecting digital microphones. All terminal
assignment options for digital microphones are described in Rows E and J of the terminal muxing tables in and
(located in Multifunction Terminals). Depending on the performance of the digital microphone (for example
PSRR) and the noise level on the IOVDDx_33 power supply, some additional filtering may be needed for Vmic
near the digital microphone for best performance.
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IOVDD
(1.1 V – 3.6 V)
IOVDD1_33
10uF
0.1uF
AIC3268
IOVSS
Vmic
VDD
CLK
DATA
L/R
GPIO1
GPIO5
GND
Vmic
VDD
CLK
DATA
L/R
GND
Vmic
VDD
CLK
GPIO2
VSS
DATA
L/R
GND
Vmic
VDD
CLK
DATA
L/R
GND
Figure 52. Typical Digital Microphone External Circuitry
8.3.2.8.4 Channel-to-Channel Phase Adjustment
The TLV320AIC3268 has a built-in feature to fine-adjust the phase between the stereo ADC record signals. The
phase compensation is particularly helpful to adjust delays when using dual microphones for noise cancellation
and other processing. This delay can be controlled in fine amounts in the following fashion.
Delay(7:0) = B0_P0_R85_D[7:0]
Where
RIGHT _ ADC _PHASE _ COMP(t) = RIGHT _ ADC _ OUT(t - tpr
where
tpr
)
(3)
(4)
(Delay(4 : 0) + Delay(6 : 5) * AOSR * kf )
=
AOSR * ADC _FS
Where kf is a function of the decimation filter:
Decimation Filter Type
kf
A
B
C
0.25
0.5
1
and
LEFT _ ADC _ PHASE _ COMP (t) = LEFT _ ADC _ OUT (t - tpl )
(5)
(6)
Where
Delay(7)
=
tpl
ADC _FS
This feature is available for stereo analog inputs or Digital Mic 1 channel.
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8.3.2.8.5 Fast Charging AC Capacitors
The value of the coupling capacitor must be so chosen that the high-pass filter formed by the coupling capacitor
and the input impedance do not affect the signal content. At power-up, before proper recording can begin, this
coupling capacitor must be charged up to the common-mode voltage. To enable quick charging, the
TLV320AIC3268 has modes to speed up the charging of the coupling capacitor. These are controlled by the
values in B0_P1_R122_D[1:0].
8.3.2.8.6 Anti Thump
For normal voice or audio recording, the analog input terminals of the TLV320AIC3268, must be AC-coupled to
isolate the DC-common mode voltage of the driving circuit from the common-mode voltage of the
TLV320AIC3268.
When the analog inputs are not selected for any routing, the input terminals are 3-stated and the voltage on the
terminals is undefined. When the unselected inputs are selected for any routing, the input terminals must charge
from the undefined voltage to the input common-mode voltage. This charging signal can cause audible artifacts.
In order to avoid such artifacts the TLV320AIC3268 also incorporates anti-thump circuitry to allow connection of
unused inputs to the common-mode level. This feature is disabled by default, and can be enabled by writing the
appropriate values into B0_P1_R58_D[7:0]. The use of this feature in combination with the PTM_R1 setting in
B0_P0_R61 when the ADC channel is powered down causes the additional current consumption of 700μA from
AVDDx_18 and 125μA from DVDDx_18 in the sleep mode.
8.3.2.8.7 Adaptive Filtering
After the ADC is running, the filter coefficients are locked and cannot be accessed for read or write. However the
TLV320AIC3268 offers an adaptive filter mode as well. Setting B40_P0_R1_D2=1 turns on double buffering of
the coefficients. In this mode filter coefficients can be updated through the host and activated without
stopterminalg and restarting the ADC, enabling advanced adaptive filtering applications.
To support double buffering, all coefficients are stored in two buffers (Buffer A and B). When the ADC is running
and adaptive filtering mode is turned on, setting the control bit B40_P0_R1_D0=1 switches the coefficient buffers
at the next start of a sampling period. The bit reverts to 0 after the switch occurs. At the same time, the flag
B40_P0_R1_D1 toggles.
The flag in B40_P0_R1_D1 indicates which of the two buffers is actually in use.
For B40_P0_R1_D1=0: Buffer A is in use by the ADC engine. For B40_P0_R1_D1=1: Buffer B is in use.
While the device is running, coefficient updates are always made to the buffer not in use by the ADC, regardless
to which buffer the coefficients have been written.
ADC running
Flag, B40_P0_R1_D1
Coefficient Buffer in use
Writing to
C4, Buffer A
C4, Buffer B
C4, Buffer A
C4, Buffer B
C4, Buffer A
C4, Buffer B
Will update
C4, Buffer A
C4, Buffer B
C4, Buffer B
C4, Buffer B
C4, Buffer A
C4, Buffer A
No
No
0
0
0
0
1
1
None
None
Yes
Yes
Yes
Yes
Buffer A
Buffer A
Buffer B
Buffer B
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8.3.3 DAC
The TLV320AIC3268 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation
filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed
within the audio band to beyond 20kHz. To handle multiple input rates and optimize power dissipation and
performance, the TLV320AIC3268 allows the system designer to program the oversampling rates over a wide
range from 1 to 1024. The system designer can choose higher oversampling ratios for lower input data rates and
lower oversampling ratios for higher input data rates.
The TLV320AIC3268 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320AIC3268 features many options for signal conditioning and signal routing:
•
2 headphone amplifiers
–
–
Usable in single-ended stereo or differential mono mode
Analog volume setting with a range of -6 to +14 dB
•
•
Line-out amplifiers
Usable in streo single-ended or stereo differential modes
Class-D speaker amplifier
–
–
–
Usable with left, right, or monophonic mix modes
Analog volume control with a settings of +6, +12, +18, +24, and +30 dB
•
1 Receiver amplifier
–
–
Usable in mono differential mode
Analog volume setting with a range of -6 to +29 dB
•
•
Digital volume control with a range of -63.5 to +24dB
Mute function
In addition to the standard set of DAC features the TLV320AIC3268 also offers the following special features:
•
•
Digital auto mute
Adaptive coefficient update mode
In addition to the above signal processing functions, extensive algorithms are available by programming the
miniDSP. For specific details on available algorithms, please contact Texas Instruments.
8.3.3.1 DAC Processing Blocks
The TLV320AIC3268 implements signal processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
Table 18 gives an overview over all available processing blocks of the DAC channel and their properties. The
Resource Class Column (RC) gives an approximate indication of power consumption.
The signal processing blocks available are:
•
•
First-order IIR
Scalable number of biquad filters
The processing blocks can be chosen based on mono or stereo playback requirement and need for additional
filtering for frequency shaping. The available first-order IIR and biquad filters have fully user-programmable
coefficients.
58
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Table 18. Overview – DAC Predefined Processing Blocks
Processing
Block No.
Interpolation
Filter
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
RC Class
PRB_P1(1)
PRB_P3
PRB_P6
A
A
A
Stereo
Stereo
Left
No
Yes
Yes
2
6
6
No
No
No
No
No
No
No
No
No
8
10
5
(1) Default
8.3.3.2 DAC Processing Blocks – Details
8.3.3.2.1 2 Biquads, Interpolation Filter A
Interp.
Filter A
to Modulator
from Interface
BiQuad A
BiQuad B
Digital
Volume Ctrl
Figure 53. Signal Chain for PRB_P1 (Stereo)
8.3.3.2.2 6 Biquads, 1st order IIR, Interpolation Filter A or B
Interp.
BiQuad
A
BiQuad
B
BiQuad
C
BiQuad
D
BiQuad
E
BiQuad
F
to
IIR
Filter
A,B
from
Modulator
Interface
Digital
Volume
Ctrl
Figure 54. Signal Chain for PRB_P3 (Stereo) and PRB_P6 (Left)
8.3.3.3 User Programmable Filters
The TLV320AIC3268 allows either 3 or 6 user programmable BiQuad filters in DAC channel. Some processing
blocks also support a first order IIR filter for dc-blocking.
The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive
coefficient update mode is chosen, the coefficient banks can be switched on-the-fly. For more details on adaptive
filtering please see Adaptive Filtering.
The coefficients of these filters are each 24-bits wide, in two's-complement and occupy 3 consecutive 8-bit
registers in the register space. For default values please see DAC Defaults.
8.3.3.3.1 1st-Order IIR Section
The IIR is of first-order and its transfer function is given by
N0 + N1z-1
H(z) =
223 - D1z-1
(7)
The frequency response for the 1st order IIR Section with default coefficients is flat. Details on DAC coefficient
default values are given in DAC Defaults.
Table 19. DAC IIR Filter Coefficients
Filter
Filter Coefficient DAC Coefficient Left Channel DAC Coefficient Right
Channel
1st Order IIR
N0
N1
D1
C1 (B80_P1_R12-R14)
C2 (B80_P3_R16-R18)
C3 (B80_P3_R20-R22)
C36 (B80_P3_R32-R34)
C37 (B80_P3_R36-R38)
C38 (B80_P3_R40-R42)
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8.3.3.3.2 Biquad Section
The transfer function of each of the Biquad Filters is given by
N0 + 2 * N1z-1 + N2z-2
223 - 2 *D1z-1 -D2z-2
H(z) =
(8)
The frequency response for each biquad section with default coefficients is flat at a gain of 0dB. Details on DAC
coefficient default values are given in DAC Defaults.
Table 20. DAC Biquad Filter Coefficients
Filter
Coefficient
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
Left DAC Channel
Right DAC Channel
BIQUAD A
C4 (B80_P1_R24-R26)
C5 (B80_P1_R28-R30)
C6 (B80_P1_R32-R34)
C7 (B80_P1_R36-R38)
C8 (B80_P1_R40-R42)
C9 (B80_P1_R44-R46)
C10 (B80_P1_R48-R50)
C11 (B80_P1_R52-R54)
C12 (B80_P1_R56-R58)
C13 (B80_P1_R60-R62)
C14 (B80_P1_R64-R66)
C15 (B80_P1_R68-R70)
C16 (B80_P1_R72-R74)
C17 (B80_P1_R76-R78)
C18 (B80_P1_R80-R82)
C19 (B80_P1_R84-R86)
C20 (B80_P1_R88-R90)
C21 (B80_P1_R92-R94)
C22 (B80_P1_R96-R98)
C23 (B80_P1_R100-R102)
C24 (B80_P1_R104-R106)
C25 (B80_P1_R108-R110)
C26 (B80_P1_R112-R114)
C27 (B80_P1_R116-R118)
C28 (B80_P1_R120-R122)
C29 (B80_P1_R124-R126)
C30 (B80_P2_R8-R10)
C31 (B80_P2_R12-R14)
C32 (B80_P2_R16-R18)
C33 (B80_P2_R20-R22)
C39 (B80_P2_R44-R46)
C40 (B80_P2_R48-R50)
C41 (B80_P2_R52-R54)
C42 (B80_P2_R56-R58)
C43 (B80_P2_R60-R62)
C44 (B80_P2_R64-R66)
C45 (B80_P2_R68-R70)
C46 (B80_P2_R72-R74)
C47 (B80_P2_R76-R78)
C48 (B80_P2_R80-R82)
C49 (B80_P2_R84-R86)
C50 (B80_P2_R88-R90)
C51 (B80_P2_R92-R94)
C52 (B80_P2_R96-R98)
C53 (B80_P2_R100-R102)
C54 (B80_P2_R104-R106)
C55 (B80_P2_R108-R110)
C56 (B80_P2_R112-R114)
C57 (B80_P2_R116-R118)
C58 (B80_P2_R120-R122)
C59 (B80_P2_R124-R126)
C60 (B80_P3_R8-R10)
C61 (B80_P3_R12-R14)
C62 (B80_P3_R16-R18)
C63 (B80_P3_R20-R22)
C64 (B80_P3_R24-R26)
C65 (B80_P3_R28-R30)
C66 (B80_P3_R32-R34)
C67 (B80_P3_R36-R38)
C68 (B80_P3_R40-R42)
BIQUAD B
BIQUAD C
BIQUAD D
BIQUAD E
BIQUAD F
60
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8.3.3.4 Interpolation Filters
8.3.3.4.1 Interpolation Filter A
Filter A is designed for an Fs up to 48ksps with a flat passband of 0kHz–20kHz.
Table 21. DAC Interpolation Filter A, Specification
Parameter
Condition
Value (Typical)
±0.015
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 … 0.45fS
0.55Fs… 7.455fS
–65
dB
21/fS
s
DAC Channel Response for Interpolation Filter A
(Red line corresponds to –65 dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1
2
3
4
5
6
7
Frequency Normalized to fS
G016
Figure 55. DAC Interpolation Filter A, Frequency Response
8.3.3.4.2 Interpolation Filter B
Filter B is specifically designed for an Fs of above 96ksps. Thus, the flat pass-band region easily covers the
required audio band of 0-20kHz.
Table 22. DAC Interpolation Filter B, Specification
Parameter
Condition
Value (Typical)
±0.015
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 … 0.45fS
0.55Fs… 3.45fS
–58
dB
18/fS
s
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DAC Channel Response for Interpolation Filter B
(Red line corresponds to –58 dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Frequency Normalized to fS
G017
Figure 56. Channel Interpolation Filter B, Frequency Response
8.3.3.4.3 Interpolation Filter C
Filter C is specifically designed for the 192ksps mode. The pass band extends up to 0.40*Fs (corresponds to
80kHz), more than sufficient for audio applications.
DAC Channel Response for Interpolation Filter C
(Red line corresponds to –43 dB)
0
–10
–20
–30
–40
–50
–60
–70
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Frequency Normalized to fS
G018
Figure 57. DAC Interpolation Filter C, Frequency Response
Table 23. DAC Interpolation Filter C, Specification
Parameter
Condition
Value (Typical)
±0.03
Units
dB
Filter Gain Pass Band
Filter Gain Stop Band
Filter Group Delay
0 … 0.35fS
0.60Fs… 1.4fS
–43
dB
13/fS
s
62
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8.3.3.5 DAC Gain Setting
8.3.3.5.1 PowerTune Modes
As part of the PowerTune strategy, the analog properties of the DAC are adjusted. As a consequence, the full-
scale signal swing achieved at the headphone outputs must be adjusted.
Please see Table 24 for the proper gain compensation values across the different combinations.
Table 24. DAC Gain versus PowerTune Modes
DAC PowerTune
Mode Control
PowerTune Mode
Headphone Gain
Page 1,Register 3/4,
Bits D4-D2)
CM = 0.75V, Gain for 375mVRMS output
CM = 0.9V, Gain for 500mVRMS output
swing at 0dB full scale input
swing at 0dB full scale input
000
001
010
PTM_P3, PTM_P4
PTM_P2
0
4
0
4
PTM_P1
14
14
8.3.3.5.2 Digital Volume Control
The TLV320AIC3268 signal processing blocks incorporate a digital volume control block that can control the
volume of the playback signal from +24dB to –63.5dB in steps of 0.5dB. These can be controlled by writing to
B0_P0_R65 and B0_P0_R66. The volume control of left and right channels by default can be controlled
independently, but by programming B0_P0_R64_D[1:0], they can be made interdependent. The volume changes
are soft-stepped in steps of 0.5dB to avoid audible artifacts during gain change. The rate of soft-stepping can be
controlled by programming B0_P0_R63_D[1:0] to either one step per frame (DAC_FS ) or one step per 2 frames.
The soft-stepping feature can also be entirely disabled. During soft-stepping the value of the actual applied gain
would differ from the programmed gain in register. The TLV320AIC3268 gives a feedback to the user in form of
register readable flag to indicate that soft-stepping is currently in progress. The flags for left and right channels
can be read back by reading B0_P0_R38_D4 and B0_P0_R38_D0 respectively. A value of 0 in these flags
indicates a soft-stepping operation in progress, and a value of 1 indicates that soft-stepping has completed. A
soft-stepping operation comes into effect during a) power-up, when the volume control soft-steps from –63.5dB
to programmed gain value b) volume change by user when DAC is powered up and c) power-down, when the
volume control block soft-steps to –63.5dB before powering down the channel.
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8.3.3.6 DAC Special Functions
8.3.3.6.1 Digital Auto Mute
The TLV320AIC3268 also incorporates a special feature, in which the DAC channel is auto-muted when a
continuous stream of DC-input is detected. When using PRB_Px modes, the Data Input 1 (L1,R1) ports of
miniDSP_D are monitoted for DC-inputs. Signals routed to Data Input 1 port is controlled by configuring
B0_P4_R118_D[5:4].By default, this feature is disabled. It can be enabled by writing a non-000 value into
B0_P0_R64_D[6:4]. The non-zero value controls the duration of continuous stream of DC-input before which the
auto-mute feature takes effect. This feature is especially helpful for eliminating high-frequency-noise power being
delivered into the load even during silent periods of speech or music.
8.3.3.6.2 Adaptive Filtering
When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed for either
read or write.
However, the TLV320AIC3268 offers an adaptive filter mode as well, and the DAC contains two separate
adaptive filter coefficient banks (Primary Adaptive Bank in Book 80, and Secondary Adaptive Bank in Book 82).
Setting B80_P0_R1_D2=1 for the Primary Adaptive Bank will turn on double buffering of the coefficients.
Similarly, setting B82_P0_R1_D2=1 will turn on double buffering of the coefficients in the Secondary Adaptive
Bank. In this mode, filter coefficients can be updated through the host, and activated without stopping and
restarting the DAC. This enables advanced adaptive filtering applications.
In the double-buffering scheme, all coefficients are stored in two buffers (Buffers A and B). When the DAC is
running and adaptive filtering mode is turned on, setting the control bit B80_P0_R1_D0=1 (B82_P0_R1_D0=1 if
using Secondary Bank) switches the coefficient buffers at the next start of a sampling period. This bit is set back
to 0 after the switch occurs. At the same time, the flag B80_P0_R1_D1 (B82_P0_R1_D1 if using Secondary
Bank) toggles.
The flag in B80_P0_R1_D1 indicates which of the two buffers in the Primary Bank is actually in use.
B80_P0_R1_D1=0: Buffer A is in use by the DAC engine, Bit D1=1: Buffer B is in use.
While the device is running, coefficient updates are always made to the buffer not in use by the DAC, regardless
to which buffer the coefficients have been written.
DAC running
B80_P0_R1_D1 for Primary Bank Coefficient Buffer in use
Writing to
Will update
(B82_P0_R1_D1 for Secondary
Bank)
No
0
0
0
0
1
1
None
C1, Buffer A
C1, Buffer B
C1, Buffer A
C1, Buffer B
C1, Buffer A
C1, Buffer B
C1, Buffer A
C1, Buffer B
C1, Buffer B
C1, Buffer B
C1, Buffer A
C1, Buffer A
No
None
Yes
Yes
Yes
Yes
Buffer A
Buffer A
Buffer B
Buffer B
The user programmable coefficients C1 to C70 are defined on B80_P1-P3 for Buffer A and B80_P9-P11 for
Buffer B. For the Secondary Bank, the coefficients are located on similar pages on Book 82.
8.3.4 Clock Generation and PLL
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output terminal and may be used elsewhere in the system. The clock system is
flexible enough that it even allows the internal clocks to be derived directly from an external clock source, while
the PLL is used to generate some other clock that is only used outside the TLV320AIC3268.
The ADC_CLKIN and DAC_CLKIN can then be routed through highly-flexible clock dividers to generate the
various clocks required for ADC, DAC and the miniDSP sections.
64
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The TLV320AIC3268 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as the interface and other control blocks as shown in Figure 58. The clocks for the ADC and the DAC
require a source reference clock. In the TLV320AIC3268 the ADC and DAC clock-trees can have different root
clocks. These clocks can be provided on a variety of device terminals such as MCLK, BCLK1, BCLK2, GPIO1,
GPIO2 and GPIO3, and the onchip high-frequency reference clock (HF_REF_CLK) and high-frequency oscillator
clock (HF_OSC_CLK) can also be provided as sources. The source reference clock for the ADC can be chosen
by programming the ADC_CLKIN value on B0_P0_R4_D[3:0]. The source reference clock for the DAC can be
chosed by programming the DAC_CLKIN value on B0_P0_R4_D[7:4]. The ADC_CLKIN and DAC_CLKIN can
then be routed through highly flexible clock dividers shown in Figure 58 to generate the various clocks required
for the ADC, DAC, and miniDSP sections. In the event that the desired audio miniDSP clocks cannot be
generated from the reference clocks coming from the device terminals listed above, the TLV320AIC3268 also
provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to
generate the required clocks. Starting from ADC_CLKIN and DAC_CLKIN, the TLV320AIC3268 provides several
programmable clock dividers to help achieve a variety of sampling rates for the ADC and DAC, as well as clocks
for the miniDSP sections.
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MCLK
BCLK1
BCLK2
GPIO1
GPIO2
GPIO3
PLL_CLK
HF_REF_CLK
HF_OSC_CLK
DAC_CLKIN
ADC_CLKIN
NDAC=1,2,…..,
127,128
NADC=1,2,…..,
127,128
¸ NDAC
¸ NADC
To DAC miniDSP clock
generation
DAC_CLK
ADC_CLK
To ADC miniDSP
clock generation
MDAC=1,2,…..,
127,128
MADC=1,2,…..,
127,128
¸ MDAC
¸ MADC
DAC_MOD_CLK
ADC_MOD_CLK
DOSR=1,2,…..,
1023,1024
AOSR=1,2,…..,
255,256
¸ DOSR
¸ AOSR
DAC_FS
ADC_FS
Figure 58. Clock Distribution Tree
The DAC and ADC clocks are obtained as follows:
DAC_CLKIN
NDAC ´ MDAC ´ DOSR
DAC_CLKIN
DAC_fs =
(9)
(10)
(11)
DAC_MOD_CLK =
NDAC ´ MDAC
ADC _CLKIN
NADC´MADC´ AOSR
ADC _ fS
=
66
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ADC_CLKIN
ADC_MOD_CLK =
NADC ´ MADC
(12)
The MUX settings in the ADC clock tree allow alternative clock settings:
DAC_CLKIN
ADC_fs =
NDAC ´ MADC ´ AOSR
or
DAC_CLKIN
ADC_fs =
NDAC ´ MDAC ´ AOSR
(13)
(14)
DAC_CLKIN
ADC_MOD_CLK =
NDAC ´ MADC
or
DAC_CLKIN
ADC_MOD_CLK =
NDAC ´ MDAC
By default ADC_CLK = DAC_CLK and ADC_MOD_CLK = DAC_MOD_CLK.
Table 25. DAC CLKIN and ADC CLKIN Clock Dividers
Divider Bits
Range
NDAC
MDAC
DOSR
NADC
MADC
AOSR
B0_P0_R11_D[6:0]
1, 2, … 127, 128
1, 2, … 127, 128
1, 2, … 1023, 1024
1, 2, … 127, 128
1, 2, … 127, 128
1, 2, … 255, 256
B0_P0_R12_D[6:0]
B0_P0_R13_D[1:0] and B0_P0_R14_D[7:0]
B0_P0_R18_D[6:0]
B0_P0_R19_D[6:0]
B0_P0_R20_D[7:0]
The registers used for DAC and ADC clock selection are listed in Table 26.
Table 26. DAC and ADC Clock Selectors
Selector
Bits
Inputs
MCLK1, MCLK2, BCLK1, GPIO1, PLL_CLK, BCLK2, GPI1, HR_REF_CLK,
HF_OSC_CLK, GPIO2, GPI2
DAC_CLKIN
B0_P0_R4_D[7:4]
MCLK1, MCLK2, BCLK1, GPIO1, PLL_CLK, BCLK2, GPI1, HR_REF_CLK,
HF_OSC_CLK, GPIO2, GPI2
ADC_CLKIN
ADC_CLK
B0_P0_R4_D[3:0]
B0_P0_R18_D7
NDAC output (DAC_CLK), NADC output
ADC_MOD_CLK B0_P0_R19_D7
MDAC output (DAC_MOD_CLK), MADC output
The DAC Modulator is clocked by DAC_MOD_CLK. For proper power-up of the DAC Channel, these clocks must
be enabled by configuring the NDAC and MDAC clock dividers (B0_P0_R11_D7=1 and B0_P0_R12_D7=1).
When the DAC channel is powered down, the device internally initiates a power-down sequence for proper shut-
down. During this shut-down sequence, the NDAC and MDAC dividers must not be powered down, or else a
proper low power shut-down may not take place. The user can read the power-status flag in B0_P0_R37_D7 for
the Left DAC and B0_P0_R37_D3 for the Right DAC. When both flags indicate power-down, the MDAC divider
may be powered down, followed by the NDAC divider.
The ADC modulator is clocked by ADC_MOD_CLK. For proper power-up of the ADC Channel, these clocks are
enabled by the NADC and MADC clock dividers (B0_P0_R18_D7=1 and B0_P0_R19_D7=1). When the ADC
channel is powered down, the device internally initiates a power-down sequence for proper shut-down. During
this shut-down sequence, the NADC and MADC dividers must not be powered down, or else a proper low power
shut-down may not take place. The user can read the power-status flag in B0_P0_R36_D6 for the Left ADC and
B0_P0_R36_D2 for the Right ADC. When both flags indicate power-down, the MADC divider may be powered
down, followed by NADC divider.
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When ADC_CLK is derived from the NDAC divider output, the NDAC must be kept powered up till the power-
down status flags for ADC do not indicate that the ADC is still in the process of powering down. When the input
to the AOSR clock divider is derived from DAC_MOD_CLK, then MDAC must be powered up when ADC_FS is
needed (that is when WCLK is generated by TLV320AIC3268 or AGC is enabled) and can be powered down
only after the ADC power-down flags indicate power-down status.
In general, all the root clock dividers should be powered down only after the child clock dividers have been
powered down for proper operation.
The TLV320AIC3268 also has options for routing some of the internal clocks to the output terminals of the device
to be used as general purpose clocks in the system.
For example, the TLV320AIC3268 can be configured to drive the bit clock signals ASI1_BCLK_OUT,
ASI2_BCLK_OUT, and ASI3_BCLK_OUT on the three serial interfaces as shown in Figure 59.
DAC_MOD_CLK
ADC_MOD_CLK
DAC_MOD_CLK
ADC_MOD_CLK
DAC_MOD_CLK
ADC_MOD_CLK
DAC_CLK ADC_CLK
DAC_CLK ADC_CLK
DAC_CLK
ADC_CLK
ASI1_BDIV_CLKIN
N=1,2,…..,127,128
ASI2_BDIV_CLKIN
ASI3_BDIV_CLKIN
¸
¸
¸
N=1,2,…..,127,128
N=1,2,…..,127,128
ASI1_BDIV
ASI2_BDIV
ASI3_BDIV
ASI1_BDIV_OUT
ASI2_BDIV_OUT
ASI3_BDIV_OUT
ASI1_BCLK
ASI1_BCLK
ASI2_BCLK
ASI2_BCLK
ASI3_BCLK
ASI3_BCLK
ASI1_BCLK_OUT
ASI2_BCLK_OUT
ASI3_BCLK_OUT
Figure 59. Bit Clock Output Options for ASI1, ASI2, and ASI3
When TLV320AIC3268 is configured to drive ASI1_BCLK_OUT, the clock signal can be selected via
B0_P4_R14_D[6:4] to come from ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI2_BCLK Input, or
ASI3_BCLK Input.
When TLV320AIC3268 is configured to drive ASI2_BCLK_OUT, the clock signal can be selected via
B0_P4_R30_D[6:4] to come from ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI1_BCLK Input, or
ASI3_BCLK Input.
When TLV320AIC3268 is configured to drive ASI3_BCLK_OUT, the clock signal can be selected via
B0_P4_R46_D[6:4] to come from ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI1_BCLK, or
ASI2_BCLK.
ASI1_BDIV_OUT is a divided value of ASI1_BDIV_CLKIN, where the division value can be programmed in
B0_P4_R12_D[6:0] from 1 to 128, and this bit clock divider can be powered on by setting B0_P4_R12_D7. The
ASI1_BDIV_CLKIN can itself be configured to be one of DAC_CLK, DAC_MOD_CLK, ADC_CLK or
ADC_MOD_CLK by configuring the ASI1_BDIV_CLKIN mux in B0_P4_R11_D[1:0].
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ASI2_BDIV_OUT is a divided value of ASI2_BDIV_CLKIN, where the division value can be programmed in
B0_P4_R28_D[6:0] from 1 to 128, and this bit clock divider can be powered on by setting B0_P4_R28_D7. The
ASI2_BDIV_CLKIN can itself be configured to be one of DAC_CLK, DAC_MOD_CLK, ADC_CLK or
ADC_MOD_CLK by configuring the ASI2_BDIV_CLKIN mux in B0_P4_R27_D[1:0].
ASI3_BDIV_OUT is a divided value of ASI3_BDIV_CLKIN, where the division value can be programmed in
B0_P4_R44_D[6:0] from 1 to 128, and this bit clock divider can be powered on by setting B0_P4_R44_D7. The
ASI3_BDIV_CLKIN can itself be configured to be one of DAC_CLK, DAC_MOD_CLK, ADC_CLK or
ADC_MOD_CLK by configuring the ASI3_BDIV_CLKIN mux in B0_P4_R43_D[1:0].
The TLV320AIC3268 can also be configured to provide the world clocks for ASI1, ASI2, and ASI3 as shown in
Figure 60.
ASI3_BCLK
ASI1_BCLK
ASI2_BCLK
¸
¸
N=32,33,…..,127,128
¸
N=32,33,…..,127,128
N=32,33,…..,127,128
ASI1_WDIV
ASI2_WDIV
ASI3_WDIV
ASI1_WDIV_OUT
ASI2_WDIV_OUT
ASI3_WDIV_OUT
ASI1_WDIV_OUT ASI1_WCLK
ASI2_WDIV_OUT
ASI2_WCLK
ASI1_WDIV_OUT
ASI1_WDIV_OUT ASI1_WCLK
ASI2_WDIV_OUT
ASI2_WDIV_OUT
ASI2_WCLK
ADC_FS
ADC_FS
DAC_FS
ADC_FS
DAC_FS
DAC_FS
ASI3_WDIV_OUT
ASI3_WCLK
ASI3_WDIV_OUT
ASI3_WDIV_OUT
ASI3_WCLK
ASI1_WCLK_OUT
ASI2_WCLK_OUT
ASI3_WCLK_OUT
Figure 60. Word Clock Options for ASI1, ASI2, and ASI3
ASI1_WCLK_OUT can be selected to come from DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT,
ASI3_WDIV_OUT, as well as ASI2_WCLK Input, and ASI3_WCLK Input using B0_P4_R14_D[2:0].
ASI1_WDIV_OUT is driven as a divided value of ASI1_BCLK, where the division can be programmed in
B0_P4_R13_D[6:0] from 32 to 128, and this word clock divider can be powered on by setting B0_P4_R13_D7.
ASI2_WCLK_OUT can be selected to come from DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT,
ASI3_WDIV_OUT, as well as ASI1_WCLK Input, and ASI3_WCLK Input using B0_P4_R30_D[2:0].
ASI2_WDIV_OUT is driven as a divided value of ASI2_BCLK, where the division can be programmed in
B0_P4_R29_D[6:0] from 32 to 128, and this word clock divider can be powered on by setting B0_P4_R29_D7.
ASI3_WCLK_OUT can be selected to come from DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT,
ASI3_WDIV_OUT, as well as ASI1_WCLK Input, and ASI2_WCLK Input using B0_P4_R46_D[2:0].
ASI3_WDIV_OUT is driven as a divided value of ASI3_BCLK, where the division can be programmed in
B0_P4_R45_D[6:0] from 32 to 128, and this word clock divider can be powered on by setting B0_P4_R45_D7.
The bit clock and work clock dividers are summarized in Table 27. The bit clock and word clock selectors are
summarized in Table 28.
Table 27. ASI1, ASI2, and ASI3 Bit and Word Clock Dividers
Divider
Bits
Range
ASI1_BDIV
B0_P4_R12_D[6:0]
1, 2, … 127, 128
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Table 27. ASI1, ASI2, and ASI3 Bit and Word Clock Dividers (continued)
Divider
Bits
Range
ASI2_BDIV
ASI3_BDIV
ASI1_WDIV
ASI2_WDIV
ASI3_WDIV
B0_P4_R28_D[6:0]
B0_P4_R44_D[6:0]
B0_P4_R13_D[6:0]
B0_P4_R29_D[6:0]
B0_P4_R45_D[6:0]
1, 2, … 127, 128
1, 2, … 127, 128
32, 33, … 127, 128
32, 33, … 127, 128
32, 33, … 127, 128
Table 28. ASI1, ASI2, and ASI3 Bit and Word Clock Selection
Selector
Bits
Inputs
ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI2_BCLK,
ASI3_BCLK
ASI1_BCLK_OUT
B0_P4_R14_D[6:4]
B0_P4_R30_D[6:4]
B0_P4_R46_D[6:4]
ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI1_BCLK,
ASI3_BCLK
ASI2_BCLK_OUT
ASI3_BCLK_OUT
ASI1_BDIV_OUT, ASI2_BDIV_OUT, ASI3_BDIV_OUT, ASI1_BCLK,
ASI2_BCLK
ASI1_BDIV_CLKIN
ASI2_BDIV_CLKIN
ASI3_BDIV_CLKIN
B0_P4_R11_D[1:0]
B0_P4_R27_D[1:0]
B0_P4_R43_D[1:0]
DAC_CLK, DAC_MOD_CLK, ADC_CLK, ADC_MOD_CLK
DAC_CLK, DAC_MOD_CLK, ADC_CLK, ADC_MOD_CLK
DAC_CLK, DAC_MOD_CLK, ADC_CLK, ADC_MOD_CLK
DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT, ASI3_WDIV_OUT,
ASI2_WCLK, ASI3_WCLK
ASI1_WCLK_OUT
ASI2_WCLK_OUT
ASI3_WCLK_OUT
B0_P4_R14_D[2:0]
B0_P4_R30_D[2:0]
B0_P4_R46_D[2:0]
DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT, ASI3_WDIV_OUT,
ASI1_WCLK, ASI3_WCLK
DAC_FS, ADC_FS, ASI1_WDIV_OUT, ASI2_WDIV_OUT, ASI3_WDIV_OUT,
ASI1_WCLK, ASI2_WCLK
Additionally a general purpose clock CLKOUT can be driven out on DOUT1, WCLK2, BCLK2, GPIO1, GPIO2, or
GPO1 according to the settings in Table 29.
Table 29. CLKOUT Selection
Clock Output
DOUT1
Bits
B0_P4_R67_D[4:1] = ’0011’
B0_P4_R69_D[5:2] = ’0100’
B0_P4_R70_D[5:2] = ’0100’
B0_P4_R86_D[6:2] = ’00100’
B0_P4_R87_D[6:2] = ’00100’
B0_P4_R96_D[4:1] = ”0011’
WCLK2
BCLK2
GPIO1
GPIO2
MISO_GPO1
70
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This clock can be a divided down version of CDIV_CLKIN. The value of this clock divider can be programmed
from 1 to 128 by writing to B0_P0_R22_D[6:0], and this CDIV clock divider can be powered on by setting
B0_P4_R22_D7. The CDIV_CLKIN can itself be programmed as one of the clocks among the list shown in
Figure 61. This can be controlled by programming the mux in B0_P0_R21_D[3:0].
MCLK
BCLK1
DIN1
BCLK2
GPIO3
CDIV_CLKIN
CLKOUT
¸ CDIV
PLL_CLK
DAC_CLK
DAC_MOD_CLK
ADC_CLK
N=1,2,…,128
ADC_MOD_CLK
HF_REF_CLK
HF_OSC_CLK
Figure 61. General Purpose Clock Output Options
Table 30. Maximum TLV320AIC3268 Clock Frequencies
DVDD_18 ≥ 1.26V
50MHz
DVDD_18 ≥ 1.65V
137MHz
DVDD_18 ≥ 1.71V
137MHz
ADC_CLKIN
DAC_CLKIN
50MHz
137MHz
137MHz
ADC_CLK
50MHz
70MHz
70MHz
ADC_miniDSP_CLK
ADC_MOD_CLK
ADC_FS
37.5MHz
6.758MHz
0.192MHz
50.0MHz
35.0MHz
6.758MHz
0.192MHz
50MHz
63.0MHz
6.758MHz
0.192MHz
70MHz
69.0MHz
6.758MHz
0.192MHz
70MHz
DAC_CLK
DAC_miniDSP_CLK
DAC_MOD_CLK
DAC_FS
59.0MHz
6.758MHz
0.192MHz
70MHz
62.5MHz
6.758MHz
0.192MHz
70MHz
ASI1_BDIV_CLKIN,
ASI2_BDIV_CLKIN,
ASI3_BDIV_CLKIN
CDIV_CLKIN
50MHz
137MHz
137MHz
8.3.4.1 PLL
The TLV320AIC3268 has an on-chip PLL to generate the clock frequency for the audio ADC, DAC, and Digital
Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that
may be available in the system. The PLL Clocking and muxing is shown in Figure 62.
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MCLK1
BCLK1
DIN1
GPIO2
BCLK2 HF_REF_CLK
GPI1
MCLK2
GPIO1
GPI2
PLL_CLKIN
%PLL
_CLKI
N_DIV
PLL_CLKIN_DIV=1,2,…,128
%P
P=1,2,…,8
PLL
R=1,2,…,16
J=1,2,..,63
D=0000,0001,…,9999
×(R×J·D)
PLL_CLK
MCLK
BCLK1
GPIO1
GPIO3
GPIO2 HF_REF_CLK
DIN1
BCLK2
PLL_CLKIN
%PLL_CL
KIN_DIV
PLL_CLKIN_DIV=1,2,…,128
%P
P=1,2,…,8
R=1,2,…,16
J=1,2,..,63
PLL
D=0000,0001,…,9999
×(R×J·D)
PLL_CLK
Figure 62. PLL Clocking and Mux
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The PLL input supports clocks varying from 512kHz to 20MHz and is register programmable to enable
generation of required sampling rates with fine resolution. The PLL can be turned on by writing to
B0_P0_R6_D7. When the PLL is enabled, the PLL output clock PLL_CLK is given by the following equation
PLL_CLK = (PLL_CLKIN x R x J.D)/(PxPLL_CLKIN_DIV)
PLL_CLKIN ´ R ´ J.D
PLL_CLK =
PxPLL_CLKIN_DIV
(15)
R = 1, 2, … 16.
J = 1, 2, 3, 4,… 63, and D = 0, 1, 2, 3, 4, … 9999
P = 1, 2, 3, 4, … 8
PLL_CLKIN_DIV = 1, 2, … 128.
R, J, D, P, and PLL_CLKIN_DIV are register programmable.
The PLL can be programmed via B0_P0_R6-R10. The PLL can be turned on via B0_P0_R6_D7. The variable P
can be programmed via B0_P0_R6_D[6:4]. The default register value for P is 1. The variable R can be
programmed via B0_P0_R6_D[3:0]. The default register value for R is 1. The variable J can be programmed via
B0_P0_R7_D[5:0]. The default register value for J is 4. The variable D is 12-bits, programmed into two registers.
The MSB portion can be programmed via B0_P0_R8_D[5:0], and the LSB portion is programmed via
B0_P0_R9_D[7:0]. The default register value for D is 0. The PLL_CLKIN_DIV value can be programmed via
B0_P0_R10_D[6:0]. The default register value for PLL_CLKIN_DIV is 1.
When the PLL is enabled the following conditions must be satisfied
•
When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
PLL_CLKIN
512 kHz £
£ 20 MHz
P ´ PLL_CLKIN_DIV
(16)
(17)
•
When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:
PLL_CLKIN
10 MHz £
£ 20 MHz
P ´ PLL_CLKIN_DIV
In the TLV320AIC3268 the PLL_CLK supports a wide range of output clock values, based on register settings
and power-supply conditions.
Table 31. PLL_CLK Frequency Range
AVdd
PLL Mode
Min PLL_CLK
Max PLL_CLK
B0_P0_R5_D6
frequency (MHz)
frequency (MHz)
≥1.5V
0
1
0
1
0
1
80
95
80
92
80
92
103
110
118
123
132
137
≥1.65V
≥1.80V
The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a general
purpose PLL by selecting its output as an input to the General Purpose Output Clock mux (enabling routing to a
variety of digital output terminals). After powering up the PLL, PLL_CLK is available typically after 10ms. The PLL
output frequency is controlled by J.D and R dividers
PLL Divider
Bits
J
B0_P0_R7_D[5:0]
D
R
B0_P0_R8_D[5:0] and B0_P0_R9_D[7:0]
B0_P0_R6_D[3:0]
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The D-divider value is 14-bits wide and is controlled by 2 registers. For proper update of the D-divider value,
B0_P0_R8 must be programmed first followed immediately by B0_P0_R9. Unless the write to B0_P0_R9 is
completed, the new value of D will not take effect.
The clocks for codec and various signal processing blocks, ADC_CLKIN and DAC_CLKIN can be generated
from MCLK, BCLK1, GPIO1, BCLK2, GPIO3, HF_REF_CLK, HF_OSC_CLK, GPIO2, GPIO6, BCLK3 or
PLL_CLK (B0_P0_R4_D[7:0]).
If the ADC_CLKIN and/or the DAC_CLKIN are derived from the PLL, then the PLL must be powered up first and
powered down last.
Table 32 lists several example cases of typical MCLK rates and how to program the PLL to achieve a sample
rate Fs of either 44.1kHz or 48kHz.
Table 32. PLL Example Configurations
Fs = 44.1kHz
MCLK (MHz)
2.8224
5.6448
12
PLL_CLKIN_DIV
PLLP
PLLR
PLLJ
PLLD
0
MADC
NADC
AOSR
128
128
128
64
MDAC
NDAC
DOSR
128
128
128
104
128
128
128
1
1
1
1
1
1
1
1
1
1
1
1
1
4
3
3
1
2
1
1
1
10
5
3
3
5
5
5
3
5
5
5
3
3
3
4
3
3
3
5
5
5
6
5
5
5
0
7
560
2336
2920
4100
560
3
13
4
13
3
16
5
128
128
128
19.2
4
3
48
7
3
Fs = 48kHz
2.048
3.072
4.096
6.144
8.192
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
3
4
3
2
4
1
1
1
1
14
7
0
0
2
2
2
2
2
2
2
2
2
7
7
7
7
8
7
7
7
7
128
128
128
128
128
128
128
128
128
7
7
7
7
4
7
7
7
7
2
2
2
2
4
2
2
2
2
128
128
128
128
128
128
128
128
128
7
0
7
0
3
0
7
1680
3760
4800
1680
16
5
19.2
4
48
7
8.3.4.2 Low Frequency Reference Clock
To extend the frequency locking range of the on-chip PLL to an external clock at low frequencies, a clock
frequency multiplier is used to generate its output clock with the frequency K times of its input reference clock
frequency for the PLL to lock, where K is a 28-bit value of the control register bits {B0_P0_R25_D[3:0],
B0_P1_R26, B0_P0R27, B0_P0_R28}. The reference clock source can be selected with the control register bits,
B0_P0_R24_D[7:4]. The clock routing for the low frequency clock is shown in Figure 63.
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WCLK1
MCLK
BCLK2
GPIO1
GPIO3
WCLK2
DIN2
GPIO2
ONE TIME
CALLIBRATION
MCLK
HIGH FREQ
LFR_CLKIN
OSCILLATOR
HF_OSC_CLK
HF_CLK
Clock Frequency
Multiplier
HF_REF_CLK
Figure 63. Low-Frequency Clocking
The output clock, HF_REF_CLOCK, is generated by delta-sigma modulation with a high frequency clock,
HF_CLK. The source of HF_CLK can be setup by programming the control bits, B0_P0_R24_R[3:0]. If the on-
chip high frequency oscillator clock, HF_OSC_CLK, is selected as the source, it is recommended to calibrate the
oscillator clock by following the proper calibration procedure before turning on the clock multiplier.
The HF_OSC_CLK can have large device-to-device variation of its default frequency. For proper functioning, the
HF_OSC_CLK can be calibrated with respect to the LFR_CLKIN. This calibration happens at power-up of the
block when this feature is enabled (HF_OSC_CLK is used by any other function). By default this calibration is
enabled and if so desired can be disabled by writing B0_P0_R29_D5 = ‘0’. For calibrating the HF_OSC_CLK the
26-bit ratio of frequencies (Desired HF_OSC_CLK freq / Frequency of LFR_CLKIN) can be programmed in
B0_P0_R29_D[1:0], B0_P0_R30_D[7:0], B0_P0_R31_D[7:0], and B0_P0_R32_D[7:0]. This ratio must be
programmed before enabling this block. Also, the LFR_CLKIN must be present when the HF_OSC_CLK is
enabled, and the LFR_CLKIN frequency should be less than 50 kHz. This calibration is an approximate
calibration, and the frequency of HF_OSC_CLK will approximately equal Programmed Ratio * LFR_CLKIN
frequency. The error can be approx ±7MHz. The desired frequency should ideally be kept between 50MHz and
57.5MHz for good audio performance. Once the calibration is over, the calibrated clock will be available for use
by other blocks. The HF_OSC_CLK has an additional programmability by which this block can be used even
when AVDD1_18 supply is not powered up. This can be useful when a free running clock is required when
AVDD1_18 is not powered as no other analog blocks may be powered up. This feature can be controlled by
B0_P0_R29_D6.
For a better quality of the PLL clock, the clock multiplier output should be set at higher frequency by choosing a
higher multiplication value of K, if there are multiple options. But the multiplied frequency should not be higher
than ¼ times of HF_REF_CLK frequency and the frequency has to be within the PLL locking range, 10-20MHz
for D≠0 and 512kHz – 20MHz for D=0. To select HF_REF_CLK as the PLL reference, B0_P0_R5_D[5:2] should
be set as '0110'.
8.3.5 Reference Voltage
All audio data converters require a DC reference voltage. The TLV320AIC3268 achieves its low-noise
performance by internally generating a low-noise reference voltage. This reference voltage is generated using a
band-gap circuit with a good PSRR performance. This audio converter reference voltage must be filtered
externally using a minimum 1μF capacitor connected from the VREF_AUDIO terminal to analog ground (VSS).
To achieve low power consumption, this audio reference block is powered down when all analog blocks inside
the device are powered down. In this condition, the VREF_AUDIO terminal is 3-stated. On powerup of any
analog block, the audio reference block is also powered up and the VREF_AUDIO terminal settles to its steady-
state voltage after the settling time (a function of the decoupling capacitor on the VREF_AUDIO terminal). This
time is approximately equal to 1 second when using a 1μF decoupling capacitor. In the event that a faster power-
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up is required, either the audio reference block can be kept powered up (even when no other analog block is
powered up) by programming B0_P1_R122_D2 = 1. However, in this case, an additional 100μA of current from
AVDDx_18 is consumed. Additionally, to achieve a faster powerup, a fast-charge option is also provided where
the charging time can be controlled between 40ms and 120ms by programming B0_P1_R122_D[1:0]. By default,
the fast charge option is enabled.
In addition, the TLV320AIC3268 can also generate a separate 1.25V DC reference which is utilized by the SAR
ADC for measurement. This SAR reference voltage must also be filtered externally using a minimum 1μF
capacitor connected from the VREF_SAR terminal to analog ground (AVSS).
To achieve low power consumption, this SAR reference block is powered down by default when SAR
conversations are not occurring. The system could utilize this reference voltage outside of SAR ADC conversions
by powering it continuously by programming B0_P3_R6_D5 =0.
8.3.6 SAR ADC
This section describes how to use the SAR ADC for the functions:
•
•
•
Temperature measurement
Battery measurement
Auxiliary voltage measurement
The analog inputs of the TLV320AIC3268 are shown in Figure 64.
AVDD
VREF_SAR
GPIO1/GPIO2/
GPO1/DOUT1/
WCLK2/BCLK2/
DOUT2
VREF
DATA_AVA
REFP
IN+
IN-
CONVERTER
REFM
VBAT
IN1L/AUX1
IN1R/AUX2
AVSS
Figure 64. Simplified Diagram of the SAR ADC Analog Input Section
The ADC is controlled by an ADC control register (B0_P3_R3_D[7:0]). Several modes of operation are possible,
depending on the bits set in the control register. Channel selection, scan operation, resolution, and conversion
rate may all be programmed through this register. These modes are outlined in the following sections for each
type of analog input. The results of conversions made are stored in the appropriate result register.
The SAR ADC can be powered down forcefully by writing to B0_P3_R2_D7. Overall SAR configuration and
mode is controlled by writing to B0_P3_R3_D[7:0].
Voltage Reference
The TLV320AIC3268 can use an internal voltage reference of 1.25V or an external reference through the
reference control register (B0_P3_R6). The internal reference voltage should only be used in the single-ended
mode for battery monitoring, for temperature measurement, and for using the auxiliary inputs.
The TLV320AIC3268 may use an external voltage reference (B0_P3_R6). In many systems, a 2.5V reference is
supplied; however, this device supports a reference voltage up to the AVDDx_18 level. The external reference
should be a low-noise signal and accordingly, depending on the application, it might need some R-C filtering at
the VREF_SAR terminal.
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This voltage reference should only be used in the single-ended mode for measuring the auxiliary inputs
(IN1L/AUX1, IN1R/AUX2, and VBAT).
Variable Resolution
The TLV320AIC3268 provides three different resolutions for the ADC: 8, 10, or 12 bits. Lower resolutions are
often practical for measurements such as system voltages. Performing the conversions at lower resolution
reduces the amount of time it takes for the ADC to complete its conversion process, which lowers power
consumption. The ADC resolution can be programmed by writing to B0_P3_R2_D[6:5].
Data Format
The TLV320AIC3268 output data is unsigned binary format and can be read from two 8-bit registers over the
Control interface (SPI or I2C). The SAR ADC's output data is MSB zero appended to make a 16-bit word.
8.3.6.1 Conversion Clock and Conversion Time
The TLV320AIC3268 contains an internal oscillator (LF_OSC_CLK), which is used to drive the state machines
inside the device that perform the many functions of the part. MCLK is also available as a high frequency clock
source. The clock source (LF_OSC_CLK or divided down MCLK) is selected by writing to B0_P3_R17_D7.
When using the high frequency clock source MCLK , the clock divider B0_P3_R17_D[6:0] should be
programmed to result in output clock pulses to be larger than 40ns. This clock (ADC_SAR_Clock) is further
divided down to provide a clock to run the SAR ADC. The division ratio for this clock is set by writing to
B0_P3_R2_D[4:3]. The ability to change the conversion clock rate allows the user to choose the optimal value for
the resolution, speed, and power. If the division value is used as 1 , the ADC is limited to 8-bit resolution, division
value of 2 is suitable for 10-bit resolution; 12-bit resolution requires the division value to be set as 4 or
8(recommended).
Similarly, the internal delay timers operate on clocks derived from either the LF_OSC_CLK or MCLK. The clock
selection is controlled by writing to B0_P0_R23_D7. When using MCLK as the clock source the clock divider
B0_P0_R23_D[6:0] should be programmed to have the resultant output clock to be approximately 1MHz in
frequency. To avoid asynchronous issues, the system should use the same value for both B0_P0_R23_D7 and
B0_P3_R17_D7.
Details for clock selection can be seen in Figure 65.
LF_OSC_CLK/8
%8
Internal 8MHz
Oscillator
LF_OSC_CLK
0
ADC_SAR_Conversion_Clock
SAR ADC Clock Divider
B0_P3_R2_D[4:3]
1
To SAR ADC FSMs
MCLK
Clock Divider
B0_P3_R17_D[6:0]
ADC_SAR_Clock
SAR_ADC_Clock Select
B0_P3_R17_D[7]
Clock Divider
1
B0_P0_R23_D[6:0]
REF_1MHz_CLK
To Interval Timers
LF_OSC_CLK/8
0
Timer_Clock Select
B0_P0_R23_D[7]
Figure 65. SAR ADC and Interval Timer Clock Select
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Regardless of the conversion clock speed, the internal clock runs nominally at 8.2 MHz. The conversion time of
the TLV320AIC3268 depends on several functions. While the conversion clock speed plays an important role in
the time it takes for a conversion to complete, a certain number of internal clock cycles are needed for proper
sampling of the signal. Conversion time can vary, depending on the mode in which the TLV320AIC3268 is used.
Throughout this document, internal and conversion clock cycles are used to describe the times that many
functions take to execute. Considering the total system design, these times must be taken into account by the
user.
The ADC uses either the internal MCLK signal or the internal oscillator for the SAR conversions.
8.3.6.2 Data Available - INT1 or INT2 Programmed as DATA_AVA
The interrupt signals INT1 and INT2 can be programmed by writing to B0_P0_R50_D[7:6] (INT1) or
B0_P0_R50_D[5:4] (INT2). These terminals function as the DATA_AVA signal. To enable the SAR data available
interrupt, B0_P3_R3_D[1:0] must be programmed to '01'. The DATA_AVA signal and interrupts INT1 and INT2
can be mapped to GPIO1, GPIO2, GPO1, DOUT1, WCLK2, BCLK2, or DOUT2.
8.3.6.3 Temperature Measurement
In some applications, such as battery charging, a measurement of ambient temperature is required. The
temperature measurement technique used in the TLV320AIC3268 relies on the characteristics of a
semiconductor junction operating at a fixed current level. The forward diode voltage (Vj) has a well-defined
characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the
25°C value of the Vj voltage and then monitoring the variation of that voltage as the temperature changes.
The TLV320AIC3268 offers two modes of temperature measurement. The first mode requires a single reading to
predict the ambient temperature. A diode, as shown in Figure 66, is used during this measurement cycle. This
voltage is typically 600 mV at 25°C with a 20μA current through it. The absolute value of this diode voltage can
vary a few millivolts. The temperature coefficient of this voltage is typically 2 mV/°C. During the final test of the
end product, the diode voltage at a known room temperature is stored in nonvolatile memory. Further calibration
can be done to calculate the precise temperature coefficient of the particular device. This method has a
temperature resolution of approximately 0.4°C/LSB and accuracy of approximately ±3°C with two-temperature
calibration. Figure 67 and Figure 68 show typical plots with single and two-temperature calibration, respectively.
A/D
MUX
Converter
TEMP0
TEMP1
Figure 66. Functional Block Diagram of Temperature-Measurement Mode
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20
15
10
5
0
−5
−10
−15
−20
−25
−40
−20
0
20
40
60
80
100
TA − Free−Air Temperature (°C)
G000
Figure 67. Typical Plot of Single-Measurement Method After Calibrating
for Offset at Room Temperature
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−40
−20
0
20
40
60
80
100
TA − Free−Air Temperature (°C)
G001
Figure 68. Typical Plot of Single-Measurement Method After Calibrating
for Offset and Gain at Two Temperatures
The second mode uses a two-measurement (differential) method. This mode requires a second conversion with
a current 82 times larger. The voltage difference between the first (TEMP1) and second (TEMP2) conversion,
using 82 times the bias current, is represented by:
kT
V
=
´ln(N)
(Temp1 - Temp2)
q
(18)
where
N is the current ratio = 82
k = Boltzmann’s constant (1.38054 × 10−23 electron volts/Kelvin)
q = the electron charge (1.602189 × 10−19 C)
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T = the temperature in degrees Kelvin
The equation for the relation between differential code and temperature may vary slightly from device to device
and can be calibrated at final system test by the user. This method provides resolution of approximately 2°C/LSB
and accuracy of approximately ±6°C after calibrating at room temperature. A plot of typical calibration error for
this method is shown in Figure 69.
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−40
−20
0
20
40
60
80
100
TA − Free−Air Temperature (°C)
G002
Figure 69. Typical Plot of Differential Measurement Method After Calibrating
for Offset and Gain at Two Temperatures
The TLV320AIC3268 supports programmable auto-temperature measurement mode, which can be enabled by
setting B0_P3_R19_D4. In this mode, the TLV320AIC3268 can auto-start the temperature measurement after a
programmable interval. The user can program minimum and maximum threshold values through a register. In the
case of temperature measurements, these thresholds are controlled in B0_P3_R30-R33. If the measurement
goes outside the threshold range, the TLV320AIC3268 sets a flag in read-only B0_P3_R21, which is cleared
after the flag is read. The TLV320AIC3268 can also be configured to send an active-high interrupt over INT1 or
INT2 by setting bits in B0_P0_R50. The duration of the interrupt is approximately 2 ms, if B0_P0_R51_D[7:6] =
'00' or B0_P0_R51_D[5:4] = '00', or these interrupt signals can be configured for alternate output signals. See
Interrupt Generation and Diagnostic Flags for more details on interrupt generation.
Temperature measurement can only be done in host-controlled mode.
8.3.6.4 Auxiliary Battery-Voltage Measurement for VBAT
The TLV320AIC3268 can be used to measure battery voltage up to 6V. This measurement can made using the
VBAT terminal, which has a voltage divider (divide by 5), as seen in Figure 64. This analog prescaler is available
on the terminal to allow higher voltages to be measured by the SAR ADC. This battery measurement function is
supported in 8-bit, 10-bit, and 12-bit modes.
To enable the battery-voltage measurement mode, write a '0110' to B0_P3_R3_D[5:2].
Because the ADC code is 1/5 of the actual voltage value applied at VBAT, the correct value can be found by
multiplying the ADC code by 5. For low voltages of VREF_SAR, this function can support voltages from 0 to (5 ×
VREF_SAR), where the upper voltage limit for VBAT is 6V, and is also limited by the value listed in the Absolute
Maximum Ratings table in the TLV320AIC3268 data sheet.
In the battery-voltage measurement mode, the conversion results in an ADC output code of B, where the voltage
at the input terminal (VBAT) can be calculated as:
B
2N
VBAT
=
´ (5´ VREF _SAR)
(19)
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where:
N is the programmed resolution of the SAR ADC.
VREF_SAR is the applied external reference voltage.
For an example of a script for battery voltages on VBAT, download the Example Scripts zip file from the
TLV320AIC3268 product page.
8.3.6.5 Auxiliary Voltage Measurements
The TLV320AIC3268 can be used to measure voltage on IN1L/AUX1 and IN1R/AUX2 terminals. This voltage
measurement function is supported in 8-bit, 10-bit, and 12-bit modes.
For IN1L/AUX1 and IN1R/AUX2:
If the conversion results in an ADC output code of B, then the voltage at the input terminals (IN1L/AUX1 and
IN1R/AUX2) can be calculated as:
B
2N
VPIN
=
´ VREF _SAR
(20)
where:
N is the programmed resolution of the SAR ADC.
VREF_SAR is the applied external reference voltage.
For an example of a script for reading voltages on IN1L, download the Example Scripts zip file from the
TLV320AIC3268 product page.
The TLV320AIC3268 supports a special mode of conversion on IN1L/AUX1 and IN1R/AUX2 terminals called the
resistance measurement mode. This mode is useful for measuring the value of an external resistance connected
to this terminal. Conversion for IN1L/AUX1 input works in resistance measurement mode by writing '1' to
B0_P3_R19_D2 and conversion for IN1R/AUX2 works in resistance measurement mode by writing '1' to
B0_P3_R19_D1.
VREF_SAR
VREF_SAR
50kΩ
50kΩ
50kΩ
50kΩ
IN1L/AUX1
IN1L/AUX1
IN1R/AUX2
SAR ADC
SAR ADC
Rext
Rext
IN1R/AUX2
External Bias Resistance Measurement Mode
Internal Bias Resistance Measurement Mode
Figure 70. Resistance measurement mode for IN1L/AUX1 and IN1R/AUX2
The resistance measurement mode works in two ways. In Internal Bias Resistance measurement mode the value
of external resistance Rext is measured as a ratio with internal bias resistance which is nominally of 50kΩ value.
The value of Rext is calculated by Equation 21. This value is useful to measure external resistance without any
external components. The internal bias resistance will however exhibit device to device variation and should thus
be used where a very high accuracy measurement is not required.
Rext=ADCOUT.50000/(2N-ADCOUT)
(1) Where N is the resolution of the SAR ADC
(2) Where bias resistor is 50kΩ. The equation will scale for a different value of bias resistor.
(21)
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The resistance measurement mode can be also enabled to work with external bias resistor by writing '1' to
B0_P3_R19_D0. When using this mode, an external bias resistor of 50kΩ should be connected between
VREF_SAR and IN1L/AUX1 or IN1R/AUX2 terminals. This mode enables a higher accuracy conversion by using
a higher accuracy bias resistance. The value of Rext is determined by Equation 21.
8.3.6.6 Auto Scan
If making voltage measurements on one or many of the inputs from IN1L/AUX1, IN1R/AUX2, VBAT and TEMP1
(or TEMP2) is desired on a continuous basis, then the auto-scan mode can be used. This mode causes the
TLV320AIC3268 to sample and convert each of selected inputs in a repetetive manner with programmed
intervals. The set of inputs that can be selected are programmed by configuring B0_P3_R19_D[7:4]. Auto scan
can be set up by writing "1001" to B0_P3_R3_D[5:2]. Programming B0_P3_R15_D[3:0], allows a programmable
interval delay to be introduced between successive conversions of the set of inputs selected for covnersion.
See Conversion Time Calculations for the TLV320AIC3268, Host-Controlled Auto Scan Mode for conversion-time
calculations and timing diagrams.
8.3.6.7 Port Scan
If making voltage measurements on the inputs IN1L/AUX1, IN1R/AUX2, and VBAT is desired on a periodic basis,
then the port-scan mode can be used. This mode causes the TLV320AIC3268 to sample and convert each of the
auxiliary inputs once. At the end of this cycle, all of the auxiliary result registers contain the updated values.
Thus, with one write to the TLV320AIC3268, the host can cause three different measurements to be made. Port
scan can be set up by writing "1011" to B0_P3_R3_D[5:2].
See Conversion Time Calculations for the TLV320AIC3268, Port-Scan Operation, Port-Scan Operation, for
conversion-time calculations and timing diagrams.
8.3.6.8 Buffer Mode
The TLV320AIC3268 supports a programmable buffer mode for all conversions (VBAT, IN1L/AUX1, IN1R/AUX2,
TEMP1, TEMP2). Buffer mode is implemented using a circular FIFO with a depth of 64. The number of interrupts
required to be serviced by a host processor can be reduced significantly in buffer mode. Buffer mode can be
enabled using B0_P3_R13_D7.
l
Figure 71. Circular Buffer
82
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Converted data is automatically written into the FIFO. To control the writing, reading and interrupt process, a
write pointer (WRPTR), a read pointer (RDPTR), and a trigger pointer (TGPTR) are used. The read pointer
always shows the location that is read next. The write pointer indicates the location in which the next converted
data is to be written. The trigger pointer indicates the location at which an interrupt is generated if the write
pointer reaches that location. Trigger level is the number of the data values needed to be present in the FIFO
before generating an interrupt. Figure 71 shows the case when the trigger level is programmed as 32. On
resetting the buffer mode, RDPTR moves to location 1, WRPTR moves to location 1, and TGPTR moves to a
location equal to the programmed trigger level.
The user can select the input or input sequence to be converted by writing to B0_P3_R3_D[5:2]. The converted
values are written in a predefined sequence to the circular buffer. The user has flexibility to program a specific
trigger level in order to choose the configuration which best fits the application. When the number of converted
data values written in FIFO becomes equal to the programmed trigger level, then the device generates an
interrupt signal on INT1 or INT2. In buffer mode, the user should program this terminal as Data Available. In
buffer mode, conversions (VBAT, IN1L/AUX1, IN1R/AUX2, TEMP1, TEMP2) are allowed only in host-controlled
mode.
Buffer mode can be used in single-shot conversion or continuous-conversion mode.
In single-shot conversion mode, once the number of data values written reaches the programmed trigger level,
the TLV320AIC3268 generates an interrupt and waits for the user to start reading. As soon as the user starts
reading the first data value from the last converted set, the TLV320AIC3268 clears the interrupt and starts a new
set of conversions, and the trigger pointer is incremented by the programmed trigger level. An interrupt is
generated again when the trigger condition is satisfied.
In continuous-conversion mode, once the number of data values written reaches the programmed trigger level,
the TLV320AIC3268 generates an interrupt. It immediately starts a new set of conversions, and the trigger
pointer is incremented by the programmed trigger level. An interrupt is cleared either by writing the next
converted data value into the FIFO or by starting to read from the FIFO.
Depending on how the user is reading data, the FIFO can become empty or full. If the user is trying to read data
even if the FIFO is empty, then RDPTR keeps pointing to same location. If the FIFO becomes full, then the next
location is overwritten with newly converted data values, and the read pointer is incremented by one.
While reading the FIFO, the TLV320AIC3268 provides FIFO-empty and -full status flags along with the data. The
user can also read a status flag from B0_P3_R13_D[1:0]. See Table 33 for buffer-mode control and Table 34 for
buffer-mode 16-bit read-data format.
Table 33. SAR/Buffer Mode Data Read Control (B0_P3_R18_D[7:5])(1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
0: SPI interface is used for SAR/buffer data reading.
1: I2C interface is used for SAR/buffer data reading.
D7
R/W
0
0: SAR/buffer data update is automatically halted (to avoid simultaneous buffer read and
write operations) based on internal detection logic. Valid only for SPI interface.
1: SAR/buffer data update is held using software control (B0_P3_R18_D5).
D6
D5
R/W
0
0: SAR/buffer data update is enabled all the time (valid only if B0_P3_R18_D6 = 1).
1: SAR/buffer data update is stopped so that user can read the last updated data without
any data corruption (valid only if B0_P3_R18_D6 = 1).
R/W
0
(1) To enable buffer mode, write a 1 to B0_P3_R13_D7.
Table 34. Buffer Mode 16-Bit Read Data Format (B0_P252_R1 and B0_P252_R2)
BUFFER
READ DATA
BIT
RESET
VALUE
NAME
FUF
DESCRIPTION
COMMENT
Buffer-Full flag - This flag indicates that all the 64 locations of
the buffer contain unread data.
D15
0
B0_P252_R1_D7
Buffer-Empty flag - This flag indicates that there is no un-read
data available in FIFO. This is generated while reading the
last converted data.
D14
D13
EMF
1
B0_P252_R1_D6
B0_P252_R1_D5
X
Reserved
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Table 34. Buffer Mode 16-Bit Read Data Format (B0_P252_R1 and B0_P252_R2) (continued)
BUFFER
READ DATA
BIT
RESET
VALUE
NAME
DESCRIPTION
COMMENT
Data identification:
0 = VBAT or IN1R/AUX2 data in R11-R0
1= IN1L/AUX1 or TEMP data in R11-R0
Order for writing data in buffer when multiple inputs are
selected:
D12
ID
X
B0_P252_R1_D4
For autoscan conversion: IN1L/AUX1 (if selected),
IN1R/AUX2 (if selected), VBAT, TEMP1 or TEMP2 (if
selected)
For port-scan conversion: IN1L/AUX1, IN1R/AUX2, VBAT
D11-D8
D7-D0
R11-R8
R7-R0
X
X
Converted data (MSB, 4 bits)
Converted data (LSB, 8 bits)
B0_P252_R1_D[3:0]
B0_P252_R2_D[7:0]
8.3.6.8.1 Buffer Mode Access through I2C for TLV320AIC3268
To enable faster data access, SPI protocol is preferred, but if I2C is required, note the following.
•
In continuous buffer mode:
Only one measurement type, that is choice of IN1L, IN1R, VBAT, TEMP1 or TEMP2, can be used.
In single-shot mode:
–
•
–
–
Multiple measurement types can be stored in the buffer consecutively.
The I2C read must completely empty the buffer. In other words, the number of bytes read must be equal to
the trigger-level multiplied by 2 (for 2 bytes per converted data). If the buffer is empty, this will be reflected
by bit B0_P252_R1_D6=1 in the last measurement read.
–
The I2C read must empty the buffer in a single call. Note that some I2C drivers may break auto-increment
instructions into multiple, smaller calls. This can cause the SAR buffer to return invalid data, so the SAR
trigger level must be less than or equal to the max I2C auto-increment size divided by 2.
•
If 64 elements (128 bytes) are read, the last byte will be invalid data since I2C allows a maximum of 127
bytes.
8.3.6.9 Reading AUX Data in Non-Buffer Mode From SPI
Reading from the TLV320AIC3268 is done by using the protocol called out in Figure 72.
SS
SCLK
Hi-Z
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
Don’t Care
MOSI
MISO
7-Bit Register Address
Read
16-Bit Register Data
D(14)
Hi-Z
D(15)
D(0)
Figure 72. 16-Bit Data-Read Timing, 24 Clocks per 16-Bit Data Read, 8-Bit Bus Interface
This protocol uses a 24-clock sequence to get a 16-bit data read. Set the INT1 or INT2 interrupt for monitoring
the data-available status by writing '01' to B0_P3_R3_D[1:0]. Reading is normally done when the interrupt is low
(data is available for reading). Status from the ADC conversion can be read from B0_P3_R9. If bit D6 is 0, then
the ADC is actively converting, so a BUSY status is read. If bit D5 is set, then some data is now available for
reading. Next, reading from a status register on B0_P3_R10 lets us know if data is available for IN1L/AUX1,
IN1R/AUX2, or VBAT. If bit D7 is set, then IN1L/AUX1 data can be read. If bit D6 is set, then IN1R/AUX2 data
can be read. If bit D5 is set, then VBAT data can be read.
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The first 7 bits in the read sequence are for the first register address of the two sequential 8-bit registers. The
next bit is high, which specifies that a read operation follows; then the 16 remaining clocks are used to get the
16-bit data that is read out in the order of D15–D0. The register address specified in the first seven clocks of the
24-clock sequence reads out as bits D15–D8, where D15 is the MSB of the byte, then the register number is
incremented by 1 and the data is read from D7–D0, where D7 is the MSB of that byte. (For reading data for
IN1L/AUX1, use B0_P3_R54 and B0_P3_R55; for reading data for IN1R/AUX2, use B0_P3_R56 and
B0_P3_R57; and for reading data for VBAT, use B0_P3_R58 and B0_P3_R59.) From this cycle, the first 16-bit
data word has been read. This sequence can be repeated to read further values of IN1L/AUX1, IN1R/AUX2, and
VBAT data.
8.3.6.10 Auto Threshold Detect
The SAR ADC in TLV320AIC3268 has a special auto threshold detect feature where the device can detect a
conversion exceeding the pre-programmed minimum and maximum thresholds for the input. Upon such a
detection the TLV320AIC3268 can interrupt the host processor. This feature is useful as it allows the host to be
immediately informed about out of range conditions, without the host having to poll for converted values. Upon
receiving an interrupt, the host can read the flag register to find the input which exceeded the maximum or
minimum threshold. The register settings for Auto Threshold Detect feature are described in Table 35.
Table 35. Threshold Detect Settings
Parameter
IN1L/AUX1
IN1R/AUX2
TEMP
Maximum Threshold
check enable
B0_P3_R22_D[4]='1'
B0_P3_R26_D[4]='1'
B0_P3_R30_D[4]='1'
Maximum Threshold
Code
B0_P3_R22_D[3:0],
B0_P3_R23_D[7:0]
B0_P3_R26_D[3:0],
B0_P3_R27_D[7:0]
B0_P3_R30_D[3:0],
B0_P3_R31_D[7:0]
Minimum Threshold
check enable
B0_P3_R24_D[4]='1'
B0_P3_R28_D[4]='1'
B0_P3_R32_D[4]='1'
Minimum Threshold
Code
B0_P3_R24_D[3:0],
B0_P3_R25_D[7:0]
B0_P3_R28_D[3:0],
B0_P3_R29_D[7:0]
B0_P3_R32_D[3:0],
B0_P3_R33_D[7:0]
Maximum Threshold
Flag
B0_P3_R21_D5
B0_P3_R21_D4
B0_P3_R21_D3
B0_P3_R21_D2
B0_P0_R50_D7
B0_P0_R50_D5
B0_P3_R21_D1
B0_P3_R21_D0
Minimum Threshold
Flag
INT1 interrupt on
Threshold exceed
INT2 interrupt on
Threshold exceed
8.3.6.11 Conversion Time Calculations for the TLV320AIC3268
This section discusses conversion time calculations for temperature, auxiliary, and battery measurements for
TLV320AIC3268.
The timing signals can be programmed by B0_P3_R3. INT1 or INT2 can be programmed as DATA_AVA by
programming B0_P0_R50_D[7:4]. DATA_AVA can also be sent to GPIO1, GPIO2, GPO1, DOUT1, WCLK2,
BCLK2, or DOUT2.
Table 36. Parameters for calculating Conversion Times
Parameter
Definition
SAR ADC output is provided after averaging over Navgsamples. Averaging is controlled by
B0_P3_R2_D[2:0] where
000 => Mean Filter, Navg=1
001 => Mean Filter, Navg=4
010 => Mean Filter, Navg=8
011 => Mean Filter, Navg=16
Navg
100 => Median Filter, Navg=1
101 => Median Filter, Navg=5
110 => Median Filter, Navg=9
111 => Median Filter, Navg=15
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Table 36. Parameters for calculating Conversion Times (continued)
Parameter
Definition
Number of inputs to be converted for scan conversion, for example, for Scan mode Ninp=1
and Port-Scan mode Ninp=3
Ninp
Nbits
tclk
Resolution of SAR ADC. Can be set to 8, 10 or 12bits by programming B0_P3_R2_D[6:5]
Clock period of ADC_SAR_CLK. See Figure 65
tconv
Clock period of ADC_SAR_Conversion_Clock. See Figure 65
Power up stabilization time for internal reference. This is configured by programming
B0_P3_R6_D[3:2] where
00 => tref = 0
01 => tref = 8000*tclk
10 => tref = 32000*tclk
11 => tref = 64000*tclk
tref
Programmable interval delay timer used for Auto-Scan Mode. Configured by programming
B0_P3_R15_D[3:0]. This is the programmable interval delay between two consecutive
conversions sets. A conversion set it the set of inputs that have been enabled in Auto-Scan
mode.
tdel
n1 = 6 for SAR_ADC_CLK_DIV=2 for 8-bit conversion mode. SAR_ADC_CLK_DIV is
programmed in B0_P3_R2_D[4:3]=00.
n1 = 7 for all other values of SAR_ADC_CLK_DIV
n1
n2
n2 = 11 for TEMP1 conversion mode
n2 = 387 for IN1L/AUX1 , IN1R/AUX2 conversions in resistance mode.
n2 = 0 for all other conversions
n3 = 0 if external reference is used for SAR_ADC. B0_P3_R6_D[7] = '0'
n3 = 3 if internal reference is used and always powered up. B0_P3_R6_D[7]='1' and
B0_P3_R6_D[5]='0'
n3
n3 = 1 + tref/tclk for all other conversions
n4=0, if programmable interval delay timer is diabled or B0_P3_R15_D[3] = '0'
n4=7, if programmable interval delay timer is enabled or B0_P3_R15_D[3] = '1'
n4
8.3.6.11.1 Host-Controlled Scan Mode
The time needed to make one single conversion for VBAT, IN1L/AUX1, IN1R/AUX2, TEMP1 (or TEMP2) is given
by
Tcycle=Navg.{(Nbits+ 1).tconv + (n1+ 13).tclk} + Navg.n2.tclk + (n3 + 17).tclk
(1) This equation is valid if B0_P3_R18_D[6:5] = 00, which means SAR data update is not kept on hold for reading
converted data.
(2) The programmable delay tREF scales accordingly based on the actual divider setting and time period of the
clock used to generate this. See the respective control register settings to understand the scale factors.
Programmed for
Host-Controlled
Mode With Invalid
A/D Function
P3/R3
Is Updated
for
VBAT Scan
Mode
Reading
VBAT Data
Register
CONTROL INTERFACE DEACTIVATED
Selected
Sample, Conversion
and Averaging for
VBAT input
Wait for Reference Power-Up Delay in Case
of Internal Reference Mode if Applicable
Waiting for Host to
Write Into P3/R3
Waiting for Host to
Write Into P3/R3
PINTDAV (As DATA_AVA
[P3/R3, D1–D0 = 01])
Figure 73. Host-Controlled VBAT Scan Mode
8.3.6.11.2 Host-Controlled Auto Scan Mode
The time needed for one cycle of Auto Scan Mode is given by:
Tcycle=Ninp.Navg.{(Nbits+ 1).tconv + (n1+ 13).tclk} + Navg.n2.tclk + Ninp.9.tclk + (n3 + n4).tclk + tdel
(1) This equation is valid if B0_P3_R18_D[6:5] = 00, which means SAR data update is not kept on hold for reading
converted data.
(2) This equation is valid only from the second conversion onward.
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(3) All the programmable delays, tDEL and tREF, scale accordingly based on the actual divider setting and time
period of the clock used to generate this. See the respective control register settings to understand the scale
factors.
B0_P3_R3_D[5:2]
programmed to
“1001”
Control Interface
Read
Data
Read
Data
Sample, Convert Sample, Convert Sample, Convert
and Average
Input
FSM State
Waiting for Host to
program B0_P3_R3
Waiting for tref if applicable
and Average
Input
and Average
Input
/Data_Available
B0_P3_R3_D[1:0]=”01'
Figure 74. Host-Controlled Auto Scan Mode
8.3.6.11.3 Port-Scan Operation
The time needed to complete one set of Port-Scan conversions is given by:
Tcycle=3.Navg.{(Nbits+ 1).tconv + (n1+ 13).tclk} + (n3 + 35).tclk
(1) This equation is valid if B0_P3_R18_D[6:5] = 00, which means SAR data update is not kept on hold for reading
converted data.
(2) The programmable delay tREF scales based on the actual divider setting and time period of the clock used to
generate this. See the respective control register settings to understand the scale factors.
B0_P3_R3_D[5:2]
programmed to
“1011”
Read
IN1L/
AUX1
Read
IN2L/
AUX2
Control Interface
Read
VBAT
Sample and
Convert
IN1L/AUX1
Sample and
Convert
IN2L/AUX2
Sample and
Convert
VBAT
FSM State
Waiting for Host to
program B0_P3_R3
Waiting for tref if applicable
Waiting for Host to program B0_P3_R3
/Data_Available
B0_P3_R3_D[1:0]=”01'
Figure 75. Host-Controlled Port Scan Mode
8.3.7 Headset Detection
The TLV320AIC3268 includes extensive capability to monitor a headphone, microphone, or headset jack to find if
a plug has been inserted into the jack, and if inserted find the nature of headset or headphone inserted in the
jack. The device also includes the capability to detect a button press for actions such as starting a call with
headset button press. The figures below show the circuit configuration to enable this feature for stereo
headphones and stereo headset with microphone and button, as well as mono headset with and without
microphone. It is recommended to use IN1L or IN1R for external headset microphones.
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Stereo Headset with
Microphone, Button
Stereo
Headphones
s
s
HPR
g
g
HPVSS_SENSE
AVSS
s
s
HPL
Micpga
m
m
IN1L
MICDET
Micbias_ext
MICBIAS_EXT
Figure 76. Jack Connections for Detection of Stereo Headsets
Mono Headset with
Microphone, Button
Mono Headset
HPR
g
g
HPVSS_SENSE
AVSS
s
s
HPL
Micpga
m
m
IN1L
MICDET
Micbias_ext
MICBIAS_EXT
Figure 77. Jack Connections for Detection of Mono Headsets
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This feature is enabled by programming B0_P0_R67_D7. In order to avoid false detections due to mechanical
vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the
case of headset insertion/removal, a debounce function with a range of 16ms - 512ms is provided. This can be
programmed via B0_P0_R67_D[4:2]. For improved button-press detection, the debounce function has a range of
8ms to 32ms by programming B0_P0_R67_D[1:0].
The TLV320AIC3268 also provides feedback to user when a button press, or a headset insertion/removal event
is detected through register readable flags as well as an interrupt on the IO terminals. The value in
B0_P0_R46_D[5:4] provides the instantaneous state of button press and headset insertion. B0_P0_R44_D5 is a
sticky (latched) flag that is set when the button-press event is detected. B0_P0_R44_D4 is a sticky flag that is set
when the headset insertion or removal event is detected. These sticky flags are set by the event occurrence, and
are reset only when read. This requires polling B0_P0_R44. To avoid polling and the associated overhead, the
TLV320AIC3268 also provides an interrupt feature where the events can trigger the INT1 and/or INT2 interrupts.
These interrupt events can be routed to one of the digital output terminals. Please see Interrupt Generation and
Diagnostic Flags for details on interrupts (INT1 and INT2) and Interrupt Generation and Diagnostic Flags for
details on digital terminal routing.
As shown in Figure 76 and Figure 77, the TLV320AIC3268 not only detects a headset insertion event, but also
distinguishes between the different headsets inserted, such as stereo headphones, stereo cellular headsets with
microphone, mono headsets with microphone, and mono headset without microphone. After the headset-
detection event, the user can read B0_P0_R37_D[5:4] and B0_P0_R37_D[1:0] to determine the type of headset
inserted.
Table 37. Headset Detection Types
Headset Type
Microphone Detection
Headset Detection
Stereo Headphones without
Microphone
B0_P0_R37_D[5:4] = 01
B0_P0_R37_D[1:0] = 10
Stereo Headset with
Microphone
B0_P0_R37_D[5:4] = 11
B0_P0_R37_D[5:4] = 01
B0_P0_R37_D[1:0] = 10
B0_P0_R37_D[1:0] = 01
B0_P0_R37_D[1:0] = 01
Mono Headset without
Microphone
Mono Headset with Microphone B0_P0_R37_D[5:4] = 11
For proper detection of these different types, it is important to follow the guidelines in Table 38.
Table 38. Detection Specifications for Microphone, Button, Headset
Parameter
Minimum
Typical
Maximum
Unit
Ω
Headphone load resistance
16
300
2
Key switch resistance (includes all jack-to-plug
contact resistances)
Ω
Effective capacitance between MICDET and ground
Microphone effective resistance
150
8
pF
kΩ
kΩ
0.8
Micbias_ext resistor for microphone detection
2.09
2.2
2.31
Table 39. Headset Detection Block Registers
Register
Description
B0_P0_R67_D7
B0_P0_R67_D[4:2]
B0_P0_R67_D[1:0]
B0_P0_R44_D5
B0_P0_R44_D4
B0_P0_R46_D5
B0_P0_R46_D4
Headset Detection Enable/Disable
Debounce Programmability for Headset Detection
Debounce Programmability for Button Press
Sticky Flag for Button Press Event
Sticky Flag for Headset Insertion or Removal Event
Status Flag for Button Press Event
Status Flag for Headset Insertion and Removal
B0_P0_R37_D[5:4] and B0_P0_R37_D[1:0] Flags for type of Headset Detected
B0_P1_R119 and B0_P1_R120
Headset Detection Tuning Registers
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The headset detection block requires AVDDx_18 and AVDD3_33 to be powered. In addition, the weak
connection of AVDDx_18 to DVDD_18 should be disabled (B0_P1_R1_D3="0"), and External Analog Supplies
should be enabled (B0_P1_R1_D2="0"). The headset detection feature in the TLV320AIC3268 is achieved with a
very low power overhead, requiring less than 30μA of additional current from AVDDx_18 supplies.
8.3.8 Interrupt Generation and Diagnostic Flags
The TLV320AIC3268 an trigger interrupts to the host processor for events that require host processor
intervention. This avoids polling the status-flag registers continuously. The TLV320AIC3268 has two defined
interrupts; INT1 and INT2 that can be configured by programming Page 0, Register 48 and 49. A user can
configure the interrupts INT1 and INT2 to be triggered by one or many events such as:
•
•
•
•
•
•
•
Headset Detection
Button Press
Noise Detected by AGC
Over-current Condition in Headphones
Data Overflow in ADC and DAC Processing Blocks and Filters
Over-temperature Condition in Speaker Drivers
SAR ADC Data Available or Exceeding Threshold
Each of these INT1 and INT2 interrupts can be routed to output terminals like GPIO1, GPIO2, GPO1, DOUT1,
WCLK2, BCLK2, and DOUT2 by configuring B0_P4_R67-R96. Table 40 displays how to individually configure
the INT1 or INT2 interrupts.
Table 40. Register Settings for Interrupt Routing
Terminal
GPIO1
GPIO2
GPO1
INT1
INT2
B0_P4_R86_D[5:2] = 0101
B0_P4_R87_D[5:2] = 0101
B0_P4_R96_D[5:2] = 0100
B0_P4_R67_D[4:1] = 0100
B0_P4_R69_D[5:2] = 0101
B0_P4_R70_D[5:2] = 0101
B0_P4_R71_D[4:1] = 0100
B0_P4_R86_D[5:2] = 0110
B0_P4_R87_D[5:2] = 0110
B0_P4_R96_D[5:2] = 0101
B0_P4_R67_D[4:1] = 0101
B0_P4_R69_D[5:2] = 0110
B0_P4_R70_D[5:2] = 0101
B0_P4_R71_D[4:1] = 0101
DOUT1
WCLK2
BCLK2
DOUT2
These interrupt signals can either be configured as a single pulse, a series of pulses, or a change in output level
by programming B0_P0_R51_D[7:6] and B0_P0_R51_D[5:4]. If the user configures the interrupts as a series of
pulses, the events will trigger the start of pulses that will stop when the flag registers in B0_P0_R42,
B0_P0_R44, B0_P0_R45 are read by the user to determine the cause of the interrupt. Similarly, if the user
configures the interrupts as an active-high, level-based interrupt generated from these sticky flags, the interrupt
port will reset low when the flag registers in B0_P0_R42, B0_P0_R44, B0_P0_R45 are read by the user.
When the interrupts are configured for multiple events simultaneously, the user can read associated flags to
determine the triggering events. Sometimes upon reading the Primary Flag Registers, additional Secondary Flag
Registers may have to be read back to resolve the triggering event. For example, on receiving an interrupt, the
user can read Primary Flag Registers B0_P0_R44 and B0_P0_R45. If B0_P0_R44_D[7] is '1', it indicates an
over-current condition on one of HPL, RECP or SPK drivers has happened. To determine which of the three
drivers had an over-current condition, the Secondary Flag Register B0_P1_R69 should be read back. Table 41
provides details of Primary Flag Registers and Secondary Flag Registers which can be used to resolve events
causing the interrupts.
Table 41. Flags for Interrupt
Primary Flag
Register
Secondary Flag
Register
Type
FLAG Details
B0_P0_R42_D[7]
B0_P0_R42_D[6]
B0_P0_R42_D[5]
B0_P0_R42_D[3]
Sticky
Sticky
Sticky
Sticky
Left DAC Overflow Flag
Right DAC Overflow Flag
DAC Barrel Shifter Overflow Flag
Left ADC Overflow Flag
90
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Table 41. Flags for Interrupt (continued)
Primary Flag
Register
Secondary Flag
Register
Type
FLAG Details
B0_P0_R42_D[2]
B0_P0_R42_D[1]
B0_P0_R44_D[7]
Sticky
Sticky
Sticky
Sticky
Sticky
Sticky
Sticky
Sticky
Sticky
Right ADC Overflow Flag
ADC Barrel Shifter Overflow Flag
Over Current Flag for HPL, RECP and SPK Drivers
Over Current Flag for RECP Driver
B0_P1_R69_D[7]
B0_P1_R69_D[6]
B0_P1_R69_D[5]
Over Current Flag for HPL Driver
Over Current Flag for SPK Driver
B0_P0_R44_D[6]
B0_P0_R44_D[5]
B0_P0_R44_D[4]
Over Current Flag for HPR and RECM
Button Press Flag
Headset Insertion/Removal Detected Flag
Mic Presence on Inserted Headset Status
Headphone Load Status
B0_P0_R37_D[5:4] Status
B0_P0_R37_D[1:0] Status
B0_P0_R44_D[1]
B0_P0_R44_D[0]
B0_P0_R45_D[7]
B0_P0_R45_D[6]
B0_P0_R45_D[5]
B0_P0_R45_D[4]
B0_P0_R45_D[3]
B0_P0_R50_D[2]
Sticky
Sticky
Sticky
Sticky
Sticky
Sticky
Sticky
Sticky
miniDSP_D Standard Interrupt Port Flag
miniDSP_D Auxilliary Interrupt Port Flag
SPK Driver Over Temperature Flag
Left AGC Noise Detect Flag
Right AGC Noise Detect Flag
miniDSP_A Standard Interrupt Port Flag
miniDSP_A Auxilliary Interrupt Port Flag
SAR ADC Data Available Flag
B0_P0_R9_D[5]
B0_P0_R10_D[7]
B0_P0_R10_D[6]
B0_P0_R10_D[5]
B0_P0_R10_D[1]
B0_P0_R10_D[0]
Status
Status
Status
Status
Status
Status
Sticky
Status
Status
Status
Status
Status
Status
SAR ADC Data Available Status
SAR ADC IN1L/AUX1 New Converted Data Available Status
SAR ADC IN1R/AUX2 New Converted Data Available Status
SAR ADC VBAT New Converted Data Available Status
SAR ADC TEMP1 New Converted Data Available Status
SAR ADC TEMP2 New Converted Data Available Status
SAR ADC Threshold Exceed Flag
B0_P0_R50_D[1]
B0_P3_R21_D[5]
B0_P3_R21_D[4]
B0_P3_R21_D[3]
B0_P3_R21_D[2]
B0_P3_R21_D[1]
B0_P3_R21_D[0]
SAR ADC IN1L/AUX1 Max. Threshold Compare Status
SAR ADC IN1L/AUX1 Min. Threshold Compare Status
SAR ADC IN1R/AUX2 Max. Threshold Compare Status
SAR ADC IN1R/AUX2 Min. Threshold Compare Status
SAR ADC TEMP Max. Threshold Compare Status
SAR ADC TEMP Min. Threshold Compare Status
In addition to the interrupt flags, the TLV320AIC3268 features additional status flags which are very helpful for
diagnostics since they enable reporting of the status of various internal blocks of the device. Table 42 provides
list of the other flags available in TLV320AIC3268.
Table 42. Miscellaneous Flags
Flag Register
B0_P0_R36_D[7]
B0_P0_R36_D[6]
B0_P0_R36_D[5]
B0_P0_R36_D[3]
B0_P0_R36_D[2]
B0_P0_R36_D[1]
B0_P0_R37_D[7]
B0_P0_R37_D[3]
Type
Status
Status
Sticky
Status
Status
Sticky
Status
Status
FLAG Details
Left ADCPGA Gain Status
Left ADC Power Status
Left AGC Gain Saturation Flag
Right ADCPGA Gain Status
Right ADC Power Status
Right AGC Gain Saturation Flag
Left DAC Power Status
Right DAC Power Status
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Table 42. Miscellaneous Flags (continued)
Flag Register
B0_P0_R38_D[6]
B0_P0_R38_D[4]
B0_P0_R38_D[2]
B0_P0_R38_D[0]
B0_P1_R62_D[1]
B0_P1_R62_D[0]
B0_P1_R63_D[7]
B0_P1_R63_D[6]
B0_P1_R63_D[5]
B0_P1_R63_D[4]
B0_P1_R64_D[7]
B0_P1_R64_D[6]
B0_P1_R64_D[5]
B0_P1_R64_D[4]
B0_P1_R64_D[3]
B0_P1_R64_D[0]
B0_P1_R65_D[7]
B0_P1_R65_D[6]
B0_P1_R65_D[5]
B0_P1_R65_D[4]
B0_P1_R66_D[7]
B0_P1_R66_D[6]
B0_P1_R66_D[5]
B0_P1_R66_D[4]
B0_P1_R66_D[3]
B0_P1_R66_D[2]
B0_P1_R66_D[1]
Type
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
FLAG Details
Left DAC Volume Control Mute Status
Left DAC Volume Control Soft-stepping Status
Right DAC Volume Control Mute Status
Right DAC Volume Control Soft-stepping Status
Left ADCPGA Gain Status
Right ADCPGA Gain Status
HPL Driver Gain Status
HPR Driver Gain Status
RECP Driver Gain Status
RECM Driver Gain Status
LOL to HPL Volume Control Status
LOR to HPR Volume Control Status
LOL to RECP Volume Control Status
LOR to RECM Volume Control Status
LOL to SPK Volume Control Status
Charge Pump Power Status
IN1L to RECP Volume Control Status
IN1R to RECM Volume Control Status
Left ADCPGA to MAL Volume Control Status
Right ADCPGA to MAR Volume Control Status
LOL Driver Power Up Status
LOR Driver Power Up Status
HPL Driver Power Up Status
HPR Driver Power Up Status
RECP Driver Power Up Status
RECM Driver Power Up Status
SPK Driver Power Up Status
Sticky Flags are useful for reporting events which could be intermittent. These flags are set by the triggering
events like over-current detect but are reset only when the flag register is read back the user. Status Flags on
the other hand are useful for reporting events which are steady state in nature like power-up status of a block.
The flag value reflects the triggering event's status when the register is being read by the user.
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8.3.9 Interfaces
8.3.9.1 Control Interfaces
The TLV320AIC3268 control interface supports SPI or I2C communication protocols. For SPI, the SPI_SELECT
terminal should be tied high; for I2C, SPI_SELECT should be tied low. It is not recommended to change the state
of SPI_SELECT during device operation.
8.3.9.1.1 I2C Control Mode
The TLV320AIC3268 supports the I2C control protocol, and will respond by default (I2C_ADDR_SCLK grounded)
to the 7-bit I2C address of 0011000. With the one I2C address terminal, I2C_ADDR_SCLK, the device can be
configured to respond to one of two 7-bit I2C addresses, 0011000 or 0011001. The full 8-bit I2C address can be
calculated as:
8-Bit I2C Address = "001100" + I2C_ADDR_SCLK + R/W
Example: to write to the TLV320AIC3268 with I2C_ADDR_SCLK = 1 the 8-Bit I2C Address is "001100" +
I2C_ADDR_SCLK + R/W = "00110010" = 0x32
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the TLV320AIC3268 can only act as a slave
device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock. All
data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven
to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero, while a HIGH indicates the
bit is one).
Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line clocks the
SDA bit into the receiver’s shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start communication on the bus.
Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state
while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START
condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when
the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that selects the slave device for communication. This
byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds.
(Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in
the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device.
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW
to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (Remember that the master always
drives the clock line.)
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it will receive a not−acknowledge because no device
is present at that address to pull the line LOW.
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When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320AIC3268 can also respond to and acknowledge a General Call, which consists of the master issuing
a command with a slave address byte of 00H. This feature is disabled by default, but can be enabled via
B0_P0_R115_D5.
SCL
DA(6)
DA(0)
RA(7)
RA(0)
D(7)
D(0)
SDA
Slave
Ack
(S)
Slave
Ack
(S)
Slave
Ack
(S)
Start
(M)
7-bit Device Address
(M)
Write
(M)
8-bit Register Address
(M)
8-bit Register Data
(M)
Stop
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
Figure 78. I2C Write
SCL
SDA
DA(6)
DA(0)
D(7)
D(0)
DA(6)
DA(0)
RA(7)
RA(0)
Master
No Ack
(M)
Start
(M)
Stop
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
Repeat
Start
(M)
7-bit Device Address
(M)
Read
(M)
Slave
Ack
(S)
8-bit Register Data
(S)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
Figure 79. I2C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-
increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues a ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the
next 8 clocks the data of the next incremental register.
8.3.9.1.2 SPI Digital Interface
In the SPI control mode, the TLV320AIC3268 uses the terminals SCL_SSZ as SS, I2C_ADDR_SCLK as SCLK,
MISO_GPO1 as MISO, SDA_MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0) and clock phase setting of 1 (typical microprocessor SPI control bit
CPHA = 1). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3268) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI terminal under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI terminal, a byte shifts out
on the MISO terminal to the master shift register.
The TLV320AIC3268 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI
control bit CPHA = 1), the master begins driving its MOSI terminal and the slave begins driving its MISO terminal
on the first serial clock edge. The SSZ terminal can remain low between transmissions; however, the
TLV320AIC3268 only interprets the first 8 bits transmitted after the falling edge of SSZ as a command byte, and
the next 8 bits as a data byte only if writing to a register. Reserved register bits should be written to their default
values. The TLV320AIC3268 is entirely controlled by registers. Reading and writing these registers is
accomplished by an 8-bit command sent to the MOSI terminal of the part prior to the data for that register. The
command is structured as shown in Table 43. The first 7 bits specify the address of the register which is being
written or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction
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of data flow on the serial bus. In the case of a register write, the R/W bit should be set to 0. A second byte of
data is sent to the MOSI terminal and contains the data to be written to the register. Reading of registers is
accomplished in a similar fashion. The 8-bit command word sends the 7-bit register address, followed by the R/W
bit = 1 to signify a register read is occurring. The 8-bit register data is then clocked out of the part on the MISO
terminal during the second 8 SCLK clocks in the frame.
Table 43.
COMMAND WORD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR(6)
ADDR(5)
ADDR(4)
ADDR(3)
ADDR(2)
ADDR(1)
ADDR(0)
R/WZ
SS
SCLK
MOSI
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
D(7)
D(6)
D(0)
7-bit Register Address
Write
8-bit Register Data
Hi-Z
Hi-Z
MISO
Figure 80. SPI Timing Diagram for Register Write
SS
SCLK
MOSI
Hi-Z
Hi-Z
Hi-Z
RA(6)
RA(5)
RA(0)
Don’t Care
7-bit Register Address
Read
8-bit Register Data
Hi-Z
MISO
D(7)
D(6)
D(0)
Figure 81. SPI Timing Diagram for Register Read
8.3.9.2 Digital Audio Interfaces
The TLV320AIC3268 features three digital audio data serial interfaces, or audio buses. These three interfaces
can be run simultaneously, thereby enabling reception and transmission of digital audio for or to three separate
devices. A common example of usage of multiple digital audio serial interfaces is to allow connections with
application processor, bluetooth chipset, digital input Class-D amplifiers and so forth. By utilizing the
TLV320AIC3268 as the center of the audio processing in a portable audio system, mixing of voice and music
audio is greatly simplified. In addition, the miniDSP can be utilized to greatly enhance the portable device
experience by providing advanced audio processing to both communication and media audio streams
simultaneously.
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Audio Serial Interfaces
AUDIO SERIAL INTERFACE 1
AUDIO SERIAL INTERFACE 2
AUDIO SERIAL INTERFACE 3
WCLK
BCLK
DIN
DOUT
WCLK
BCLK
DIN
DOUT
WCLK
BCLK
DIN
DOUT
Figure 82. Typical Multiple Connections to Three Audio Serial Interfaces
Each audio bus on the TLV320AIC3268 is very flexible, including left or right-justified data options, support for
I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible
master or slave configurability for each bus clock line, and the ability to communicate with multiple devices within
a system directly.
Each of the three audio buses of the TLV320AIC3268 can be configured for left or right-justified, I2S, DSP, or
TDM modes of operation, where communication with PCM interfaces is supported within the TDM mode. These
modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock and
bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide
variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as
either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
ADC and DAC sampling frequencies. When configuring an audio interface for six-wire mode, the ADC and DAC
paths can operate based on separate word clocks.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider. The number
of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support
the case when multiple TLV320AIC3268s may share the same audio bus. When configuring an audio interface
for six-wire mode, the ADC and DAC paths can operate based on separate bit clocks.
The TLV320AIC3268 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks.
The TLV320AIC3268 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen.
The TLV320AIC3268 further includes programmability to 3-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on
a single audio serial data bus. When the audio serial data bus is powered down while configured in master
mode, the terminals associated with the interface are put into a 3-state output condition.
By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3268, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word-
clock or bit-clocks are used in the system as general-purpose clocks.
The TLV320AIC3268 contains advanced Digital Audio interfaces features to enable:
•
•
Connections of Multiple Digital Audio interfaces
6-wire Digital Audio interfaces for separate uplink/downlink clocks or ADC/DAC clocks
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•
Multi-channel, Multiple terminal operation
8.3.9.2.1 Connecting Multiple Audio Digital Interfaces
The TLV320AIC3268 enables connections to multiple audio data buses. Figure 82 shows a typical example of
utilizing the digital terminals on the device to connect to four separate 4-wire digital audio buses, with up to three
of these 4-wire buses receiving and sending digital audio data simultaneously. This configuration can be utilized
when using I2C for control of the device. If only 3 total audio interface connections are needed (that is, a fourth
audio bus does not need to be muxed into Audio Serial Interface 1), either I2C or SPI control can be used.
(Further details on SPI control and terminals utilized can be found in SPI Digital Interface and Table 47.)
To configure each of the three audio serial interfaces, both the audio interface and the terminals should be set up
for appropriate routing of the signals. Audio Serial Interface 1 configuration registers are located in B0_P4_R1-
R16 and B0_P4_R49-R52. Audio Serial Interface 2 configuration registers are located in B0_P4_R17-R32 and
B0_P4_R53-R54. Audio Serial Interface 3 configuration registers are located in B0_P4_R33-R48 and
B0_P4_R55-R56. The terminal muxing registers are located in B0_P4_R65-R96. Table 44 displays the
appropriate register settings needed to implement the Audio Serial Interface configuration found in Figure 82.
Table 44. Register Settings for Typical Multiple Audio Digital Interface Connections
Terminal Control
(Codec Interface as
Slave)
Terminal Control
(Codec Interface as
Master)
Interface Control (Codec
Interface is Slave)
Interface Control (Codec
Interface is Master)
TERMINAL
Audio Serial
Interface 1 Word
Clock to WCLK1
Terminal
B0_P4_R10_D[7:5] = 000
B0_P4_R10_D[4:2] = 000
B0_P4_R10_D[7:5] = 001
B0_P4_R10_D[4:2] = 001
B0_P4_R65_D[5:2] = 0001
Audio Serial
Interface 1 Bit
Clock to BCLK1
Terminal
N/A
Audio Serial
Interface 1 Data
Input to DIN1
Terminal
B0_P4_R49_D[4:0] = 00001 (default)
B0_P4_R8_D[7:4] = 0101 (default) (ASI1-to-DAC datapath)
B0_P4_R68_D[6:5] = 01 (default)
B0_P4_R67_D[4:1] = 0001 (default)
B0_P4_R69_D[5:2] = 0001 (default)
B0_P4_R70_D[5:2] = 0001 (default)
B0_P4_R72_D[6:5] = 01
Audio Serial
Interface 1 Data
Output to DOUT1
Terminal
B0_P4_R15_D[1:0] = 00 (default)
B0_P4_R7_D[2:0] = 001 (default)
Audio Serial
Interface 2 Word
Clock to WCLK2
Terminal
B0_P4_R26_D5 = 0 (default)
B0_P4_R26_D2 = 0 (default)
B0_P4_R26_D5 = 1
B0_P4_R26_D2 = 1
Audio Serial
Interface 2 Bit
Clock to BCLK2
Terminal
Audio Serial
Interface 2 Data
Input to DIN2
Terminal
B0_P4_R24_D[7:4] = 0101 (ASI2-to-DAC datapath)
Audio Serial
Interface 2 Data
Output to DOUT2
Terminal
B0_P4_R23_D[2:0] = 101 (ADC-to-ASI2 routing - Port 2),
B0_P4_R31_D[1:0] = 00 (default)
B0_P4_R71_D[4:1] = 0001 (default)
Audio Serial
Interface 3 Word
Clock to GPIO2
Terminal
B0_P4_R87_D[6:2] =
10100
B0_P4_R87_D[6:2] =
B0_P4_R55_D[6:5] = 10
B0_P4_R55_D[2:0] = 001
00001
Audio Serial
Interface 3 Bit
Clock to GPIO1
Terminal
B0_P4_R86_D[6:2] =
10101
B0_P4_R86_D[6:2] =
00001
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Table 44. Register Settings for Typical Multiple Audio Digital Interface Connections (continued)
Terminal Control
(Codec Interface as
Slave)
Terminal Control
(Codec Interface as
Master)
Interface Control (Codec
Interface is Slave)
Interface Control (Codec
Interface is Master)
TERMINAL
Audio Serial
Interface 3 Data
Input to GPIO3
Terminal
B0_P4_R40_D[7:4] = 0101 (ASI3-to-DAC datapath)
B0_P4_R88_D[6:2] = 11101
Audio Serial
Interface 3 Data
Output to GPIO4
Terminal
B0_P4_R39_D[2:0] = 110 (ADC-to-ASI3 routing - Port 3)
B0_P4_R47_D[1:0] = 00 (default)
B0_P4_R89_D[6:2] = 11101
Since each interface can be configured separately as master or slave, the appropriate settings are displayed for
both possible configurations for each of the three audio serial interfaces. When in master mode, the bit clock and
work clock source can be derived from a variety of sources, and more details on the possible sources of these
clocks can be found in the Clock Generation and PLL section.
8.3.9.2.2 Six-Wire Digital Audio Interface
The six-wire audio interface mode allows independent configuration of receive and transmist word and bit clocks
for the device. The TLV320AIC3268 supports six-wire audio interface on ASI1 and ASI2. The six-wire inteface
mode is available in all interface formats such as I2S, LJF, RJF, DSP and PCM modes. Due to terminal
limitations, only one of ASI1 or ASI2 can operate in six-wire mode at a time.
When ASI1 operates in six-wire mode, WCLK1 functions as DAC_WCLK or receive word clock, BCLK1 functions
as DAC_BCLK or receive bit clock. The tranmist word clock and transmit bit clock function can get supported on
any of the pair of terminals amongst GPIO1, GPIO2, GPIO3 or GPIO4.
Audio Serial Interfaces
AUDIO SERIAL INTERFACE 1
AUDIO SERIAL INTERFACE 2
DAC_WCLK
DAC_BCLK
DIN
ADC_WCLK
ADC_BCLK
DOUT
WCLK
BCLK
DIN
DOUT
Figure 83. Six-Wire Audio Serial Interface with ASI1
When ASI2 operates in six-wire mode, WCLK1 functions as DAC_WCLK or receive word clock, BCLK1 functions
as DAC_BCLK or receive bit clock. The tranmist word clock and transmit bit clock function can get supported on
any of the pair of terminals amongst GPIO1, GPIO2, GPIO3 or GPIO4.
Audio Serial Interfaces
AUDIO SERIAL INTERFACE 2
AUDIO SERIAL INTERFACE 1
DAC_WCLK
DAC_BCLK
DIN
ADC_WCLK
ADC_BCLK
DOUT
WCLK
BCLK
DIN
DOUT
Figure 84. Six-Wire Audio Serial Interface with ASI2
The details of register settings to enable six-wire interface mode are shown in Table 51.
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8.3.9.2.3 Multiple Channel, Multiple Terminal Setup
The TLV320AIC3268 also enables connections of up to four stereo pairs (8 total channels) of input and output
data on Audio Serial Interface 1. These eight bidirectional channels are all synchronized to a single word clock
(WCLK1) and bit clock (BCLK1). Figure 85 displays a typical configuration for this multi-channel setup.
Audio Serial Interfaces
AUDIO SERIAL INTERFACE 1
WCLK
BCLK
DIN(L1,R1)
DIN(L2,R2)
DIN(L3,R3)
DIN(L4,R4)
DOUT(L1,R1)
DOUT(L2,R2)
DOUT(L3,R3)
DOUT(L4,R4)
Figure 85. Multi-channel, Multi-Terminal Inputs and Outputs to Audio Serial Interface 1
Table 45. Register Settings for Replacing ASI2 and ASI3 with Multi-Channel Connections
Terminal
Interface Control
Terminal Control
Audio Serial Interface 1 DIN_1 Input to
DIN1 Terminal
To configure to 8 channels - B0_P4_R4_D[7:6] = 11
To configure multiterminal mode - B0_P4_R6_D[7] = 1
To configure input routings for DIN1 - B0_P4_R49_D[4:0] =
00001
To configure input routings for DIN2 - B0_P4_R50_D[4:0] =
00010
B0_P4_R68_D[6:5] = 01 (default)
Audio Serial Interface 1 DIN_2 Input to
DIN2 (1)terminal
B0_P4_R72_D[6:5] = 01 (default)
B0_P4_R70_D[5:2] = 1110
Audio Serial Interface 1 DIN_3 Input to
BCLK2(1) terminal
To configure input routings for BCLK2 - B0_P4_R51_D[4:0]
= 01100
Audio Serial Interface 1 DIN_4 Input to
WCLK2(1) terminal
To configure input routings for WCLK2 -
B0_P4_R51_D[4:0] = 01110
B0_P4_R69_D[5:2] = 1111
Audio Serial Interface 1 DOUT_1 Input to
DOUT1 terminal
B0_P4_R67_D[4:1] = 0001
(default)
Audio Serial Interface 1 DOUT_2 Input to
DOUT2(1) terminal
B0_P4_R71_D[4:1] = 1101
B0_P4_R86_D[6:2] = 01110
B0_P4_R87_D[6:2] = 01111
To configure to 8 channels - B0_P4_R4_D[7:6] = 11
To configure multiterminal mode - B0_P4_R6_D[7] = 1
Audio Serial Interface 1 DOUT_3 Input to
GPIO1 terminal
Audio Serial Interface 1 DOUT_4 Input to
GPIO2 terminal
(1) BCLK2, WCLK2, DIN2 and DOUT2 terminals are with respect to IOVDD2 supply therefore using with ASI-1 in multiterminal 8-ch mode
requires either shorting IOVDD1 and IOVDD2 with same voltage level or putting on-board level-shifter for the above signals.
The configuration shown in Figure 85 can be used with either I2C or SPI for control interface. In this configuration
ASI2 and ASI3 cannot be used. Other combinations with reduced channels or I2C only control interface allow
simultaneous use of ASI2 or ASI3 by choosing different set of terminals. For details of various functions
supported on terminals, see Table 47.
8.3.9.2.4 Audio Formats
Each Audio Serial Interface supports left or right-justified, I2S, DSP, or mono PCM modes. In addition, time-
division multiplexing (TDM) can be implemented in each of these formats to enable multi-channel operation.
8.3.9.2.4.1 Right Justified Mode
Audio Serial Interface 1 can be put into Right Justified Mode by programming B0_P4_R1_D[7:5] = 010. Audio
Serial Interface 2 can be put into Right Justified Mode by programming B0_P4_R17_D[7:5] = 010. Audio Serial
Interface 3 can be put into Right Justified Mode by programming B0_P4_R33_D[7:5] = 010. In right-justified
mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the
word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising
edge of the word clock.
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1/fs
WCLK
BCLK
Left Channel
Right Channel
n-1 n-2 n-3
MSB
DIN/
DOUT
0
n-1 n-2 n-3
MSB
2
1
0
2
1
0
LSB
LSB
Figure 86. Timing Diagram for Right-Justified Mode
For Right-Justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-
length of the data.
8.3.9.2.4.2 Left Justified Mode
Audio Serial Interface 1 can be put into Left Justified Mode by programming B0_P4_R1_D[7:5] = 011. Audio
Serial Interface 2 can be put into Left Justified Mode by programming B0_P4_R17_D[7:5] = 011. Audio Serial
Interface 3 can be put into Left Justified Mode by programming B0_P4_R33_D[7:5] = 011. In left-justified mode,
the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word
clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of
the word clock.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 87. Timing Diagram for Left-Justified Mode
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 88. Timing Diagram for Left-Justified Mode with Offset=1
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WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 89. Timing Diagram for Left-Justified Mode with Offset=0 and Inverted Bit Clock
For Left-Justified mode, the programmed offset value should be less than the number of bit-clocks per frame by
at least the programmed word-length of the data.
8.3.9.2.4.3 I2S Mode
Audio Serial Interface 1 can be put into I2S Mode by programming B0_P4_R1_D[7:5] = 000. Audio Serial
Interface 2 can be put into I2S Mode by programming B0_P4_R17_D[7:5] = 000. Audio Serial Interface 3 can be
put into I2S Mode by programming B0_P4_R33_D[7:5] = 000. In I2S mode, the MSB of the left channel is valid on
the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right
channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 90. Timing Diagram for I2S Mode
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
DATA
5
4
3
2
1
0
5
4
3
2
1
0
5
1
1
1
LD(n)
LD(n) = n'th sample of left channel data
RD(n)
RD(n) = n'th sample of right channel data
LD(n+1)
Figure 91. Timing Diagram for I2S Mode with Offset=2
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WORD
LEFT CHANNEL
CLOCK
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 92. Timing Diagram for I2S Mode with Offset=0 and Bit Clock Inverted
For I2S mode, the programmed offset value should be less than the number of bit-clocks per frame by at least
the programmed word-length of the data.
8.3.9.2.4.4 DSP Mode
Audio Serial Interface 1 can be put into DSP Mode by programming B0_P4_R1_D[7:5] = 001. Audio Serial
Interface 2 can be put into DSP Mode by programming B0_P4_R17_D[7:5] = 001. Audio Serial Interface 3 can
be put into DSP Mode by programming B0_P4_R33_D[7:5] = 001. In DSP mode, the rising edge of the word
clock starts the data transfer with the left channel data first and immediately followed by the right channel data.
Each data bit is valid on the falling edge of the bit clock.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 93. Timing Diagram for DSP Mode
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 94. Timing Diagram for DSP Mode with Offset = 1
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WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
LD(n)
RD(n)
LD(n+1)
Figure 95. Timing Diagram for DSP Mode with Offset = 0 and Bit Clock Inverted
For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of
the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least
the programmed word-length of the data.
8.3.9.2.4.5 Mono PCM Mode
Audio Serial Interface 1 can be put into Mono PCM Mode by programming B0_P4_R1_D[7:5] = 100. Audio Serial
Interface 2 can be put into DSP Mode by programming B0_P4_R17_D[7:5] = 100. Audio Serial Interface 3 can
be put into DSP Mode by programming B0_P4_R33_D[7:5] = 100. In mono PCM mode, the rising edge of the
word clock starts the data transfer of the single channel of data. Each data bit is valid on the falling edge of the
bit clock.
WORD
CLOCK
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
D(n)
D(n+1)
D(n+2)
Figure 96. Timing Diagram for Mono PCM Mode
WORD
CLOCK
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
D(n+1)
D(n)
D(n+2)
Figure 97. Timing Diagram for Mono PCM Mode with Offset=2
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WORD
CLOCK
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
3
2
1
0
3
2
1
0
3
DATA
1
2
3
1
2
3
1
2
3
D(n+1)
D(n)
D(n+2)
Figure 98. Timing Diagram for Mono PCM Mode with Offset=2 and Bit Clock Inverted
For mono PCM mode, the programmed offset value should be less than the number of bit-clocks per frame by at
least the programmed word-length of the data.
8.3.9.2.5 Multi-channel Configurations
The TLV320AIC3268 can utilize TDM techniques to enable several multi-channel system scenarios. First,
multiple codecs can transmit/receive on a single digital audio interface bus. Second, multiple stereo pairs can be
sent and received by a single TLV320AIC3268 on a single 4-wire digital audio interface bus. Lastly, up to 4
individual stereo data pairs to/from the TLV320AIC3268 can be routed to individual DIN and DOUT lines in the
system which are synchronized to a single BCLK and WCLK.
8.3.9.2.5.1 Single Host, Multiple Audio Codecs
Using the offset programmability and the DOUT line 3-state feature, the TLV320AIC3268 enables the flexibility
where multiple TLV320AIC3268 devices can be interfaced together and can communicate to a host/multimedia
processor using a single digital audio serial interface. Figure 99 displays a typical configuration where M devices
are connected to a single host processor.
CODEC-1
TLV320AIC32x
CODEC-2
TLV320AIC32x
Host
CODEC-M
TLV320AIC32x
Figure 99. Interfacing Multiple TLV320AIC3268 Devices Using Single I2S Interface
By changing the programmable offset for each device, the bit clock in each frame where the data begins can be
changed, and the serial data output driver (DOUT) also can be programmed to a 3-state mode during all bit
clocks except when valid data is being put onto the bus. This allows other codecs to be programmed with
different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the
codec simply ignores data on the bus except where it is expected based on the programmed offset.
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LEFT
CHANNEL
1
RIGHT
CHANNEL
1
LEFT
CHANNEL
2
RIGHT
CHANNEL
2
LEFT
CHANNEL
M
RIGHT
CHANNEL
M
WORD
CLOCK
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
DATA
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
1
2
1
2
1
2
1
2
1
2
1
2
LD(n)
CODEC-1
RD(n)
CODEC-1
LD(n)
CODEC-M
RD(n)
CODEC-M
LD(n)
CODEC-2
RD(n)
CODEC-2
LD(n+1)
CODEC-1
Figure 100. DSP Timing for Multiple Devices Interfaced Together, Sequential Left/Right Pairs
The digital audio serial interface timing diagram for the interface in Figure 99 is shown in Figure 100. In this
particular configuration, the TLV320AIC3268 (or any other TLV320AIC32x codec) is programmed for DSP mode
with N-bit word length per channel. The offset programmed for the Codec-1 is 0, for Codec-2 it is 2N, and
likewise, the offset programmed for the Codec-M is (M-1) x 2N. In this TDM mode, the number of bit-clocks per
frame should be greater than M*2N. The TLV320AIC3268 allows a maximum offset of 255 bit clocks, and this
enables connections of up to 4 codecs for 32-bit stereo data and 8 codecs for 16-bit stereo data.
For each of the three individual Digital Audio interfaces, this offset controls when data is received and sent by
these interfaces. For Audio Serial Interface 1, this offset can be set to a value in the range of 0 to 255 bit clocks
by programming B0_P4_R2. For Audio Serial Interface 2, this offset can be set to a value in the range of 0 to
255 bit clocks by programming B0_P4_R18. For Audio Serial Interface 3, this offset can be set to a value in the
range of 0 to 255 bit clocks by programming B0_P4_R34. When utilized in DSP mode, each of these offsets will
set the start of the left channel, with the right channel data immediately following the LSB of the left channel.
8.3.9.2.5.1.1 Time Slot Mode
In addition, Audio Serial Interface 1 can also control the offset of the right channel with respect to the end of the
left channel of data. This is achieved by enabling Time Slot Mode (setting B0_P4_R8_D0) and configuring the
Right Channel Offset 2 (in the range of 0 to 255 bit clocks) in B0_P4_R3. Thus, the Right Channel Offset 2
control allows us to place the right channel anywhere in the frame after the left channel, and this functionality can
be utilized in each of the audio formats (DSP, left or right-justified, or I2S).
LEFT
CHANNEL
1
LEFT
CHANNEL
2
RIGHT
CHANNEL
M
LEFT
CHANNEL
M
RIGHT
CHANNEL
1
WORD
CLOCK
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
DATA
1
0
1
0
1
0
1
0
1
0
1
0
1
2
1
2
1
2
1
2
1
2
1
2
LD(n)
CODEC-1
LD(n)
CODEC-2
RD(n)
CODEC-M
LD(n)
CODEC-M
RD(n)
CODEC-1
LD(n+1)
CODEC-1
Figure 101. DSP Timing for Multiple Devices Interfaced Together, Grouped Left Channels and Right
Channels
By utilizing Time Slot Mode, the individual left and right channels can be grouped together, as shown in
Figure 101. Assuming each channel contains N bits in this example, Codec-1 would have an offset1=0 and
offset2=M*N, Codec-2 would have an offset1=N and offset2=M*N, and likewise, Codec-M would have an
offset1=(M-1)*N and offset2=M*N.
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8.3.9.2.5.2 Multiple Channel Operation, Single Data Lines (Audio Serial Interface 1)
The TLV320AIC3268 can receive and send multiple stereo pairs on a single 4-wire digital audio interface bus.
This particularly useful when sending multi-channel audio data to the miniDSP for stereo downmix and playback
over the integrated stereo headphones, speakers, or line-outs. Alternatively, the host could utilize the audio
miniDSP engine as a multi-channel audio co-processor. This multi-channel operation is only available on Audio
Serial Interface 1, and this is enabled by increasing the number of available channels in B0_P4_R4_D[7:6] to
greater than 1 stereo pair. By increasing the number of stereo pairs, the interface essentially lengthens the data
length for each channel. Thus, the first half of the X channels are interpreted as Left Channels, while the second
half of X channels are interpreted as Right Channels. Once these channels are inside the miniDSP, they can be
interpreted as any channel for surround processing. Figure 102 shows the timing for X channels of data utilizing
DOUT1 and DIN1 data lines.
WORD
CLOCK
CHANNEL
1
CHANNEL
X/2
CHANNEL
X/2+1
CHANNEL
X
CHANNEL
2
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
DATA
1
0
1
0
1
0
1
0
1
0
1
0
1
2
1
2
1
2
1
2
1
2
1
2
LD1(n)
RD1(n)
RDX/2(n)
LD2(n)
LDX/2(n)
LD1(n+1)
Figure 102. DSP Timing for Multi-channel Mode, Single DOUT and DIN Lines
Because Audio Serial Interface 1 interprets the first X/2 channels as Left data, the last X/2 "Right" channels can
be shifted utilizing Time Slot Mode. Figure 103 shows how, in DSP mode, the start of the first X/2 channels can
be delayed by one bit clock (by setting offset1=1 in B0_P4_R2), while the last X/2 "Right" channels can be
delayed by two bit clocks after the end of the first X/2 "Left" channels.
For this multi-channel DSP mode, the number of bit-clocks per frame should be greater than M times the
programmed word-length of the data, where M is the total number of channels set in B0_P4_R4_D[7:6]. Also the
sum of the two programmed offset values should be less than the number of bit-clocks per frame by at least M
times the programmed word-length of the data.
WORD
CLOCK
CHANNEL
1
CHANNEL
X/2
CHANNEL
X/2+1
CHANNEL
X
CHANNEL
2
BIT
CLOCK
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
N
-
DATA
1
0
1
0
1
0
1
0
1
0
1
1
2
1
2
1
2
1
2
1
2
1
2
LD1(n)
RD1(n)
RDX/2(n)
LD2(n)
LDX/2(n)
LD1(n+1)
offset1=1
offset1=1
offset2=2
Figure 103. DSP Timing for Multi-channel Mode, Single DOUT and DIN Lines
106
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8.3.9.2.5.3 Multiple Channel Operation, Multiple Data Lines (Audio Serial Interface 1)
The TLV320AIC3268 can receive or send up to 4 individual stereo data pairs can be routed to individual DIN and
DOUT lines in the system which are synchronized to a single BCLK and WCLK. This multi-channel, multi-
terminal operation is only available on Audio Serial Interface 1. The multi-terminal mode is enabled by setting
B0_P4_R6_D7 to 1. In addition to routing the channels to/from the interface, the individual terminals also need to
be configured (refer to Table 46 and Table 47 for possible digital terminal muxing setups). Just as in the multi-
channel, single-terminal case, the audio serial interface should configure the appropriate number of channels by
writing to B0_P4_R4_D[7:6]. Figure 104 shows an example of multi-channel, multi-terminal mode using 4 stereo
data pairs (8 channels) in DSP format.
WORD
CLOCK
CHANNELS
1, 3, 5, 7
CHANNELS
2, 4, 6, 8
CHANNELS
1, 3, 5, 7
BIT
CLOCK
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN1,
DOUT1
1
1
0
0
1
1
0
0
1
LD1(n)
RD1(n)
LD1(n+1)
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN2,
DOUT2
1
LD2(n)
RD2(n)
LD2(n+1)
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN3,
DOUT3
1
0
1
0
1
LD3(n)
RD3(n)
LD3(n+1)
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN4,
DOUT4
1
0
1
0
1
LD4(n)
RD4(n)
LD4(n+1)
Figure 104. DSP Timing for Multi-channel Mode, Four Data Lines
For this multi-channel DSP mode, the number of bit-clocks per frame should be greater than twice the
programmed word-length of the data. Also, any programmed offset1 value (for shift of start of left channel) should
be less than the number of bit-clocks per frame by at least twice the programmed word-length of the data.
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WORD
CLOCK
CHANNELS
1, 3, 5, 7
CHANNELS
2, 4, 6, 8
CHANNELS
1, 3, 5, 7
BIT
CLOCK
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN1,
DOUT1
1
1
0
0
0
1
0
0
1
LD1(n)
RD1(n)
LD1(n+1)
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN2,
DOUT2
1
1
LD2(n)
RD2(n)
LD2(n+1)
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN3,
DOUT3
1
1
0
0
1
LD3(n)
RD3(n)
LD3(n+1)
N
-
1
N
-
2
N
-
1
N
-
2
N
-
1
N
-
2
DIN4,
DOUT4
1
0
1
1
LD4(n)
RD4(n)
LD4(n+1)
offset2=2
offset1=1
Figure 105. DSP Timing for Multi-channel Mode, Time Slot Mode, Four Data Lines with Offset1=1 and
Offset2=2
By enabling Time Slot Mode, the start of the left and right channels on each data line can be controlled by offset1
and offset2. In other words, offset1 would control the start of all four left channels in Figure 105, and offset2
would delay the start of all right channels after the end of the left channels' LSB. For this multi-channel, multi-
terminal DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-
length of the data. Also the sum of the two programmed offset values should be less than the number of bit-
clocks per frame by at least twice the programmed word-length of the data.
108
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WORD
CLOCK
LEFT CHANNELS
(1, 3, 5, 7)
RIGHT CHANNELS
(2, 4, 6, 8)
BIT
CLOCK
DATA
IN 1,
DATA
OUT 1
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
2
2
1
1
0
0
3
2
2
1
1
0
0
3
LD1(n)
RD1(n)
LD1(n+1)
DATA
IN 2,
DATA
OUT 2
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
3
3
LD2(n)
RD2(n)
LD2(n+1)
DATA
IN 3,
DATA
OUT 3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
2
2
1
1
0
0
3
2
2
1
1
0
0
3
LD3(n)
RD3(n)
LD3(n+1)
DATA
IN 4,
DATA
OUT 4
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
3
3
LD4(n)
RD4(n)
LD4(n+1)
Figure 106. I2S Timing for Multi-channel Mode, Four Data Lines
On Audio Serial Interface 1, any format (DSP, left or right-justified, or I2S) can be utilized in multi-channel, multi-
terminal mode. Figure 106 shows an example of multi-channel, multi-terminal mode using 4 stereo data pairs (8
channels) in I2S format.
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WORD
CLOCK
LEFT CHANNELS
(1, 3, 5, 7)
RIGHT CHANNELS
(2, 4, 6, 8)
BIT
CLOCK
DATA
IN 1,
DATA
OUT 1
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
2
2
1
1
0
0
3
2
2
1
1
0
0
3
LD1(n)
RD1(n)
LD1(n+1)
DATA
IN 2,
DATA
OUT 2
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
3
3
LD2(n)
RD2(n)
LD2(n+1)
DATA
IN 3,
DATA
OUT 3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
2
2
1
1
0
0
3
2
2
1
1
0
0
3
LD3(n)
RD3(n)
LD3(n+1)
DATA
IN 4,
DATA
OUT 4
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
N
-
1
N
-
2
N
-
3
3
3
3
LD4(n)
RD4(n)
LD4(n+1)
offset1=1
offset1=1
Figure 107. I2S Timing for Multi-channel Mode, Four Data Lines with Offset1=1
For I2S multi-channel, multi-terminal mode, the programmed offset value should be less than the number of bit-
clocks per frame by at least the programmed word-length of the data.
8.3.10 miniDSP
The TLV320AIC3268 features two fully programmable miniDSP cores. The first miniDSP core is tightly coupled
to the ADC, the second miniDSP core is tightly coupled to the DAC. The algorithms for the miniDSP must be
loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the
ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each
miniDSP can run up to 1229 instructions on every audio sample at a 48kHz sample rate. The two cores can run
fully synchronized and can exchange data. The miniDSPs in TLV320AIC3268 enable advanced sound
enhancement algorithms on an audio device.
The TLV320AIC3268 features two fully programmable miniDSP cores and three ASI ports. The miniDSP_A is
capable of generating 8 channels of audio data, which can either be routed to the ASIs to be output from the
device or routed back to the miniDSP_D for a loopback function. Similarly the miniDSP_D can take in audio data
from multiple ASIs or the miniDSP_A.
The miniDSP_A can generate
8
channels of data called the miniDSP_A_DataOutput[1:8]. The
miniDSP_A_DataOutput[1,2,3,...,8] are also referred to as miniDSP_A_DataOutput[L1,R1,L2,...,R4]. When the
device is used in pre-programmed PRB modes only miniDSP_A_DataOutput[1:2] are generated by the device for
stereo modes and only miniDSP_A_DataOutput[1] is generated in the mono modes.
The miniDSP_D features
miniDSP_D_DataInput_3.
3
input ports called miniDSP_D_DataInput_1, miniDSP_D_DataInput_2 and
The input port miniDSP_D_DataInput_1 features channels,
8
miniDSP_D_DataInput_1[1:8], also referred to as miniDSP_D_DataInput_1[L1,R1,...,R4]. In the pre-programmed
stereo PRB modes only miniDSP_D_DataInput_1[1:2] are processed and other input ports are ignored. Similarly
for the pre-programmed mono PRB modes only miniDSP_D_DataInput[1] is processed. The input port
miniDSP_D_DataInput_2 features
2
channels called miniDSP_D_DataInput_2[1:2] also referred to as
110
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miniDSP_D_DataInput_2[L1,R1]. The input port miniDSP_D_DataInput_3 also features 2 channels of audio data
called miniDSP_D_DataInput_3[1:2] also referred to as miniDSP_D_DataInput_3[L1,R1]. Signal routing to
miniDSP_D_DataInput_1[1:8] is controlled by programming B0_P4_R118_D[5:4]. Signal routing to
miniDSP_D_DataInput_2[1,2] is controlled by programming B0_P4_R118_D[3:2]. Signal routing to
miniDSP_D_DataInput_3[1,2] is controlled by programming B0_P4_R118_D[1:0].
The audio serial port ASI1, can take in 8 channels of audio data. By default the miniDSP_A_DataOutput[1:8] is
routed to ASI1_DataOutput. By programming B0_P4_R7_D[2:0], the default programming can be changed to
one of ASI1_DataInput[1:8], ASI2_DataInput[1:2] or ASI3_DataInput[1:2] to acheive ASI to ASI loopback.
Similarly the serial output of ASI1 is routed to ASI1_DOUT by default but by programming B0_P4_R15_D[1:0],
this can be changed to route ASI1_DIN, ASI2_DIN or ASI3_DIN to achieve terminal-to-terminal loopback
between ASIs. The ASI1's parallel output ASI1_DataInput can be routed to any of the miniDSP_D input ports.
The audio serial port ASI2 and ASI3, can take in 2 channels of audio data each. By default the inputs to
ASI2_DataOutput[1:2] and ASI3_DataOutput[1:2] are disabled. By programming B0_P4_R23_D[2:0], one of
miniDSP_A_DataOutput[1:2], miniDSP_A_DataOutput[3:4], ASI1_DataInput[1:2], ASI2_DataInput[1:2] or
ASI3_DataInput[1:2] can be routed to ASI2_DataOutput[1:2]. Similarly by programming B0_P4_R39_D[2:0], one
of miniDSP_A_DataOutput[1:2], miniDSP_A_DataOutput[5:6], ASI1_DataInput[1:2], ASI2_DataInput[1:2] or
ASI3_DataInput[1:2] can be routed to ASI3_DataOutput[1:2]. The ASI2_DataInput and ASI3_DataInput can be
routed to any of the miniDSP_D input ports.
The serial output ASI2_DOUT can be configured to route serial output of ASI2 or loop back ASI1_DIN, ASI2_DIN
or ASI3_DIN. This feature is controlled by configuring B0_P4_R31_D[1:0]. The serial output of ASI3_DOUT can
be configured to route serial output of ASI3 or loop back ASI1_DIN, ASI2_DIN or ASI3_DIN. This feature is
controlled by configuring B0_P4_R47_D[1:0].
The signal routing between ASIs and miniDSPs is shown in Figure 108.
B0_P4_R7_D[2:0]
‘Z’
B0_P4_R15_D[1:0]
000
miniDSP_A_DataOutput[1:8]
ASI1_DataInput[1:8]
DOUT
miniDSP_A_DataOutput[1:8]
001
00
ASI1_DOUT
ASI2_DOUT
ASI3_DOUT
ASI1_DIN
ASI1_DataOutput[1:8]
01
010
011
100
ASI2_DIN
ASI2_DataInput[1:2]
10
ASI3_DIN
ASI3_DataInput[1:2]
ASI1
11
miniDSP_A/PRB_R<>
ASI1_DataInput[1:8]
AS1_DataInput[1:8]
DIN
ASI1_DIN
B0_P4_R23_D[2:0]
‘Z’
B0_P4_R31_D[1:0]
000
miniDSP_A_DataOutput[1:2]
DOUT
00
001
ASI1_DIN
ASI1_DataInput[1:2]
ASI2_DataInput[1:2]
ASI2_DataOutput[1:2]
01
010
011
100
101
ASI2_DIN
10
ASI3_DIN
ASI3_DataInput[1:2]
ASI2
11
miniDSP_A_DataOutput[3:4]
B0_P4_R118_D[5:4]
00
ASI2_DataInput[1:2]
ASI2_DataInput[1:2]
miniDSP_D_DataInput_1[1:8]
DIN
ASI2_DIN
01
10
B0_P4_R39_D[2:0]
‘Z’
11
B0_P4_R47_D[1:0]
B0_P4_R118_D[3:2]
000
miniDSP_D/PRB_P<>
miniDSP_A_DataOutput[1:2]
DOUT
001
00
00
ASI1_DIN
ASI1_DataInput[1:2]
ASI2_DataInput[1:2]
ASI3_DataOutput[1:2]
miniDSP_D_DataInput_2[1:2]
01
01
010
011
100
110
ASI2_DIN
10
10
ASI3_DIN
ASI3_DataInput[1:2]
ASI3
B0_P4_R118_D[1:0]
11
miniDSP_A_DataOutput[5:6]
00
01
10
miniDSP_D_DataInput_3[1:2]
ASI2_DataInpput[1:2]
ASI3_DataInput[1:2]
DIN
ASI3_DIN
Figure 108. Audio Routing Between ASI ports,÷ miniDSP
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8.3.11 Device Connections
8.3.11.1 Digital Terminals
Only a small number of digital terminals are dedicated to a single function; whenever possible, the digital
terminals have a default function, and also can be reprogrammed to cover alternative functions for various
applications.
The fixed-function terminals are hardware-control terminals RESET and SPI_SELECT terminal. Depending on
the state of SPI_SELECT, four terminals SCL_SSZ, SDA_MOSI, MISO_GPO1, and I2C_ADDR_SCLK are
configured for either I2C or SPI protocol. Only in I2C mode, I2C_ADDR_SCLK provide two possible I2C
addresses for the TLV320AIC3268, while this terminal receives the SPI SCLK when the device is set to SPI
mode.
Other digital IO terminals can be configured for various functions via register control.
8.3.11.2 Analog Terminals
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
The possible analog routings of analog input terminals to ADCs and output amplifiers as well as the routing from
DACs to output amplifiers can be seen in the Analog Routing Diagram.
8.3.11.3 Multifunction Terminals
Table 46 and Table 47 show the possible allocation of terminals for specific functions. The PLL input, for
example, can be programmed to be any of 7 terminals (MCLK, BCLK1, DIN1, BCLK2,GPIO1, GPIO2, GPIO3).
Table 46. Multifunction Terminal Assignments for Terminals SDA_MOSI, SCL_SSZ,
I2C_ADDR_SCLK,MISO_GPO1,MCLK, WCLK1, BCLK1, DIN1, and DOUT1
I2C_
SDA_
MOSI
(1)
SCL_
SSZ
(2)
MISO_
GPO1
(4)
ADDR_
SCLK
(3)
MCLK
(5)
WCLK1
(6)
BCLK1
(7)
DIN1
(8)
DOUT1
(9)
Terminal Function
A
B
C
D
E
F
I2C Clock
E(1)
I2C Data
E(1)
I2C Address (LSB)
SPI Chip Select
SPI Clock
E(1)
E(1)
E(1)
SPI Slave Data Input
SPI Slave Data Output
E(1)
G
E(1), D(2)
Word Clock
Input,Output for ASI1
H
I
S(3),D(2)
Word Clock Input,
Output for ASI2
Word Clock Input,
Output for ASI3
J
Bit Clock Input, Output
for ASI1
K
L
S(3),D(2)
Bit Clock Input, Output
for ASI2
Bit Clock Input, Output
for ASI3
M
N
DOUT for ASI1 All
Channels
E(1),D(2)
E(1),D(2)
O
P
Q
R
S
T
DOUT for ASI1 (L1, R1)
DOUT for ASI1 (L2, R2)
DOUT for ASI1 (L3, R3)
DOUT for ASI1 (L4, R4)
DOUT for ASI2
E(1)
E(1)
E(1)
E(1)
DOUT for ASI3
DIN for ASI1 All
Channels
U
V
E(1),D(2)
E(1),D(2)
DIN for ASI1 (L1, R1)
112
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Table 46. Multifunction Terminal Assignments for Terminals SDA_MOSI, SCL_SSZ,
I2C_ADDR_SCLK,MISO_GPO1,MCLK, WCLK1, BCLK1, DIN1, and DOUT1 (continued)
I2C_
SDA_
MOSI
(1)
SCL_
SSZ
(2)
MISO_
GPO1
(4)
ADDR_
SCLK
(3)
MCLK
(5)
WCLK1
(6)
BCLK1
(7)
DIN1
(8)
DOUT1
(9)
Terminal Function
W
X
DIN for ASI1 (L2, R2)
DIN for ASI1 (L3, R3)
DIN for ASI1 (L4, R4)
DIN for ASI2
Y
Z
AA
DIN for ASI3
ASI1 ADC BCLK Input,
Output
AB
AC
AD
AE
AF
ASI2 ADC BCLK Input,
Output
ASI1 ADC WCLK Input,
Output
ASI2 ADC WCLK Input,
Output
ADC_MOD_CLK
Output
E(1)
AG
AH
AI
Digmic Data 1
E(1)
E(1)
S(3)
Digmic Data 2
Input to PLL_CLKIN
Input to ADC_CLKIN
Input to DAC_CLKIN
Input to CDIV_CLKIN
Input to LFR_CLKIN
Input to HF_CLKIN
S(3),D(2)
S(3),D(2)
S(3),D(2)
S(3),D(2)
S(3),D(2)
S(3)
S(3)
S(3)
S(3)
S(3)
AJ
AK
AL
AM
AN
S(3)
S(3)
Input to
REF_1MHz_CLK
(3)
AO
S
AP
AQ
AR
AS
AT
AU
AV
CLKOUT Output
Bit Bang Input
E(1)
E(1)
E(1)
Bit Bang Output
INT1 Output
E(1)
E(1)
E(1)
E(1)
INT2 Output
Interrupt for miniDSP
SAR ADC Interrupt
E(1)
E(1)
E(1)
E(1)
General Purpose
Output
AW
AX
General Purpose Input
E(1)
(1) E: The terminal is exclusively used for this function, no other function can be implemented with the same terminal (such as if DOUT1
has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)
(2) D: The terminal is the default selection for the function
(3) S: This terminal can be simultaneously used with other functions marked S for the same terminal. (such as MCLK terminal could be
chosen to drive the PLL, ADC Clock, DAC Clock, CDIV Clock, LFR Clock, HF Clock, and REF_1MHz_CLK inputs simultaneously)
(4) MISO_GPO1 can only be utilized for functions defined in this table when part utilizes I2C for control. In SPI mode, this terminal serves
as MISO.
Table 47. Multifunction Terminal Assignments for Terminals WCLK2, BCLK2, DIN2, DOUT2, GPIO1,
GPIO2, GPIO3, GPIO4 and GPIO5
WCLK2
(10)
BCLK2
(11)
DIN2
(12)
DOUT2
(13)
GPIO1
(14)
GPIO2
(15)
GPIO3
(16)
GPIO4
(17)
GPIO5
(18)
Terminal Function
A
B
C
D
E
F
I2C Clock
I2C Data
I2C Address (LSB)
SPI Chip Select
SPI Clock
SPI Slave Data Input
SPI Slave Data Output
G
Word Clock Input,
Output for ASI1
H
S(3)
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Table 47. Multifunction Terminal Assignments for Terminals WCLK2, BCLK2, DIN2, DOUT2, GPIO1,
GPIO2, GPIO3, GPIO4 and GPIO5 (continued)
WCLK2
(10)
BCLK2
(11)
DIN2
(12)
DOUT2
(13)
GPIO1
(14)
GPIO2
(15)
GPIO3
(16)
GPIO4
(17)
GPIO5
(18)
Terminal Function
Word Clock Input,
Output for ASI2
I
S(3),D(2)
S(3)
Word Clock Input,
Output for ASI3
J
S(3)
S(3)
S(3)
Bit Clock Input, Output
for ASI1
K
L
Bit Clock Input, Output
for ASI2
S(3),D(2)
Bit Clock Input, Output
for ASI3
M
N
S(3)
DOUT for ASI1 All
Channels
E(1)
O
P
Q
R
S
T
DOUT for ASI1 (L1, R1)
DOUT for ASI1 (L2, R2)
DOUT for ASI1 (L3, R3)
DOUT for ASI1 (L4, R4)
DOUT for ASI2
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1),D(2)
E(1)
DOUT for ASI3
E(1)
DIN for ASI1 All
Channels
U
V
W
X
DIN for ASI1 (L1, R1)
DIN for ASI1 (L2, R2)
DIN for ASI1 (L3, R3)
DIN for ASI1 (L4, R4)
DIN for ASI2
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
Y
E(1)
Z
E(1),D(2)
AA
DIN for ASI3
E(1)
E(1)
ADC BCLK1 Input,
Output
AB
AC
AD
AE
AF
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
ADC BCLK2 Input,
Output
E(1)
E(1)
E(1)
E(1)
ADC WCLK1 Input,
Output
ADC WCLK2 Input,
Output
ADC_MOD_CLK
Output
E(1)
E(1)
E(1)
E(1)
AG
AH
AI
Digmic Data 1
E(1)
E(1)
E(1)
E(1)
S(3)
S(3)
S(3)
E(1)
E(1)
S(3)
S(3)
S(3)
E(1)
E(1)
S(3)
S(3)
S(3)
S(3)
S(3)
E(1)
E(1)
E(1)
E(1)
Digmic Data 2
Input to PLL_CLKIN
Input to ADC_CLKIN
Input to DAC_CLKIN
Input to CDIV_CLKIN
Input to LFR_CLKIN
Input to HF_CLKIN
S(3)
S(3)
S(3)
S(3)
S(3)
AJ
AK
AL
AM
AN
S(3)
E(1)
S(3)
S(3)
Input to
REF_1MHz_CLK
AO
AP
AQ
AR
AS
AT
AU
AV
CLKOUT Output
Bit Bang Input
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
Bit Bang Output
INT1 Output
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
INT2 Output
Interrupt for miniDSP
SAR ADC Interrupt
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
E(1)
General Purpose
Output
AW
AX
E(1)
E(1)
E(1)
E(1)
General Purpose Input
E(1)
E(1)
E(1)
114
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
(1) E: The terminal is exclusively used for this function, no other function can be implemented with the same terminal (such as if DOUT1
has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)
(2) D: The terminal is the default selection for the function
(3) S: This terminal can be simultaneously used with other functions marked S for the same terminal. (such as MCLK terminal could be
chosen to drive the PLL, ADC Clock, DAC Clock, CDIV Clock, LFR Clock, HF Clock, and REF_1MHz_CLK inputs simultaneously)
See Register Settings for Multifunction Terminals for details on register configuration of multi-function terminals.
8.3.11.3.1 Register Settings for Multifunction Terminals
Table 48 summarizes the register settings that must be applied to configure the terminal assignments for general
inputs and outputs, interrupts, clocking outputs, and digital microphones. In Table 48, the letter/number
combination represents the row and the column number from and in bold type.
Please be aware that more settings may be necessary to obtain a full functionality matching the application
requirement.
Table 48. Multifunction Terminal Register Configuration - General Inputs/Outputs, Interrupts
Description
Required Register Setting
Description
Required Register Setting
Bit Bang input for miniDSP on
GPIO1
B0_P4_R86_D[6:2]=00001;
Value stored to B0_P4_R107_D[0]
B0_P4_R87_D[6:2]=00001;
Value stored to B0_P4_R107_D[1]
AQ14
AQ16
AQ15
AQ17
Bit Bang input for miniDSP on GPIO2
Bit Bang input for miniDSP on
GPIO3
B0_P4_R88_D[6:2]=00001;
Value stored to B0_P4_R107_D[2]
B0_P4_R89_D[6:2]=00001;
Value stored to B0_P4_R107_D[3]
Bit Bang input for miniDSP on GPIO4
B0_P4_R86_D[6:2]=01011;
B0_P4_R113_D[6]=0;
Value written in B0_P4_R104_D[0]
Host controlled Bit Bang output from
miniDSP on GPIO1
miniDSP_D controlled Bit Bang output
from miniDSP on GPIO1
B0_P4_R86_D[6:2]=01011;
B0_P4_R113_D[6]=1;
AR14
AR15
AR16
AR17
AR14
AR15
AR16
AR17
B0_P4_R87_D[6:2]=01011;
B0_P4_R113_D[6]=0;
Value written in B0_P4_R104_D[1]
Host controlled Bit Bang output from
miniDSP on GPIO2
miniDSP_D controlled Bit Bang output
from miniDSP on GPIO2
B0_P4_R87_D[6:2]=01011;
B0_P4_R113_D[6]=1;
B0_P4_R88_D[6:2]=01011;
B0_P4_R113_D[6]=0;
Value written in B0_P4_R104_D[2]
Host controlled Bit Bang output from
miniDSP on GPIO3
miniDSP_D controlled Bit Bang output
from miniDSP on GPIO3
B0_P4_R88_D[6:2]=01011;
B0_P4_R113_D[6]=1;
B0_P4_R89_D[6:2]=01011;
B0_P4_R113_D[6]=0;
Value written in B0_P4_R104_D[3]
Host controlled Bit Bang output from
miniDSP on GPIO4
miniDSP_D controlled Bit Bang output
from miniDSP on GPIO4
B0_P4_R89_D[6:2]=01011;
B0_P4_R113_D[6]=1;
INT1 interrupt output on
MISO_GPO1
B0_P4_R96_D[4:1]=0100;
Configure B0_P0_R51_D[7:6]
B0_P4_R67_D[4:1]=0100;
Configure B0_P0_R51_D[7:6]
AS4
AS9
INT1 interrupt output on DOUT1
INT1 interrupt output on BCLK2
INT1 interrupt output on GPIO1
INT1 interrupt output on GPIO3
INT2 interrupt output on MISO_GPO1
INT2 interrupt output on WCLK2
INT2 interrupt output on DOUT2
INT2 interrupt output on GPIO2
INT2 interrupt output on GPIO4
B0_P4_R69_D[5:2]=0101;
Configure B0_P0_R51_D[7:6]
B0_P4_R70_D[5:2]=0101;
Configure B0_P0_R51_D[7:6]
AS9
INT1 interrupt output on WCLK2
INT1 interrupt output on DOUT2
INT1 interrupt output on GPIO2
INT1 interrupt output on GPIO4
INT2 interrupt output on DOUT1
INT2 interrupt output on BCLK2
INT2 interrupt output on GPIO1
INT2 interrupt output on GPIO3
AS11
AS14
AS16
AT4
B0_P4_R71_D[4:1]=0100;
Configure B0_P0_R51_D[7:6]
B0_P4_R86_D[6:2]=00101;
Configure B0_P0_R51_D[7:6]
AS13
AS15
AS17
AT9
B0_P4_R87_D[6:2]=00101;
Configure B0_P0_R51_D[7:6]
B0_P4_R88_D[6:2]=00101;
Configure B0_P0_R51_D[7:6]
B0_P4_R89_D[6:2]=00101;
Configure B0_P0_R51_D[7:6]
B0_P4_R96_D[4:1]=0101;
Configure B0_P0_R51_D[5:4]
B0_P4_R67_D[4:1]=0101;
Configure B0_P0_R51_D[5:4]
B0_P4_R69_D[5:2]=0110;
Configure B0_P0_R51_D[5:4]
AT9
B0_P4_R70_D[5:2]=0110;
Configure B0_P0_R51_D[5:4]
B0_P4_R71_D[4:1]=0101;
Configure B0_P0_R51_D[5:4]
AT11
AT14
AT16
AT13
AT15
AT17
B0_P4_R86_D[6:2]=00110;
Configure B0_P0_R51_D[5:4]
B0_P4_R87_D[6:2]=00110;
Configure B0_P0_R51_D[5:4]
B0_P4_R88_D[6:2]=00110;
Configure B0_P0_R51_D[5:4]
B0_P4_R89_D[6:2]=00110;
Configure B0_P0_R51_D[5:4]
B0_P4_R72_D[6:5]=01;
B0_P4_R72_D[6:5]=01;
AU12
AU14
AU15
ISR interrupt for miniDSP_A on DIN2 B100_P0_R58_D[2:0]=100;
Configure B100_P0_R58_D[4]
AU12
AU14
AU15
ISR interrupt for miniDSP_D on DIN2
B120_P0_R58_D[2:0]=100;
Configure B120_P0_R58_D[4]
B0_P4_R86_D[6:2]=00001;
ISR interrupt for miniDSP_A on
B100_P0_R58_D[2:0]=001;
B0_P4_R86_D[6:2]=00001;
ISR interrupt for miniDSP_D on GPIO1 B120_P0_R58_D[2:0]=001;
Configure B120_P0_R58_D[4]
GPIO1
Configure B100_P0_R58_D[4]
B0_P4_R87_D[6:2]=00001;
ISR interrupt for miniDSP_A on
B100_P0_R58_D[2:0]=010;
B0_P4_R72_D[6:2]=00001;
ISR interrupt for miniDSP_D on GPIO2 B120_P0_R58_D[2:0]=010;
Configure B120_P0_R58_D[4]
GPIO2
Configure B100_P0_R58_D[4]
B0_P4_R96_D[4:1]=0110;
SAR ADC Interrupt on MISO_GPO1
B0_P4_R67_D[4:1]=0110;
SAR ADC Interrupt on DOUT1
AV4
AV9
Configure B0_P3_R3_D[1:0]
Configure B0_P3_R3_D[1:0]
B0_P4_R69_D[5:2]=1001;
SAR ADC Interrupt on WCLK2
B0_P4_R70_D[5:2]=1001;
SAR ADC Interrupt on BCLK2
AV10
AV13
AV15
AV11
AV14
AW4
Configure B0_P3_R3_D[1:0]
Configure B0_P3_R3_D[1:0]
B0_P4_R71_D[4:1]=0110;
SAR ADC Interrupt on DOUT2
B0_P4_R86_D[6:2]=01001;
SAR ADC Interrupt on GPIO1
Configure B0_P3_R3_D[1:0]
Configure B0_P3_R3_D[1:0]
B0_P4_R87_D[6:2]=01001;
SAR ADC Interrupt on GPIO2
General Purpose Output on
MISO_GPO1
B0_P4_R96_D[4:1]=0010;
Output value write to B0_P4_R96_D[0]
Configure B0_P3_R3_D[1:0]
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Table 48. Multifunction Terminal Register Configuration - General Inputs/Outputs, Interrupts (continued)
Description
Required Register Setting
Description
Required Register Setting
B0_P4_R67_D[4:1]=0010;
Output value write to B0_P4_R67_D[0]
B0_P4_R69_D[5:2]=0011;
Output value write to B0_P4_R69_D[0]
AW9
General Purpose Output on DOUT1
AW10
AW13
AW15
General Purpose Output on WCLK2
B0_P4_R70_D[5:2]=0011;
Output value write to B0_P4_R70_D[0]
B0_P4_R71_D[4:1]=0010;
Output value write to B0_P4_R71_D[0]
AW11
AW14
General Purpose Output on BCLK2
General Purpose Output on GPIO1
General Purpose Output on DOUT2
General Purpose Output on GPIO2
B0_P4_R86_D[6:2]=00011;
Output value write to B0_P4_R86_D[0]
B0_P4_R87_D[6:2]=00011;
Output value write to B0_P4_R87_D[0]
B0_P4_R69_D[5:2]=0010;
Input value available in
B0_P4_R69_D[1]
B0_P4_R68_D[6:5]=10;
Input value available in B0_P4_R68_D[4]
AX9
General Purpose Input on DIN1
General Purpose Input on BCLK2
General Purpose Input on GPIO1
AX10
AX13
AX15
General Purpose Input on WCLK2
General Purpose Input on DIN2
General Purpose Input on GPIO2
B0_P4_R72_D[6:5]=10;
Input value available in
B0_P4_R72_D[4]
B0_P4_R70_D[5:2]=0010;
Input value available in B0_P4_R70_D[1]
AX11
AX14
B0_P4_R87_D[6:2]=00010;
Input value available in
B0_P4_R87_D[1]
B0_P4_R86_D[6:2]=00010;
Input value available in B0_P4_R86_D[1]
Table 49 summarizes the register settings that must be applied to configure the terminal assignments for
clocking inputs and outputs from the device. In Table 49, the letter/number combination represents the row and
the column number from and in bold type.
Please be aware that more settings may be necessary to obtain a full functionality matching the application
requirement.
Table 49. Multifunction Terminal Register Configuration - Clocking Inputs/Outputs
Description
Required Register Setting
Description
Required Register Setting
AI5
AI8
PLL_CLKIN input on MCLK
B0_P0_R5_D[5:2]=0000;
AI7
PLL_CLKIN input on BCLK1
B0_P0_R5_D[5:2]=0001;
B0_P0_R5_D[5:2]=0011;
B0_P4_R68_D[6:5]=01;
B0_P0_R5_D[5:2]=0100;
B0_P4_R70_D[5:2]=0010;
PLL_CLKIN input on DIN1
PLL_CLKIN input on GPIO1
PLL_CLKIN input on GPIO3
ADC_CLKIN input on BCLK1
ADC_CLKIN input on GPIO1
ADC_CLKIN input on GPIO3
DAC_CLKIN input on BCLK1
DAC_CLKIN input on GPIO1
DAC_CLKIN input on GPIO3
CDIV_CLKIN input on BCLK1
AI11
PLL_CLKIN input on BCLK2
PLL_CLKIN input on GPIO2
ADC_CLKIN input on MCLK
ADC_CLKIN input on BCLK2
ADC_CLKIN input on GPIO2
DAC_CLKIN input on MCLK
DAC_CLKIN input on BCLK2
DAC_CLKIN input on GPIO2
CDIV_CLKIN input on MCLK
CDIV_CLKIN input on DIN1
B0_P0_R5_D[5:2]=0010;
B0_P4_R86_D[6:2]=00001;
B0_P0_R5_D[5:2]=0111;
B0_P4_R87_D[6:2]=00001;
AI14
AI16
AJ7
AI15
AJ5
B0_P0_R5_D[5:2]=0101;
B0_P4_R88_D[6:2]=00001;
B0_P0_R4_D[3:0]=0000;
B0_P0_R4_D[3:0]=0100;
B0_P4_R70_D[5:2]=0010;
B0_P0_R4_D[3:0]=0001;
AJ11
AJ15
AK5
AK11
AK15
AL5
B0_P0_R4_D[3:0]=0010;
B0_P4_R86_D[6:2]=00001;
B0_P0_R4_D[3:0]=1001;
B0_P4_R87_D[6:2]=00001;
AJ14
AJ16
AK7
B0_P0_R4_D[3:0]=0101;
B0_P4_R88_D[6:2]=00001;
B0_P0_R4_D[7:4]=0000;
B0_P0_R4_D[7:4]=0100;
B0_P4_R70_D[5:2]=0010;
B0_P0_R4_D[7:4]=0001;
B0_P0_R4_D[7:4]=0010;
B0_P4_R86_D[6:2]=00001;
B0_P0_R4_D[7:4]=1001;
B0_P4_R87_D[6:2]=00001;
AK14
AK16
AL7
B0_P0_R4_D[7:4]=0101;
B0_P4_R88_D[6:2]=00001;
B0_P0_R21_D[4:0]=0000;
B0_P0_R21_D[4:0]=0010;
B0_P4_R68_D[6:5]=01;
B0_P0_R21_D[4:0]=0001;
AL8
B0_P0_R21_D[4:0]=1000;
B0_P4_R70_D[5:2]=0010;
B0_P0_R21_D[4:0]=1001;
B0_P4_R88_D[6:2]=00001;
AL11
AM5
CDIV_CLKIN input on BCLK2
LFR_CLKIN input on MCLK
LFR_CLKIN input on WCLK2
AL16
AM6
CDIV_CLKIN input on GPIO3
LFR_CLKIN input on WCLK1
LFR_CLKIN input on BCLK2
B0_P0_R24_D[7:4]=0000;
B0_P0_R24_D[7:4]=0001;
B0_P0_R24_D[7:4]=0011;
B0_P4_R69_D[5:2]=0010;
B0_P0_R24_D[7:4]=0100;
B0_P4_R70_D[5:2]=0010;
AM10
AM11
B0_P0_R24_D[7:4]=0110;
B0_P4_R72_D[6:5]=01;
B0_P0_R24_D[7:4]=0010;
B0_P4_R86_D[6:2]=00001;
AM12
LFR_CLKIN input on DIN2
AM14
LFR_CLKIN input on GPIO1
B0_P0_R24_D[7:4]=1000;
B0_P4_R87_D[6:2]=00001;
B0_P0_R24_D[7:4]=0101;
B0_P4_R88_D[6:2]=00001;
AM15
AN5
LFR_CLKIN input on GPIO2
HF_CLK input on MCLK
AM16
AO5
LFR_CLKIN input on GPIO3
B0_P0_R24_D[3:0]=0000;
REF_1MHz_CLK input on MCLK
B0_P0_R23_D[7]=1;
B0_P4_R96_D[4:1]=0011;
Configure B0_P0_R21_D[4:0] and
B0_P0_R22_D[7:0]
B0_P4_R65_D[5:2]=0100;
Configure B0_P0_R21_D[4:0] and
B0_P0_R22_D[7:0]
AP4
CLKOUT output on MISO
CLKOUT output on DOUT1
CLKOUT output on BCLK2
CLKOUT output on GPIO2
AP6
CLKOUT output on WCLK1
CLKOUT output on WCLK2
CLKOUT output on GPIO1
B0_P4_R67_D[4:1]=0011;
Configure B0_P0_R21_D[4:0] and
B0_P0_R22_D[7:0]
B0_P4_R69_D[5:2]=0100;
Configure B0_P0_R21_D[4:0] and
B0_P0_R22_D[7:0]
AP9
AP10
AP14
B0_P4_R70_D[5:2]=0100;
Configure B0_P0_R21_D[4:0] and
B0_P0_R22_D[7:0]
B0_P4_R86_D[6:2]=00100;
Configure B0_P0_R21_D[4:0] and
B0_P0_R22_D[7:0]
AP11
AP15
B0_P4_R87_D[6:2]=00100;
Configure B0_P0_R21_D[4:0] and
B0_P0_R22_D[7:0]
116
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TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Table 50 summarizes the register settings that must be applied to configure the terminal assignments for digital
microphone feature in the device. In Table 50, the letter/number combination represents the row and the column
number from and in bold type.
Please be aware that more settings may be necessary to obtain a full functionality matching the application
requirement.
Table 50. Multifunction Terminal Register Configuration - Digital Microphone
Description
Required Register Setting
Description
Required Register Setting
ADC_MOD_CLK (DigMic clock) on
MISO_GPO1
ADC_MOD_CLK (DigMic clock) on
WCLK2
AF4
B0_P4_R96_D[4:1]=0111;
AF10
AF13
AF15
AF17
B0_P4_R69_D[5:2]=1010;
ADC_MOD_CLK (DigMic clock) on
BCLK2
ADC_MOD_CLK (DigMic clock) on
DOUT2
AF11
AF14
AF16
AF18
B0_P4_R70_D[5:2]=1010;
B0_P4_R86_D[6:2]=01010;
B0_P4_R88_D[6:2]=01010;
B0_P4_R90_D[6:2]=01010;
B0_P4_R71_D[4:1]=1010;
B0_P4_R87_D[6:2]=01010;
B0_P4_R89_D[6:2]=01010;
ADC_MOD_CLK (DigMic clock) on
GPIO1
ADC_MOD_CLK (DigMic clock) on
GPIO2
ADC_MOD_CLK (DigMic clock) on
GPIO3
ADC_MOD_CLK (DigMic clock) on
GPIO4
ADC_MOD_CLK (DigMic clock) on
GPIO5
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[7:4]=1000;
B0_P4_R68_D[6:5] = 01;
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[7:4]=1000;
B0_P4_R68_D[6:5] = 01;
Digital Mic 1 Left channel data on
DIN1 latched on rising edge of
DigMic clock
Digital Mic 1 Left channel data on
DIN1 latched on falling edge of DigMic
clock
AG8
AG8
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[3:0]=1000;
B0_P4_R68_D[6:5] = 01;
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[3:0]=1000;
B0_P4_R68_D[6:5] = 01;
Digital Mic 1 Right channel data on
DIN1 latched on rising edge of
DigMic clock
Digital Mic 1 Right channel data on
DIN1 latched on falling edge of DigMic
clock
AG8
AG8
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[7:4]=1001;
B0_P4_R72_D[6:5] = 01;
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[7:4]=1001;
B0_P4_R72_D[6:5] = 01;
Digital Mic 1 Left channel data on
DIN2 latched on rising edge of
DigMic clock
Digital Mic 1 Left channel data on
DIN2 latched on falling edge of DigMic
clock
AG12
AG12
AG14
AG14
AG15
AG15
AG16
AG16
AG17
AG17
AG18
AG18
AG12
AG12
AG14
AG14
AG15
AG15
AG16
AG16
AG17
AG17
AG18
AG18
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[3:0]=1001;
B0_P4_R72_D[6:5] = 01;
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[3:0]=1001;
B0_P4_R72_D[6:5] = 01;
Digital Mic 1 Right channel data on
DIN2 latched on rising edge of
DigMic clock
Digital Mic 1 Right channel data on
DIN2 latched on falling edge of DigMic
clock
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[7:4]=0000;
B0_P4_R86_D[6:2] = 00001;
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[7:4]=0000;
B0_P4_R86_D[6:2] = 00001;
Digital Mic 1 Left channel data on
GPIO1 latched on rising edge of
DigMic clock
Digital Mic 1 Left channel data on
GPIO1 latched on falling edge of
DigMic clock
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[3:0]=0000;
B0_P4_R86_D[6:2] = 00001;
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[3:0]=0000;
B0_P4_R86_D[6:2] = 00001;
Digital Mic 1 Right channel data on
GPIO1 latched on rising edge of
DigMic clock
Digital Mic 1 Right channel data on
GPIO1 latched on falling edge of
DigMic clock
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[7:4]=0001;
B0_P4_R87_D[6:2] = 00001;
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[7:4]=0001;
B0_P4_R87_D[6:2] = 00001;
Digital Mic 1 Left channel data on
GPIO2 latched on rising edge of
DigMic clock
Digital Mic 1 Left channel data on
GPIO2 latched on falling edge of
DigMic clock
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[3:0]=0001;
B0_P4_R87_D[6:2] = 00001;
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[3:0]=0001;
B0_P4_R87_D[6:2] = 00001;
Digital Mic 1 Right channel data on
GPIO2 latched on rising edge of
DigMic clock
Digital Mic 1 Right channel data on
GPIO2 latched on falling edge of
DigMic clock
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[7:4]=0010;
B0_P4_R88_D[6:2] = 00001;
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[7:4]=0010;
B0_P4_R88_D[6:2] = 00001;
Digital Mic 1 Left channel data on
GPIO3 latched on rising edge of
DigMic clock
Digital Mic 1 Left channel data on
GPIO3 latched on falling edge of
DigMic clock
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[3:0]=0010;
B0_P4_R88_D[6:2] = 00001;
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[3:0]=0010;
B0_P4_R88_D[6:2] = 00001;
Digital Mic 1 Right channel data on
GPIO3 latched on rising edge of
DigMic clock
Digital Mic 1 Right channel data on
GPIO3 latched on falling edge of
DigMic clock
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[7:4]=0011;
B0_P4_R89_D[6:2] = 00001;
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[7:4]=0011;
B0_P4_R89_D[6:2] = 00001;
Digital Mic 1 Left channel data on
GPIO4 latched on rising edge of
DigMic clock
Digital Mic 1 Left channel data on
GPIO4 latched on falling edge of
DigMic clock
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[3:0]=0011;
B0_P4_R89_D[6:2] = 00001;
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[3:0]=0011;
B0_P4_R89_D[6:2] = 00001;
Digital Mic 1 Right channel data on
GPIO4 latched on rising edge of
DigMic clock
Digital Mic 1 Right channel data on
GPIO4 latched on falling edge of
DigMic clock
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[7:4]=0100;
B0_P4_R90_D[6:2] = 00001;
B0_P0_R81_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[7:4]=0100;
B0_P4_R90_D[6:2] = 00001;
Digital Mic 1 Left channel data on
GPIO5 latched on rising edge of
DigMic clock
Digital Mic 1 Left channel data on
GPIO5 latched on falling edge of
DigMic clock
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R101_D[3:0]=0100;
B0_P4_R90_D[6:2] = 00001;
B0_P0_R81_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R101_D[3:0]=0100;
B0_P4_R90_D[6:2] = 00001;
Digital Mic 1 Right channel data on
GPIO5 latched on rising edge of
DigMic clock
Digital Mic 1 Right channel data on
GPIO5 latched on falling edge of
DigMic clock
Copyright © 2014, Texas Instruments Incorporated
117
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Table 50. Multifunction Terminal Register Configuration - Digital Microphone (continued)
Description
Required Register Setting
Description
Required Register Setting
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[7:4]=1000;
B0_P4_R68_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
DIN1 latched on falling edge of DigMic B0_P4_R102_D[7:4]=1000;
Digital Mic 2 Left channel data on
DIN1 latched on rising edge of
DigMic clock
Digital Mic 2 Left channel data on
AH8
AH8
clock
B0_P4_R68_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[3:0]=1000;
B0_P4_R68_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
DIN1 latched on falling edge of DigMic B0_P4_R102_D[3:0]=1000;
Digital Mic 2 Right channel data on
DIN1 latched on rising edge of
DigMic clock
Digital Mic 2 Right channel data on
AH8
AH8
clock
B0_P4_R68_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[7:4]=1001;
B0_P4_R72_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
DIN2 latched on falling edge of DigMic B0_P4_R102_D[7:4]=1001;
Digital Mic 2 Left channel data on
DIN2 latched on rising edge of
DigMic clock
Digital Mic 2 Left channel data on
AH12
AH12
AH14
AH14
AH15
AH15
AH16
AH16
AH17
AH17
AH18
AH18
AH12
AH12
AH14
AH14
AH15
AH15
AH16
AH16
AH17
AH17
AH18
AH18
clock
B0_P4_R72_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[3:0]=1001;
B0_P4_R72_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
DIN2 latched on falling edge of DigMic B0_P4_R102_D[3:0]=1001;
Digital Mic 2 Right channel data on
DIN2 latched on rising edge of
DigMic clock
Digital Mic 2 Right channel data on
clock
B0_P4_R72_D[6:5] = 01;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[7:4]=0000;
B0_P4_R86_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[7:4]=0000;
B0_P4_R86_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Left channel data on
GPIO1 latched on rising edge of
DigMic clock
Digital Mic 2 Left channel data on
GPIO1 latched on falling edge of
DigMic clock
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[3:0]=0000;
B0_P4_R86_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[3:0]=0000;
B0_P4_R86_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Right channel data on
GPIO1 latched on rising edge of
DigMic clock
Digital Mic 2 Right channel data on
GPIO1 latched on falling edge of
DigMic clock
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[7:4]=0001;
B0_P4_R87_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[7:4]=0001;
B0_P4_R87_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Left channel data on
GPIO2 latched on rising edge of
DigMic clock
Digital Mic 2 Left channel data on
GPIO2 latched on falling edge of
DigMic clock
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[3:0]=0001;
B0_P4_R87_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[3:0]=0001;
B0_P4_R87_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Right channel data on
GPIO2 latched on rising edge of
DigMic clock
Digital Mic 2 Right channel data on
GPIO2 latched on falling edge of
DigMic clock
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[7:4]=0010;
B0_P4_R88_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[7:4]=0010;
B0_P4_R88_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Left channel data on
GPIO3 latched on rising edge of
DigMic clock
Digital Mic 2 Left channel data on
GPIO3 latched on falling edge of
DigMic clock
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[3:0]=0010;
B0_P4_R88_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[3:0]=0010;
B0_P4_R88_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Right channel data on
GPIO3 latched on rising edge of
DigMic clock
Digital Mic 2 Right channel data on
GPIO3 latched on falling edge of
DigMic clock
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[7:4]=0011;
B0_P4_R89_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[7:4]=0011;
B0_P4_R89_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Left channel data on
GPIO4 latched on rising edge of
DigMic clock
Digital Mic 2 Left channel data on
GPIO4 latched on falling edge of
DigMic clock
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[3:0]=0011;
B0_P4_R89_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[3:0]=0011;
B0_P4_R89_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Right channel data on
GPIO4 latched on rising edge of
DigMic clock
Digital Mic 2 Right channel data on
GPIO4 latched on falling edge of
DigMic clock
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[7:4]=0100;
B0_P4_R90_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[5:4] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[7:4]=0100;
B0_P4_R90_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Left channel data on
GPIO5 latched on rising edge of
DigMic clock
Digital Mic 2 Left channel data on
GPIO5 latched on falling edge of
DigMic clock
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 0;
B0_P4_R102_D[3:0]=0100;
B0_P4_R90_D[6:2] = 00001;
Configure miniDSP_A
B0_P0_R112_D[3:2] = 01;
B0_P4_R100_D[7] = 1;
B0_P4_R102_D[3:0]=0100;
B0_P4_R90_D[6:2] = 00001;
Configure miniDSP_A
Digital Mic 2 Right channel data on
GPIO5 latched on rising edge of
DigMic clock
Digital Mic 2 Right channel data on
GPIO5 latched on falling edge of
DigMic clock
Table 51 summarizes the register settings that must be applied to configure the terminal assignments for the
audio serial interfaces. In Table 51, the letter/number combination represents the row and the column number
from Table 46 and Table 47 in bold type.
Please be aware that more settings may be necessary to obtain a full audio serial interface definition matching
the application requirement (for example B0_P4_R1-R16 for Audio Serial Interface 1, B0_P4_R17-R32 for Audio
Serial Interface 2, and B0_P4_R33-R48 for Audio Serial Interface 3).
118
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Table 51. Multifunction Terminal Register Configuration - Audio Serial Interfaces
Description
Required Register Setting
Description
Required Register Setting
B0_P4_R65_D[5:2]=0001;
B0_P4_R10_D[7:5]=001;
Configure B0_P4_R14_D[3:0]
B0_P4_R65_D[5:2]=0001;
B0_P4_R10_D[7:5]=000;
H6
I10
ASI1 WCLK Output on WCLK1
ASI2 WCLK Output for WCLK2
H6
I10
ASI1 WCLK Input on WCLK1
B0_P4_R69_D[5:2]=0001;
B0_P4_R26_D5=1;
B0_P4_R53_D[6:4]=000;
Configure B0_P4_R30_D[3:0]
B0_P4_R69_D[5:2]=0010;
B0_P4_R26_D5=0;
B0_P4_R53_D[6:4]=000;
ASI2 WCLK Input for WCLK2
B0_P4_R87_D[6:2]=10100;
B0_P4_R55_D[6:4]=010;
Configure B0_P4_R46_D[3:0]
B0_P4_R87_D[6:2]=00001;
B0_P4_R55_D[6:4]=010;
J15
K7
ASI3 WCLK Output on GPIO2
ASI1 BCLK Output on BCLK1
J15
K7
ASI3 WCLK Input on GPIO2
ASI1 BCLK Input on BCLK1
B0_P4_R10_D[4:2]=001;
Configure B0_P4_R14_D[7:4]
B0_P4_R10_D[4:2]=000
B0_P4_R53_D[2:0]=000;
B0_P4_R26_D2 = 1;
B0_P4_R70_D[5:2]=0001;
Configure B0_P4_R30_D[7:4]
B0_P4_R53_D[2:0]=000;
B0_P4_R26_D2=0;
B0_P4_R70_D[5:2]=0001;
L11
ASI2 BCLK Output on BCLK2
ASI3 BCLK Output on GPIO1
L11
ASI2 BCLK Input on BCLK2
B0_P4_R55_D[2:0]=001;
B0_P4_R86_D[6:2=10101;
Configure B0_P4_R46_D[7:4]
B0_P4_R55_D[2:0]=001;
B0_P4_R86_D[6:2=00001;
M14
N9
M14
O9
ASI3 BCLK Input on GPIO1
B0_P4_R4_D[7:6]=00 or 01 or 10 or 11;
B0_P4_R6_D[7]=0;
B0_P4_R67_D[4:1]=0001;
B0_P4_R4_D[7:6] = 01 or 10 or 11;
B0_P4_R6_D[7]=1;
B0_P4_R67_D[4:1]=0001;
Single terminal multi-channel ASI1
DOUT on DOUT1
ASI1 DOUT (L1,R1) on DOUT1
ASI1 DOUT (L2,R2) on DOUT2
ASI1 DOUT (L3,R3) on MISO_GPO1
ASI1 DOUT (L3,R3) on GPIO1
ASI1 DOUT (L4,R4) on WCLK2
ASI1 DOUT (L4,R4) on GPIO2
B0_P4_R4_D[7:6] = 01 or 10 or 11;
ASI1 DOUT (L2,R2) on MISO_GPO1 B0_P4_R6_D[7]=1;
B0_P4_R96_D[4:1]=1101;
B0_P4_R4_D[7:6] = 01 or 10 or 11;
B0_P4_R6_D[7]=1;
B0_P4_R71_D[4:1]=1101;
P4
P13
Q4
B0_P4_R4_D[7:6] = 01 or 10 or 11;
B0_P4_R6_D[7]=1;
B0_P4_R87_D[6:2]=01101;
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]=1;
B0_P4_R96_D[4:1]=1110;
P15
Q11
Q15
ASI1 DOUT (L2,R2) on GPIO2
ASI1 DOUT (L3,R3) on BCLK2
ASI1 DOUT (L3,R3) on GPIO2
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]=1;
B0_P4_R70_D[5:2]=1110;
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]=1;
B0_P4_R86_D[6:2]=01110;
Q14
R10
R15
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]=1;
B0_P4_R87_D[6:2]=01110;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]=1;
B0_P4_R69_D[5:2]=1111;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]=1;
B0_P4_R86_D[6:2]=01111;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]=1;
B0_P4_R87_D[6:2]=01111;
R14
S13
ASI1 DOUT (L4,R4) on GPIO1
ASI2 DOUT on DOUT2
B0_P4_R71_D[4:1]=0001;
B0_P4_R89_D[6:2]=11101;
B0_P4_R4_D[7:6] = 00 or 01 or 10 or
Single terminal multi-channel ASI1 DIN 11;
T17
ASI3 DOUT on GPIO4
U8
on DIN1
B0_P4_R6_D[7]= 0;
B0_P4_R68_D[6:5]=01;
B0_P4_R4_D[7:6] = 01 or 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R49_D[4:0]=00001;
B0_P4_R68_D[6:5]=01;
B0_P4_R4_D[7:6] = 01 or 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R50_D[4:0]=00010;
B0_P4_R72_D[6:5]=01;
V8
ASI1 DIN (L1,R1) on DIN1
ASI1 DIN (L2,R2) on GPIO2
ASI1 DIN (L3,R3) on BCLK2
W12
W16
X14
ASI1 DIN (L2,R2) on DIN2
ASI1 DIN (L2,R2) on GPIO3
ASI1 DIN (L3,R3) on GPIO1
B0_P4_R4_D[7:6] = 01 or 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R50_D[4:0]=00101;
B0_P4_R4_D[7:6] = 01 or 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R50_D[4:0]=00110;
W15
X11
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=01100;
B0_P4_R70_D[5:2]=1110;
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=00100;
B0_P4_R86_D[6:2]=01110;
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=00101;
B0_P4_R87_D[6:2]=01110;
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=00110;
B0_P4_R88_D[6:2]=01110;
X15
X18
Y14
ASI1 DIN (L3,R3) on GPIO2
ASI1 DIN (L3,R3) on GPIO5
ASI1 DIN (L4,R4) on GPIO1
X16
Y10
Y15
ASI1 DIN (L3,R3) on GPIO3
ASI1 DIN (L4,R4) on WCLK2
ASI1 DIN (L4,R4) on GPIO2
B0_P4_R4_D[7:6] = 10 or 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=01000;
B0_P4_R90_D[6:2]=01110;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=01110;
B0_P4_R69_D[5:2]=1111;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=00100;
B0_P4_R86_D[6:2]=01111;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=00101;
B0_P4_R87_D[6:2]=01111;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=00110;
B0_P4_R88_D[6:2]=01111;
B0_P4_R4_D[7:6] = 11;
B0_P4_R6_D[7]= 1;
B0_P4_R51_D[4:0]=01000;
B0_P4_R90_D[6:2]=01111;
Y16
ASI1 DIN (L4,R4) on GPIO3
ASI2 DIN on DIN2
Y18
ASI1 DIN (L4,R4) on GPIO5
ASI3 DIN on GPIO3
B0_P4_R54_D[2:0]=000;
B0_P4_R72_D[6:5]=01;
B0_P4_R56_D[2:0]=011;
B0_P4_R88_D[6:2]=11101;
Z12
AA16
AB14
B0_P4_R11_D[7]=1;
B0_P4_R16_D[2:0]=001;
B0_P4_R86_D[6:2]=10111;
Configure B0_P4_R1115_D[7:4]
B0_P4_R16_D[2:0]=001;
B0_P4_R86_D[6:2]=00001;
AB14
ASI1 ADC BCLK output on GPIO1
ASI1 ADC BCLK input on GPIO1
Copyright © 2014, Texas Instruments Incorporated
119
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Table 51. Multifunction Terminal Register Configuration - Audio Serial Interfaces (continued)
Description
Required Register Setting
Description
Required Register Setting
B0_P4_R11_D[7]=1;
B0_P4_R16_D[2:0]=010;
B0_P4_R87_D[6:2]=10111;
Configure B0_P4_R115_D[7:4]
B0_P4_R16_D[2:0]=010;
B0_P4_R87_D[6:2]=00001;
AB15
AB16
AB17
AC14
AC15
AC16
AC17
AD14
AD15
AD16
AD17
AE14
AE15
AE16
AE17
ASI1 ADC BCLK output on GPIO2
AB15
AB16
AB17
AC14
AC15
AC16
AC17
AD14
AD15
AD16
AD17
AE14
AE15
AE16
AE17
ASI1 ADC BCLK input on GPIO2
B0_P4_R11_D[7]=1;
B0_P4_R16_D[2:0]=011;
B0_P4_R88_D[6:2]=10111;
Configure B0_P4_R115_D[7:4]
B0_P4_R16_D[2:0]=011;
B0_P4_R88_D[6:2]=00001;
ASI1 ADC BCLK output on GPIO3
ASI1 ADC BCLK output on GPIO4
ASI2 ADC BCLK output on GPIO1
ASI2 ADC BCLK output on GPIO2
ASI2 ADC BCLK output on GPIO3
ASI2 ADC BCLK output on GPIO4
ASI1 ADC WCLK output on GPIO1
ASI1 ADC WCLK output on GPIO2
ASI1 ADC WCLK output on GPIO3
ASI1 ADC WCLK output on GPIO4
ASI2 ADC WCLK output on GPIO1
ASI2 ADC WCLK output on GPIO2
ASI2 ADC WCLK output on GPIO3
ASI2 ADC WCLK output on GPIO4
ASI1 ADC BCLK input on GPIO3
ASI1 ADC BCLK input on GPIO4
ASI2 ADC BCLK input on GPIO1
ASI2 ADC BCLK input on GPIO2
ASI2 ADC BCLK input on GPIO3
ASI2 ADC BCLK input on GPIO4
ASI1 ADC WCLK input on GPIO1
ASI1 ADC WCLK input on GPIO2
ASI1 ADC WCLK input on GPIO3
ASI1 ADC WCLK input on GPIO4
ASI2 ADC WCLK input on GPIO1
ASI2 ADC WCLK input on GPIO2
ASI2 ADC WCLK input on GPIO3
ASI2 ADC WCLK input on GPIO4
B0_P4_R11_D[7]=1;
B0_P4_R16_D[2:0]=100;
B0_P4_R89_D[6:2]=10111;
Configure B0_P4_R115_D[7:4]
B0_P4_R16_D[2:0]=100;
B0_P4_R89_D[6:2]=00001;
B0_P4_R27_D[7]=1;
B0_P4_R32_D[2:0]=001;
B0_P4_R86_D[6:2]=11001;
Configure B0_P4_R116_D[7:4]
B0_P4_R32_D[2:0]=001;
B0_P4_R86_D[6:2]=00001;
B0_P4_R27_D[7]=1;
B0_P4_R32_D[2:0]=010;
B0_P4_R87_D[6:2]=11001;
Configure B0_P4_R116_D[7:4]
B0_P4_R32_D[2:0]=010;
B0_P4_R87_D[6:2]=00001;
B0_P4_R27_D[7]=1;
B0_P4_R32_D[2:0]=011;
B0_P4_R88_D[6:2]=11001;
Configure B0_P4_R116_D[7:4]
B0_P4_R32_D[2:0]=011;
B0_P4_R88_D[6:2]=00001;
B0_P4_R27_D[7]=1;
B0_P4_R32_D[2:0]=100;
B0_P4_R89_D[6:2]=11001;
Configure B0_P4_R116_D[7:4]
B0_P4_R32_D[2:0]=100;
B0_P4_R89_D[6:2]=00001;
B0_P4_R11_D[6]=1;
B0_P4_R16_D[6:4]=001;
B0_P4_R86_D[6:2]=10110;
Configure B0_P4_R115_D[3:0]
B0_P4_R16_D[6:4]=001;
B0_P4_R86_D[6:2]=00001;
B0_P4_R11_D[6]=1;
B0_P4_R16_D[6:4]=010;
B0_P4_R87_D[6:2]=10110;
Configure B0_P4_R115_D[3:0]
B0_P4_R16_D[6:4]=010;
B0_P4_R87_D[6:2]=00001;
B0_P4_R11_D[6]=1;
B0_P4_R16_D[6:4]=011;
B0_P4_R88_D[6:2]=10110;
Configure B0_P4_R115_D[3:0]
B0_P4_R16_D[6:4]=011;
B0_P4_R88_D[6:2]=00001;
B0_P4_R11_D[6]=1;
B0_P4_R16_D[6:4]=100;
B0_P4_R89_D[6:2]=10110;
Configure B0_P4_R115_D[3:0]
B0_P4_R16_D[6:4]=100;
B0_P4_R89_D[6:2]=00001;
B0_P4_R27_D[6]=1;
B0_P4_R32_D[6:4]=001;
B0_P4_R86_D[6:2]=11000;
Configure B0_P4_R116_D[3:0]
B0_P4_R32_D[6:4]=001;
B0_P4_R86_D[6:2]=00001;
B0_P4_R27_D[6]=1;
B0_P4_R32_D[6:4]=010;
B0_P4_R87_D[6:2]=11000;
Configure B0_P4_R116_D[3:0]
B0_P4_R32_D[6:4]=010;
B0_P4_R87_D[6:2]=00001;
B0_P4_R27_D[6]=1;
B0_P4_R32_D[6:4]=011;
B0_P4_R88_D[6:2]=11000;
Configure B0_P4_R116_D[3:0]
B0_P4_R32_D[6:4]=011;
B0_P4_R88_D[6:2]=00001;
B0_P4_R27_D[6]=1;
B0_P4_R32_D[6:4]=100;
B0_P4_R89_D[6:2]=11000;
Configure B0_P4_R116_D[3:0]
B0_P4_R32_D[6:4]=100;
B0_P4_R89_D[6:2]=00001;
8.4 Device Functional Modes
Functions
Modes
Details
•
•
Single Ended Input Mode
Differential Input Mode
Analog Inputs
See ADC Signal Routing for details.
•
•
High Input Impedance Mode
Low Input Impedance Mode
•
•
Analog Inputs
Digital Microphone/PDM Input
Audio Inputs
See Digital Microphone Function for
details.
120
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Device Functional Modes (continued)
•
•
Single-ended Output Mode
Differential Output Mode
Line Output
See Line Out Amplifier
Configurations for details.
•
•
Built-in Processing Block (PRB) Mode
Programmable miniDSP Mode
Signal Processing
Digital Audio Interface
See ADC Processing Blocks, DAC
Processing Blocks and for details.
•
•
WCLK and BCLK Master Mode
WCLK and BCLK Slave Mode
See Digital Audio Interfaces for
details.
•
•
•
•
•
•
I2S Mode
LJF Mode
RJF Mode
DSP Mode
PCM Mode
TDM Mode
•
•
SPI Mode
I2C Mode
Control Interface
SAR ADC
See Control Interfaces for details.
See SAR ADC for details.
•
•
Internal Reference Mode
External Reference Mode
•
•
Auxiliary Voltage Measurement Mode
Resistive Measurement Mode
•
•
Pulsed Mode
Level Mode
Interrupts
See Interrupt Generation and
Diagnostic Flags for details.
•
Terminal Muxing
Multifunction Terminals
See Multifunction Terminals for
details.
8.5 Programming
To enable the TLV320AIC3268 in a particular application, it needs to be comfigured or programmed. Initialization
Setup describes various configurations required to enable the device.
To enable use of miniDSP in configurable modes, PurePath tools are provided. Please contact Texas
Instruments for more details.
8.6 Register Maps
8.6.1 Register Map Summary
Table 52. Summary of Register Map
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
Page Select Register
Software Reset Register
Reserved Registers
1
2-3
0x02-
0x03
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Clock Control Register 1, Clock Input Multiplexers
Clock Control Register 2, PLL Input Multiplexer
Clock Control Register 3, PLL P and R Values
Clock Control Register 4, PLL J Value
5
6
7
8
Clock Control Register 5, PLL D Values (MSB)
Clock Control Register 6, PLL D Values (LSB)
Clock Control Register 7, PLL_CLKIN Divider
Clock Control Register 8, NDAC Divider Values
Clock Control Register 9, MDAC Divider Values
DAC OSR Control Register 1, MSB Value
DAC OSR Control Register 2, LSB Value
9
10
11
12
13
14
Copyright © 2014, Texas Instruments Incorporated
121
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
15-17
0x00
0x00
0x0F-
0x11
Reserved Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33-35
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
Clock Control Register 10, NADC Values
Clock Control Register 11, MADC Values
ADC Oversampling (AOSR) Register
CLKOUT MUX
Clock Control Register 12, CLKOUT M Divider Value
Timer clock
Low Frequency Clock Generation Control
High Frequency Clock Generation Control 1
High Frequency Clock Generation Control 2
High Frequency Clock Generation Control 3
High Frequency Clock Generation Control 4
High Frequency Clock Trim Control 1
High Frequency Clock Trim Control 2
High Frequency Clock Trim Control 3
High Frequency Clock Trim Control 4
Reserved Registers
0x21-
0x23
0
0
0
0
0
0
0
0
36
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x24
0x25
0x26
ADC Flag Register
DAC Flag Register
DAC Flag Register
Reserved Registers
37
38
39-41
0x27-
0x29
0
0
0
0
0
0
0
0
0
0
42
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x2A
0x2B
0x2C
0x2D
Sticky Flag Register 1
Reserved Register
43
44
Sticky Flag Register 2
Sticky Flag Register 3
Reserved Register
45
46-47
0x2E-
0x2F
0
0
0
0
0
0
0
0
0
0
48
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x30
0x31
0x32
0x33
INT1 Interrupt Control
INT2 Interrupt Control
SAR Control 1
49
50
51
Interrupt Format Control Register
Reserved Registers
52-59
0x34-
0x3B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
60
61
62
63
64
65
66
67
68
69
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
DAC Processing Block and miniDSP Power Control
ADC Processing Block Control
Reserved Register
Primary DAC Power and Soft-Stepping Control
Primary DAC Master Volume Configuration
Primary DAC Left Volume Control Setting
Primary DAC Right Volume Control Setting
Headset Detection
Reserved Register
Reserved Register
122
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
70
0x00
0x00
0x00
0x00
0x46
Reserved Register
71-80
0x47-
0x50
Reserved Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
ADC Channel Power Control
ADC Fine Gain Volume Control
Left ADC Volume Control
Right ADC Volume Control
ADC Phase Control
Left AGC Control 1
Left AGC Control 2
Left AGC Control 3
Left AGC Attack Time
Left AGC Decay Time
Left AGC Noise Debounce
Left AGC Signal Debounce
Left AGC Gain
Right AGC Control 1
Right AGC Control 2
Right AGC Control 3
Right AGC Attack Time
Right AGC Decay Time
Right AGC Noise Debounce
Right AGC Signal Debounce
Right AGC Gain
102-111 0x00
0x66-
0x6F
Reserved Registers
0
0
0
0
112
0x00
0x00
0x00
0x70
Digital Microphone 2 Control
Reserved Registers
113-114 0x00
0x71-
0x72
0
0
0
0
115
0x00
0x00
0x00
0x73
I2C Interface Miscellaneous Control
Reserved Registers
116-119 0x00
0x74-
0x77
0
0
0
0
120
0x00
0x00
0x00
0x78
miniDSP Control Register access
Reserved Registers
121-126 0x00
0x79-
0x7E
0
0
0
0
0
0
0
0
1
1
1
1
1
1
127
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x7F
0x00
0x01
0x02
0x03
0x04
Book Selection Register
Page Select Register
1
Power Configuration Register
Reserved Register
2
3
Left DAC PowerTune Configuration Register
Right DAC PowerTune Configuration Register
Reserved Registers
4
5-7
0x05-
0x07
0
0
0
1
1
1
8
0x00
0x00
0x00
0x01
0x01
0x01
0x08
0x09
0x0A
Common Mode Register
9
Headphone Output Driver Control
Receiver Output Driver Control
10
Copyright © 2014, Texas Instruments Incorporated
123
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
1
1
1
11
0x00
0x00
0x00
0x01
0x01
0x01
0x0B
0x0C
Headphone Output Driver De-pop Control
Receiver Output Driver De-Pop Control
Reserved Registers
12
13-16
0x0D-
0x10
0
0
0
0
1
1
1
1
17
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x11
0x12
0x13
Mixer Amplifier Control
18
Left ADC PGA to Left Mixer Amplifier (MAL) Volume Control
Right ADC PGA to Right Mixer Amplifier (MAR) Volume Control
Reserved Registers
19
20-21
0x14-
0x15
0
0
0
1
1
1
22
0x00
0x00
0x00
0x01
0x01
0x01
0x16
0x17
Lineout Amplifier Control 1
Lineout Amplifier Control 2
Reserved
23
24-26
0x18-
0x1A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43-44
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
Headphone Amplifier Control 1
Headphone Amplifier Control 2
Headphone Amplifier Control 3
Reserved Register
HPL Driver Volume Control
HPR Driver Volume Control
Reserved Register
Reserved Register
Ground Centered Headphone Offset Correction Control
Receiver Amplifier Control 1
Receiver Amplifier Control 2
Receiver Amplifier Control 3
Receiver Amplifier Control 4
Receiver Amplifier Control 5
Receiver Amplifier Control 6
Receiver Amplifier Control 7
Reserved Registers
0x2B-
0x2C
0
0
0
0
0
1
1
1
1
1
45
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x2D
0x2E
0x2F
0x30
Speaker Amplifier Control 1
Speaker Amplifier Control 2
Speaker Amplifier Control 3
Speaker Amplifier Volume Controls
Reserved Registers
46
47
48
49-50
0x31-
0x32
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
51
52
53
54
55
56
57
58
59
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
Microphone Bias Control
Input Select 1 for Left Microphone PGA P-Terminal
Input Select 2 for Left Microphone PGA P-Terminal
Input Select for Left Microphone PGA M-Terminal
Input Select 1 for Right Microphone PGA P-Terminal
Input Select 2 for Right Microphone PGA P-Terminal
Input Select for Right Microphone PGA M-Terminal
Input Common Mode Control
Left Microphone PGA Control
124
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
60
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
Right Microphone PGA Control
ADC PowerTune Configuration Register
ADC Analog PGA Gain Flag Register
DAC Analog Gain Flags Register 1
DAC Analog Gain Flags Register 2
Analog Bypass Gain Flags Register
Driver Power-Up Flags Register
Reserved Registers
61
62
63
64
65
66
67-68
0x43-
0x44
0
0
1
1
69
0x00
0x00
0x01
0x01
0x45
Over current Flags
Reserved Registers
67-76
0x43-
0x4C
0
0
1
1
77
0x00
0x00
0x01
0x01
0x4D
Reserved Registers
Reserved Registers
78-118
0x4E-
0x76
0
0
0
0
0
1
1
1
1
1
119
120
121
122
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x01
0x77
0x78
0x79
0x7A
Headset Detection Tuning Register 1
Headset Detection Tuning Register 2
Reserved Register
Reference Powerup Control
Reserved Registers
123-127 0x00
0x7B-
0x7F
0
0
0
0
0
3
3
3
3
3
0
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x00
0x01
0x02
0x03
Page Select Register
1
Reserved Register
2
Primary SAR ADC Control
Primary SAR ADC Conversion Mode
Reserved Registers
3
4-5
0x04-
0x05
0
0
3
3
6
0x00
0x00
0x03
0x03
0x06
SAR Reference Control
Reserved Registers
7-8
0x07-
0x08
0
0
0
3
3
3
9
0x00
0x00
0x00
0x03
0x03
0x03
0x09
0x0A
SAR ADC Flags Register 1
SAR ADC Flags Register 2
Reserved Registers
10
11-12
0x0B-
0x0C
0
0
0
0
0
0
0
0
0
0
0
0
0
3
3
3
3
3
3
3
3
3
3
3
3
3
13
14
15
16
17
18
19
20
21
22
23
24
25
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
SAR ADC Buffer Mode Control
Reserved Register
Scan Mode Timer Control
Reserved Register
SAR ADC Clock Control
SAR ADC Buffer Mode Data Read Control
SAR ADC Measurement Control
Reserved Register
SAR ADC Measurement Threshold Flags
IN1L Max Threshold Check Control 1
IN1L Max Threshold Check Control 2
IN1L Min Threshold Check Control 1
IN1L Min Threshold Check Control 2
Copyright © 2014, Texas Instruments Incorporated
125
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0
0
3
3
3
3
3
3
3
3
3
26
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
IN1R Max Threshold Check Control 1
IN1R Max Threshold Check Control 2
IN1R Min Threshold Check Control 1
IN1R Min Threshold Check Control 2
TEMP Max Threshold Check Control 1
TEMP Max Threshold Check Control 2
TEMP Min Threshold Check Control 1
TEMP Min Threshold Check Control 2
Reserved Registers
27
28
29
30
31
32
33
34-53
0x22-
0x35
0
0
0
0
0
0
0
3
3
3
3
3
3
3
54
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x36
0x37
0x38
0x39
0x3A
0x3B
IN1L Measurement Data (MSB)
IN1L Measurement Data (LSB)
IN1R Measurement Data (MSB)
IN1R Measurement Data (LSB)
VBAT Measurement Data (MSB)
VBAT Measurement Data (LSB)
Reserved Registers
55
56
57
58
59
60-65
0x3C-
0x41
0
0
0
0
0
3
3
3
3
3
66
0x00
0x00
0x00
0x00
0x00
0x03
0x03
0x03
0x03
0x03
0x42
0x43
0x44
0x45
TEMP1 Measurement Data (MSB)
TEMP1 Measurement Data (LSB)
TEMP2 Measurement Data (MSB)
TEMP2 Measurement Data (LSB)
Reserved Registers
67
68
69
70-127
0x46-
0x7F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
Page Select Register
1
ASI1, Audio Bus Format Control Register
ASI1, Left Ch_Offset_1 Control Register
ASI1, Right Ch_Offset_2 Control Register
ASI1, Channel Setup Register
2
3
4
5
ASI1, ADC Audio Bus Format Control Register
Audio Serial Interface 1, Multi-Pin Mode
ASI1, ADC Input Control
6
7
8
ASI1, DAC Output Control
9
ASI1, Control Register 9, ADC Slot Tristate Control
ASI1, WCLK and BCLK Control Register
ASI1, Bit Clock N Divider Input Control
ASI1, Bit Clock N Divider
10
11
12
13
14
15
16
17
18
19-20
ASI 1, Word Clock N Divider
ASI1, BCLK and WCLK Output
ASI1, Data Output
ASI1, ADC Word Clock and Bit Clock Control
ASI2, Audio Bus Format Control Register
ASI2, Data Offset Control Register
Reserved Registers
0x13-
0x14
0
4
21
0x00
0x04
0x15
ASI2, ADC Audio Bus Format Control Register
126
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
22
23
24
25
26
27
28
29
30
31
32
33
34
35-36
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
Reserved Register
ASI2, ADC Input Control
ASI 2, DAC Output Control
Reserved Register
ASI2, Word Clock and Bit Clock Control Register
ASI2, Bit Clock N Divider Input Control
ASI2, Bit Clock N Divider
ASI2, Word Clock N Divider
ASI2, Bit Clock and Word Clock Output
ASI2, Data Output
ASI2, ADC Word Clock and Bit Clock Control
ASI3, Audio Bus Format Control Register
ASI3, Data Offset Control Register
Reserved Registers
0x23-
0x24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57-64
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
Reserved Register
Reserved Register
ASI3, ADC Input Control
ASI3, DAC Output Control
Reserved Register
ASI3, Word Clock and Bit Clock Control Register
ASI3, Bit Clock N Divider Input Control
ASI3, Bit Clock N Divider
ASI3, Word Clock N Divider
ASI3, Bit Clock and Word Clock Output
ASI3, Data Output
Reserved Register.
ASI1 L1, R1 Input Control
ASI1 L2, R2 Input Control
ASI1 L3, R3 Input Control
ASI1 L4, R4 Input Control
Reserved Register
ASI2, DIN Input Multiplexer Control
ASI3, Word Clock and Bit Clock Input Multiplexer Control
ASI3, DIN Input Multiplexer Control
Reserved Registers
0x39-
0x40
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
65
66
67
68
69
70
71
72
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
WCLK1 (Input or Output) Pin Control
Reserved Register
DOUT1 (Output) Pin Control
DIN1 (Input) Pin Control
WCLK2 (Input or Output) Pin Control
BCLK2 (Input or Output) Pin Control
DOUT2 (Output) Pin Control
DIN2 (Input) Pin Control
Copyright © 2014, Texas Instruments Incorporated
127
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
0
4
73-74
0x00
0x04
0x49-
0x4A
Reserved Register
0
0
0
4
4
4
75
0x00
0x00
0x00
0x04
0x04
0x04
0x4B
0x4C
Reserved Register
Reserved Register
Reserved Registers
76
77-85
0x4D-
0x55
0
0
0
0
0
0
0
4
4
4
4
4
4
4
86
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x56
0x57
0x58
0x59
0x5A
0x5B
GPIO1 (Input or Output) Pin Control
GPIO2 (Input or Output) Pin Control
GPIO3 (Input or Output) Pin Control
GPIO4 (Input or Output) Pin Control
GPIO5 (Input or Output) Pin Control
Reserved Register
87
88
89
90
91
92-95
0x5C-
0x5F
Reserved Registers
0
0
4
4
96
0x00
0x00
0x04
0x04
0x60
MISO_GPO1 (Output) Pin Control
Reserved Registers
97-99
0x61-
0x63
0
0
0
0
0
0
4
4
4
4
4
4
100
101
102
103
104
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x64
0x65
0x66
0x67
0x68
Digital Microphone Clock Control
Digital Microphone 1 Input Pin Control
Digital Microphone 2 Input Pin Control
Reserved Register
Bit-Bang Output
105-106 0x00
0x69-
0x6A
Reserved Registers
0
0
4
4
107
0x00
0x04
0x04
0x6B
Bit-Bang Input
108-112 0x00
0x6C-
0x70
Reserved Registers
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
113
114
115
116
117
118
119
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x04
0x71
0x72
0x73
0x74
0x75
0x76
0x77
Bit-Bang miniDSP Output Control
Reserved Register
ASI1, ADC Bit Clock and ADC Word Clock Output
ASI2, ADC Bit Clock and ADC Word Clock Output
ASI3, ADC Bit Clock and ADC Word Clock Output
miniDSP Data Port Control
Digital Audio Engine Synchronization Control
Reserved Registers
120-127 0x00
0x78-
0x7F
0
0
0
0
252
252
252
252
0
0x00
0x00
0x00
0x00
0xFC
0xFC
0xFC
0xFC
0x00
0x01
0x02
Page Select Register
1
SAR Buffer Mode Data (MSB) and Buffer Flags
SAR Buffer Mode Data (LSB)
Reserved Registers
2
3-127
0x03-
0x7F
20
20
0
0
0
0x14
0x14
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-126
0x01-
0x7E
20
20
0
127
0
0x14
0x14
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-26
0x01-
0x1A
128
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
20
1-26
1-7
0x14
0x01-
0x1A
0x01-
0x07
Reserved Registers
20
1-26
8-127
0x14
0x01-
0x1A
0x08-
0x7F
ADC Fixed Coefficients C(0:767)
40
40
40
0
0
0
0
0x28
0x28
0x28
0x00
0x00
0x00
0x00
0x01
Page Select Register
1
ADC Adaptive CRAM Configuration Register
Reserved Registers
2-126
0x02-
0x7E
40
40
0
127
0
0x28
0x28
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-17
0x01-
0x11
40
40
1-17
1-17
1-7
0x28
0x28
0x01-
0x11
0x01-
0x07
Reserved Registers
8-127
0x01-
0x11
0x08-
0x7F
ADC Adaptive Coefficients C(0:509)
40
40
18
18
0
0x28
0x28
0x12
0x12
0x00
Page Select Register
Reserved Registers
1-7
0x01-
0x07
40
40
18
18
8-15
0x28
0x28
0x12
0x12
0x08-
0x0F
ADC Adaptive Coefficients C(510:511)
Reserved Registers
16-127
0x10-
0x7F
60
60
0
0
0
0x3C
0x3C
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-126
0x01-
0x7E
60
60
0
127
0
0x3C
0x3C
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-35
0x01-
0x23
60
60
1-35
1-35
1-7
0x3C
0x3C
0x01-
0x23
0x01-
0x07
Reserved Registers
8-127
0x01-
0x23
0x08-
0x7F
DAC Fixed Coefficients C(0:1023)
80
80
80
0
0
0
0
0x50
0x50
0x50
0x00
0x00
0x00
0x00
0x01
Page Select Register
1
DAC Adaptive Coefficient Bank 1 Configuration Register
Reserved Registers
2-126
0x02-
0x7E
80
80
0
127
0
0x50
0x50
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-17
0x01-
0x11
80
80
1-17
1-17
1-7
0x50
0x50
0x01-
0x11
0x01-
0x07
Reserved Registers
8-127
0x01-
0x11
0x08-
0x7F
DAC Adaptive Coefficient Bank 1 C(0:509)
80
80
18
18
0
0x50
0x50
0x12
0x12
0x00
Page Select Register
Reserved Registers
1-7
0x01-
0x07
80
80
82
18
18
0
8-15
16-127
0
0x50
0x50
0x52
0x12
0x12
0x00
0x08-
0x0F
DAC Adaptive Coefficient Bank 1 C(510:511)
Reserved Registers
0x10-
0x7F
0x00
Page Select Register
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Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
82
82
0
0
1
0x52
0x52
0x00
0x00
0x01
DAC Adaptive Coefficient Bank 2 Configuration Register
Reserved Registers
2-126
0x02-
0x7E
82
82
0
127
0
0x52
0x52
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-17
0x01-
0x11
82
82
1-17
1-17
1-7
0x52
0x52
0x01-
0x11
0x01-
0x07
Reserved Registers
8-127
0x01-
0x11
0x08-
0x7F
DAC Adaptive Coefficient Bank 2 C(0:509)
82
82
18
18
0
0x52
0x52
0x12
0x12
0x00
Page Select Register
Reserved Registers
1-7
0x01-
0x07
82
82
18
18
8-15
0x52
0x52
0x12
0x12
0x08-
0x0F
DAC Adaptive Coefficient Bank 2 C(510:511)
Reserved Registers
16-127
0x10-
0x7F
100
100
0
0
0
0x64
0x64
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-46
0x01-
0x2E
100
100
100
100
100
0
0
0
0
0
47
0x64
0x64
0x64
0x64
0x64
0x00
0x00
0x00
0x00
0x00
0x2F
0x30
0x31
0x32
Non-Programmable Override Options
48
ADC miniDSP_A Instruction Control Register 1
ADC miniDSP_A Instruction Control Register 2
49
50
ADC miniDSP_A CIC Input and Decimation Ratio Control Register
Reserved Registers
51-59
0x33-
0x3B
100
100
100
0
0
0
60
0x64
0x64
0x64
0x00
0x00
0x00
0x3C
0x3D
ADC miniDSP_A Secondary CIC Input Control
miniDSP_A to Audio Serial Interface Handoff Control
Reserved Registers
61
62-126
0x3E-
0x7E
100
100
0
127
0
0x64
0x64
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-52
0x01-
0x34
100
100
1-52
1-52
1-7
0x64
0x64
0x01-
0x34
0x01-
0x07
Reserved Registers
8-127
0x01-
0x34
0x08-
0x7F
miniDSP_A Instructions
120
120
0
0
0
0x78
0x78
0x00
0x00
0x00
Page Select Register
Reserved Registers
1-46
0x01-
0x2E
120
120
120
120
120
0
0
0
0
0
47
0x78
0x78
0x78
0x78
0x78
0x00
0x00
0x00
0x00
0x00
0x2F
0x30
0x31
0x32
Non-Programmable Override Options
DAC miniDSP_D Instruction Control Register 1
DAC miniDSP_D Instruction Control Register 2
DAC miniDSP_D Interpolation Factor Control Register
Reserved Registers
48
49
50
51-126
0x33-
0x7E
120
120
0
127
0
0x78
0x78
0x00
0x7F
0x00
Book Selection Register
Page Select Register
1-103
0x01-
0x67
130
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Register Maps (continued)
Table 52. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
BOOK
NO.
PAGE
NO.
REG.
NO.
BOOK
NO.
PAGE
NO.
REG.
NO.
120
1-103
1-7
0x78
0x01-
0x67
0x01-
0x07
Reserved Registers
120
1-103
8-127
0x78
0x01-
0x67
0x08-
0x7F
miniDSP_D Instructions
8.6.2 Book 0 Page 0
Book 0 / Page 0 / Register 0: Page Select Register - 0x00 / 0x00 / 0x00 (B0_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 0 / Page 0 / Register 1: Software Reset Register - 0x00 / 0x00 / 0x01 (B0_P0_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D1
D0
R
0000 000 Reserved. Write only reset values.
R/W
0
Self clearing software reset bit
0: Don't care
1: Self clearing software reset
Book 0 / Page 0 / Register 2-3: Reserved Registers - 0x00 / 0x00 / 0x02-0x03 (B0_P0_R2-3)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 0 / Page 0 / Register 4: Clock Control Register 1, Clock Input Multiplexers - 0x00 / 0x00 / 0x04
(B0_P0_R4)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0000
DAC_CLKIN Selection Control
0000: DAC_CLKIN = MCLK (Device Pin) **** Refer to the clocking diagram
0001: DAC_CLKIN = BCLK1 (Device Pin) **** Refer to the clocking diagram
0010: DAC_CLKIN = GPIO1 (Device Pin) **** Refer to the clocking diagram
0011: DAC_CLKIN = PLL_CLK (Generated On-Chip) **** Refer to the clocking diagram
0100: DAC_CLKIN = BCLK2 (Device Pin) **** Refer to the clocking diagram
0101: DAC_CLKIN = GPIO3 (Device Pin) **** Refer to the clocking diagram
0110: DAC_CLKIN = HF_REF_CLK **** Refer to the clocking diagram
0111: DAC_CLKIN = HF_OSC_CLK **** Refer to the clocking diagram
1000: Reserved. Do not use.
1001: DAC_CLKIN = GPIO2 (Device Pin) **** Refer to the clocking diagram
1010: Reserved. Do not use.
1011-1111: Reserved. Do not use.
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Book 0 / Page 0 / Register 4: Clock Control Register 1, Clock Input Multiplexers - 0x00 / 0x00 / 0x04
(B0_P0_R4) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D0
R/W
0000
ADC_CLKIN Selection Control
0000: ADC_CLKIN = MCLK (Device Pin) **** Refer to the clocking diagram
0001: ADC_CLKIN = BCLK1 (Device Pin) **** Refer to the clocking diagram
0010: ADC_CLKIN = GPIO1 (Device Pin) **** Refer to the clocking diagram
0011: ADC_CLKIN = PLL_CLK (Generated On-Chip) **** Refer to the clocking diagram
0100: ADC_CLKIN = BCLK2 (Device Pin) **** Refer to the clocking diagram
0101: ADC_CLKIN = GPIO3 (Device Pin) **** Refer to the clocking diagram
0110: ADC_CLKIN = HF_REF_CLK **** Refer to the clocking diagram
0111: ADC_CLKIN = HF_OSC_CLK **** Refer to the clocking diagram
1000: Reserved. Do not use.
1001: ADC_CLKIN = GPIO2 (Device Pin) **** Refer to the clocking diagram
1010: Reserved. Do not use.
1011-1111: Reserved. Do not use.
Book 0 / Page 0 / Register 5: Clock Control Register 2, PLL Input Multiplexer - 0x00 / 0x00 / 0x05
(B0_P0_R5)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
D6
R
0
0
Reserved. Write only reset values.
R/W
PLL Clock Range Selection Control
0: Low PLL Clock Range
1: High PLL Clock Range
D5-D2
R/W
00 00
PLL_CLKIN Selection Control
0000: PLL_CLKIN = MCLK (Device Pin)
0001: PLL_CLKIN = BCLK1 (Device Pin)
0010: PLL_CLKIN = GPIO1 (Device Pin)
0011: PLL_CLKIN = DIN1 (can be used for the system where DAC is not used)
0100: PLL_CLKIN = BCLK2 (Device Pin)
0101: PLL_CLKIN = GPIO3 (Device Pin)
0110: PLL_CLKIN = HF_REF_CLK **** Refer to the clocking diagram
0111: PLL_CLKIN = GPIO2 (Device Pin) **** Refer to the clocking diagram
1000-1001: Reserved. Do not use.
1010-1111: Reserved. Do not use.
D1-D0
R
00
Reserved. Write only reset values.
Book 0 / Page 0 / Register 6: Clock Control Register 3, PLL P and R Values - 0x00 / 0x00 / 0x06
(B0_P0_R6)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
PLL Power Control
0: PLL Power Down
1: PLL Power Up
D6-D4
001
PLL Divider P Control
000: P=8
001: P=1
010: P=2
011: P=3
100: P=4
101: P=5
110: P=6
111: P=7
D3-D0
R/W
0001
PLL Multiplier R Control
0000: R = 16
0001: R = 1
0010: R = 2
...
1110: R = 14
1111: R = 15
132
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 7: Clock Control Register 4, PLL J Value - 0x00 / 0x00 / 0x07 (B0_P0_R7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5-D0
R/W
R/W
00
Reserved. Write only reset values.
00 0100
PLL Multiplier J
00 0000: Reserved. Do not use.
00 0001: J=1
00 0010: J=2
…
11 1110: J=62
11 1111: J=63
Book 0 / Page 0 / Register 8: Clock Control Register 5, PLL D Values (MSB) - 0x00 / 0x00 / 0x08
(B0_P0_R8)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5-D0
R
00
Reserved. Write only reset values.
R/W
00 0000
PLL D Value MSB 6 Bits of 14-Bit Fraction
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
...
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000 ... 11 1111 1111 1111: Do not use
Note: This register will be updated only when the B0_P0_R9 is written immediately after
B0_P0_R8
Book 0 / Page 0 / Register 9: Clock Control Register 6, PLL D Values (LSB) - 0x00 / 0x00 / 0x09
(B0_P0_R9)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 PLL D Value LSB 8 Bits of 14-Bit Fraction
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
...
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000 ...11 1111 1111 1111: Do not use
Note: B0_P0_R9 should be written immediately after B0_P0_R8.
Book 0 / Page 0 / Register 10: Clock Control Register 7, PLL_CLKIN Divider - 0x00 / 0x00 / 0x0A
(B0_P0_R10)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D0
R/W
000 0001 PLL_CLKIN Divider (Generates Input Clock for PLL P Divider)
000 0000: PLL_CLKIN Divider = 128
000 0001: PLL_CLKIN Divider = 1
000 0010: PLL_CLKIN Divider = 2
...
111 1110: PLL_CLKIN Divider = 126
111 1111: PLL_CLKIN Divider = 127
Book 0 / Page 0 / Register 11: Clock Control Register 8, NDAC Divider Values - 0x00 / 0x00 / 0x0B
(B0_P0_R11)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
NDAC Divider Power Control
0: NDAC divider powered down
1: NDAC divider powered up
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Book 0 / Page 0 / Register 11: Clock Control Register 8, NDAC Divider Values - 0x00 / 0x00 / 0x0B
(B0_P0_R11) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
000 0001 NDAC Value
000 0000: NDAC=128
000 0001: NDAC=1
000 0010: NDAC=2
...
111 1110: NDAC=126
111 1111: NDAC=127
Note: Please check the clock frequency requirements in the Overview section
Book 0 / Page 0 / Register 12: Clock Control Register 9, MDAC Divider Values - 0x00 / 0x00 / 0x0C
(B0_P0_R12)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
MDAC Divider Power Control
0: MDAC divider powered down
1: MDAC divider powered up
D6-D0
000 0001 MDAC Value
000 0000: MDAC=128
000 0001: MDAC=1
000 0010: MDAC=2
...
111 1110: MDAC=126
111 1111: MDAC=127
Note: Please check the clock frequency requirements in the Overview section
Book 0 / Page 0 / Register 13: DAC OSR Control Register 1, MSB Value - 0x00 / 0x00 / 0x0D (B0_P0_R13)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1-D0
R
0000 00
00
Reserved. Write only reset values.
R/W
DAC OSR (DOSR) Control
DAC OSR(MSB) and DAC OSR(LSB)
00 0000 0000: DOSR=1024
00 0000 0001: DOSR=1
00 0000 0010: DOSR=2
...
11 1111 1110: DOSR=1022
11 1111 1111: DOSR=1023
Note: This register is updated when B0_P0_R14 is written to immediately after B0_P0_R13.
Book 0 / Page 0 / Register 14: DAC OSR Control Register 2, LSB Value - 0x00 / 0x00 / 0x0E (B0_P0_R14)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
1000 0000 DAC OSR (DOSR) Control
DAC OSR(MSB) and DAC OSR(LSB)
00 0000 0000: DOSR=1024
00 0000 0001: DOSR=1
00 0000 0010: DOSR=2
...
11 1111 1110: DOSR=1022
11 1111 1111: DOSR=1023
Note: This register should be written immediately after B0_P0_R13.
Book 0 / Page 0 / Register 15-17: Reserved Registers - 0x00 / 0x00 / 0x0F-0x11 (B0_P0_R15-17)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
134
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 18: Clock Control Register 10, NADC Values - 0x00 / 0x00 / 0x12 (B0_P0_R18)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
NADC Clock Divider Power Control
0: NADC divider powered down, ADC_CLK is same as DAC_CLK
1: NADC divider powered up
D6-D0
000 0001 NADC Value
000 0000: NADC=128
000 0001: NADC=1
...
111 1110: NADC=126
111 1111: NADC=127
Book 0 / Page 0 / Register 19: Clock Control Register 11, MADC Values - 0x00 / 0x00 / 0x13 (B0_P0_R19)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
MADC Clock Divider Power Control
0: MADC divider powered down, ADC_MOD_CLK is same as DAC_MOD_CLK
1: MADC divider powered up
D6-D0
000 0001 MADC Value
000 0000: MADC=128
000 0001: MADC=1
...
111 1110: MADC=126
111 1111: MADC=127
Book 0 / Page 0 / Register 20: ADC Oversampling (AOSR) Register - 0x00 / 0x00 / 0x14 (B0_P0_R20)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
1000 0000 ADC Oversampling Value
0000 0000: ADC AOSR = 256
0000 0001: ADC AOSR = 1
0000 0010: ADC AOSR = 2
...
0010 0000: ADC AOSR=32 (Use with ADC Filter Type C)
...
0100 0000: AOSR=64 (Use with ADC Filter Type A or B)
...
1000 0000: AOSR=128 (Use with ADC Filter Type A)
...
1111 1110: ADC AOSR = 254
1111 1111: ADC AOSR = 255
Note: If the ADC miniDSP will be used for signal processing ADC (B0_P0_R61) AOSR should be
an integral multiple of ADC DECIM factor.
Book 0 / Page 0 / Register 21: CLKOUT MUX - 0x00 / 0x00 / 0x15 (B0_P0_R21)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D0
R
000
Reserved. Write only reset values.
R/W
0 0000
00000: CDIV_CLKIN = MCLK (Device Pin)
00001: CDIV_CLKIN = BCLK1 (Device Pin)
00010: CDIV_CLKIN = DIN1 (Can be used for the systems where DAC is not required)
00011: CDIV_CLKIN = PLL_CLK (Generated On-Chip)
00100: CDIV_CLKIN = DAC_CLK (Generated On-Chip)
00101: CDIV_CLKIN = DAC_MOD_CLK (Generated On-Chip)
00110: CDIV_CLKIN = ADC_CLK (Generated On-Chip)
00111: CDIV_CLKIN = ADC_MOD_MCLK (Generated On-Chip)
01000: CDIV_CLKIN = BCLK2 (Device Pin)
01001: CDIV_CLKIN = GPIO3 (Device Pin)
01010: CDIV_CLKIN = High Frequency Reference Clock Generated On-Chip using HF_OSC_CLK
and LFR_CLKIN
01011: CDIV_CLKIN = High Frequency Oscillator Clock (Generated On-Chip)
01100-11111: Reserved. Do not use.
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Book 0 / Page 0 / Register 22: Clock Control Register 12, CLKOUT M Divider Value - 0x00 / 0x00 / 0x16
(B0_P0_R22)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
CLKOUT M Divider Power Control
0: CLKOUT M divider powered down
1: CLKOUT M divider powered up
D6-D0
000 0001 CLKOUT M Divider Value
000 0000: CLKOUT M divider = 128
000 0001: CLKOUT M divider = 1
000 0010: CLKOUT M divider = 2
...
111 1110: CLKOUT M divider = 126
111 1111: CLKOUT M divider = 127
Note: Please check the clock frequency requirments in the application overview section.
Book 0 / Page 0 / Register 23: Timer clock - 0x00 / 0x00 / 0x17 (B0_P0_R23)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
This timer clock of 1MHz is used for multiple purpose like all the interrupt generation for GPIO1,
GPIO2, debounce logic, and headset detection.
Select the 1MHz Timer Clock Source
0: REF_1MHZ_CLK = LF_OSC_CLK / 8
1: REF_1MHZ_CLK = MCLK / M ( M as defined in D6:0 below)
D6-D0
R/W
000 0001 MCLK Divider (M) Used to Generate REF_1MHZ_CLK
000 0000: M = 128
000 0001: M = 1
000 0010: M = 2
…
111 1110: M = 126
111 1111: M = 127
Book 0 / Page 0 / Register 24: Low Frequency Clock Generation Control - 0x00 / 0x00 / 0x18 (B0_P0_R24)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0000
0000: LFR_CLKIN (Low frequency reference clock) = MCLK (Device Pin)
0001: LFR_CLKIN = WCLK1 (Device Pin)
0010: LFR_CLKIN = GPIO1 (Device Pin)
0011: LFR_CLKIN = WCLK2 (Device Pin)
0100: LFR_CLKIN = BCLK2 (Device Pin)
0101: LFR_CLKIN = GPIO3 (Device Pin)
0110: LFR_CLKIN = DIN2 (Device Pin)
0111: Reserved. Do not use.
1000: LFR_CLKIN = GPIO2 (Device Pin)
1001: Reserved. Do not use.
1010-1111: Reserved. Do not use.
D3-D0
R/W
1111
0000: HF_CLKIN (High frequency clock) = MCLK (Device Pin)
0001 - 1110: Reserved. Do not use.
1111: HF_CLKIN = HF_OSC_CLK
Book 0 / Page 0 / Register 25: High Frequency Clock Generation Control 1 - 0x00 / 0x00 / 0x19
(B0_P0_R25)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
1
0
High Frequency Reference Clock Settling Flag
0: High Frequency Reference Clock is Settled
1: High Frequency Reference Clock is not Settled
D6
High Frequency Reference Clock Modulator Overflow Flag
0: High Frequency Reference Clock Modulator Overflow has not occurred
1: High Frequency Reference Clock Modulator Overflow has occurred
136
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 25: High Frequency Clock Generation Control 1 - 0x00 / 0x00 / 0x19
(B0_P0_R25) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D4
R/W
00
HF_REF_CLK Lock Ready Threshold
00: 2048 reference clock cycles
01: 512 reference clock cycles
10: 32 reference clock cycles
11: 8 reference clock cycles
D3-D0
R/W
0000
Ratio(27:24): Upper 4-bits of 28-bit Multiplication Ratio. Used when a low frequency clock
is used to generate the internal reference clock (See B0_P0_R24 for low frequency
clock settings). The recommended ratio is "round( 12,500,000 / LFR_CLKIN_FREQ)"
Book 0 / Page 0 / Register 26: High Frequency Clock Generation Control 2 - 0x00 / 0x00 / 0x1A
(B0_P0_R26)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Ratio(23:16): Next 8-bits of 28-bit Multiplication Ratio. Used when a low frequency clock
is used to generate the internal reference clock (See B0_P0_R24 for low frequency
clock settings). The recommended ratio is "round( 12,500,000 / LFR_CLKIN_FREQ)"
Book 0 / Page 0 / Register 27: High Frequency Clock Generation Control 3 - 0x00 / 0x00 / 0x1B
(B0_P0_R27)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0001 1000 Ratio(16:8): Next 8-bits of 28-bit Multiplication Ratio. Used when a low frequency clock
is used to generate the internal reference clock (See B0_P0_R24 for low frequency
clock settings). The recommended ratio is "round( 12,500,000 / LFR_CLKIN_FREQ)"
Book 0 / Page 0 / Register 28: High Frequency Clock Generation Control 4 - 0x00 / 0x00 / 0x1C
(B0_P0_R28)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0110 1010 Ratio(7:0): Lower 8-bits of 28-bit Multiplication Ratio. Used when a low frequency clock
is used to generate the internal reference clock (See B0_P0_R24 for low frequency
clock settings). The recommended ratio is "round( 12,500,000 / LFR_CLKIN_FREQ)"
Book 0 / Page 0 / Register 29: High Frequency Clock Trim Control 1 - 0x00 / 0x00 / 0x1D (B0_P0_R29)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
0
1
High Frequency Oscillator Calibration Flag
0: Calibration is not complete
1: Calibration is complete
D6
D5
R/W
R/W
High Frequency Oscillator Voltage Source Control
0: AVDDx_18
1: DVDD_18
High Frequency Oscillator Calibration Enable Control
0: Calibration is disabled
1: Calibration is enabled
D4-D2
D1-D0
R
0 00
00
Reserved. Write only reset values.
R/W
Ratio(25:24): Upper 2 bits of 26-bit integer ratio between desired high-frequency oscillator
frequency and low-frequency reference clock input
Book 0 / Page 0 / Register 30: High Frequency Clock Trim Control 2 - 0x00 / 0x00 / 0x1E (B0_P0_R30)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Ratio(23:16): Next 8 bits of 26-bit integer ratio between desired high-frequency oscillator frequency
and low-frequency reference clock input
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Book 0 / Page 0 / Register 31: High Frequency Clock Trim Control 3 - 0x00 / 0x00 / 0x1F (B0_P0_R31)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0110 Ratio(15:8): Next 8 bits of 26-bit integer ratio between desired high-frequency oscillator
frequency and low-frequency reference clock input
Book 0 / Page 0 / Register 32: High Frequency Clock Trim Control 4 - 0x00 / 0x00 / 0x20 (B0_P0_R32)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0001 1010 Ratio(7:0): Lower 8 bits of 26-bit integer ratio between desired high-frequency oscillator
frequency and low-frequency reference clock input
Book 0 / Page 0 / Register 33-35: Reserved Registers - 0x00 / 0x00 / 0x21-0x23 (B0_P0_R33-35)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 0 / Register 36: ADC Flag Register - 0x00 / 0x00 / 0x24 (B0_P0_R36)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
0
0
0
Left ADC PGA Status Flag
0: Gain Applied in Left ADC PGA is not equal to Programmed Gain in Control Register
1: Gain Applied in Left ADC PGA is equal to Programmed Gain in Control Register
D6
D5
Left ADC Power Status Flag
0: Left ADC Powered Down
1: Left ADC Powered Up
Left AGC Gain Status. This sticky flag will self clear on reading
0: Gain in Left AGC is not saturated
1: Gain in Left ADC is equal to maximum allowed gain in Left AGC
D4
D3
R
R
0
0
Reserved. Write only reset values.
Right ADC PGA Status Flag
0: Gain Applied in Right ADC PGA is not equal to Programmed Gain in Control Register
1: Gain Applied in Right ADC PGA is equal to Programmed Gain in Control Register
D2
D1
D0
R
R
R
0
0
0
Right ADC Power Status Flag
0: Right ADC Powered Down
1: Right ADC Powered Up
Right AGC Gain Status. This sticky flag will self clear on reading
0: Gain in Right AGC is not saturated
1: Gain in Right ADC is equal to maximum allowed gain in Right AGC
Reserved. Write only reset values.
Book 0 / Page 0 / Register 37: DAC Flag Register - 0x00 / 0x00 / 0x25 (B0_P0_R37)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
0: Left DAC Powered Down
1: Left DAC Powered Up
D6
R
R
0
Reserved. Write only reset values.
D5-D4
00
00: Jack is not inserted
01: Jack is inserted without Microphone
10: Reserved. Do not use.
11: Jack is inserted with Microphone
D3
R
0
0: Right DAC Powered Down
1: Right DAC Powered Up
D2
R
R
0
Reserved. Write only reset values.
00: Headset is not inserted
D1-D0
00
01: Jack is inserted with mono-HS (Ground-Centered or Capless Headphone Mode Only)
10: Jack is inserted with stereo-HS (Ground-Centered or Capless Headphone Mode Only)
11: Reserved. Do not use.
138
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 38: DAC Flag Register - 0x00 / 0x00 / 0x26 (B0_P0_R38)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
D6
R
R
1
1
Reserved
0: Primary Left DAC PGA is not muted
1: Primary Left DAC PGA is muted
D5
D4
R
R
0
0
Reserved
0: Primary Left DAC PGA , Applied Gain /= Programmed Gain
1: Primary Left DAC PGA , Applied Gain = Programmed Gain
D3
D2
R
R
1
1
Reserved
0: Primary Right DAC PGA is not muted
1: Primary Right DAC PGA is muted
D1
D0
R
R
0
0
Reserved
0: Primary Right DAC PGA , Applied Gain /= Programmed Gain
1: Primary Right DAC PGA , Applied Gain = Programmed Gain
Book 0 / Page 0 / Register 39-41: Reserved Registers - 0x00 / 0x00 / 0x27-0x29 (B0_P0_R39-41)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only default values.
Book 0 / Page 0 / Register 42: Sticky Flag Register 1 - 0x00 / 0x00 / 0x2A (B0_P0_R42)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
0
0
Left DAC Overflow Status. This sticky flag will self clear on read
0: No overflow in Left DAC
1: Overflow has happened in Left DAC since last read of this register
D6
Right DAC Overflow Status. This sticky flag will self clear on read
0: No overflow in Right DAC
1: Overflow has happened in Right DAC since last read of this register
D5
D4
D3
R
R
R
0
0
0
miniDSP_D Barrel Shifter Output Overflow Sticky Flag. Flag is reset on register reading
Reserved.
Left ADC Overflow Status. This sticky flag will self clear on read
0: No overflow in Left ADC
1: Overflow has happened in Left ADC since last read of this register
D2
R
0
Right ADC Overflow Status. This sticky flag will self clear on read
0: No overflow in Right ADC
1: Overflow has happened in Right ADC since last read of this register
D1
D0
R
R
0
0
miniDSP_A Barrel Shifter Output Overflow Sticky Flag. Flag is reset on register reading
Reserved. Write only reset values.
Book 0 / Page 0 / Register 43: Reserved Register - 0x00 / 0x00 / 0x2B (B0_P0_R43)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved Register
Book 0 / Page 0 / Register 44: Sticky Flag Register 2 - 0x00 / 0x00 / 0x2C (B0_P0_R44)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
0
0
0: No Short Circuit detected at HPL or SPL or RECP driver.
1: Short Circuit is detected at HPL or SPL or RECP driver. (will be cleared when the register is
read)
D6
0: No Short Circuit detected at HPR or SPR or RECM driver.
1: Short Circuit is detected at HPR or SPR or RECM driver. (will be cleared when the register is
read)
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Book 0 / Page 0 / Register 44: Sticky Flag Register 2 - 0x00 / 0x00 / 0x2C (B0_P0_R44) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5
R
0
Headset Button Press
0: Button Press not detected
1: Button Press detected (will be cleared when the register is read)
D4
R
0
Headset Insertion or Removal Detect Flag
0: Insertion or Removal event not detected
1: Insertion or Removal event detected (will be cleared when the register is read)
D3-D2
D1
R
R
R
00
0
Reserved.
miniDSP_D Standard Interrupt Port Output. This is a sticky bit
miniDSP_D Auxilliary Interrupt Port Output. This is a sticky bit
D0
0
Book 0 / Page 0 / Register 45: Sticky Flag Register 3 - 0x00 / 0x00 / 0x2D (B0_P0_R45)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
0: No over-temperature detected by Speaker driver.
1: Over-temperature detected by Speaker driver. (will be cleared when the register is read)
D6
D5
R
0
Left AGC Noise Threshold Flag
0: Signal Power is greater than Noise Threshold
1: Signal Power was lower than Noise Threshold (will be cleared when the register is read)
R
0
Right AGC Noise Threshold Flag
0: Signal Power is greater than Noise Threshold
1: Signal Power was lower than Noise Threshold (will be cleared when the register is read)
D4
D3
R
R
R
0
0
miniDSP_A Standard Interrupt Port Output. This is a sticky bit
miniDSP_A Auxilliary Interrupt Port Output. This is a sticky bit
Reserved.
D2-D0
000
Book 0 / Page 0 / Register 46-47: Reserved Register - 0x00 / 0x00 / 0x2E-0x2F (B0_P0_R46-47)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved Register
Book 0 / Page 0 / Register 48: INT1 Interrupt Control - 0x00 / 0x00 / 0x30 (B0_P0_R48)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
INT1 Interrupt for Headset Insertion Event
0: Headset Insertion event will not generate a INT1 interrupt
1: Headset Insertion even will generate a INT1 interrupt
D6
INT1 Interrupt for Button Press Event
0: Button Press event will not generate a INT1 interrupt
1: Button Press event will generate a INT1 interrupt
D5
D4
R/W
R/W
0
0
Reserved. Write only default value
INT1 Interrupt for AGC Noise Interrupt
0: Noise level detected by AGC will not generate a INT1 interrupt
1: Noise level detected by either off Left or Right Channel AGC will generate a INT1 interrupt.
Read B0_P0_R45 to distinguish between Left or Right Channel
D3
R/W
0
INT1 Interrupt for Over Current Condition
0: Headphone Over Current condition will not generate a INT1 interrupt.
1: Headphone Over Current condition on either off Left or Right Channels will generate a INT1
interrupt.
Read B0_P0_R44 to distinguish between HPL and HPR
D2
D1
R/W
R/W
0
0
INT1 Interrupt for miniDSP-generated interrupt or overflow event
0: Engine generated interrupts and Overflow flags do not result in a INT1 interrupt
1: Engine generated interrupts and Overflow flags will result in a INT1 interrupt.
Read B0_P0_R42 to distinguish between miniDSP_A or miniDSP_D interrupt
0: SPK over-tempeature detected Interrupt is not used in the generation of INT1 Interrupt
1: SPK over-tempeature detected Interrupt is used in the generation of INT1 Interrupt
140
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 48: INT1 Interrupt Control - 0x00 / 0x00 / 0x30 (B0_P0_R48) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D0
R
0
Reserved. Write only reset values.
Book 0 / Page 0 / Register 49: INT2 Interrupt Control - 0x00 / 0x00 / 0x31 (B0_P0_R49)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
INT2 Interrupt for Headset Insertion Event
0: Headset Insertion event will not generate a INT2 interrupt
1: Headset Insertion even will generate a INT2 interrupt
D6
INT2 Interrupt for Button Press Event
0: Button Press event will not generate a INT2 interrupt
1: Button Press event will generate a INT2 interrupt
D5
D4
R/W
R/W
0
0
Reserved. Write only default value
INT2 Interrupt for AGC Noise Interrupt
0: Noise level detected by AGC will not generate a INT2 interrupt
1: Noise level detected by either off Left or Right Channel AGC will generate a INT2 interrupt.
Read B0_P0_R45 to distinguish between Left or Right Channel
D3
D2
R/W
R/W
0
0
INT2 Interrupt for Over Current Condition
0: Headphone Over Current condition will not generate a INT2 interrupt.
1: Headphone Over Current condition on either off Left or Right Channels will generate a INT2
interrupt.
Read B0_P0_R44 to distinguish between HPL and HPR
INT2 Interrupt for miniDSP-generated interrupt or overflow event
0: Engine generated interrupts and Overflow flags do not result in a INT2 interrupt
1: Engine generated interrupts and Overflow flags will result in a INT2 interrupt.
Read B0_P0_R42 to distinguish between miniDSP_A or miniDSP_D interrupt
D1
D0
R/W
R
0
0
0: SPK over-tempeature detected Interrupt is not used in the generation of INT2 Interrupt
1: SPK over-tempeature detected Interrupt is used in the generation of INT2 Interrupt
Reserved. Write only reset values.
Book 0 / Page 0 / Register 50: SAR Control 1 - 0x00 / 0x00 / 0x32 (B0_P0_R50)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: If SAR measurement data out of threshold range, interrupt is not used in the generation of INT1
Interrupt.
1: If SAR measurement data out of threshold range, interrupt is used in the generation of INT1
Interrupt.
D6
D5
R/W
R/W
0
0
0: SAR Data Available Interrupt is not used in the generation of INT1 Interrupt.
1: SAR Data Available Interrupt is used in the generation of INT1 Interrupt.
0: SAR measurement data out of threshold range Interrupt is not used in the generation of INT2
Interrupt.
1: SAR measurement data out of threshold range Interrupt is used in the generation of INT2
Interrupt.
D4
R/W
0
0: SAR Data Available Interrupt is not used in the generation of INT2 Interrupt.
1: SAR Data Available Interrupt is used in the generation of INT2 Interrupt.
D3
D2
R
R
0
0
Reserved. Write only default values.
SAR Data Available Sticky Flag (will be cleared when the register is read)
0: No SAR Data Available for read.
1: SAR Data Available for read.
D1
D0
R
R
0
0
SAR Data Threshold Sticky Flag (will be cleared when the register is read)
0: SAR data is within threshold program.
1: SAR data is out of programmed threshold range.
Reserved. Write only default values.
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Book 0 / Page 0 / Register 51: Interrupt Format Control Register - 0x00 / 0x00 / 0x33 (B0_P0_R51)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
R/W
R
00
INT1 pulse control
00: INT1 is active high interrupt of 1 pulse of minimum 2ms duration
01: INT1 is active high interrupt of multiple pulses, each of minimum duration 2ms and a total
period of 4ms. To stop the pulse train, read B0_P0_R42, B0_P0_R44, or B0_P0_R45
10: INT1 is active high, level-based interrupt generated out of sticky bits in Flag registers. To clear
this interrupt, read B0_P0_R42, B0_P0_R44, or B0_P0_R45.
11: INT1 is active high, level-based interrupt generated out of instantaneous value of interrupt port.
D5-D4
D3-D0
00
INT2 pulse control
00: INT2 is active high interrupt of 1 pulse of approx. 2ms duration
01: INT2 is active high interrupt of multiple pulses, each of duration 2ms. To stop the pulse train,
read B0_P0_R42, B0_P0_R44, or B0_P0_R45
10: INT2 is active high, level-based interrupt generated out of sticky bits in Flag registers. To clear
this interrupt, read B0_P0_R42, B0_P0_R44, or B0_P0_R45.
11: INT2 is active high, level-based interrupt generated out of instantaneous value of interrupt port.
0000
Reserved. Write only reset values.
Book 0 / Page 0 / Register 52-59: Reserved Registers - 0x00 / 0x00 / 0x34-0x3B (B0_P0_R52-59)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 0 / Register 60: DAC Processing Block and miniDSP Power Control - 0x00 / 0x00 / 0x3C
(B0_P0_R60)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
0: miniDSP_A and miniDSP_D are independently powered up
1: miniDSP_A and miniDSP_D are powered up together. Useful when there is data transfer
between miniDSP_A and miniDSP_D
D6
miniDSP_D Power Configuration
0: miniDSP_D is powered down with DAC Channel Power Down
1: miniDSP_D is powered up if ADC Channel is powered up
D5
R
0
Reserved. Write only reset values.
D4-D0
R/W
0 0001
0 0000: The miniDSP_D will be used for signal processing
0 0001: DAC Signal Processing Block PRB_P1
0 0010: Do not use.
0 0011: DAC Signal Processing Block PRB_P3
0 0100-0 0101: Do not use.
0 0110: DAC Signal Processing Block PRB_P6
0 0111-1 1111: Do not use.
Book 0 / Page 0 / Register 61: ADC Processing Block Control - 0x00 / 0x00 / 0x3D (B0_P0_R61)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D0
R
000
Reserved. Write only reset values.
R/W
0 0001
0 0000: The miniDSP_A will be used for signal processing
0 0001: ADC Singal Processing Block PRB_R1
0 0010-0 0011: Do not use.
0 0100: ADC Signal Processing Block PRB_R4
0 0101-1 1111: Do not use.
Book 0 / Page 0 / Register 62: Reserved Register - 0x00 / 0x00 / 0x3E (B0_P0_R62)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
142
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 63: Primary DAC Power and Soft-Stepping Control - 0x00 / 0x00 / 0x3F
(B0_P0_R63)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: Left DAC channel is powered-down
1: Left DAC channel is powered-up
D6
R/W
0
0: Right DAC channel is powered-down
1: Right DAC channel is powered-up
D5-D2
D1-D0
R
00 00
00
Reserved. Write only reset values.
R/W
00: DAC channel volume control soft-stepping is enabled for one-step per Fs
01: DAC channel volume control soft-stepping is enabled for one-step per 2Fs
10: DAC channel volume control soft-stepping is disabled
11: Reserved. Do not use.
Book 0 / Page 0 / Register 64: Primary DAC Master Volume Configuration - 0x00 / 0x00 / 0x40
(B0_P0_R64)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
Right Modulator Output Control
0: When Right DAC Channel is powered down, the data is zero.
1: When Right DAC Channel is powered down, the data is inverted version of Left DAC Modulator
Output. Can be used when differential mono output is used
D6-D4
R/W
000
DAC Auto Mute Control
000: Auto Mute disabled
001: DAC is auto muted if input data is DC for more than 100 consecutive inputs
010: DAC is auto muted if input data is DC for more than 200 consecutive inputs
011: DAC is auto muted if input data is DC for more than 400 consecutive inputs
100: DAC is auto muted if input data is DC for more than 800 consecutive inputs
101: DAC is auto muted if input data is DC for more than 1600 consecutive inputs
110: DAC is auto muted if input data is DC for more than 3200 consecutive inputs
111: DAC is auto muted if input data is DC for more than 6400 consecutive inputs
D3
D2
R/W
R/W
R/W
1
1
Left DAC Channel Mute Control
0: Left DAC Channel not muted
1: Left DAC Channel muted
Right DAC Channel Mute Control
0: Right DAC Channel not muted
1: Right DAC Channel muted
D1-D0
00
DAC Master Volume Control
00: Left and Right Channel have independent volume control
01: Left Channel Volume is controlled by Right Channel Volume Control setting
10: Right Channel Volume is controlled by Left Channel Volume Control setting
11: Reserved. Do not use
Book 0 / Page 0 / Register 65: Primary DAC Left Volume Control Setting - 0x00 / 0x00 / 0x41 (B0_P0_R65)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Left DAC Channel Digital Volume Control Setting
0111 1111-0011 0001: Reserved. Do not use.
0011 0000: Digital Volume Control = +24dB
0010 1111: Digital Volume Control = +23.5dB
...
0000 0001: Digital Volume Control = +0.5dB
0000 0000: Digital Volume Control = 0.0dB
1111 1111: Digital Volume Control = -0.5dB
...
1000 0010: Digital Volume Control = -63dB
1000 0001: Digital Volume Control = -63.5dB
1000 0000: Reserved. Do not use.
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Book 0 / Page 0 / Register 66: Primary DAC Right Volume Control Setting - 0x00 / 0x00 / 0x42
(B0_P0_R66)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Right DAC Channel Digital Volume Control Setting
0111 1111-0011 0001: Reserved. Do not use.
0011 0000: Digital Volume Control = +24dB
0010 1111: Digital Volume Control = +23.5dB
...
0000 0001: Digital Volume Control = +0.5dB
0000 0000: Digital Volume Control = 0.0dB
1111 1111: Digital Volume Control = -0.5dB
...
1000 0010: Digital Volume Control = -63dB
1000 0001: Digital Volume Control = -63.5dB
1000 0000: Reserved. Do not use.
Book 0 / Page 0 / Register 67: Headset Detection - 0x00 / 0x00 / 0x43 (B0_P0_R67)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: Headset Detection Disabled
1: Headset Detection Enabled
D6-D5
D4-D2
R
00
Reserved. Write only reset values.
R/W
0 00
Headset Detection Debounce Programmability
000: Debounce Time = 16ms
001: Debounce Time = 32ms
010: Debounce Time = 64ms
011: Debounce Time = 128ms
100: Debounce Time = 256ms
101: Debounce Time = 512ms
110-111: Reserved. Do not use
Note: All times are typical values
D1-D0
R/W
00
Headset Button Press Debounce Programmability
00: Debounce disabled
01: Debounce Time = 8ms
10: Debounce Time = 16ms
11: Debounce Time = 32ms
Note: All times are typical values
Book 0 / Page 0 / Register 68: Reserved Register - 0x00 / 0x00 / 0x44 (B0_P0_R68)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0110 1111 Reserved. Write only reset values.
Book 0 / Page 0 / Register 69: Reserved Register - 0x00 / 0x00 / 0x45 (B0_P0_R69)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0011 1000 Reserved. Write only reset values.
Book 0 / Page 0 / Register 70: Reserved Register - 0x00 / 0x00 / 0x46 (B0_P0_R70)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000
Book 0 / Page 0 / Register 71-80: Reserved Registers - 0x00 / 0x00 / 0x47-0x50 (B0_P0_R71-80)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Do not write
144
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Book 0 / Page 0 / Register 81: ADC Channel Power Control - 0x00 / 0x00 / 0x51 (B0_P0_R81)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
R/W
0
0
Left Channel ADC Power Control
0: Left Channel ADC power down
1: Left Channel ADC power up
D6
Right Channel ADC Power Control
0: Right Channel ADC power down
1: Right Channel ADC power up
D5-D4
00
Left Channel Digital Microphone Power Control
00: Left Channel ADC not configured for Digital Microphone
01: Left Channel ADC configured for Digital Microphone
10: Left Channel DAC Modulator output fed thru ADC CIC Filter (Loopback)
11: Reserved. Do not use.
D3-D2
D1-D0
R/W
R/W
00
00
Right Channel Digital Microphone Power Control
00: Right Channel ADC not configured for Digital Microphone
01: Right Channel ADC configured for Digital Microphone
10: Right Channel DAC Modulator output fed thru ADC CIC Filter (Loopback)
11: Reserved. Do not use.
ADC Volume Control Soft-Stepping Control
00: ADC Volume Control changes by 1 gain step per ADC Word Clock
01: ADC Volume Control changes by 1 gain step per two ADC Word Clocks
10: ADC Volume Control Soft-Stepping disabled
11: Reserved. Do not use
Book 0 / Page 0 / Register 82: ADC Fine Gain Volume Control - 0x00 / 0x00 / 0x52 (B0_P0_R82)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
1
Left ADC Channel Mute Control
0: Left ADC Channel Un-Mute
1: Left ADC Channel Mute
D6-D4
000
Left ADC Channel Fine Gain Adjust
000: Left ADC Channel Fine Gain = 0 dB
111: Left ADC Channel Fine Gain = -0.1 dB
110: Left ADC Channel Fine Gain = -0.2 dB
101: Left ADC Channel Fine Gain = -0.3 dB
100: Left ADC Channel Fine Gain = -0.4 dB
001-011: Reserved. Do not use.
D3
R/W
R/W
1
Right ADC Channel Mute Control
0: Right ADC Channel Un-Mute
1: Right ADC Channel Mute
D2-D0
000
Right ADC Channel Fine Gain Adjust
000: Right ADC Channel Fine Gain = 0 dB
111: Right ADC Channel Fine Gain = -0.1 dB
110: Right ADC Channel Fine Gain = -0.2 dB
101: Right ADC Channel Fine Gain = -0.3 dB
100: Right ADC Channel Fine Gain = -0.4 dB
001-011: Reserved. Do not use.
Book 0 / Page 0 / Register 83: Left ADC Volume Control - 0x00 / 0x00 / 0x53 (B0_P0_R83)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
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Book 0 / Page 0 / Register 83: Left ADC Volume Control - 0x00 / 0x00 / 0x53 (B0_P0_R83) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
000 0000 Left ADC Channel Volume Control
000 0000-110 0111: Reserved. Do not use.
110 1000: Left ADC Channel Volume = -12.0 dB
110 1001: Left ADC Channel Volume = -11.5 dB
110 1010: Left ADC Channel Volume = -11.0 dB
…
111 1111: Left ADC Channel Volume = -0.5 dB
000 0000: Left ADC Channel Volume = 0.0 dB
000 0001: Left ADC Channel Volume = 0.5 dB
...
010 0110: Left ADC Channel Volume = 19.0 dB
010 0111: Left ADC Channel Volume = 19.5 dB
010 1000: Left ADC Channel Volume = 20.0 dB
010 1001-111 1111: Reserved. Do not use.
Book 0 / Page 0 / Register 84: Right ADC Volume Control - 0x00 / 0x00 / 0x54 (B0_P0_R84)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D0
R/W
000 0000 Right ADC Channel Volume Control
000 0000-110 0111: Reserved. Do not use.
110 1000: Right ADC Channel Volume = -12.0 dB
110 1001: Right ADC Channel Volume = -11.5 dB
110 1010: Right ADC Channel Volume = -11.0 dB
…
111 1111: Right ADC Channel Volume = -0.5 dB
000 0000: Right ADC Channel Volume = 0.0 dB
000 0001: Right ADC Channel Volume = 0.5 dB
...
010 0110: Right ADC Channel Volume = 19.0 dB
010 0111: Right ADC Channel Volume = 19.5 dB
010 1000: Right ADC Channel Volume = 20.0 dB
010 1001-111 1111: Reserved. Do not use.
Book 0 / Page 0 / Register 85: ADC Phase Control - 0x00 / 0x00 / 0x55 (B0_P0_R85)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 ADC Phase Compensation Control
1000 0000-1111 1111: Left ADC Channel Data is delayed with respect to Right ADC Channel
Data.
For details of delayed amount please refer to the description of Phase Compensation in the
Overview
section.
0000 0000: Left and Right ADC Channel data are not delayed with respect to each other
0000 0001-0111 1111: Right ADC Channel Data is delayed with respect to Left ADC Channel
Data.
For details of delayed amount please refer to the description of Phase Compensation in the
Overview section.
Book 0 / Page 0 / Register 86: Left AGC Control 1 - 0x00 / 0x00 / 0x56 (B0_P0_R86)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: Left Channel AGC Disabled
1: Left Channel AGC Enabled
146
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Book 0 / Page 0 / Register 86: Left AGC Control 1 - 0x00 / 0x00 / 0x56 (B0_P0_R86) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D4
R/W
000
Left Channel AGC Target Level Setting
000: Left Channel AGC Target Level = -5.5 dBFS
001: Left Channel AGC Target Level = -8.0 dBFS
010: Left Channel AGC Target Level = -10. 0dBFS
011: Left Channel AGC Target Level = -12.0 dBFS
100: Left Channel AGC Target Level = -14.0 dBFS
101: Left Channel AGC Target Level = -17.0 dBFS
110: Left Channel AGC Target Level = -20.0 dBFS
111: Left Channel AGC Target Level = -24.0 dBFS
D3-D2
D1-D0
R
00
00
Reserved. Write only reset values.
R/W
Left Channel AGC Gain Hysteresis Control
00: Left Channel AGC Gain Hysteresis is disabled
01: Left Channel AGC Gain Hysteresis is +/-0.5 dB
10: Left Channel AGC Gain Hysteresis is +/-1.0 dB
11: Left Channel AGC Gain Hysteresis is +/-1.5 dB
Book 0 / Page 0 / Register 87: Left AGC Control 2 - 0x00 / 0x00 / 0x57 (B0_P0_R87)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
00
Left Channel AGC Hysteresis Setting
00: Left Channel AGC Hysteresis is 1.0 dB
01: Left Channel AGC Hysteresis is 2.0 dB
10: Left Channel AGC Hysteresis is 4.0 dB
11: Left Channel AGC Hysteresis is disabled
D5-D1
R/W
0 0000
Left Channel AGC Noise Threshold
0 0000: Left Channel AGC Noise Gate disabled
0 0001: Left Channel AGC Noise Threshold is -30 dB
0 0010: Left Channel AGC Noise Threshold is -32 dB
0 0011: Left Channel AGC Noise Threshold is -34 dB
...
1 1101: Left Channel AGC Noise Threshold is -86 dB
1 1110: Left Channel AGC Noise Threshold is -88 dB
1 1111: Left Channel AGC Noise Threshold is -90 dB
D0
R
0
Reserved. Write only reset values.
Book 0 / Page 0 / Register 88: Left AGC Control 3 - 0x00 / 0x00 / 0x58 (B0_P0_R88)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D0
R/W
111 1111 Left Channel AGC Maximum Gain Setting
000 0000: Left Channel AGC Maximum Gain = 0.0 dB
000 0001: Left Channel AGC Maximum Gain = 0.5 dB
000 0010: Left Channel AGC Maximum Gain = 1.0 dB
...
111 1110: Left Channel AGC Maximum Gain = 63.0 dB
111 1111: Left Channel AGC Maximum Gain = 63.5 dB
Book 0 / Page 0 / Register 89: Left AGC Attack Time - 0x00 / 0x00 / 0x59 (B0_P0_R89)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
R/W
0000 0
Left Channel AGC Attack Time Setting
0 0000: Left Channel AGC Attack Time = 1*32 ADC Word Clocks
0 0001: Left Channel AGC Attack Time = 3*32 ADC Word Clocks
0 0010: Left Channel AGC Attack Time = 5*32 ADC Word Clocks
...
1 1101: Left Channel AGC Attack Time = 59*32 ADC Word Clocks
1 1110: Left Channel AGC Attack Time = 61*32 ADC Word Clocks
1 1111: Left Channel AGC Attack Time = 63*32 ADC Word Clocks
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Book 0 / Page 0 / Register 89: Left AGC Attack Time - 0x00 / 0x00 / 0x59 (B0_P0_R89) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D2-D0
R/W
000
Left Channel AGC Attack Time Scale Factor Setting
000: Scale Factor = 1
001: Scale Factor = 2
010: Scale Factor = 4
...
101: Scale Factor = 32
110: Scale Factor = 64
111: Scale Factor = 128
Book 0 / Page 0 / Register 90: Left AGC Decay Time - 0x00 / 0x00 / 0x5A (B0_P0_R90)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
R/W
0000 0
Left Channel AGC Decay Time Setting
0 0000: Left Channel AGC Decay Time = 1*512 ADC Word Clocks
0 0001: Left Channel AGC Decay Time = 3*512 ADC Word Clocks
0 0010: Left Channel AGC Decay Time = 5*512 ADC Word Clocks
...
1 1101: Left Channel AGC Decay Time = 59*512 ADC Word Clocks
1 1110: Left Channel AGC Decay Time = 61*512 ADC Word Clocks
1 1111: Left Channel AGC Decay Time = 63*512 ADC Word Clocks
D2-D0
R/W
000
Left Channel AGC Decay Time Scale Factor Setting
000: Scale Factor = 1
001: Scale Factor = 2
010: Scale Factor = 4
...
101: Scale Factor = 32
110: Scale Factor = 64
111: Scale Factor = 128
Book 0 / Page 0 / Register 91: Left AGC Noise Debounce - 0x00 / 0x00 / 0x5B (B0_P0_R91)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D0
R
000
Reserved. Write only reset values.
R/W
0 0000
Left Channel AGC Noise Debounce Time Setting
0 0001: Left Channel AGC Noise Debounce Time = 0
0 0010: Left Channel AGC Noise Debounce Time = 4 ADC Word Clocks
0 0011: Left Channel AGC Noise Debounce Time = 8 ADC Word Clocks
...
0 1010: Left Channel AGC Noise Debounce Time = 2048 ADC Word Clocks
0 1011: Left Channel AGC Noise Debounce Time = 4096 ADC Word Clocks
0 1100: Left Channel AGC Noise Debounce Time = 2*4096 ADC Word Clocks
0 1101: Left Channel AGC Noise Debounce Time = 3*4096 ADC Word Clocks
...
1 1101: Left Channel AGC Noise Debounce Time = 19*4096 ADC Word Clocks
1 1110: Left Channel AGC Noise Debounce Time = 20*4096 ADC Word Clocks
1 1111: Left Channel AGC Noise Debounce Time = 21*4096 ADC Word Clocks
Book 0 / Page 0 / Register 92: Left AGC Signal Debounce - 0x00 / 0x00 / 0x5C (B0_P0_R92)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R
0000
Reserved. Write only reset values.
148
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 92: Left AGC Signal Debounce - 0x00 / 0x00 / 0x5C (B0_P0_R92) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D0
R/W
0000
Left Channel AGC Signal Debounce Time Setting
0001: Left Channel AGC Signal Debounce Time = 0
0010: Left Channel AGC Signal Debounce Time = 4 ADC Word Clocks
0011: Left Channel AGC Signal Debounce Time = 8 ADC Word Clocks
...
1001: Left Channel AGC Signal Debounce Time = 1024 ADC Word Clocks
1010: Left Channel AGC Signal Debounce Time = 2048 ADC Word Clocks
1011: Left Channel AGC Signal Debounce Time = 2*2048 ADC Word Clocks
1100: Left Channel AGC Signal Debounce Time = 3*2048 ADC Word Clocks
1101: Left Channel AGC Signal Debounce Time = 4*2048 ADC Word Clocks
1110: Left Channel AGC Signal Debounce Time = 5*2048 ADC Word Clocks
1111: Left Channel AGC Signal Debounce Time = 6*2048 ADC Word Clocks
Book 0 / Page 0 / Register 93: Left AGC Gain - 0x00 / 0x00 / 0x5D (B0_P0_R93)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Left Channel AGC Gain
1110 1000: Left Channel AGC Gain = -12.0dB
1110 1001: Left Channel AGC Gain = -11.5dB
1110 1010: Left Channel AGC Gain = -11.0dB
...
0000 0000: Left Channel AGC Gain = 0.0dB
...
0111 1101: Left Channel AGC Gain = 62.5dB
0111 1110: Left Channel AGC Gain = 63.0dB
0111 1111: Left Channel AGC Gain = 63.5dB
Book 0 / Page 0 / Register 94: Right AGC Control 1 - 0x00 / 0x00 / 0x5E (B0_P0_R94)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: Right Channel AGC Disabled
1: Right Channel AGC Enabled
D6-D4
R/W
000
Right Channel AGC Target Level Setting
000: Right Channel AGC Target Level = -5.5 dBFS
001: Right Channel AGC Target Level = -8.0 dBFS
010: Right Channel AGC Target Level = -10.0 dBFS
011: Right Channel AGC Target Level = -12.0 dBFS
100: Right Channel AGC Target Level = -14.0 dBFS
101: Right Channel AGC Target Level = -17.0 dBFS
110: Right Channel AGC Target Level = -20.0 dBFS
111: Right Channel AGC Target Level = -24.0 dBFS
D3-D2
D1-D0
R
00
00
Reserved. Write only reset values.
R/W
Right Channel AGC Gain Hysteresis Control
00: Right Channel AGC Gain Hysteresis is disabled
01: Right Channel AGC Gain Hysteresis is +-0.5 dB
10: Right Channel AGC Gain Hysteresis is +-1.0 dB
11: Right Channel AGC Gain Hysteresis is +-1.5 dB
Book 0 / Page 0 / Register 95: Right AGC Control 2 - 0x00 / 0x00 / 0x5F (B0_P0_R95)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
00
Right Channel AGC Hysteresis Setting
00: Right Channel AGC Hysteresis is 1.0dB
01: Right Channel AGC Hysteresis is 2.0dB
10: Right Channel AGC Hysteresis is 4.0dB
11: Right Channel AGC Hysteresis is disabled
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Book 0 / Page 0 / Register 95: Right AGC Control 2 - 0x00 / 0x00 / 0x5F (B0_P0_R95) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D1
R/W
00 000
Right Channel AGC Noise Threshold
0 0000: Right Channel AGC Noise Gate disabled
0 0001: Right Channel AGC Noise Threshold is -30dB
0 0010: Right Channel AGC Noise Threshold is -32dB
0 0011: Right Channel AGC Noise Threshold is -34dB
...
1 1101: Right Channel AGC Noise Threshold is -86dB
1 1110: Right Channel AGC Noise Threshold is -88dB
1 1111: Right Channel AGC Noise Threshold is -90dB
D0
R
0
Reserved. Write only reset values.
Book 0 / Page 0 / Register 96: Right AGC Control 3 - 0x00 / 0x00 / 0x60 (B0_P0_R96)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D0
R/W
111 1111 Right Channel AGC Maximum Gain Setting
000 0000: Right Channel AGC Maximum Gain = 0.0dB
000 0001: Right Channel AGC Maximum Gain = 0.5dB
000 0010: Right Channel AGC Maximum Gain = 1.0dB
...
111 1110: Right Channel AGC Maximum Gain = 63.0dB
111 1111: Right Channel AGC Maximum Gain = 63.5dB
Book 0 / Page 0 / Register 97: Right AGC Attack Time - 0x00 / 0x00 / 0x61 (B0_P0_R97)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
R/W
0000 0
Right Channel AGC Attack Time Setting
0 0000: Right Channel AGC Attack Time = 1*32 ADC Word Clocks
0 0001: Right Channel AGC Attack Time = 3*32 ADC Word Clocks
0 0010: Right Channel AGC Attack Time = 5*32 ADC Word Clocks
...
1 1101: Right Channel AGC Attack Time = 59*32 ADC Word Clocks
1 1110: Right Channel AGC Attack Time = 61*32 ADC Word Clocks
1 1111: Right Channel AGC Attack Time = 63*32 ADC Word Clocks
D2-D0
R/W
000
Right Channel AGC Attack Time Scale Factor Setting
000: Scale Factor = 1
001: Scale Factor = 2
010: Scale Factor = 4
...
101: Scale Factor = 32
110: Scale Factor = 64
111: Scale Factor = 128
Book 0 / Page 0 / Register 98: Right AGC Decay Time - 0x00 / 0x00 / 0x62 (B0_P0_R98)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
R/W
0 0000
Right Channel AGC Decay Time Setting
0 0000: Right Channel AGC Decay Time = 1*512 ADC Word Clocks
0 0001: Right Channel AGC Decay Time = 3*512 ADC Word Clocks
0 0010: Right Channel AGC Decay Time = 5*512 ADC Word Clocks
...
1 1101: Right Channel AGC Decay Time = 59*512 ADC Word Clocks
1 1110: Right Channel AGC Decay Time = 61*512 ADC Word Clocks
1 1111: Right Channel AGC Decay Time = 63*512 ADC Word Clocks
150
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 98: Right AGC Decay Time - 0x00 / 0x00 / 0x62 (B0_P0_R98) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D2-D0
R/W
000
Right Channel AGC Decay Time Scale Factor Setting
000: Scale Factor = 1
001: Scale Factor = 2
010: Scale Factor = 4
...
101: Scale Factor = 32
110: Scale Factor = 64
111: Scale Factor = 128
Book 0 / Page 0 / Register 99: Right AGC Noise Debounce - 0x00 / 0x00 / 0x63 (B0_P0_R99)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D0
R
000
Reserved. Write only default values.
R/W
0 0000
Right Channel AGC Noise Debounce Time Setting
0 0001: Right Channel AGC Noise Debounce Time = 0
0 0010: Right Channel AGC Noise Debounce Time = 4 ADC Word Clocks
0 0011: Right Channel AGC Noise Debounce Time = 8 ADC Word Clocks
...
0 1010: Right Channel AGC Noise Debounce Time = 2048 ADC Word Clocks
0 1011: Right Channel AGC Noise Debounce Time = 4096 ADC Word Clocks
0 1100: Right Channel AGC Noise Debounce Time = 2*4096 ADC Word Clocks
0 1101: Right Channel AGC Noise Debounce Time = 3*4096 ADC Word Clocks
...
1 1101: Right Channel AGC Noise Debounce Time = 19*4096 ADC Word Clocks
1 1110: Right Channel AGC Noise Debounce Time = 20*4096 ADC Word Clocks
1 1111: Right Channel AGC Noise Debounce Time = 21*4096 ADC Word Clocks
Book 0 / Page 0 / Register 100: Right AGC Signal Debounce - 0x00 / 0x00 / 0x64 (B0_P0_R100)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3-D0
R
0000
0000
Reserved. Write only reset values.
R/W
Right Channel AGC Signal Debounce Time Setting
0001: Right Channel AGC Signal Debounce Time = 0
0010: Right Channel AGC Signal Debounce Time = 4 ADC Word Clocks
0011: Right Channel AGC Signal Debounce Time = 8 ADC Word Clocks
...
1001: Right Channel AGC Signal Debounce Time = 1024 ADC Word Clocks
1010: Right Channel AGC Signal Debounce Time = 2048 ADC Word Clocks
1011: Right Channel AGC Signal Debounce Time = 2*2048 ADC Word Clocks
1100: Right Channel AGC Signal Debounce Time = 3*2048 ADC Word Clocks
1101: Right Channel AGC Signal Debounce Time = 4*2048 ADC Word Clocks
1110: Right Channel AGC Signal Debounce Time = 5*2048 ADC Word Clocks
1111: Right Channel AGC Signal Debounce Time = 6*2048 ADC Word Clocks
Book 0 / Page 0 / Register 101: Right AGC Gain - 0x00 / 0x00 / 0x65 (B0_P0_R101)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Right Channel AGC Gain
1110 1000: Left Channel AGC Gain = -12.0dB
1110 1001: Left Channel AGC Gain = -11.5dB
1110 1010: Left Channel AGC Gain = -11.0dB
...
0000 0000: Left Channel AGC Gain = 0.0dB
...
0111 1101: Left Channel AGC Gain = 62.5dB
0111 1110: Left Channel AGC Gain = 63.0dB
0111 1111: Left Channel AGC Gain = 63.5dB
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Book 0 / Page 0 / Register 102-111: Reserved Registers - 0x00 / 0x00 / 0x66-0x6F (B0_P0_R102-111)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Reserved. Write only default values.
Book 0 / Page 0 / Register 112: Digital Microphone 2 Control - 0x00 / 0x00 / 0x70 (B0_P0_R112)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
R/W
0
0: CIC2 Left Channel is disabled
1: CIC2 Left Channel is enabled
D6
0
0: CIC2 Right Channel is disabled
1: CIC2 Right Channel is enabled
D5-D4
00
00: CIC2 Left Channel not in use (B0_P0_R112_D7 is set to '0')
01: Digital Microphone is fed to CIC2 Left Channel
10: Left DAC Modulator output is fed to CIC2 Left Channel
11: Reserved. Do not use.
D3-D2
D1-D0
R/W
R
00
00
00: CIC2 Right Channel not in use (B0_P0_R112_D6 is set to '0')
01: Digital Microphone is fed to CIC2 Right Channel
10: Right DAC Modulator output is fed to CIC2 Right Channel
11: Reserved. Do not use.
Reserved. Write only reset values.
Book 0 / Page 0 / Register 113-114: Reserved Registers - 0x00 / 0x00 / 0x71-0x72 (B0_P0_R113-114)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 0 / Register 115: I2C Interface Miscellaneous Control - 0x00 / 0x00 / 0x73 (B0_P0_R115)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
00
0
Reserved. Write only reset values.
R/W
I2C General Call Address Configuration
0: I2C General Call Address will be ignored
1: I2C General Call Address accepted
D4-D0
R
0 0000
Reserved. Write only reset values.
Book 0 / Page 0 / Register 116-119: Reserved Registers - 0x00 / 0x00 / 0x74-0x77 (B0_P0_R116-119)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Do not write.
Book 0 / Page 0 / Register 120: miniDSP Control Register access - 0x00 / 0x00 / 0x78 (B0_P0_R120)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: miniDSP does not have write access to control registers
1: miniDSP has write access to control registers
D6-D0
R/W
00 0000
Reserved. Write only default value
Book 0 / Page 0 / Register 121-126: Reserved Registers - 0x00 / 0x00 / 0x79-0x7E (B0_P0_R121-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Do not write
152
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 0 / Register 127: Book Selection Register - 0x00 / 0x00 / 0x7F (B0_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
8.6.3 Book 0 Page 1
Book 0 / Page 1 / Register 0: Page Select Register - 0x00 / 0x01 / 0x00 (B0_P1_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Book 0 / Page 1 / Register 1: Power Configuration Register - 0x00 / 0x01 / 0x01 (B0_P1_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3
R
0000
1
Reserved. Write only reset values.
R/W
0: Disable weak connection of AVDDx_18 with DVDD_18
1: AVDDx_18 is weakly connected to DVDD_18. Use when DVDD_18 is powered-up and
AVDDx_18 is not externally powered-up.
D2
R/W
R
1
0: All the external analog supplies are available.
1: All the external analog supplies are not available.
D1-D0
00
Reserved. Write only reset values.
Book 0 / Page 1 / Register 2: Reserved Register - 0x00 / 0x01 / 0x02 (B0_P1_R2)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 3: Left DAC PowerTune Configuration Register - 0x00 / 0x01 / 0x03 (B0_P1_R3)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D2
R
000
Reserved. Write only reset values.
R/W
0 00
Left DAC PTM Control
000: Left DAC in mode PTM_P3, PTM_P4
001: Left DAC in mode PTM_P2
010: Left DAC in mode PTM_P1
011-111: Reserved. Do not use
D1-D0
R
00
Reserved. Write only reset values.
Book 0 / Page 1 / Register 4: Right DAC PowerTune Configuration Register - 0x00 / 0x01 / 0x04
(B0_P1_R4)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D2
R
000
Reserved. Write only reset values.
Right DAC PTM Control
R/W
0 00
000: Right DAC in mode PTM_P3, PTM_P4
001: Right DAC in mode PTM_P2
010: Right DAC in mode PTM_P1
011-111: Reserved. Do not use
D1-D0
R
00
Reserved. Write only reset values.
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Book 0 / Page 1 / Register 5-7: Reserved Registers - 0x00 / 0x01 / 0x05-0x07 (B0_P1_R5-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 8: Common Mode Register - 0x00 / 0x01 / 0x08 (B0_P1_R8)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: Soft-stepping of all the PGA are enabled for DAC channel.
1: Soft-stepping of all the PGA are disabled for DAC channel.
D6
R/W
0
0: Normal Mode
1: Soft-stepping time for all the PGA of DAC channel is doubled.
D5
R
0
Reserved. Write only reset values.
D4-D3
R/W
00
00: Output Common Mode for HP (valid only if the cap-coupled mode is enabled) Output Drivers =
Input Common Mode
01: Output Common Mode for HP (valid only if the cap-coupled mode is enabled) Output Drivers =
1.25V
10: Output Common Mode for HP (valid only if the cap-coupled mode is enabled) Output Drivers =
1.5V
11: Output Common Mode for HP (valid only if the cap-coupled mode is enabled) Output Drivers =
1.65V
D2
R/W
R/W
0
0: Input Common Mode for full-chip (ADC and All Output Drivers except Receiver Output) = 0.9V
1: Input Common Mode for full-chip (ADC and All Output Drivers except Receiver Output) = 0.75V
D1-D0
00
00: Output Common Mode for REC Output Drivers = Input Common Mode
01: Output Common Mode for REC Output Drivers = 1.25V
10: Output Common Mode for REC Output Drivers = 1.5V
11: Output Common Mode for REC Output Drivers = 1.65V
Book 0 / Page 1 / Register 9: Headphone Output Driver Control - 0x00 / 0x01 / 0x09 (B0_P1_R9)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D5
R/W
00
00: Headphone Driver Output Stage is 100%.
01: Headphone Driver Output Stage is 75%.
10: Headphone Driver Output Stage is 50%.
11: Headphone Driver Output Stage is 25%.
D4
R
1
Reserved. Write only reset values.
D3-D1
R/W
000
Debounce Programming for Glitch Rejection during Short Circuit Detection
000: 0us
001: 8us
010: 16us
011: 32us
100: 64us
101: 128us
110: 256us
111: 512us
D0
R/W
0
HPL and HPR Over Current Response Control
0: If Over Current Detected Limit the current delivered by HPL and HPR
1: If Over Current Detected Power-Down the HPL and HPR driver.
Book 0 / Page 1 / Register 10: Receiver Output Driver Control - 0x00 / 0x01 / 0x0A (B0_P1_R10)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R
0001
Reserved. Write only reset values.
154
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Book 0 / Page 1 / Register 10: Receiver Output Driver Control - 0x00 / 0x01 / 0x0A
(B0_P1_R10) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D1
R/W
000
Debounce Programming for Glitch Rejection during Short Circuit Detection
000: 0us
001: 8us
010: 16us
011: 32us
100: 64us
101: 128us
110: 256us
111: 512us
D0
R/W
0
Receiver RECP and RECM Over-Current Response Control
0: If Over-Current Detected Limit the current.
1: If Over-Current Detected Power-Down the RECP and RECM driver
Book 0 / Page 1 / Register 11: Headphone Output Driver De-pop Control - 0x00 / 0x01 / 0x0B (B0_P1_R11)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
00
Headphone De-Pop Due to Input Offset Control (Note: Headphone depop control should only be
used in unipolar configuration. This control should be disabled in Ground-Centered Headphone
configuration.)
00: Disable
01: Enable (Duration = 50ms)
10: Enable (Duration = 100ms)
11: Enable (Duration = 200ms)
D5-D2
R/W
00 00
Headphone Output Driver De-Pop Control (Note: Headphone depop control should only be used in
unipolar configuration. This control should be disabled in Ground-Centered Headphone
configuration.)
0000: Disabled
0001: Enabled (Duration = 0.500*RC)
0010: Enabled (Duration = 0.625*RC)
0011: Enabled (Duration = 0.750*RC}
0100: Enabled (Duration = 0.875*RC)
0101: Enabled (Duration = 1.000*RC)
0110: Enabled (Duration = 2.000*RC)
0111: Enabled (Duration = 3.000*RC)
1000: Enabled (Duration = 4.000*RC)
1001: Enabled (Duration = 5.000*RC)
1010: Enabled (Duration = 6.000*RC)
1011: Enabled (Duration = 7.000*RC)
1100: Enabled (Duration = 8.000*RC)
1101: Enabled (Duration = 16.000*RC - do not use for Rchg=25K)
1110: Enabled (Duration = 24.000*RC - do not use for Rchg=25K)
1111: Enabled (Duration = 32.000*RC - do not use for Rchg=25K)
D1-D0
R/W
00
Headphone De-Pop Scheme Duration Based on RC Delay Control
00: Internal R = 25K typical and C is external cap.assumed to be 47uF
01: Internal R = 6K typical and C is external cap. assumed to be 47uF
10: Internal R = 2K typical and C is external cap. assumed to be 47uF
11: Reserved.
Book 0 / Page 1 / Register 12: Receiver Output Driver De-Pop Control - 0x00 / 0x01 / 0x0C (B0_P1_R12)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
00
Receiver De-Pop Due to Input Offset Control
00: Disable
01: Enable (Duration = 50ms)
10: Enable (Duration = 100ms)
11: Enable (Duration = 200ms)
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Book 0 / Page 1 / Register 12: Receiver Output Driver De-Pop Control - 0x00 / 0x01 / 0x0C
(B0_P1_R12) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D2
R/W
00 00
Receiver Output Driver De-Pop Control
0000: Disabled
0001: Enabled (Duration = 0.500*RC)
0010: Enabled (Duration = 0.625*RC)
0011: Enabled (Duration = 0.750*RC}
0100: Enabled (Duration = 0.875*RC)
0101: Enabled (Duration = 1.000*RC)
0110: Enabled (Duration = 2.000*RC)
0111: Enabled (Duration = 3.000*RC)
1000: Enabled (Duration = 4.000*RC)
1001: Enabled (Duration = 5.000*RC)
1010: Enabled (Duration = 6.000*RC)
1011: Enabled (Duration = 7.000*RC)
1100: Enabled (Duration = 8.000*RC)
1101: Enabled (Duration = 16.000*RC - do not use for Rchg=25K)
1110: Enabled (Duration = 24.000*RC - do not use for Rchg=25K)
1111: Enabled (Duration = 32.000*RC - do not use for Rchg=25K)
D1-D0
R/W
00
Receiver De-Pop Scheme Duration Based on RC Delay Control
00: Internal R = 25K typical and C is external cap.assumed to be 47uF
01: Internal R = 6K typical and C is external cap. assumed to be 47uF
10: Internal R = 2K typical and C is external cap. assumed to be 47uF
11: Reserved.
Book 0 / Page 1 / Register 13-16: Reserved Registers - 0x00 / 0x01 / 0x0D-0x10 (B0_P1_R13-16)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 17: Mixer Amplifier Control - 0x00 / 0x01 / 0x11 (B0_P1_R17)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
00
0
Reserved. Write only reset values.
R/W
IN1L to Mixer Amplifier Left (MAL) Routing Control
0: IN1L input for high-impedance mode is not routed to MAL
1: IN1L input for high-impedance mode is routed to MAL
D4
D3
R/W
R/W
R/W
R
0
0
IN1R to Mixer Amplifier Right (MAR) Routing Control
0: IN1R input for high-impedance mode is not routed to MAR
1: IN1R input for high-impedance mode is routed to MAR
Mixer Amp Left (MAL) Power Control
0: MAL is powered down
1: MAL is powered up
D2
0
Mixer Amp Right (MAR) Power Control
0: MAR is powered down
1: MAR is powered up
D1-D0
00
Reserved. Write only reset values.
Book 0 / Page 1 / Register 18: Left ADC PGA to Left Mixer Amplifier (MAL) Volume Control - 0x00 / 0x01 /
0x12 (B0_P1_R18)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R
00
Reserved. Write only reset values.
156
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Book 0 / Page 1 / Register 18: Left ADC PGA to Left Mixer Amplifier (MAL) Volume Control - 0x00 / 0x01 /
0x12 (B0_P1_R18) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D0
R/W
11 1111
Left ADC PGA Output Routed to Left Mixer Amplifier (MAL) Volume Control:
00 0000: Volume Control = 0.0 dB
00 0001: Volume Control = -0.4 dB
00 0010: Volume Control = -0.9 dB
00 0011: Volume Control = -1.3 dB
00 0100: Volume Control = -1.8 dB
00 0101: Volume Control = -2.3 dB
00 0110: Volume Control = -2.9 dB
00 0111: Volume Control = -3.3 dB
00 1000: Volume Control = -3.9 dB
00 1001: Volume Control = -4.3 dB
00 1010: Volume Control = -4.8 dB
00 1011: Volume Control = -5.2 dB
00 1100: Volume Control = -5.8 dB
00 1101: Volume Control = -6.3 dB
00 1110: Volume Control = -6.6 dB
00 1111: Volume Control = -7.2 dB
01 0000: Volume Control = -7.8 dB
01 0001: Volume Control = -8.2 dB
01 0010: Volume Control = -8.5 dB
01 0011: Volume Control = -9.3 dB
01 0100: Volume Control = -9.7 dB
01 0101: Volume Control = -10.1 dB
01 0110: Volume Control = -10.6 dB
01 0111: Volume Control = -11.0 dB
01 1000: Volume Control = -11.5 dB
01 1001: Volume Control = -12.0 dB
01 1010: Volume Control = -12.6 dB
01 1011: Volume Control = -13.2 dB
01 1100: Volume Control = -13.8 dB
01 1101: Volume Control = -14.5 dB
01 1110: Volume Control = -15.3 dB
01 1111: Volume Control = -16.1 dB
10 0000: Volume Control = -17.0 dB
10 0001: Volume Control = -18.1 dB
10 0010: Volume Control = -19.2 dB
10 0011: Volume Control = -20.6 dB
10 0100: Volume Control = -22.1 dB
10 0101: Volume Control = -24.1 dB
10 0110: Volume Control = -26.6 dB
10 0111: Volume Control = -30.1 dB
10 1000: Volume Control = -36.1 dB
10 1001 - 11 1110: Reserved
11 1111: Left ADC PGA output is not routed to Left Mixer Amplifier (MAL)
Book 0 / Page 1 / Register 19: Right ADC PGA to Right Mixer Amplifier (MAR) Volume Control - 0x00 /
0x01 / 0x13 (B0_P1_R19)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R
0
0
0: Use the Right ADC PGA output routing setting to MAR as defined in this Register D5-D0
1: Use the Right ADC PGA output routing setting to MAR same as defined for Left ADC PGA in
Page 1, Register 18, bits D5-D0 (previous register)
D6
Reserved. Write only reset values.
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Book 0 / Page 1 / Register 19: Right ADC PGA to Right Mixer Amplifier (MAR) Volume Control - 0x00 /
0x01 / 0x13 (B0_P1_R19) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D0
R/W
11 1111
Right ADC PGA Output Routed to Right Mixer Amplifier Volume Control:
00 0000: Volume Control = 0.0 dB
00 0001: Volume Control = -0.4 dB
00 0010: Volume Control = -0.9 dB
00 0011: Volume Control = -1.3 dB
00 0100: Volume Control = -1.8 dB
00 0101: Volume Control = -2.3 dB
00 0110: Volume Control = -2.9 dB
00 0111: Volume Control = -3.3 dB
00 1000: Volume Control = -3.9 dB
00 1001: Volume Control = -4.3 dB
00 1010: Volume Control = -4.8 dB
00 1011: Volume Control = -5.2 dB
00 1100: Volume Control = -5.8 dB
00 1101: Volume Control = -6.3 dB
00 1110: Volume Control = -6.6 dB
00 1111: Volume Control = -7.2 dB
01 0000: Volume Control = -7.8 dB
01 0001: Volume Control = -8.2 dB
01 0010: Volume Control = -8.5 dB
01 0011: Volume Control = -9.3 dB
01 0100: Volume Control = -9.7 dB
01 0101: Volume Control = -10.1 dB
01 0110: Volume Control = -10.6 dB
01 0111: Volume Control = -11.0 dB
01 1000: Volume Control = -11.5 dB
01 1001: Volume Control = -12.0 dB
01 1010: Volume Control = -12.6 dB
01 1011: Volume Control = -13.2 dB
01 1100: Volume Control = -13.8 dB
01 1101: Volume Control = -14.5 dB
01 1110: Volume Control = -15.3 dB
01 1111: Volume Control = -16.1 dB
10 0000: Volume Control = -17.0 dB
10 0001: Volume Control = -18.1 dB
10 0010: Volume Control = -19.2 dB
10 0011: Volume Control = -20.6 dB
10 0100: Volume Control = -22.1 dB
10 0101: Volume Control = -24.1dB
10 0110: Volume Control = -26.6dB
10 0111: Volume Control = -30.1dB
10 1000: Volume Control = -36.1dB
10 1001 - 11 1110: Reserved
11 1111: Right ADC PGA output is not routed to Right Mixer Amplifer (MAR)
Book 0 / Page 1 / Register 20-21: Reserved Registers - 0x00 / 0x01 / 0x14-0x15 (B0_P1_R20-21)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 22: Lineout Amplifier Control 1 - 0x00 / 0x01 / 0x16 (B0_P1_R22)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
Left DAC to LOL Driver Routing Control:
0: Left DAC is not routed to LOL driver.
1: Left DAC M-terminal is routed to LOL driver.
D6
Right DAC to LOR Driver Routing Control:
0: Right DAC is not routed to LOR driver.
1: Right DAC M-terminal is routed to LOR driver.
158
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Book 0 / Page 1 / Register 22: Lineout Amplifier Control 1 - 0x00 / 0x01 / 0x16 (B0_P1_R22) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5
R/W
0
Right DAC to LOL Driver Routing Control:
0: Right DAC is not routed to LOL driver.
1: Right DAC P-terminal is routed to LOL driver.(This is provided to support differential DAC output
to LO and should be done only when B0_P1_R22_D6=1 and B0_P1_R27_D4=0)
D4-D3
D2
R
0 0
0
Reserved. Write only reset values.
R/W
LOL to LOR Driver Routing Control:
0: LOL output not routed to LOR driver.
1: LOL output routed to LOR driver.
D1
D0
R/W
R/W
0
0
LOL Output Driver Power Control:
0: LOL output driver power-down
1: LOL output driver power-up
LOR Output Driver Power Control:
0: LOR output driver power-down
1: LOR output driver power-up
Book 0 / Page 1 / Register 23: Lineout Amplifier Control 2 - 0x00 / 0x01 / 0x17 (B0_P1_R23)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
Left Mixer Amplifier to LOL Driver Routing Control:
0: MAL output is not routed to LOL driver.
1: MAL output is routed to LOL driver.
D6
Right Mixer Amplifier to LOR Driver Routing Control:
0: MAR output is not routed to LOR driver.
1: MAR output is routed to LOR driver.
D5
R
0
Reserved. Write only reset values.
D4-D3
R/W
0 0
IN1L Input to LOL Driver Routing and Gain Control:
00: IN1L input is not routed to LOL driver.
01: IN1L input is routed to LOL driver with gain = 0dB
10: IN1L input is routed to LOL driver with gain = -6dB
11: IN1L input is routed to LOL driver with gain = -12dB
D2
R
0
Reserved. Write only reset values.
D1-D0
R/W
00
IN1R Input to LOR Driver Routing and Gain Control:
00: IN1R input is not routed to LOR driver.
01: IN1R input is routed to LOR driver with gain = 0dB
10: IN1R input is routed to LOR driver with gain = -6dB
11: IN1R input is routed to LOR driver with gain = -12dB
Book 0 / Page 1 / Register 24-26: Reserved - 0x00 / 0x01 / 0x18-0x1A (B0_P1_R24-26)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 27: Headphone Amplifier Control 1 - 0x00 / 0x01 / 0x1B (B0_P1_R27)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
R/W
R/W
0
0
0
0
Left Mixer Amplifier to HPL Driver Routing Control:
0: MAL output is not routed to HPL driver.
1: MAL output is routed to HPL driver.
D6
D5
D4
Right Mixer Amplifier to HPL Driver Routing Control:
0: MAR output is not routed to HPR driver.
1: MAR output is routed to HPR driver.
Left DAC to HPL Driver Routing Control:
0: Left DAC is not routed to HPL driver.
1: Left DAC is routed to HPL driver.
Right DAC to HPR Driver Routing Control:
0: Right DAC is not routed to HPR driver.
1: Right DAC is routed to HPR driver.
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Book 0 / Page 1 / Register 27: Headphone Amplifier Control 1 - 0x00 / 0x01 / 0x1B
(B0_P1_R27) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3
D2
R
0
0
Reserved. Write only reset values.
R/W
Left DAC to HPR Driver Routing Control:
0: Left DAC is not routed to HPR driver.
1: Left DAC M-terminal is routed to HPR driver. (This is provided to support differential DAC output
for HP and should be done only when B0_P1_R27_D5=1 and B0_P1_R22_D7=0)
D1
D0
R/W
R/W
0
0
HPL Output Driver Power Control:
0: HPL output driver is powered down
1: HPL output driver is powered up
HPR Output Driver Power Control:
0: HPR output driver is powered down
1: HPR output driver is powered up
Book 0 / Page 1 / Register 28: Headphone Amplifier Control 2 - 0x00 / 0x01 / 0x1C (B0_P1_R28)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
160
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 28: Headphone Amplifier Control 2 - 0x00 / 0x01 / 0x1C
(B0_P1_R28) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 LOL Output Routed to HPL Driver Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
Copyright © 2014, Texas Instruments Incorporated
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Book 0 / Page 1 / Register 28: Headphone Amplifier Control 2 - 0x00 / 0x01 / 0x1C
(B0_P1_R28) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0010: Volume Control = -33.1 dB
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: LOL Output Not Routed to HPL Driver (Default)
Book 0 / Page 1 / Register 29: Headphone Amplifier Control 3 - 0x00 / 0x01 / 0x1D (B0_P1_R29)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
LOR Output to HPR Driver Master Volume Control
0: LOL to HPL and LOR to HPR Volume are Independently Controlled
1: LOL to HPL and LOR to HPR Volume are Both Controlled by Page 1, Register 28, bits D6-D0
162
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 29: Headphone Amplifier Control 3 - 0x00 / 0x01 / 0x1D
(B0_P1_R29) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 LOR Output Routed to HPR Driver Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
Copyright © 2014, Texas Instruments Incorporated
163
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Book 0 / Page 1 / Register 29: Headphone Amplifier Control 3 - 0x00 / 0x01 / 0x1D
(B0_P1_R29) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0010: Volume Control = -33.1 dB
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: LOR Output Not Routed to HPR Driver (Default)
Book 0 / Page 1 / Register 30: Reserved Register - 0x00 / 0x01 / 0x1E (B0_P1_R30)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
164
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 31: HPL Driver Volume Control - 0x00 / 0x01 / 0x1F (B0_P1_R31)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
1
Headphone Configuration:
0: Headphone driver is configured for unipolar or cap-coupled mode.
1: Headphone driver is configured for ground-centered mode. B0_P1_R8_D[4:3] should be set to
"00".
D6
R
0
Reserved. Write only reset values.
D5-D0
R/W
11 1001
HPL Driver Gain Control:
Do not change after HP amp power-up
10 0000 - 11 1000: Reserved. Do not use.
11 1001: Output is Muted (Default)
11 1010: Gain = -6 dB
11 1011: Gain = -5 dB
11 1100: Gain = -4 dB
11 1101: Gain = -3 dB
11 1110: Gain = -2 dB
11 1111: Gain = -1 dB
00 0000: Gain = 0 dB
00 0001: Gain = 1 dB
00 0010: Gain = 2 dB
00 0011: Gain = 3 dB
00 0100: Gain = 4 dB
00 0101: Gain = 5 dB
00 0110: Gain = 6 dB
00 0111: Gain = 7 dB
00 1000: Gain = 8 dB
00 1001: Gain = 9 dB
00 1010: Gain = 10 dB
00 1011: Gain = 11 dB
00 1100: Gain = 12 dB
00 1101: Gain = 13 dB
00 1110: Gain = 14 dB
001111 - 111111: Reserved. Do not use.
Book 0 / Page 1 / Register 32: HPR Driver Volume Control - 0x00 / 0x01 / 0x20 (B0_P1_R32)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
1
Headphone Right (HPR) Driver Configuration:
0: Use the HPR driver volume setting as defined in B0_P1_R32_D[5:0]. (Only to be used in
unipolar or cap-coupled configuration)
1: Use the HPR driver volume setting as defined as same as the HPL volume of
B0_P1_R31_D[5:0].
D6
R
0
Reserved. Write only reset values.
Copyright © 2014, Texas Instruments Incorporated
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www.ti.com.cn
Book 0 / Page 1 / Register 32: HPR Driver Volume Control - 0x00 / 0x01 / 0x20 (B0_P1_R32) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D0
R/W
11 1001
HPR Driver Volume Control (Only used in Unipolar o rCap-Coupled Configuration):
10 0000 - 11 1000: Reserved. Do not use.
11 1001: Volume Control is Muted (Default)
11 1010: Volume Control = -6 dB
11 1011: Volume Control = -5 dB
11 1100: Volume Control = -4 dB
11 1101: Volume Control = -3 dB
11 1110: Volume Control = -2 dB
11 1111: Volume Control = -1 dB
00 0000: Volume Control = 0 dB
00 0001: Volume Control = 1 dB
00 0010: Volume Control = 2 dB
00 0011: Volume Control = 3 dB
00 0100: Volume Control = 4 dB
00 0101: Volume Control = 5 dB
00 0110: Volume Control = 6 dB
00 0111: Volume Control = 7 dB
00 1000: Volume Control = 8 dB
00 1001: Volume Control = 9 dB
00 1010: Volume Control = 10 dB
00 1011: Volume Control = 11 dB
00 1100: Volume Control = 12 dB
00 1101: Volume Control = 13 dB
00 1110: Volume Control = 14 dB
001111 - 111111: Reserved. Do not use.
Book 0 / Page 1 / Register 33: Reserved Register - 0x00 / 0x01 / 0x21 (B0_P1_R33)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0010 1000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 34: Reserved Register - 0x00 / 0x01 / 0x22 (B0_P1_R34)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0011 1110 Reserved. Write only reset values.
Book 0 / Page 1 / Register 35: Ground Centered Headphone Offset Correction Control - 0x00 / 0x01 / 0x23
(B0_P1_R35)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
00
0
Reserved. Write only reset values.
R/W
Ground Centered Headphone Offset Calibration
0: For ground-centered headphone amplifier, offset correction happens only for first power-up of
amplifier after hardware reset
1: For ground-centered headphone amplifier, offset correction happens at every power-up of
headphone amplifier
D4-D0
R
1 0000
Reserved. Write only reset values.
Book 0 / Page 1 / Register 36: Receiver Amplifier Control 1 - 0x00 / 0x01 / 0x24 (B0_P1_R36)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
166
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 36: Receiver Amplifier Control 1 - 0x00 / 0x01 / 0x24 (B0_P1_R36) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 LOL Output Routed to RECP Driver Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
100 0010: Volume Control = -33.1 dB
Copyright © 2014, Texas Instruments Incorporated
167
TLV320AIC3268
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www.ti.com.cn
Book 0 / Page 1 / Register 36: Receiver Amplifier Control 1 - 0x00 / 0x01 / 0x24 (B0_P1_R36) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: LOL Output Not Routed to RECP Driver (Default)
Book 0 / Page 1 / Register 37: Receiver Amplifier Control 2 - 0x00 / 0x01 / 0x25 (B0_P1_R37)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
LOR Output to RECM Driver Master Volume Control
0: LOL to RECP and LOR to RECM Volume are Independently Controlled
1: LOL to RECP and LOR to RECM Volume are Both Controlled by B0_P1_R36_D[6:0]. Should
only be used when load of receiver amplifier is differential.
168
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 37: Receiver Amplifier Control 2 - 0x00 / 0x01 / 0x25 (B0_P1_R37) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 LOR Output Routed to RECM Driver Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
100 0010: Volume Control = -33.1 dB
Copyright © 2014, Texas Instruments Incorporated
169
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www.ti.com.cn
Book 0 / Page 1 / Register 37: Receiver Amplifier Control 2 - 0x00 / 0x01 / 0x25 (B0_P1_R37) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: LOR Output Not Routed to RECM Driver (Default)
Book 0 / Page 1 / Register 38: Receiver Amplifier Control 3 - 0x00 / 0x01 / 0x26 (B0_P1_R38)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
170
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 38: Receiver Amplifier Control 3 - 0x00 / 0x01 / 0x26 (B0_P1_R38) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 IN1L Input Routed to RECP Driver Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
100 0010: Volume Control = -33.1 dB
Copyright © 2014, Texas Instruments Incorporated
171
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Book 0 / Page 1 / Register 38: Receiver Amplifier Control 3 - 0x00 / 0x01 / 0x26 (B0_P1_R38) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: IN1L Input Not Routed to RECP Driver (Default)
Book 0 / Page 1 / Register 39: Receiver Amplifier Control 4 - 0x00 / 0x01 / 0x27 (B0_P1_R39)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
IN1L Input to RECP and IN1R Input to RECM Driver Master Volume Control
0: IN1L to RECP and IN1R to RECM Volume are Independently Controlled
1: IN1L to RECP and INI1R to RECM Volume are Both Controlled by B0_P1_R38_D[6:0]. Should
only be used when load of receiver amplifier is differential.
172
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 39: Receiver Amplifier Control 4 - 0x00 / 0x01 / 0x27 (B0_P1_R39) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 IN1R Input Routed to RECM Driver Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
100 0010: Volume Control = -33.1 dB
Copyright © 2014, Texas Instruments Incorporated
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Book 0 / Page 1 / Register 39: Receiver Amplifier Control 4 - 0x00 / 0x01 / 0x27 (B0_P1_R39) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: IN1R Input Not Routed to RECM Driver (Default)
Book 0 / Page 1 / Register 40: Receiver Amplifier Control 5 - 0x00 / 0x01 / 0x28 (B0_P1_R40)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
RECP Output Driver Power Control
0: RECP Output Driver Power-Down
1: RECP Output Driver Power-Up
D6
RECM Output Driver Power Control
0: RECM Output Driver Power-Down
1: RECM Output Driver Power-Up
174
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 40: Receiver Amplifier Control 5 - 0x00 / 0x01 / 0x28 (B0_P1_R40) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D0
R/W
11 1001
RECP Driver Volume Control:
10 0000 - 11 1000: Reserved. Do not use.
11 1001: Volume Control is Muted (Default)
11 1010: Volume Control = -6 dB
11 1011: Volume Control = -5 dB
11 1100: Volume Control = -4 dB
11 1101: Volume Control = -3 dB
11 1110: Volume Control = -2 dB
11 1111: Volume Control = -1 dB
00 0000: Volume Control = 0 dB
00 0001: Volume Control = 1 dB
00 0010: Volume Control = 2 dB
...
01 1100: Volume Control = 28 dB
01 1101: Volume Control = 29 dB
Book 0 / Page 1 / Register 41: Receiver Amplifier Control 6 - 0x00 / 0x01 / 0x29 (B0_P1_R41)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
1
Receiver Master Volume Control
0: RECP and RECM Volume are Independently Controlled
1: RECP and RECM Volume are Both Controlled by B0_P1_R40_D[5:0]. Should only be used
when load of receiver amplifier is differential.
D6
R
0
Reserved. Write only reset values.
D5-D0
R/W
11 1001
RECM Driver Volume Control:
10 0000 - 11 1000: Reserved. Do not use.
11 1001: Volume Control is Muted (Default)
11 1010: Volume Control = -6 dB
11 1011: Volume Control = -5 dB
11 1100: Volume Control = -4 dB
11 1101: Volume Control = -3 dB
11 1110: Volume Control = -2 dB
11 1111: Volume Control = -1 dB
00 0000: Volume Control = 0 dB
00 0001: Volume Control = 1 dB
00 0010: Volume Control = 2 dB
...
01 1100: Volume Control = 28 dB
01 1101: Volume Control = 29 dB
Book 0 / Page 1 / Register 42: Receiver Amplifier Control 7 - 0x00 / 0x01 / 0x2A (B0_P1_R42)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
0
Receiver Amplifier Offset Calibration Flag
0: Offset Calibration is Not Done
1: Offset Calibration is Done
D6
D5
R/W
R/W
R/W
Left DAC Routing to RECP:
0: Left DAC is not routed to RECP
1: Left DAC P-terminal is routed to RECP
0
Left DAC Routing to RECM:
0: Left DAC is not routed to RECM
1: Left DAC M-terminal is routed to RECM
D4-D3
0 1
Receiver Amplifier Offset Calibration Control
00: Offset calibration is disabled
01: Force calibrate for offset at receiver amp power-up for routings selected (Default)
10: Calibrate for offset at receiver amp power-up for selected routings only for the first-power-up of
receiver amp.
11: Reserved
D2-D0
R/W
000
Reserved. Write only default value.
Copyright © 2014, Texas Instruments Incorporated
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Book 0 / Page 1 / Register 43-44: Reserved Registers - 0x00 / 0x01 / 0x2B-0x2C (B0_P1_R43-44)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 45: Speaker Amplifier Control 1 - 0x00 / 0x01 / 0x2D (B0_P1_R45)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
Left Mixer Amplifier (MAL) to Speaker Driver (SPK) Routing Control:
0: MAL output is not routed to SPK driver.
1: MAL output is routed to SPK driver.
D6
Right Mixer Amplifier (MAR) to Speaker Driver (SPK_RIGHT_CH_IN) Routing Control:
0: MAR output is not routed to SPK_RIGHT_CH_IN.
1: MAR output is routed to SPK_RIGHT_CH_IN.
D5-D3
D2
R
0
0
Reserved. Write only reset values.
R/W
Mono Speaker Control:
0: SPK_RIGHT_CH_IN is not routed to Speaker Driver (SPK).
1: SPK_RIGHT_CH_IN is routed to Speaker Driver (SPK).
D1
D0
R/W
R
0
0
Speaker Driver Power Control:
0: SPK Driver Power-Down
1: SPK Driver Power-Up
Reserved. Write only reset values.
Book 0 / Page 1 / Register 46: Speaker Amplifier Control 2 - 0x00 / 0x01 / 0x2E (B0_P1_R46)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
176
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 46: Speaker Amplifier Control 2 - 0x00 / 0x01 / 0x2E (B0_P1_R46) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 LOL Output Routed to SPK Driver Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
100 0010: Volume Control = -33.1 dB
Copyright © 2014, Texas Instruments Incorporated
177
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www.ti.com.cn
Book 0 / Page 1 / Register 46: Speaker Amplifier Control 2 - 0x00 / 0x01 / 0x2E (B0_P1_R46) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: LOL Output Not Routed to SPK Driver (Default)
Book 0 / Page 1 / Register 47: Speaker Amplifier Control 3 - 0x00 / 0x01 / 0x2F (B0_P1_R47)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
LOL Output to SPK and LOR Output to SPK_RIGHT_CH_IN Master Volume Control
0: LOL Output to SPK and LOR Output to SPK_RIGHT_CH_IN Volume are Independently
Controlled
1: LOL Output to SPK and LOR Output to SPK_RIGHT_CH_IN Volume are Both Controlled by
B0_P1_R46_D[6:0]
178
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Book 0 / Page 1 / Register 47: Speaker Amplifier Control 3 - 0x00 / 0x01 / 0x2F (B0_P1_R47) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
111 1111 LOR Output Routed to SPK_RIGHT_CH_IN Volume Control:
000 0000: Volume Control = 0.00 dB
000 0001: Volume Control = -0.5 dB
000 0010: Volume Control = -1.0 dB
000 0011: Volume Control = -1.5 dB
000 0100: Volume Control = -2.0 dB
000 0101: Volume Control = -2.5 dB
000 0110: Volume Control = -3.0 dB
000 0111: Volume Control = -3.5 dB
000 1000: Volume Control = -4.0 dB
000 1001: Volume Control = -4.5 dB
000 1010: Volume Control = -5.0 dB
000 1011: Volume Control = -5.5 dB
000 1100: Volume Control = -6.0 dB
000 1101: Volume Control = -6.5 dB
000 1110: Volume Control = -7.0 dB
000 1111: Volume Control = -7.5 dB
001 0000: Volume Control = -8.0 dB
001 0001: Volume Control = -8.5 dB
001 0010: Volume Control = -9.0 dB
001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB
001 0101: Volume Control = -10.5 dB
001 0110: Volume Control = -11.0 dB
001 0111: Volume Control = -11.5 dB
001 1000: Volume Control = -12.0 dB
001 1001: Volume Control = -12.5 dB
001 1010: Volume Control = -13.0 dB
001 1011: Volume Control = -13.5 dB
001 1100: Volume Control = -14.1 dB
001 1101: Volume Control = -14.6 dB
001 1110: Volume Control = -15.1 dB
001 1111: Volume Control = -15.6 dB
010 0000: Volume Control = -16.0 dB
010 0001: Volume Control = -16.5 dB
010 0010: Volume Control = -17.1 dB
010 0011: Volume Control = -17.5 dB
010 0100: Volume Control = -18.1 dB
010 0101: Volume Control = -18.6 dB
010 0110: Volume Control = -19.1 dB
010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB
010 1001: Volume Control = -20.6 dB
010 1010: Volume Control = -21.1 dB
010 1011: Volume Control = -21.6 dB
010 1100: Volume Control = -22.1 dB
010 1101: Volume Control = -22.6 dB
010 1110: Volume Control = -23.1 dB
010 1111: Volume Control = -23.6 dB
011 0000: Volume Control = -24.1 dB
011 0001: Volume Control = -24.6 dB
011 0010: Volume Control = -25.1 dB
011 0011: Volume Control = -25.6 dB
011 0100: Volume Control = -26.1 dB
011 0101: Volume Control = -26.6 dB
011 0110: Volume Control = -27.1 dB
011 0111: Volume Control = -27.6 dB
011 1000: Volume Control = -28.1 dB
011 1001: Volume Control = -28.6 dB
011 1010: Volume Control = -29.1 dB
011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB
011 1101: Volume Control = -30.6 dB
011 1110: Volume Control = -31.1 dB
011 1111: Volume Control = -31.6 dB
100 0000: Volume Control = -32.1 dB
100 0001: Volume Control = -32.7 dB
100 0010: Volume Control = -33.1 dB
Copyright © 2014, Texas Instruments Incorporated
179
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
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Book 0 / Page 1 / Register 47: Speaker Amplifier Control 3 - 0x00 / 0x01 / 0x2F (B0_P1_R47) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
100 0011: Volume Control = -33.6 dB
100 0100: Volume Control = -34.1 dB
100 0101: Volume Control = -34.6 dB
100 0110: Volume Control = -35.2 dB
100 0111: Volume Control = -35.7 dB
100 1000: Volume Control = -36.1 dB
100 1001: Volume Control = -36.7 dB
100 1010: Volume Control = -37.1 dB
100 1011: Volume Control = -37.7 dB
100 1100: Volume Control = -38.2 dB
100 1101: Volume Control = -38.7 dB
100 1110: Volume Control = -39.2 dB
100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB
101 0001: Volume Control = -40.7 dB
101 0010: Volume Control = -41.2 dB
101 0011: Volume Control = -41.8 dB
101 0100: Volume Control = -42.1 dB
101 0101: Volume Control = -42.7 dB
101 0110: Volume Control = -43.2 dB
101 0111: Volume Control = -43.8 dB
101 1000: Volume Control = -44.3 dB
101 1001: Volume Control = -44.8 dB
101 1010: Volume Control = -45.2 dB
101 1011: Volume Control = -45.8 dB
101 1100: Volume Control = -46.2 dB
101 1101: Volume Control = -46.7 dB
101 1110: Volume Control = -47.4 dB
101 1111: Volume Control = -47.9 dB
110 0000: Volume Control = -48.2 dB
110 0001: Volume Control = -48.7 dB
110 0010: Volume Control = -49.3 dB
110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB
110 0101: Volume Control = -51.0 dB
110 0110: Volume Control = -51.4 dB
110 0111: Volume Control = -51.8 dB
110 1000: Volume Control = -52.3 dB
110 1001: Volume Control = -52.7 dB
110 1010: Volume Control = -53.7 dB
110 1011: Volume Control = -54.2 dB
110 1100: Volume Control = -55.4 dB
110 1101: Volume Control = -56.7 dB
110 1110: Volume Control = -58.3 dB
110 1111: Volume Control = -60.2 dB
111 0000: Volume Control = -62.7 dB
111 0001: Volume Control = -64.3 dB
111 0010: Volume Control = -66.2 dB
111 0011: Volume Control = -68.7 dB
111 0100: Volume Control = -72.3 dB
111 0101: Volume Control = -78.3 dB
111 0110 - 1111110: Reserved. Do not use.
111 1111: LOR Output Not Routed to SPK_RIGHT_CH_IN (Default)
Book 0 / Page 1 / Register 48: Speaker Amplifier Volume Controls - 0x00 / 0x01 / 0x30 (B0_P1_R48)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D0
R/W
000 0000 Speaker Amplifier (SPK) Volume Control:
000 0000: SPK Driver is Muted (Default)
001 0001: SPK Driver Volume = 6 dB
010 0001: SPK Driver Volume = 12 dB
011 0001: SPK Driver Volume = 18 dB
100 0001: SPK Driver Volume = 24 dB
101 0001: SPK Driver Volume = 30 dB
Others: Reserved. Do not use.
180
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 49-50: Reserved Registers - 0x00 / 0x01 / 0x31-0x32 (B0_P1_R49-50)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 51: Microphone Bias Control - 0x00 / 0x01 / 0x33 (B0_P1_R51)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
External Mic Bias Power Control
0: MICBIAS_EXT Powered Down if Jack is not inserted.
1: MICBIAS_EXT Powered On and Off based only on P1_R51_D6, even if Jack is not inserted.
D6-D4
000
External Mic Bias Power and Voltage Control
000: MICBIAS_EXT is powered down with pull-down enabled
001: MICBIAS_EXT is powered down with tristate (this should only be used if external microphone
bias is driven from external source
010: MICBIAS_EXT powered on with MICBIAS_EXT = 1.50 V (if Input Common Mode = 0.75 V) or
1.80 V (if Input Common Mode = 0.9 V).
011: MICBIAS_EXT powered on with MICBIAS_EXT = 1.67 V (if Input Common Mode = 0.75 V) or
2.00 V (if Input Common Mode = 0.9 V).
100-101: Do not use.
110: MICBIAS_EXT powered on with MICBIAS_EXT = 2.37 V (if Input Common Mode = 0.75 V) or
2.85 V (if Input Common Mode = 0.9 V).
111: MICBIAS_EXT powered on with MICBIAS_EXT = 2.50 V (if Input Common Mode = 0.75 V) or
3.00 V (if Input Common Mode = 0.9 V).
D3
R/W
R/W
0
0: MICBIAS_EXT is not powered up upon insertion if microphone is not detected on inserted jack
1: MICBIAS_EXT is powered up upon jack detect irrespective of whether microphone is detected
or not
D2-D0
000
Mic Bias Power and Voltage Control
000: MICBIAS is powered down with pull-down enabled
001: MICBIAS is powered down with tristate (this should only be used if microphone bias is driven
from external source)
010: MICBIAS powered on with MICBIAS = 1.50 V (if Input Common Mode = 0.75 V) or 1.80 V (if
Input Common Mode = 0.9 V).
011: MICBIAS powered on with MICBIAS = 1.67 V (if Input Common Mode = 0.75 V) or 2.00 V (if
Input Common Mode = 0.9 V).
100-101: Do not use.
110: MICBIAS powered on with MICBIAS = 2.37 V (if Input Common Mode = 0.75 V) or 2.85 V (if
Input Common Mode = 0.9 V).
111: MICBIAS powered on with MICBIAS = 2.50 V (if Input Common Mode = 0.75 V) or 3.00 V (if
Input Common Mode = 0.9 V).
Book 0 / Page 1 / Register 52: Input Select 1 for Left Microphone PGA P-Terminal - 0x00 / 0x01 / 0x34
(B0_P1_R52)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
R/W
R/W
00
00
00
IN1L to Left Mic PGA (P-Terminal) Selection Control
00: IN1L Not Selected
01: IN1L Selected (RIN = 10K)
10: IN1L Selected (RIN = 20K)
11: IN1L Selected (RIN = 40K)
D5-D4
D3-D2
IN2L to Left Mic PGA (P-Terminal) Selection Control
00: IN2L Not Selected
01: IN2L Selected (RIN = 10K)
10: IN2L Selected (RIN = 20K)
11: IN2L Selected (RIN = 40K)
IN3L to Left Mic PGA (P-Terminal) Selection Control
00: IN3L Not Selected
01: IN3L Selected (RIN = 10K)
10: IN3L Selected (RIN = 20K)
11: IN3L Selected (RIN = 40K)
Copyright © 2014, Texas Instruments Incorporated
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Book 0 / Page 1 / Register 52: Input Select 1 for Left Microphone PGA P-Terminal - 0x00 / 0x01 / 0x34
(B0_P1_R52) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D1-D0
R/W
00
IN1R to Left Mic PGA (P-Terminal) Selection Control
00: IN1R Not Selected
01: IN1R Selected (RIN = 10K)
10: IN1R Selected (RIN = 20K)
11: IN1R Selected (RIN = 40K)
NOTE (For All Inputs to PGA):
PGA Value = 0 dB for Singled Ended Input with RIN = 10K
PGA Value = +6 dB for Differential Input with RIN = 10K
PGA Value = -6 dB for Singled Ended Input with RIN = 20K
PGA Value = 0 dB for Differential Input with RIN = 20K
PGA Value = -12 dB for Singled Ended Input with RIN = 40K
PGA Value = -6 dB for Differential Input with RIN = 40K
Book 0 / Page 1 / Register 53: Input Select 2 for Left Microphone PGA P-Terminal - 0x00 / 0x01 / 0x35
(B0_P1_R53)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
00
0
Reserved. Write only reset values.
R/W
IN4L to Left Mic PGA (P-Terminal) Selection Control
00: IN4L Not Selected
01: IN4L Selected (RIN = 20K)
D4
R/W
R
0
IN4R to Left Mic PGA (M-Terminal) Selection Control
00: IN4R Not Selected
01: IN4R Selected (RIN = 20K)
D3-D0
0000
Reserved. Write only reset values.
Book 0 / Page 1 / Register 54: Input Select for Left Microphone PGA M-Terminal - 0x00 / 0x01 / 0x36
(B0_P1_R54)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
R/W
R/W
R/W
00
00
00
00
Internal Common Mode (CM1) to Left Mic PGA (M-Terminal) Selection Control
00: CM1 Not Selected
01: CM1 Selected (RIN = 10K)
10: CM1 Selected (RIN = 20K)
11: CM1 Selected (RIN = 40K)
D5-D4
D3-D2
D1-D0
IN2R to Left Mic PGA (M-Terminal) Selection Control
00: IN2R Not Selected
01: IN2R Selected (RIN = 10K)
10: IN2R Selected (RIN = 20K)
11: IN2R Selected (RIN = 40K)
IN3R to Left Mic PGA (M-Terminal) Selection Control
00: IN3R Not Selected
01: IN3R Selected (RIN = 10K)
10: IN3R Selected (RIN = 20K)
11: IN3R Selected (RIN = 40K)
Internal Common Mode (CM2) to Left Mic PGA (M-Terminal) Selection Control
00: CM2 Not Selected
01: CM2 Selected (RIN = 10K)
10: CM2 Selected (RIN = 20K)
11: CM2 Selected (RIN = 40K)
182
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 55: Input Select 1 for Right Microphone PGA P-Terminal - 0x00 / 0x01 / 0x37
(B0_P1_R55)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
R/W
R/W
R/W
00
00
00
00
IN1R to Right Mic PGA (P-Terminal) Selection Control
00: IN1R Not Selected
01: IN1R Selected (RIN = 10K)
10: IN1R Selected (RIN = 20K)
11: IN1R Selected (RIN = 40K)
D5-D4
D3-D2
D1-D0
IN2R to Right Mic PGA (P-Terminal) Selection Control
00: IN2R Not Selected
01: IN2R Selected (RIN = 10K)
10: IN2R Selected (RIN = 20K)
11: IN2R Selected (RIN = 40K)
IN3R to Right Mic PGA (P-Terminal) Selection Control
00: IN3R Not Selected
01: IN3R Selected (RIN = 10K)
10: IN3R Selected (RIN = 20K)
11: IN3R Selected (RIN = 40K)
IN2L to Right Mic PGA (P-Terminal) Selection Control
00: IN2L Not Selected
01: IN2L Selected (RIN = 10K)
10: IN2L Selected (RIN = 20K)
11: IN2L Selected (RIN = 40K)
Book 0 / Page 1 / Register 56: Input Select 2 for Right Microphone PGA P-Terminal - 0x00 / 0x01 / 0x38
(B0_P1_R56)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
00
0
Reserved. Write only reset values.
R/W
IN4R to Right Mic PGA (P-Terminal) Selection Control
00: IN4R Not Selected
01: IN4R Selected (RIN = 20K)
D4
R/W
R
0
IN4L to Right Mic PGA (M-Terminal) Selection Control
00: IN4L Not Selected
01: IN4L Selected (RIN = 20K)
D3-D0
0000
Reserved. Write only reset values.
Book 0 / Page 1 / Register 57: Input Select for Right Microphone PGA M-Terminal - 0x00 / 0x01 / 0x39
(B0_P1_R57)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
R/W
R/W
R/W
00
00
00
00
Internal Common Mode (CM1) to Right Mic PGA (M-Terminal) Selection Control
00: CM1 Not Selected
01: CM1 Selected (RIN = 10K)
10: CM1 Selected (RIN = 20K)
11: CM1 Selected (RIN = 40K)
D5-D4
D3-D2
D1-D0
IN1L to Right Mic PGA (M-Terminal) Selection Control
00: IN1L Not Selected
01: IN1L Selected (RIN = 10K)
10: IN1L Selected (RIN = 20K)
11: IN1L Selected (RIN = 40K)
IN3L to Right Mic PGA (M-Terminal) Selection Control
00: IN3L Not Selected
01: IN3L Selected (RIN = 10K)
10: IN3L Selected (RIN = 20K)
11: IN3L Selected (RIN = 40K)
Internal Common Mode (CM2) to Right Mic PGA (M-Terminal) Selection Control
00: CM2 Not Selected
01: CM2 Selected (RIN = 10K)
10: CM2 Selected (RIN = 20K)
11: CM2 Selected (RIN = 40K)
Copyright © 2014, Texas Instruments Incorporated
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Book 0 / Page 1 / Register 58: Input Common Mode Control - 0x00 / 0x01 / 0x3A (B0_P1_R58)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
IN1L Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
D6
D5
D4
D3
D2
D1
D0
IN1R Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
IN2L Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
IN2R Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
IN3L Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
IN3R Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
IN4L Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
IN4R Common-Mode Control When Not Connected to PGAs
0: Floating
1: Connected to Internal Common Mode
Book 0 / Page 1 / Register 59: Left Microphone PGA Control - 0x00 / 0x01 / 0x3B (B0_P1_R59)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
1
0: Left MICPGA Gain is enabled
1: Left MICPGA Gain is set to 0dB
D6-D0
R/W
000 0000 Left MICPGA Volume Control
000 0000: Volume Control = 0.0dB
000 0001: Volume Control = 0.5dB
000 0010: Volume Control = 1.0dB
...
101 1101: Volume Control = 46.5dB
101 1110: Volume Control = 47.0dB
101 1111: Volume Control = 47.5dB
110 0000-111 1111: Reserved. Do not use.
Book 0 / Page 1 / Register 60: Right Microphone PGA Control - 0x00 / 0x01 / 0x3C (B0_P1_R60)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
1
0: Right MICPGA Gain is enabled
1: Right MICPGA Gain is set to 0dB
D6-D0
R/W
000 0000 Right MICPGA Volume Control
000 0000: Volume Control = 0.0dB
000 0001: Volume Control = 0.5dB
000 0010: Volume Control = 1.0dB
...
101 1101: Volume Control = 46.5dB
101 1110: Volume Control = 47.0dB
101 1111: Volume Control = 47.5dB
110 0000-111 1111: Reserved. Do not use.
184
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 1 / Register 61: ADC PowerTune Configuration Register - 0x00 / 0x01 / 0x3D (B0_P1_R61)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
00
00: PTM_R4 (Default)
01: PTM_R3
10: PTM_R2
11: PTM_R1
D5-D0
R/W
00 0000
Reserved. Write only reset values.
Book 0 / Page 1 / Register 62: ADC Analog PGA Gain Flag Register - 0x00 / 0x01 / 0x3E (B0_P1_R62)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1
R
R
0000 00
0
Reserved. Write only reset values.
Left Channel Analog Volume Control Flag
0: Applied Volume is not equal to Programmed Volume
1: Applied Volume is equal to Programmed Volume
D0
R
0
Right Channel Analog Volume Control Flag
0: Applied Volume is not equal to Programmed Volume
1: Applied Volume is equal to Programmed Volume
Book 0 / Page 1 / Register 63: DAC Analog Gain Flags Register 1 - 0x00 / 0x01 / 0x3F (B0_P1_R63)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
R
R
0
0
HPL Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D6
D5
HPR Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
0
RECP Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D4
0
RECM Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D3-D0
0000
Reserved. Write only reset values.
Book 0 / Page 1 / Register 64: DAC Analog Gain Flags Register 2 - 0x00 / 0x01 / 0x40 (B0_P1_R64)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
R
R
0
0
0
0
0
LOL to HPL Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D6
D5
D4
D3
LOR to HPR Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
LOL to RECP Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
LOR to RECM Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
LOL to SPK Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D2
D1
R
R
0
0
Reserved. Write only reset values.
Reserved. Write only reset values.
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Book 0 / Page 1 / Register 64: DAC Analog Gain Flags Register 2 - 0x00 / 0x01 / 0x40
(B0_P1_R64) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D0
R
0
0: Charge Pump is not Powered-Up
1: Charge Pump is Powered-Up
Book 0 / Page 1 / Register 65: Analog Bypass Gain Flags Register - 0x00 / 0x01 / 0x41 (B0_P1_R65)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
R
R
0
0
IN1L to Receiver Left (RECP) Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D6
D5
IN1R to RECM Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
0
Left ADC PGA to Mixer Amp Left (MAL) Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D4
0
Right ADC PGA to Mixer Amp Right (MAR) Driver Gain Flag
0: Applied Gain is not equal to Programmed Gain
1: Applied Gain is equal to Programmed Gain
D3-D0
0000
Reserved. Write only reset values.
Book 0 / Page 1 / Register 66: Driver Power-Up Flags Register - 0x00 / 0x01 / 0x42 (B0_P1_R66)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Line Out Left Driver (LOL) Power-Up Flag
0: LOL Driver Powered Down
1: LOL Driver Powered Up
D6
D5
D4
D3
D2
D1
D0
Line Out Right Driver (LOR) Power-Up Flag
0: LOR Driver Powered Down
1: LOR Driver Powered Up
Headphone Left Driver (HPL) Power-Up Flag
0: HPL Driver Powered Down
1: HPL Driver Powered Up
Headphone Right Driver (HPR) Power-Up Flag
0: HPR Driver Powered Down
1: HPR Driver Powered Up
Receiver Left Driver (RECP) Power-Up Flag
0: RECP Driver Powered Down
1: RECP Driver Powered Up
Receiver Right Driver (RECM) Power-Up Flag
0: RECM Driver Powered Down
1: RECM Driver Powered Up
Speaker Left Driver (SPK) Power-Up Flag
0: SPK Driver Powered Down
1: SPK Driver Powered Up
Reserved. Write only reset values.
Book 0 / Page 1 / Register 67-68: Reserved Registers - 0x00 / 0x01 / 0x43-0x44 (B0_P1_R67-68)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
186
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Book 0 / Page 1 / Register 69: Over current Flags - 0x00 / 0x01 / 0x45 (B0_P1_R69)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
R
0
Receiver Driver Over Current Sticky Flag
0: No over current was detected on Receiver driver
1: Over Current was detected on Receiver driver
D6
D5
0
0
Headphone Driver Over Current Sticky Flag
0: No over current was detected on Receiver driver
1: Over Current was detected on Receiver driver
Speaker Driver Over Current Sticky Flag
0: No over current was detected on Speaker driver
1: Over Current was detected on Speaker driver
D4-D0
x xxxx
Reserved.
Book 0 / Page 1 / Register 67-76: Reserved Registers - 0x00 / 0x01 / 0x43-0x4C (B0_P1_R67-76)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 77: Reserved Registers - 0x00 / 0x01 / 0x4D (B0_P1_R77)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D1
D0
R
000 0000 Reserved. Write only reset values.
R/W
0
Headphone Over Current Protection Enable
0: Default
1: Write '1' to enable headphone overcurrent protection
Book 0 / Page 1 / Register 78-118: Reserved Registers - 0x00 / 0x01 / 0x4E-0x76 (B0_P1_R78-118)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 1 / Register 119: Headset Detection Tuning Register 1 - 0x00 / 0x01 / 0x77 (B0_P1_R119)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
10
Headphone Load Detection Pulse Period. Detection pulse is used to identify the headphone load
type after insertion is detected.
0: Detector pulse mode is disabled
1: Detector pulse mode period is enabled with period of 144 cycles of LF_OSC_CLK (typ. 18us)
2: Detector pulse mode period is enabled with period of 288 cycles of LF_OSC_CLK (default, typ.
36us)
3: Detector pulse mode period is enabled with period of 4608 cycles of LF_OSC_CLK (typ. 576us)
D5-D2
R/W
01 01
Headphone Load Detection Pulse High Duration. Detection pulse is used to identify the headphone
load type after insertion is detected.
0000: Reserved.
0001: Detector pulse high duration is 1*Detector Pulse High Width Scale Factor*LF_OSC_CLK.
See bit D1 for Detector Pulse High Width Scale Factor.
0010: Detector pulse high duration is 2*Detector Pulse High Width Scale Factor*LF_OSC_CLK.
0011: Detector pulse high duration is 3*Detector Pulse High Width Scale Factor*LF_OSC_CLK.
0100: Detector pulse high duration is 4*Detector Pulse High Width Scale Factor*LF_OSC_CLK.
0101: Detector pulse high duration is 5*Detector Pulse High Width Scale Factor*LF_OSC_CLK.
(default)
...
1110: Detector pulse high duration is 14*Detector Pulse High Width Scale Factor*LF_OSC_CLK.
1111: Detector pulse high duration is 15*Detector Pulse High Width Scale Factor*LF_OSC_CLK.
D1
R/W
0
Headphone Load Detection Pulse High Width Scale Factor
0: Headphone Load Detection Pulse High Width Scale Factor =1
1: Headphone Load Detection Pulse High Width Scale Factor =8
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Book 0 / Page 1 / Register 119: Headset Detection Tuning Register 1 - 0x00 / 0x01 / 0x77
(B0_P1_R119) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D0
R/W
0
Headset Detection Pulse Auto configuration
0: Upon microphone insertion detection, the auto configuration of detection is enabled. This
enables the detector pulse mode with period of 4608 cycles of the LF_OSC_CLK, and sets
Detector Pulse High Width Scale Factor to 8. (default)
1: Upon microphone insertion detection, the auto configuration of detection is disabled. Therefor,
detector pulse mode period and Detector Pulse High Width Scale Factor does not change upon
insertion.
Book 0 / Page 1 / Register 120: Headset Detection Tuning Register 2 - 0x00 / 0x01 / 0x78 (B0_P1_R120)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0100
Headset Detection Pulse Width control. This pulse is used to detect button press and headset
removal.
0000: Headset Detection Pulse Width is 1*(Headphone Load Detector_Pulse_Period*0.5+1) cycles
of LF_OSC_CLK, where Headphone Load Detector_Pulse_Period is set by B0_P1_R119_D[7:6].
0001: Headset Detection Pulse Width is 1.5*(Headphone Load Detector_Pulse_Period*0.5+1)
cycles of LF_OSC_CLK.
0010: Headset Detection Pulse Width is 2*(Headphone Load Detector_Pulse_Period*0.5+1) cycles
of LF_OSC_CLK.
0011: Headset Detection Pulse Width is 2.5*(Headphone Load Detector_Pulse_Period*0.5+1)
cycles of LF_OSC_CLK.
0100: Headset Detection Pulse Width is 3*(Headphone Load Detector_Pulse_Period*0.5+1) cycles
of LF_OSC_CLK. (default)
...
1110: Headset Detection Pulse Width is 8*(Headphone Load Detector_Pulse_Period*0.5+1) cycles
of LF_OSC_CLK.
1111: Headset Detection Pulse Width is 8.5*(Headphone Load Detector_Pulse_Period*0.5+1)
cycles of LF_OSC_CLK.
D3
D2
R
0
0
Reserved. Write only reset values.
R/W
Headphone Load Detection Range control
0: Headphone detection supported in the range of 16-Ohms to 300-Ohms.
1: Headphone detection supported in the range of 16-Ohms to 64-Ohms.
D1-D0
R/W
10
Headset Detection using microphone inputs on IN4L, IN4R control:
00: Reserved. Do not use.
01: IN4L, IN4R enabled for headset microphone inputs.
10: IN4L, IN4R disabled for headset microphone inputs.
11: Reserved. Do not use.
Book 0 / Page 1 / Register 121: Reserved Register - 0x00 / 0x01 / 0x79 (B0_P1_R121)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0011 0011 Reserved. Write only reset values.
Book 0 / Page 1 / Register 122: Reference Powerup Control - 0x00 / 0x01 / 0x7A (B0_P1_R122)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
D2
R
0 0000
0
Reserved. Write only reset values.
R/W
0: Chip-Reference powered-up and powered-down internally based on other on-chip block
requirements
1: Chip-Reference will be force-fully powered-up
D1-D0
R/W
01
Reserved. Write only reset values.
Book 0 / Page 1 / Register 123-127: Reserved Registers - 0x00 / 0x01 / 0x7B-0x7F (B0_P1_R123-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
188
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8.6.4 Book 0 Page 3
Book 0 / Page 3 / Register 0: Page Select Register - 0x00 / 0x03 / 0x00 (B0_P3_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Book 0 / Page 3 / Register 1: Reserved Register - 0x00 / 0x03 / 0x01 (B0_P3_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 3 / Register 2: Primary SAR ADC Control - 0x00 / 0x03 / 0x02 (B0_P3_R2)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: Normal Mode
1: Stop Conversion and power down SAR ADC
D6-D5
D4-D3
R/W
00
00: SAR ADC resolution = 12-bit
01: SAR ADC resolution = 8-bit
10: SAR ADC resolution = 10-bit
11: SAR ADC resolution = 12-bit
R/W
1 1
00: SAR ADC clock divider = 1 (Use for 8-bit resolution case only)
01: SAR ADC clock divider = 2 (Use for 8-bit/10-bit resolution case only)
10: SAR ADC clock divider = 4 (For better performance in 8-bit/10-bit resolution mode, this setting
is recommended)
11: SAR ADC clock divider = 8 (For better performance in 12-bit resolution mode, this setting is
recommended)
D2
R/W
R/W
0
0: Mean filter is used for on-chip data averaging (if enabled)
1: Median filter is used for on-chip data averaging (if enabled)
D1-D0
00
00: On-chip data averaging is disabled.
01: 4-data averaging in case mean filter / 5-data averaging in case of median filter.
10: 8-data averaging in case mean filter / 9-data averaging in case of median filter.
11: 16-data averaging in case mean filter / 15-data averaging in case of median filter.
Book 0 / Page 3 / Register 3: Primary SAR ADC Conversion Mode - 0x00 / 0x03 / 0x03 (B0_P3_R3)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5-D2
R
00
Reserved. Write only reset values.
R/W
00 00
Conversion Mode
0000: No Scan
0001 - 0101: Reserved. Do not use.
0110: VBAT Measurement
0111: IN1R Measurement
1000: IN1L Measurment
1001: Auto Scan. Sequence used is IN1L, IN1R, VBAT, TEMP1(or TEMP2). Each of these input
can be enabled or disabled independently using register-19 and with that sequence will get
modified accordingly. Scan continues until stop bit(D7 of reg-2) is sent or D5-D2 of this register is
changed.
1010: TEMP1 Measurement
1011: PortScan : IN1L, IN1R, VBAT
1100: TEMP2 Measurement
1101 - 1111: Reserved. Do not use.
D1-D0
R/W
00
00: Interrupt Disabled
01: Interrupt = Data-Available (active LOW)
10-11: Reserved. Do not use.
Book 0 / Page 3 / Register 4-5: Reserved Registers - 0x00 / 0x03 / 0x04-0x05 (B0_P3_R4-5)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
x000 0000 Reserved. Write only reset values.
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Book 0 / Page 3 / Register 6: SAR Reference Control - 0x00 / 0x03 / 0x06 (B0_P3_R6)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
SAR Reference Selection
0: Use External Reference for SAR Measurement
1: Use Internal Reference (1.25V) for SAR Measurement
D6
D5
R
0
1
Reserved. Write only reset values.
R/W
SAR Internal Reference Power Options
0: Internal Reference powered forever for conversions
1: Internal Reference powered up or powered down automatically based on whether conversions
are going on or not.
D4
R
0
Reserved. Write only reset values.
D3-D2
R/W
10
SAR Reference Stabilization Time Before Conversion
00: 0 ms
01: 1 ms
10: 4 ms
11: 8 ms
D1-D0
R
00
Reserved. Write only reset values.
Book 0 / Page 3 / Register 7-8: Reserved Registers - 0x00 / 0x03 / 0x07-0x08 (B0_P3_R7-8)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 3 / Register 9: SAR ADC Flags Register 1 - 0x00 / 0x03 / 0x09 (B0_P3_R9)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
D6
R
R
0
1
Reserved. Write only reset values.
SAR Busy Flag
0: SAR ADC is Busy
1: SAR ADC is not Busy
D5
R
R
0
SAR Data Available Flag
0: No New Data Available
1: New Data is Available
D4-D0
0 0000
Reserved. Write only reset values.
Book 0 / Page 3 / Register 10: SAR ADC Flags Register 2 - 0x00 / 0x03 / 0x0A (B0_P3_R10)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
0
0
0
IN1L Data Available Flag
0: No New Data Available
1: New Data is Available (This bit cleared only after the converted data has been read. Not valid for
the buffer mode.)
D6
D5
IN1R Data Available Flag
0: No New Data Available
1: New Data is Available (This bit cleared only after the converted data has been read. Not valid for
the buffer mode.)
VBAT Data Available Flag
0: No New Data Available
1: New Data is Available (This bit cleared only after the converted data has been read. Not valid for
the buffer mode.)
D4-D2
D1
R
R
000
0
Reserved. Write only reset values.
TEMP1 Data Available Flag
0: No New Data Available
1: New Data is Available (This bit cleared only after the converted data has been read. Not valid for
the buffer mode.)
D0
R
0
TEMP2 Data Available Flag
0: No New Data Available
1: New Data is Available (This bit cleared only after the converted data has been read. Not valid for
the buffer mode.)
190
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Book 0 / Page 3 / Register 11-12: Reserved Registers - 0x00 / 0x03 / 0x0B-0x0C (B0_P3_R11-12)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 3 / Register 13: SAR ADC Buffer Mode Control - 0x00 / 0x03 / 0x0D (B0_P3_R13)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
R/W
0
0
Buffer Mode Enable Select
0: Buffer mode is disabled and RDPTR, WRPTR and TGPTR are set to their default value.
1: Buffer mode is enabled.
D6
Buffer Conversion Mode Select
0: Buffer mode is enabled as continuous conversion mode.
1: Buffer mode is enabled as single shot mode.
D5-D3
00 0
Buffer Mode Conversion Trigger Level Select
000: Trigger Level for conversion = 8 converted data values
001: Trigger Level for conversion = 16 converted data values
010: Trigger Level for conversion = 24 converted data values
011: Trigger Level for conversion = 32 converted data values
100: Trigger Level for conversion = 40 converted data values
101: Trigger Level for conversion = 48 converted data values
110: Trigger Level for conversion = 56 converted data values
111: Trigger Level for conversion = 64 converted data values
D2
D1
R
R
0
0
Reserved. Write only reset values.
Buffer Full Flag
0: Buffer is not full
1: Buffer is full (buffer contains 64 unread converted data).
D0
R
1
Buffer Empty Flag
0: Buffer is not empty
1: Buffer is empty (there is no unread converted data in the buffer).
Book 0 / Page 3 / Register 14: Reserved Register - 0x00 / 0x03 / 0x0E (B0_P3_R14)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 3 / Register 15: Scan Mode Timer Control - 0x00 / 0x03 / 0x0F (B0_P3_R15)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3
R
0100
0
Reserved. Write only reset values.
R/W
Programmable Delay for SAR Auto-Scan Enable
0: Disabled
1: Enabled
D2-D0
R/W
000
Programmable Interval Timer for Auto Scan delay
000: Delay = 1.12 min.
001: Delay = 3.36 min.
010: Delay = 5.59 min.
011: Delay = 7.83 min.
100: Delay = 10.01 min.
101: Delay = 12.30 min.
110: Delay = 14.54 min.
111: Delay = 16.78 min.
(Note: Based on an 8 MHz Internal Oscillator or MCLK/DIV(Page-0, Reg-23) = 1MHz)
Book 0 / Page 3 / Register 16: Reserved Register - 0x00 / 0x03 / 0x10 (B0_P3_R16)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
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Book 0 / Page 3 / Register 17: SAR ADC Clock Control - 0x00 / 0x03 / 0x11 (B0_P3_R17)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
SAR ADC Clock Selection
0: Internal Oscillator
1: External MCLK
D6-D0
000 0001 MCLK to SAR ADC Clock Divider Selection
000 0000: MCLK Divider = 128
000 0001: MCLK Divider = 1
000 0010: MCLK Divider = 2
…
111 1110: MCLK Divider = 126
111 1111: MCLK Divider = 127
Book 0 / Page 3 / Register 18: SAR ADC Buffer Mode Data Read Control - 0x00 / 0x03 / 0x12 (B0_P3_R18)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: SPI Interface is used for the SAR or Buffer data reading.
1: I2C Interface is used for the SAR or Buffer data reading.
D6
D5
R/W
0
0: SAR data update is automatically halted (to avoid simultaneous buffer read and write
operations) based on internal detection logic. Valid only for SPI interface.
1: SAR data update is held using software control (P3_R18_D5).
R/W
R
0
0: SAR data update is enabled all the time (valid only if P3_R18_D6 = 1)
1: SAR data update is stopped so that user can read the last updated data without any data
corruption (valid only if P3_R18_D6 = 1).
D4-D0
0 0000
Reserved. Write only reset values.
Book 0 / Page 3 / Register 19: SAR ADC Measurement Control - 0x00 / 0x03 / 0x13 (B0_P3_R19)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Automatic IN1L Measurement Enable
0: Disable
1: Enable
D6
D5
D4
D3
D2
D1
D0
Automatic IN1R Measurement Enable
0: Disable
1: Enable
Automatic VBAT Measurement Enable
0: Disable
1: Enable
Automatic TEMP Measurement Enable
0: Disable
1: Enable
Automatic TEMP Measurement Sensor Selection
0: TEMP1
1: TEMP2
IN1L Measurement Type Selection
0: Voltage Measurement
1: Resistance Measurement
IN1R Measurement Type Selection
0: Voltage Measurement
1: Resistance Measurement
Resistance Measurement Mode Selection
0: Internal Bias Resistance Measurment Mode
1: External Bias Resistance Measurment Mode
Book 0 / Page 3 / Register 20: Reserved Register - 0x00 / 0x03 / 0x14 (B0_P3_R20)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
192
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 3 / Register 21: SAR ADC Measurement Threshold Flags - 0x00 / 0x03 / 0x15 (B0_P3_R21)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
R
00
0
Reserved. Write only reset values.
IN1L Measurement Max Threshold Flag
0: IN1L Measurement < Programmed Max Threshold Setting
1: IN1L Measurement >= Programmed Max Threshold Setting
D4
D3
D2
D1
D0
R
R
R
R
R
0
0
0
0
0
IN1L Measurement Min Threshold Flag
0: IN1L Measurement > Programmed Min Threshold Setting
1: IN1L Measurement <= Programmed Min Threshold Setting
IN1R Measurement Max Threshold Flag
0: IN1R Measurement < Programmed Max Threshold Setting
1: IN1R Measurement >= Programmed Max Threshold Setting
IN1R Measurement Min Threshold Flag
0: IN1R Measurement > Programmed Min Threshold Setting
1: IN1R Measurement <= Programmed Min Threshold Setting
TEMP (TEMP1 or TEMP2) Measurement Max Threshold Flag
0: TEMP Measurement < Programmed Max Threshold Setting
1: TEMP Measurement >= Programmed Max Threshold Setting
3
Book 0 / Page 3 / Register 22: IN1L Max Threshold Check Control 1 - 0x00 / 0x03 / 0x16 (B0_P3_R22)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4
R
000
0
Reserved. Write only reset values.
R/W
IN1L Max Threshold Check Enable Control
0: Disable (Valid For Both Auto and non-Auto Scan Measurement)
1: Enable (Valid For Both Auto and non-Auto Scan Measurement)
D3-D0
R/W
0000
IN1L Max Threshold 12-bit Code (MSB 4-bits)
Book 0 / Page 3 / Register 23: IN1L Max Threshold Check Control 2 - 0x00 / 0x03 / 0x17 (B0_P3_R23)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 IN1L Max Threshold 12-bit Code (LSB 8-bits)
Book 0 / Page 3 / Register 24: IN1L Min Threshold Check Control 1 - 0x00 / 0x03 / 0x18 (B0_P3_R24)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4
R
000
0
Reserved. Write only reset values.
R/W
IN1L Min Threshold Check Enable Control
0: Disable (Valid For Both Auto and non-Auto Scan Measurement)
1: Enable (Valid For Both Auto and non-Auto Scan Measurement)
D3-D0
R/W
0000
IN1L Min Threshold 12-bit Code (MSB 4-bits)
Book 0 / Page 3 / Register 25: IN1L Min Threshold Check Control 2 - 0x00 / 0x03 / 0x19 (B0_P3_R25)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 IN1L Min Threshold 12-bit Code (LSB 8-bits)
Book 0 / Page 3 / Register 26: IN1R Max Threshold Check Control 1 - 0x00 / 0x03 / 0x1A (B0_P3_R26)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4
R
000
0
Reserved. Write only reset values.
R/W
IN1R Max Threshold Check Enable Control
0: Disable (Valid For Both Auto and non-Auto Scan Measurement)
1: Enable (Valid For Both Auto and non-Auto Scan Measurement)
D3-D0
R/W
0000
IN1R Max Threshold 12-bit Code (MSB 4-bits)
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Book 0 / Page 3 / Register 27: IN1R Max Threshold Check Control 2 - 0x00 / 0x03 / 0x1B (B0_P3_R27)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 IN1R Max Threshold 12-bit Code (LSB 8-bits)
Book 0 / Page 3 / Register 28: IN1R Min Threshold Check Control 1 - 0x00 / 0x03 / 0x1C (B0_P3_R28)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4
R
000
0
Reserved. Write only reset values.
R/W
IN1R Min Threshold Check Enable Control
0: Disable (Valid For Both Auto and non-Auto Scan Measurement)
1: Enable (Valid For Both Auto and non-Auto Scan Measurement)
D3-D0
R/W
0000
IN1R Min Threshold 12-bit Code (MSB 4-bits)
Book 0 / Page 3 / Register 29: IN1R Min Threshold Check Control 2 - 0x00 / 0x03 / 0x1D (B0_P3_R29)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 IN1R Min Threshold 12-bit Code (LSB 8-bits)
Book 0 / Page 3 / Register 30: TEMP Max Threshold Check Control 1 - 0x00 / 0x03 / 0x1E (B0_P3_R30)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4
R
000
0
Reserved. Write only reset values.
R/W
TEMP (TEMP1 or TEMP2) Max Threshold Check Enable Control
0: Disable (Valid For Both Auto and non-Auto Scan Measurement)
1: Enable (Valid For Both Auto and non-Auto Scan Measurement)
D3-D0
R/W
0000
IN1R Max Threshold 12-bit Code (MSB 4-bits)
Book 0 / Page 3 / Register 31: TEMP Max Threshold Check Control 2 - 0x00 / 0x03 / 0x1F (B0_P3_R31)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 TEMP (TEMP1 or TEMP2) Max Threshold 12-bit Code (LSB 8-bits)
Book 0 / Page 3 / Register 32: TEMP Min Threshold Check Control 1 - 0x00 / 0x03 / 0x20 (B0_P3_R32)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4
R
000
0
Reserved. Write only reset values.
R/W
TEMP (TEMP1 or TEMP2) Min Threshold Check Enable Control
0: Disable (Valid For Both Auto and non-Auto Scan Measurement)
1: Enable (Valid For Both Auto and non-Auto Scan Measurement)
D3-D0
R/W
0000
TEMP Min Threshold 12-bit Code (MSB 4-bits)
Book 0 / Page 3 / Register 33: TEMP Min Threshold Check Control 2 - 0x00 / 0x03 / 0x21 (B0_P3_R33)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 TEMP (TEMP1 or TEMP2) Min Threshold 12-bit Code (LSB 8-bits)
Book 0 / Page 3 / Register 34-53: Reserved Registers - 0x00 / 0x03 / 0x22-0x35 (B0_P3_R34-53)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
194
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Book 0 / Page 3 / Register 54: IN1L Measurement Data (MSB) - 0x00 / 0x03 / 0x36 (B0_P3_R54)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 MSB 8-bits of IN1L Measurement 16-bit Data
Book 0 / Page 3 / Register 55: IN1L Measurement Data (LSB) - 0x00 / 0x03 / 0x37 (B0_P3_R55)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 LSB 8-bits of IN1L Measurement 16-bit Data
Book 0 / Page 3 / Register 56: IN1R Measurement Data (MSB) - 0x00 / 0x03 / 0x38 (B0_P3_R56)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 MSB 8-bits of IN1R Measurement 16-bit Data
Book 0 / Page 3 / Register 57: IN1R Measurement Data (LSB) - 0x00 / 0x03 / 0x39 (B0_P3_R57)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 LSB 8-bits of IN1R Measurement 16-bit Data
Book 0 / Page 3 / Register 58: VBAT Measurement Data (MSB) - 0x00 / 0x03 / 0x3A (B0_P3_R58)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 MSB 8-bits of VBAT Measurement 16-bit Data
Book 0 / Page 3 / Register 59: VBAT Measurement Data (LSB) - 0x00 / 0x03 / 0x3B (B0_P3_R59)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 LSB 8-bits of VBAT Measurement 16-bit Data
Book 0 / Page 3 / Register 60-65: Reserved Registers - 0x00 / 0x03 / 0x3C-0x41 (B0_P3_R60-65)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 3 / Register 66: TEMP1 Measurement Data (MSB) - 0x00 / 0x03 / 0x42 (B0_P3_R66)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 MSB 8-bits of TEMP1 Measurement 16-bit Data
Book 0 / Page 3 / Register 67: TEMP1 Measurement Data (LSB) - 0x00 / 0x03 / 0x43 (B0_P3_R67)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 LSB 8-bits of TEMP1 Measurement 16-bit Data
Book 0 / Page 3 / Register 68: TEMP2 Measurement Data (MSB) - 0x00 / 0x03 / 0x44 (B0_P3_R68)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 MSB 8-bits of TEMP1 Measurement 16-bit Data
Book 0 / Page 3 / Register 69: TEMP2 Measurement Data (LSB) - 0x00 / 0x03 / 0x45 (B0_P3_R69)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 LSB 8-bits of TEMP1 Measurement 16-bit Data
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Book 0 / Page 3 / Register 70-127: Reserved Registers - 0x00 / 0x03 / 0x46-0x7F (B0_P3_R70-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
8.6.5 Book 0 Page 4
Book 0 / Page 4 / Register 0: Page Select Register - 0x00 / 0x04 / 0x00 (B0_P4_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table ""Summary of Memory Map" for details.
Book 0 / Page 4 / Register 1: ASI1, Audio Bus Format Control Register - 0x00 / 0x04 / 0x01 (B0_P4_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R/W
000
ASI1, format selection
000: ASI1 Audio Interface = I2S
001: ASI1 Audio Interface = DSP
010: ASI1 Audio Interface = RJF
011: ASI1 Audio Interface = LJF
100: ASI1 Audio Interface = Mono PCM
101-111: Reserved. Do not use.
D4-D3
R/W
0 0
ASI1 Data Word Length Selection
00: ASI1 Data Word length = 16 bits
01: ASI1 Data Word length = 20 bits
10: ASI1 Data Word length = 24 bits
11: ASI1 Data Word length = 32 bits
D2-D1
D0
R
00
0
Reserved. Write only default values.
R/W
DOUT1 High Impendance Output Control
0: DOUT1 will not be high impedance while ASI1 is active
1: DOUT1 will be high impedance after data has been transferred
Book 0 / Page 4 / Register 2: ASI1, Left Ch_Offset_1 Control Register - 0x00 / 0x04 / 0x02 (B0_P4_R2)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 ASI1 Data Offset Value (Ch_Offset_1) relative to rising edge of Word Clock (Offset measured from
Rising Edge of Word Clock in DSP mode)
0000 0000: Data Offset 1 = 0 BCLK's
0000 0001: Data Offset 1= 1 BCLK's
...
1111 1110: Data Offset 1 = 254 BCLK's
1111 1111: Data Offset 1 = 255 BCLK's
Book 0 / Page 4 / Register 3: ASI1, Right Ch_Offset_2 Control Register - 0x00 / 0x04 / 0x03 (B0_P4_R3)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 ASI1 Data Offset Value (Ch_Offset_2) relative to last bit of left channel (applicable only if slot mode
enabled)
0000 0000: Data Offset 2 = 0 BCLK's
0000 0001: Data Offset 2= 1 BCLK's
...
1111 1110: Data Offset 2 = 254 BCLK's
1111 1111: Data Offset 2 = 255 BCLK's
Book 0 / Page 4 / Register 4: ASI1, Channel Setup Register - 0x00 / 0x04 / 0x04 (B0_P4_R4)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
00
196
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 4: ASI1, Channel Setup Register - 0x00 / 0x04 / 0x04 (B0_P4_R4) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D4
D3-D2
R
00
00
Reserved. Write only default values.
R/W
00: For DAC all the left and right channels are enabled
01: For DAC all the left channels are disabled
10: For DAC all the right channels are disabled.
11: For DAC all the left and right channel are disabled.
D1-D0
R/W
00
00: For ADC all the left and right channels are enabled
01: For ADC all the left channels are disabled
10: For ADC all the right channels are disabled.
11: For ADC all the left and right channel are disabled.
Book 0 / Page 4 / Register 5: ASI1, ADC Audio Bus Format Control Register - 0x00 / 0x04 / 0x05
(B0_P4_R5)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R/W
000
Primary Audio Serial ADC Interface Format Selection (This control is only valid if D2 bit = '1'.)
000: ASI1 ADC Audio Interface = I2S
001: ASI1 ADC Audio Interface = DSP
010: ASI1 ADC Audio Interface = RJF
011: ASI1 ADC Audio Interface = LJF
100: ASI1 ADC Audio Interface = Mono PCM
101-111: Reserved. Do not use.
D4-D3
R/W
0 0
Primary Audio Serial ADC Interface Data Word Length Selection (This control is only valid if D2 bit
= '1'.)
00: ASI1 ADC Data Word length = 16 bits
01: ASI1 ADC Data Word length = 20 bits
10: ASI1 ADC Data Word length = 24 bits
11: ASI1 ADC Data Word length = 32 bits
D2
R/W
R
0
Primary Audio Serial ADC Six-Wire Format and Wordlength Enable
0: ASI1 ADC pathway uses same interface format and wordlength as in B0_P4_R1.
1: ASI1 ADC pathway use interface format defined in D[7:5] and wordlength defined in D[4:2] of
this register.
D1-D0
00
Reserved. Write only default values.
Book 0 / Page 4 / Register 6: Audio Serial Interface 1, Multi-Pin Mode - 0x00 / 0x04 / 0x06 (B0_P4_R6)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R
0
ASI1 Data Input and Output Mode
0: Single Data Input Pin, Single Data Output Pin
1: Multiple Data Input Pin, Multiple Data Output Pin
D6-D0
000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 7: ASI1, ADC Input Control - 0x00 / 0x04 / 0x07 (B0_P4_R7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
D2-D0
R
0000 0
001
Reserved. Write only default values.
ASI1 ADC Input Control
R/W
000: ASI1 digital audio output data source disabled (No serial data output on external ASI1 bus.
ASI1 digital output is tri-stated.)
001: ASI1_DataOutput[1:8] is sourced from miniDSP_A_DataOutput[1:8] (ADC signal fed to ASI1.)
010: ASI1_DataOutput[1:8] is sourced from ASI1_DataInput[1:8] (ASI1-to-ASI1 loopback)
011: ASI1_DataOutput[1:2] is sourced from ASI2_DataInput[1:2] (ASI2-to-ASI1 loopback)
100: ASI1_DataOutput[1:2] is sourced from ASI3_DataInput[1:2] (ASI3-to-ASI1 loopback)
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Book 0 / Page 4 / Register 8: ASI1, DAC Output Control - 0x00 / 0x04 / 0x08 (B0_P4_R8)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
01
ASI1 Left DAC Datapath
00: ASI1 Left DAC Datapath = Off
01: ASI1 Left DAC Datapath = Left Data
10: ASI1 Left DAC Datapath = Right Data
11: ASI1 Left DAC Datapath = Mono Mix of Left and Right
D5-D4
R/W
01
ASI1 Right DAC Datapath
00: ASI1 Right DAC Datapath = Off
01: ASI1 Right DAC Datapath = Right Data
10: ASI1 Right DAC Datapath = Left Data
11: ASI1 Right DAC Datapath = Mono Mix of Left and Right
D3-D2
D1
R
00
0
Reserved. Write only default values.
R/W
0: Left and right channel slot-swapping is disabled for ADC datapath.
1: Left and right channel slot-swapping is enabled for ADC datapath.
D0
R/W
0
0: Time slot mode is disabled which means the position for left and right channels will be controlled
by WCLK and offset1 programming controlled by B0_P4_R2.
1: Time slot mode is enabled which means the position for the left channels are controlled by
WCLK and offset1 programming controlled by B0_P4_R2 and for right channel the relative offset
with respect to last bit of left channel will be contolled by B0_P4_R3.
Book 0 / Page 4 / Register 9: ASI1, Control Register 9, ADC Slot Tristate Control - 0x00 / 0x04 / 0x09
(B0_P4_R9)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
R/W
R/W
0
0
0
0
0: ADC left channel <L4> slot is not tri-stated
1: ADC left channel <L4> slot is tri-stated. Must also set B0_P4_R1_D0='1'. This should only be
used in single-pin mode for ASI1 (that is cannot use multi-pin mode).
D6
D5
D4
0: ADC left channel <L3> slot is not tri-stated
1: ADC left channel <L3> slot is tri-stated. Must also set B0_P4_R1_D0='1'. This should only be
used in single-pin mode for ASI1 (that is cannot use multi-pin mode).
0: ADC left channel <L2> slot is not tri-stated
1: ADC left channel <L2> slot is tri-stated. Must also set B0_P4_R1_D0='1'. This should only be
used in single-pin mode for ASI1 (that is cannot use multi-pin mode).
0: ADC left channel <L1> slot is not tri-stated
1: ADC left channel <L1> slot is tri-stated. Must also set B0_P4_R1_D0='1'. (Note that, in multi-
channel mode, this will tristate all Left channels. If individual Left channels need to be tri-stated,
this can be achieved on the bus by disconnecting the output pin.)
D3
D2
D1
D0
R/W
R/W
R/W
R/W
0
0
0
0
0: ADC left channel <R4> slot is not tri-stated
1: ADC left channel <R4> slot is tri-stated. Must also set B0_P4_R1_D0='1'. This should only be
used in single-pin mode for ASI1 (that is cannot use multi-pin mode).
0: ADC left channel <R3> slot is not tri-stated
1: ADC left channel <R3> slot is tri-stated. Must also set B0_P4_R1_D0='1'. This should only be
used in single-pin mode for ASI1 (that is cannot use multi-pin mode).
0: ADC left channel <R2> slot is not tri-stated
1: ADC left channel <R2> slot is tri-stated. Must also set B0_P4_R1_D0='1'. This should only be
used in single-pin mode for ASI1 (that is cannot use multi-pin mode).
0: ADC right channel <R1> slot is not tri-stated
1: ADC right channel <R1> slot is tri-stated. Must also set B0_P4_R1_D0='1'. (Note that, in multi-
channel mode, this will tristate all Right channels. If individual Right channels need to be tri-stated,
this can be achieved on the bus by disconnecting the output pin.)
Book 0 / Page 4 / Register 10: ASI1, WCLK and BCLK Control Register - 0x00 / 0x04 / 0x0A (B0_P4_R10)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R/W
000
ASI1 Word Clock Direction Control
000: WCLK1 pin is Word Clock input to ASI1
001: WCLK1 pin is Word Clock output from ASI1
010-111: Reserved. Do not use.
198
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 10: ASI1, WCLK and BCLK Control Register - 0x00 / 0x04 / 0x0A
(B0_P4_R10) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D4-D2
R/W
0 00
ASI1 Bit Clock Direction Control
000: BCLK1 pin is Bit Clock input to ASI1
001: BCLK1 pin is Bit Clock output from ASI1
010-111: Reserved. Do not use.
D1
D0
R/W
R/W
0
0
Primary Audio Bit Clock Polarity Control
0: Default Bit Clock polarity
1: Bit Clock is inverted w.r.t. default polarity
ASI1 Bit Clock and ASI1 Word Clock Power control
0: ASI1 Bit Clock and ASI1 Word Clock buffers are powered down when the codec is powered
down or ASI 1 is inactive
1: ASI1 Bit Clock and ASI1 Word Clock buffers are powered up when they are used in clock
generation even when the codec is powered down
Book 0 / Page 4 / Register 11: ASI1, Bit Clock N Divider Input Control - 0x00 / 0x04 / 0x0B (B0_P4_R11)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
ASI1_ADC_BCLK_OUT configuration used for 6-wire mode with ADC Bit Clock as output:
0: ASI1_ADC_BCLK_OUT = ASI1_BCLK_OUT configured in B0_P4_R14_D[7:4].
1: ASI1_ADC_BCLK_OUT can be different from ASI1_BCLK_OUT and is configured in
B0_P4_R115_D[7:4].
D6
R/W
0
ASI1_ADC_WCLK_OUT configuration used for 6-wire mode with ADC Word Clock as output:
0: ASI1_ADC_WCLK_OUT = ASI1_WCLK_OUT configured in B0_P4_R14_D[3:0].
1: ASI1_WCLK_OUT can be different from ASI1_WCLK_OUT and is configured in
B0_P4_R115_D[3:0].
D5-D4
D3-D0
R
00
Reserved. Write only default values.
R/W
0000
ASI1 BDIV_CLKIN Multiplexer Control
0000: ASI1_BDIV_CLKIN = DAC_CLK
0001: ASI1_BDIV_CLKIN = DAC_MOD_CLK
0010: ASI1_BDIV_CLKIN = ADC_CLK
0011: ASI1_BDIV_CLKIN = ADC_MOD_CLK
0100: ASI1_BDIV_CLKIN = ASI1 Bit Clock Input Pin
0101: ASI1_BDIV_CLKIN = ASI2 Bit Clock Input Pin
0110: ASI1_BDIV_CLKIN = ASI3 Bit Clock Input Pin
0111: ASI1_BDIV_CLKIN = ASI1 ADC Bit Clock Input Pin (6-wire interface)
1000: ASI1_BDIV_CLKIN = ASI2 ADC Bit Clock Input Pin (6-wire interface)
1001-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 12: ASI1, Bit Clock N Divider - 0x00 / 0x04 / 0x0C (B0_P4_R12)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
ASI1 BCLK N Divider Power Control
0: BCLK N divider powered down
1: BCLK N divider powered up
D6-D0
000 0001 ASI1 BCLK N Divider value
0000 0000: BCLK N divider = 128
0000 0001: BCLK N divider = 1
...
1111 1110: BCLK N divider = 126
1111 1111: BCLK N divider = 127
Book 0 / Page 4 / Register 13: ASI 1, Word Clock N Divider - 0x00 / 0x04 / 0x0D (B0_P4_R13)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
ASI1 WCLK Divider Power Control
0: Primary WCLK N divider is powered down
1: Primary WCLK N divider is powered up
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Book 0 / Page 4 / Register 13: ASI 1, Word Clock N Divider - 0x00 / 0x04 / 0x0D (B0_P4_R13) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D0
R/W
010 0000 ASI1 WCLK N Divider value
000 0000: Primary WCLK divider N = 128
010 0000: Primary WCLK divider N = 32
010 0001: Primary WCLK divider N = 33
…
111 1110: Primary WCLK divider N = 126
111 1111: Primary WCLK divider N = 127
Book 0 / Page 4 / Register 14: ASI1, BCLK and WCLK Output - 0x00 / 0x04 / 0x0E (B0_P4_R14)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0000
ASI1 Bit Clock Output Mux
0000: Bit Clock Output = ASI1 Bit Clock Divider Output
0001: Reserved. Do not use.
0010: Bit Clock Output = ASI2 Bit Clock Divider Output
0011: Bit Clock Output = ASI2 Bit Clock Input
0100: Bit Clock Output = ASI3 Bit Clock Divider Output
0101: Bit Clock Output = ASI3 Bit Clock Input
0110: Bit Clock Output = ASI1 ADC Bit Clock
0111: Bit Clock Output = ASI2 ADC Bit Clock
1000-1111: Reserved. Do not use.
D3-D0
R/W
0000
ASI1 Word Clock Output Mux
0000: Word Clock Output = Generated DAC_FS
0001: Word Clock Output = Generated ADC_FS
0010: Word Clock Output = ASI1 Word Clock Divider Output
0011: Reserved. Do not use.
0100: Word Clock Output = ASI2 Word Clock Divider Output
0101: Word Clock Output = ASI2 Word Clock Input
0110: Word Clock Output = ASI3 Word Clock Divider Output
0111: Word Clock Output = ASI3 Word Clock Input
1000: Word Clock Output = ASI1 ADC Word Clock
1001: Word Clock Output = ASI2 ADC Word Clock
1010-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 15: ASI1, Data Output - 0x00 / 0x04 / 0x0F (B0_P4_R15)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1-D0
R
0000 00
00
Reserved. Write only default values.
R/W
ASI1 Data Output Control
00: DOUT1 from Codec ASI1 Output
01: DOUT1 from ASI1 Data Input (Pin-to-Pin Loopback)
10: DOUT1 from ASI2 Data Input (Pin-to-Pin Loopback)
11: DOUT1 from ASI3 Data Input (Pin-to-Pin Loopback)
Book 0 / Page 4 / Register 16: ASI1, ADC Word Clock and Bit Clock Control - 0x00 / 0x04 / 0x10
(B0_P4_R16)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only default values.
D6-D4
R/W
000
ASI1 ADC Word Clock Control for Six-Wire Interface
000: ADC Word Clock is same as DAC Word Clock (Default 4-wire Interface)
001: ADC Word Clock is input or output on GPIO1
010: ADC Word Clock is input or output on GPIO2
011: ADC Word Clock is input on GPIO3
100: ADC Word Clock is input on GPIO4
101-111: Reserved. Do not use.
D3
R
0
Reserved. Write only default values.
200
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 16: ASI1, ADC Word Clock and Bit Clock Control - 0x00 / 0x04 / 0x10
(B0_P4_R16) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D2-D0
R/W
000
ASI1 ADC Bit Clock Control for Six-Wire Interface
000: ADC Bit Clock is same as DAC Bit Clock (Default 4-wire Interface)
001: ADC Bit Clock is inputor output on GPIO1
010: ADC Bit Clock is input or output on GPIO2
011: ADC Bit Clock is input on GPIO3
100: ADC Bit Clock is input on GPIO4
101-111: Reserved. Do not use.
Book 0 / Page 4 / Register 17: ASI2, Audio Bus Format Control Register - 0x00 / 0x04 / 0x11 (B0_P4_R17)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R/W
000
ASI2, format selection
000: ASI2 Audio Interface = I2S
001: ASI2 Audio Interface = DSP
010: ASI2 Audio Interface = RJF
011: ASI2 Audio Interface = LJF
100: ASI2 Audio Interface = Mono PCM
101: Reserved. Do not use.
D4-D3
R/W
0 0
ASI2 Data Word Length Selection
00: ASI2 Data Word length = 16 bits
01: ASI2 Data Word length = 20 bits
10: ASI2 Data Word length = 24 bits
11: ASI2 Data Word length = 32 bits
D2-D1
D0
R
00
0
Reserved. Write only default values.
R/W
ASI2 Data Output High Impendance Output Control
0: DOUT2 will not be high impedance while ASI2 is active
1: DOUT2 will be high impedance after data has been transferred
Book 0 / Page 4 / Register 18: ASI2, Data Offset Control Register - 0x00 / 0x04 / 0x12 (B0_P4_R18)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 ASI2 Data Offset Value (Ch_Offset_1) relative to rising edge of Word Clock (Offset measured from
Rising Edge of Word Clock in DSP mode)
0000 0000: Data Offset 1 = 0 BCLK's
0000 0001: Data Offset 1= 1 BCLK's
...
1111 1110: Data Offset 1 = 254 BCLK's
1111 1111: Data Offset 1 = 255 BCLK's
Book 0 / Page 4 / Register 19-20: Reserved Registers - 0x00 / 0x04 / 0x13-0x14 (B0_P4_R19-20)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 21: ASI2, ADC Audio Bus Format Control Register - 0x00 / 0x04 / 0x15
(B0_P4_R21)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R/W
000
Secondary Audio Serial ADC Interface Format Selection (This control is only valid if D2 bit = '1'.)
000: ASI2 ADC Audio Interface = I2S
001: ASI2 ADC Audio Interface = DSP
010: ASI2 ADC Audio Interface = RJF
011: ASI2 ADC Audio Interface = LJF
100: ASI2 ADC Audio Interface = Mono PCM
101-111: Reserved. Do not use.
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Book 0 / Page 4 / Register 21: ASI2, ADC Audio Bus Format Control Register - 0x00 / 0x04 / 0x15
(B0_P4_R21) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D4-D3
R/W
0 0
Secondary Audio Serial ADC Interface Data Word Length Selection (This control is only valid if D2
bit = '1'.)
00: ASI2 ADC Data Word length = 16 bits
01: ASI2 ADC Data Word length = 20 bits
10: ASI2 ADC Data Word length = 24 bits
11: ASI2 ADC Data Word length = 32 bits
D2
R/W
R
0
Secondary Audio Serial ADC Six-Wire Format and Wordlength Enable
0: ASI2 ADC pathway uses same interface format and wordlength as in B0_P4_R17.
1: ASI2 ADC pathway use interface format defined in D[7:5] and wordlength defined in D[4:2] of
this register.
D1-D0
00
Reserved. Write only default values.
Book 0 / Page 4 / Register 22: Reserved Register - 0x00 / 0x04 / 0x16 (B0_P4_R22)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 23: ASI2, ADC Input Control - 0x00 / 0x04 / 0x17 (B0_P4_R23)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
D2-D0
R
0000 0
000
Reserved. Write only default values.
ASI2 ADC Input Control
R/W
000: ASI2 digital audio output data source disabled (No serial data output on external ASI2 bus.
ASI2 digital output is tri-stated.)
001: ASI2_DigitalOutput[1:2] is sourced from miniDSP_A_DataOutput[1:2]
010: ASI2_DigitalOutput[1:2] is is sourced from ASI1 DataInput (ASI1-to-ASI2 loopback)
011: ASI2_DigitalOutput[1:2] is is sourced from ASI2 DataInput (ASI2-to-ASI1 loopback)
100: ASI2_DigitalOutput[1:2] is is sourced from ASI3 DataInput (ASI3-to-ASI1 digital loopback)
101: ASI2_DigitalOutput[1:2] is sourced from miniDSP_A_DataOutput[3:4]
110-111: Reserved. Do not use.
Book 0 / Page 4 / Register 24: ASI 2, DAC Output Control - 0x00 / 0x04 / 0x18 (B0_P4_R24)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
R/W
R
00
ASI2 Left DAC Datapath
00: ASI2 Left DAC Datapath = Off
01: ASI2 Left DAC Datapath = Left Data
10: ASI2 Left DAC Datapath = Right Data
11: ASI2 Left DAC Datapath = Mono Mix of Left and Right
D5-D4
D3-D0
00
ASI2 Right DAC Datapath
00: ASI2 Right DAC Datapath = Off
01: ASI2 Right DAC Datapath = Right Data
10: ASI2 Right DAC Datapath = Left Data
11: ASI2 Right DAC Datapath = Mono Mix of Left and Right
0000
Reserved. Write only default values.
Book 0 / Page 4 / Register 25: Reserved Register - 0x00 / 0x04 / 0x19 (B0_P4_R25)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 26: ASI2, Word Clock and Bit Clock Control Register - 0x00 / 0x04 / 0x1A
(B0_P4_R26)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R
00
Reserved. Write only default values.
202
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 26: ASI2, Word Clock and Bit Clock Control Register - 0x00 / 0x04 / 0x1A
(B0_P4_R26) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5
R/W
0
ASI2 Word Clock Direction Control
0: WCLK2 pin is input to ASI2
1: WCLK2 pin is output from ASI2
D4-D3
D2
R
0 0
0
Reserved. Write only default values.
R/W
ASI2 Bit Clock Direction Control
0: BCLK2 pin is input to ASI2 Bit Clock
1: BCLK2 pin is output from ASI2 Bit Clock
D1
D0
R/W
R/W
0
0
ASI2 Bit Clock Polarity Control
0: Default Bit Clock polarity
1: Bit Clock is inverted w.r.t. default polarity
ASI2 Bit Clock and Word Clock Power control
0: ASI2 Bit Clock and Word Clock buffers are powered down when the codec is powered down or
ASI2 is inactive
1: ASI2 Bit Clock and Word Clock buffers are powered up when they are used in clock generation
even when the codec is powered down
Book 0 / Page 4 / Register 27: ASI2, Bit Clock N Divider Input Control - 0x00 / 0x04 / 0x1B (B0_P4_R27)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
ASI2_ADC_BCLK_OUT configuration used for 6-wire mode with ADC Bit Clock as output:
0: ASI2_ADC_BCLK_OUT = ASI2_BCLK_OUT configured in B0_P4_R30_D[7:4].
1: ASI2_ADC_BCLK_OUT can be different from ASI2_BCLK_OUT and is configured in
B0_P4_R116_D[7:4].
D6
R/W
0
ASI2_ADC_WCLK_OUT configuration used for 6-wire mode with ADC Bit Clock as output:
0: ASI2_ADC_WCLK_OUT = ASI2_WCLK_OUT configured in B0_P4_R30_D[3:0].
1: ASI2_ADC_WCLK_OUT can be different from ASI2_WCLK_OUT and is configured in
B0_P4_R116_D[3:0].
D5-D4
D1-D0
R
00
00
Reserved. Write only default values.
R/W
ASI2_BDIV_CLKIN Multiplexer Control
0000: ASI2_BDIV_CLKIN = DAC_CLK (Generated On-Chip)
0001: ASI2_BDIV_CLKIN = DAC_MOD_CLK (Generated On-Chip)
0010: ASI2_BDIV_CLKIN = ADC_CLK (Generated On-Chip)
0011: ASI2_BDIV_CLKIN = ADC_MOD_CLK (Generated On-Chip)
0100: ASI2_BDIV_CLKIN = ASI1 Bit Clock Input Pin
0101: ASI2_BDIV_CLKIN = ASI2 Bit Clock Input Pin
0110: ASI2_BDIV_CLKIN = ASI3 Bit Clock Input Pin
0111: ASI2_BDIV_CLKIN = ASI1 ADC Bit Clock Input Pin (6-wire interface)
1000: ASI2_BDIV_CLKIN = ASI2 ADC Bit Clock Input Pin (6-wire interface)
1001-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 28: ASI2, Bit Clock N Divider - 0x00 / 0x04 / 0x1C (B0_P4_R28)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
ASI2 BCLK Divider Power Control
0: Secondary BCLK N divider is powered down
1: Secondary BCLK N divider is powered up
D6-D0
000 0001 ASI2 BCLK N Divider value
000 0000: Secondary BCLK divider N = 128
000 0001: Secondary BCLK divider N = 1
000 0010: Secondary BCLK divider N = 2
…
111 1110: Secondary BCLK divider N = 126
111 1111: Secondary BCLK divider N = 127
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Book 0 / Page 4 / Register 29: ASI2, Word Clock N Divider - 0x00 / 0x04 / 0x1D (B0_P4_R29)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
ASI2 WCLK Divider Power Control
0: Secondary WCLK N divider is powered down
1: Secondary WCLK N divider is powered up
D6-D0
010 0000 ASI2 WCLK N Divider value
000 0000: Secondary WCLK divider N = 128
010 0000: Secondary WCLK divider N = 32
010 0001: Secondary WCLK divider N = 33
…
111 1110: Secondary WCLK divider N = 126
111 1111: Secondary WCLK divider N = 127
Book 0 / Page 4 / Register 30: ASI2, Bit Clock and Word Clock Output - 0x00 / 0x04 / 0x1E (B0_P4_R30)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0010
ASI2 Bit Clock Output Mux
0000: ASI2_BCLK_OUT = ASI1 Bit Clock Divider Output (ASI1_BDIV_OUT)
0001: ASI2_BCLK_OUT = ASI1 Bit Clock Input (ASI1_BCLK)
0010: ASI2_BCLK_OUT = ASI2 Bit Clock Divider Output (ASI2_BDIV_OUT)
0011: Reserved. Do not use.
0100: ASI2_BCLK_OUT = ASI3 Bit Clock Divider Output (ASI3_BDIV_OUT)
0101: ASI2_BCLK_OUT = ASI3 Bit Clock Input (ASI3_BCLK)
0110: ASI2_BCLK_OUT = ASI1 ADC Bit Clock
0111: ASI2_BCLK_OUT = ASI2 ADC Bit Clock
1000-1111: Reserved. Do not use.
D2-D0
R/W
000
ASI2 Word Clock Output Mux
0000: ASI2_WCLK_OUT = Generated DAC_FS
0001: ASI2_WCLK_OUT = Generated ADC_FS
0010: ASI2_WCLK_OUT = ASI1 Word Clock Divider Output (ASI1_WDIV_OUT)
0011: ASI2_WCLK_OUT = ASI1 Word Clock Input (ASI1_WCLK)
0100: ASI2_WCLK_OUT = ASI2 Word Clock Divider Output (ASI2_WDIV_OUT)
0101: Reserved. Do not use.
0110: ASI2_WCLK_OUT = ASI3 Word Clock Divider Output (ASI3_WDIV_OUT)
0111: ASI2_WCLK_OUT = ASI3 Word Clock Input (ASI3_WCLK)
1000: ASI2_WCLK_OUT = ASI1 ADC Word Clock
1001: ASI2_WCLK_OUT = ASI2 ADC Word Clock
1010-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 31: ASI2, Data Output - 0x00 / 0x04 / 0x1F (B0_P4_R31)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1-D0
R
0000 00
00
Reserved. Write only default values.
R/W
ASI2 Data Output Control
00: DOUT2 from Codec ASI2 Output
01: DOUT2 from ASI1 Data Input (Pin-to-Pin Loopback)
10: DOUT2 from ASI2 Data Input (Pin-to-Pin Loopback)
11: DOUT2 from ASI3 Data Input (Pin-to-Pin Loopback)
Book 0 / Page 4 / Register 32: ASI2, ADC Word Clock and Bit Clock Control - 0x00 / 0x04 / 0x20
(B0_P4_R32)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only default values.
D6-D4
R/W
000
ASI2 ADC Word Clock Control for Six-Wire Interface
000: ADC Word Clock is same as DAC Word Clock (Default 4-wire Interface)
001: ADC Word Clock is input or output on GPIO1
010: ADC Word Clock is input or output on GPIO2
011: ADC Word Clock is input on GPIO3
100: ADC Word Clock is input on GPIO4
101-111: Reserved. Do not use.
204
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 32: ASI2, ADC Word Clock and Bit Clock Control - 0x00 / 0x04 / 0x20
(B0_P4_R32) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3
R
0
Reserved. Write only default values.
D2-D0
R/W
000
ASI2 ADC Bit Clock Control for Six-Wire Interface
000: ADC Bit Clock is same as DAC Bit Clock (Default 4-wire Interface)
001: ADC Bit Clock is input or output on GPIO1
010: ADC Bit Clock is input or output on GPIO2
011: ADC Bit Clock is input on GPIO3
100: ADC Bit Clock is input on GPIO4
101-111: Reserved. Do not use.
Book 0 / Page 4 / Register 33: ASI3, Audio Bus Format Control Register - 0x00 / 0x04 / 0x21 (B0_P4_R33)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R/W
000
ASI3, format selection
000: ASI3 Audio Interface = I2S
001: ASI3 Audio Interface = DSP
010: ASI3 Audio Interface = RJF
011: ASI3 Audio Interface = LJF
100: ASI3 Audio Interface = Mono PCM
101-111: Reserved. Do not use.
D4-D3
R/W
0 0
ASI3, Data Word Length Selection
00: ASI3 Data Word length = 16 bits
01: ASI3 Data Word length = 20 bits
10: ASI3 Data Word length = 24 bits
11: ASI3 Data Word length = 32 bits
D2-D1
D0
R
00
0
Reserved. Write only default values.
R/W
DOUT3 High Impendance Output Control
0: DOUT3 will not be high impedance while ASI1 is active
1: DOUT3 will be high impedance after data has been transferred
Book 0 / Page 4 / Register 34: ASI3, Data Offset Control Register - 0x00 / 0x04 / 0x22 (B0_P4_R34)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 ASI3 Data Offset Value (Ch_Offset_1) relative to rising edge of Word Clock (Offset measured from
Rising Edge of Word Clock in DSP mode)
0000 0000: Data Offset 1 = 0 BCLK's
0000 0001: Data Offset 1= 1 BCLK's
...
1111 1110: Data Offset 1 = 254 BCLK's
1111 1111: Data Offset 1 = 255 BCLK's
Book 0 / Page 4 / Register 35-36: Reserved Registers - 0x00 / 0x04 / 0x23-0x24 (B0_P4_R35-36)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 37: Reserved Register - 0x00 / 0x04 / 0x25 (B0_P4_R37)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D3
D2
R/W
R/W
R/W
R
000
0 0
0
Reserved. Write only default values.
Reserved. Write only default values.
Reserved. Write only default values.
D1-D0
00
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Book 0 / Page 4 / Register 38: Reserved Register - 0x00 / 0x04 / 0x26 (B0_P4_R38)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 39: ASI3, ADC Input Control - 0x00 / 0x04 / 0x27 (B0_P4_R39)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
D2-D0
R
0000 0
000
Reserved. Write only default values.
ASI3 ADC Input Control
R/W
000: ASI3 digital audio output data source disabled (No serial data output on external ASI3 bus.
ASI3 digital output is tri-stated.)
001: ASI3_DataOutput[1:2] data is sourced from miniDSP_ADataOutput[1:2]
010: ASI3_DataOutput[1:2] is sourced from ASI1_DataInput[1:2] (ASI1-to-ASI3 loopback)
011: ASI3_DataOutput[1:2] is sourced from ASI2_DataInput[1:2] (ASI2-to-ASI3 loopback)
100: ASI3_DataOutput[1:2] is sourced from ASI3_DataInput[1:2] (ASI3-to-ASI3 loopback)
101: Reserved. Do not use.
110: ASI3_DataOutput[1:2] is sourced from miniDSP_A_DataOutput[5:6]
111: Reserved. Do not use.
Book 0 / Page 4 / Register 40: ASI3, DAC Output Control - 0x00 / 0x04 / 0x28 (B0_P4_R40)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
R/W
R
00
ASI3 Left DAC Datapath
00: ASI3 Left DAC Datapath = Off
01: ASI3 Left DAC Datapath = Left Data
10: ASI3 Left DAC Datapath = Right Data
11: ASI3 Left DAC Datapath = Mono Mix of Left and Right
D5-D4
D3-D0
00
ASI3 Right DAC Datapath
00: ASI3 Right DAC Datapath = Off
01: ASI3 Right DAC Datapath = Right Data
10: ASI3 Right DAC Datapath = Left Data
11: ASI3 Right DAC Datapath = Mono Mix of Left and Right
0000
Reserved. Write only default values.
Book 0 / Page 4 / Register 41: Reserved Register - 0x00 / 0x04 / 0x29 (B0_P4_R41)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 42: ASI3, Word Clock and Bit Clock Control Register - 0x00 / 0x04 / 0x2A
(B0_P4_R42)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1
R
000000
0
Reserved. Write only default values.
R/W
ASI3 Audio Bit Clock Polarity Control
0: Default Bit Clock polarity
1: Bit Clock is inverted w.r.t. default polarity
D0
R/W
0
ASI3 Bit Clock and Word Clock Power control
0: ASI3 Bit Clock and ASI3 Word Clock buffers are powered down when the codec is powered
down or ASI3 is inactive
1: ASI3 Bit Clock and Word Clock buffers are powered up when they are used in clock generation
even when the codec is powered down
Book 0 / Page 4 / Register 43: ASI3, Bit Clock N Divider Input Control - 0x00 / 0x04 / 0x2B (B0_P4_R43)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
D6
R/W
R/W
0
0
Reserved. Write only default values.
Reserved. Write only default values.
206
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 43: ASI3, Bit Clock N Divider Input Control - 0x00 / 0x04 / 0x2B
(B0_P4_R43) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5-D4
D3-D0
R
00
Reserved. Write only default values.
ASI3_BDIV_CLKIN Multiplexer Control
R/W
0000
0000: ASI3_BDIV_CLKIN = DAC_CLK (Generated On-Chip)
0001: ASI3_BDIV_CLKIN = DAC_MOD_CLK (Generated On-Chip)
0010: ASI3_BDIV_CLKIN = ADC_CLK (Generated On-Chip)
0011: ASI3_BDIV_CLKIN = ADC_MOD_CLK (Generated On-Chip)
0100: ASI3_BDIV_CLKIN = ASI1 Bit Clock Input Pin
0101: ASI3_BDIV_CLKIN = ASI2 Bit Clock Input Pin
0110: ASI3_BDIV_CLKIN = ASI3 Bit Clock Input Pin
0111: ASI3_BDIV_CLKIN = ASI1 ADC Bit Clock Input Pin (6-wire interface)
1000: ASI3_BDIV_CLKIN = ASI2 ADC Bit Clock Input Pin (6-wire interface)
1001-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 44: ASI3, Bit Clock N Divider - 0x00 / 0x04 / 0x2C (B0_P4_R44)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
ASI3 Bit Clock Divider Power Control
0: ASI3 Bit Clock N divider is powered down
1: ASI3 Bit Clock N divider is powered up
D6-D0
000 0001 ASI3 Bit Clock N Divider value
000 0000: ASI3 Bit Clock divider N = 128
000 0001: ASI3 Bit Clock divider N = 1
000 0010: ASI3 Bit Clock divider N = 2
…
111 1110: ASI3 Bit Clock divider N = 126
111 1111: ASI3 Bit Clock divider N = 127
Book 0 / Page 4 / Register 45: ASI3, Word Clock N Divider - 0x00 / 0x04 / 0x2D (B0_P4_R45)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
ASI3 Word Clock Divider Power Control
0: ASI3 Word Clock N divider is powered down
1: ASI3 Word Clock N divider is powered up
D6-D0
010 0000 ASI3 Word Clock N Divider value
000 0000: ASI3 Word Clock divider N = 128
010 0000: ASI3 Word Clock divider N = 32
010 0001: ASI3 Word Clock divider N = 33
…
111 1110: ASI3 Word Clock divider N = 126
111 1111: ASI3 Word Clock divider N = 127
Book 0 / Page 4 / Register 46: ASI3, Bit Clock and Word Clock Output - 0x00 / 0x04 / 0x2E (B0_P4_R46)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0100
ASI3 Bit Clock Output Mux
0000: ASI3_BCLK_OUT = ASI1 Bit Clock Divider Output (ASI1_BDIV_OUT)
0001: ASI3_BCLK_OUT = ASI1 Bit Clock Input (ASI1_BCLK)
0010: ASI3_BCLK_OUT = ASI2 Bit Clock Divider Output (ASI2_BDIV_OUT)
0011: ASI3_BCLK_OUT = ASI2 Bit Clock Input (ASI2_BCLK)
0100: ASI3_BCLK_OUT = ASI3 Bit Clock Divider Output (ASI3_BDIV_OUT)
0101: Reserved. Do not use.
0110: ASI3_BCLK_OUT = ASI1 ADC Bit Clock
0111: ASI3_BCLK_OUT = ASI2 ADC Bit Clock
1000-1111: Reserved. Do not use.
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Book 0 / Page 4 / Register 46: ASI3, Bit Clock and Word Clock Output - 0x00 / 0x04 / 0x2E
(B0_P4_R46) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D0
R/W
0000
ASI3 Word Clock Output Mux
0000: ASI3_WCLK_OUT = Generated DAC_FS
0001: ASI3_WCLK_OUT = Generated ADC_FS
0010: ASI3_WCLK_OUT = ASI1 Word Clock Divider Output (ASI1_WDIV_OUT)
0011: ASI3_WCLK_OUT = ASI1 Word Clock Input (ASI1_WCLK)
0100: ASI3_WCLK_OUT = ASI2 Word Clock Divider Output (ASI2_WDIV_OUT)
0101: ASI3_WCLK_OUT = ASI2 Word Clock Input (ASI2_WCLK)
0110: ASI3_WCLK_OUT = ASI3 Word Clock Divider Output (ASI3_WDIV_OUT)
0111: Reserved. Do not use.
1000: ASI3_WCLK_OUT = ASI1 ADC Word Clock
1001: ASI3_WCLK_OUT = ASI2 ADC Word Clock
1010-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 47: ASI3, Data Output - 0x00 / 0x04 / 0x2F (B0_P4_R47)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1-D0
R
0000 00
00
Reserved. Write only default values.
R/W
ASI3 Data Output Control
00: DOUT3 from Codec ASI 3 Output
01: DOUT3 from ASI1 Data Input (Pin-to-Pin Loopback)
10: DOUT3 from ASI2 Data Input (Pin-to-Pin Loopback)
11: DOUT3 from ASI3 Data Input (Pin-to-Pin Loopback)
Book 0 / Page 4 / Register 48: Reserved Register. - 0x00 / 0x04 / 0x30 (B0_P4_R48)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 49: ASI1 L1, R1 Input Control - 0x00 / 0x04 / 0x31 (B0_P4_R49)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D0
R
000
Reserved. Write only default values.
R/W
0 0001
Stereo Pair 1 Input Control (Valid for both Stereo mode and Multi-pin mode)
00000: No input selected. Data will be all zeroes.
00001: Left and Right Channels will be from DIN1 for Stereo Mode (L1, R1 for Multipin Mode)
00010-11111: Reserved. Do not use.
Book 0 / Page 4 / Register 50: ASI1 L2, R2 Input Control - 0x00 / 0x04 / 0x32 (B0_P4_R50)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D0
R
000
Reserved. Write only default values.
R/W
0 0000
Stereo Pair 2 Input Control (Valid for only Multi-pin mode. Do not use this register for single-pin or
stereo mode.)
00000: No input selected. Data will be all zeroes.
00001: Reserved. Do not use.
00010-00100: Reserved. Do not use.
00101: L2, R2 Channels will be input from GPIO2
00110: L2, R2 Channels will be input from GPIO3
00111-11111: Reserved. Do not use.
Book 0 / Page 4 / Register 51: ASI1 L3, R3 Input Control - 0x00 / 0x04 / 0x33 (B0_P4_R51)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R
000
Reserved. Write only default values.
208
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 51: ASI1 L3, R3 Input Control - 0x00 / 0x04 / 0x33 (B0_P4_R51) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D4-D0
R/W
0 0000
Stereo Pair 3 Input Control (Valid for only Multi-pin mode. Do not use this register for single-pin or
stereo mode.)
00000: No input selected. Data will be all zeroes.
00001-00011: Reserved. Do not use.
00100: L3, R3 Channels will be input from GPIO1
00101: L3, R3 Channels will be input from GPIO2
00110: L3, R3 Channels will be input from GPIO3
00111: Reserved. Do not use.
01000: L3, R3 Channels will be input from GPIO5
01001-11111: Reserved. Do not use.
Book 0 / Page 4 / Register 52: ASI1 L4, R4 Input Control - 0x00 / 0x04 / 0x34 (B0_P4_R52)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
D4-D0
R
000
Reserved. Write only default values.
R/W
0 0000
Stereo Pair 4 Input Control (Valid for only Multi-pin mode. Do not use this register for single-pin or
stereo mode.)
00000: No input selected. Data will be all zeroes.
00001-00011: Reserved. Do not use.
00100: L4, R4 Channels will be input from GPIO1
00101: L4, R4 Channels will be input from GPIO2
00110: L4, R4 Channels will be input from GPIO3
00111: Reserved. Do not use.
01000: L4, R4 Channels will be input from GPIO5
01001-01101: Reserved. Do not use.
01110: L4, R4 Channels will be input from WCLK2
01111-11111: Reserved. Do not use.
Book 0 / Page 4 / Register 53: Reserved Register - 0x00 / 0x04 / 0x35 (B0_P4_R53)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 54: ASI2, DIN Input Multiplexer Control - 0x00 / 0x04 / 0x36 (B0_P4_R54)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
D2-D0
R
0000 0
000
Reserved. Write only default values.
Reserved. Write only default values.
R/W
Book 0 / Page 4 / Register 55: ASI3, Word Clock and Bit Clock Input Multiplexer Control - 0x00 / 0x04 /
0x37 (B0_P4_R55)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only default values.
D6-D4
R/W
000
ASI3 Word Clock Control
000-001: Reserved. Do not use.
010: ASI3_WCLK is input or output on GPIO2
011-111: Reserved. Do not use.
D3
R
0
Reserved. Write only default values.
D2-D0
R/W
000
ASI3 Bit Clock Control
000: Reserved. Do not use.
001: ASI3_BCLK is input or output on GPIO1
010-111: Reserved. Do not use.
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Book 0 / Page 4 / Register 56: ASI3, DIN Input Multiplexer Control - 0x00 / 0x04 / 0x38 (B0_P4_R56)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D3
D2-D0
R
0000 0
000
Reserved. Write only default values.
R/W
ASI3 Data Input Multiplexer Control
000-010: Reserved. Do not use.
011: ASI3_DIN is input on GPIO3.
110-111: Reserved. Do not use.
Book 0 / Page 4 / Register 57-64: Reserved Registers - 0x00 / 0x04 / 0x39-0x40 (B0_P4_R57-64)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 65: WCLK1 (Input or Output) Pin Control - 0x00 / 0x04 / 0x41 (B0_P4_R65)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5-D2
R
00
Reserved. Write only default values.
R/W
00 01
WCLK1 Pin Control
0000: Reserved. Do not use.
0001: WCLK1 is ASI1 Word Clock Input or Output. (Note: B0_P4_R10 defines ASI1 Word Clock
routing.)
0010-0011: Reserved. Do not use.
0100: WCLK1 pin is CLKOUT output.
D1-D0
R
00
Reserved. Write only default values.
Book 0 / Page 4 / Register 66: Reserved Register - 0x00 / 0x04 / 0x42 (B0_P4_R66)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values.
Book 0 / Page 4 / Register 67: DOUT1 (Output) Pin Control - 0x00 / 0x04 / 0x43 (B0_P4_R67)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
00
1
Reserved. Write only reset values.
R/W
DOUT1 Bus Keeper Control
0: DOUT1 Bus Keeper Enabled
1: DOUT1 Bus Keeper Disabled
D4-D1
R/W
0 001
DOUT1 Pin Control
0000: DOUT1 disabled
0001: DOUT1 is ASI1 Data Output
0010: DOUT1 is General Purpose Output
0011: DOUT1 is CLKOUT
0100: DOUT1 is INT1
0101: DOUT1 is INT2
0110: DOUT1 is SAR ADC interrupt as defined in B0_P3
0111-1111: Reserved. Do not use.
D0
R/W
0
DOUT1 as General Purpose Output
0: DOUT1 General Purpose Output is '0'
1: DOUT1 General Purpose Output is '1'
Book 0 / Page 4 / Register 68: DIN1 (Input) Pin Control - 0x00 / 0x04 / 0x44 (B0_P4_R68)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
210
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Book 0 / Page 4 / Register 68: DIN1 (Input) Pin Control - 0x00 / 0x04 / 0x44 (B0_P4_R68) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D5
R/W
01
DIN1 Pin Control
00: DIN1 Disabled with input buffer powered down.
01: DIN1 Enabled with auto-power-down of input buffer if not actively used by the device.
Applicable for DIN1 used as Data Input for ASI1, Digital Microphone Input, PLL_CLKIN and
CDIV_CLKIN.
10: DIN1 Enabled with input buffer powered on. Required for DIN1 used as a General Purpose
Input and applicable for DIN1 used as Data Input for ASI1, Digital Microphone Input, PLL_CLKIN
and CDIV_CLKIN.
11: Reserved. Do not use
D4
R
R
X
DIN1 Input Pin State, used along with DIN1 as general purpose input
Reserved. Write only reset values.
D3-D0
0000
Book 0 / Page 4 / Register 69: WCLK2 (Input or Output) Pin Control - 0x00 / 0x04 / 0x45 (B0_P4_R69)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5-D2
R
00
Reserved. Write only reset values.
WCLK2 Pin Control
R/W
00 01
0000: WCLK2 pin Disabled (Input and Output buffers powered down)
0001: WCLK2 pin acts as ASI Secondary WCLK as defined in B0_P4_R26_D5
0010: WCLK2 pin is used as General Purpose Input (GPI) or chip input for any other purpose.
0011: WCLK2 pin Output = General Purpose Output
0100: WCLK2 pin Output = CLKOUT Output
0101: WCLK2 pin Output = INT1 Interrupt Output
0110: WCLK2 pin Output = INT2 Interrupt Output
0111-1000: Reserved. Do not use.
1001: WCLK2 pin Output = SAR ADC interrupt as defined in B0_P3
1010: WCLK2 pin Output = ADC_MOD_CLK Output for digital microphone
1011-1110: Reserved. Do not use.
1111: WCLK2 pin Output = L4, R4 Data Ouput for ASI1 (Multi-pin mode only)
D1
D0
R
X
0
WCLK2 Input Pin State, used along with WCLK2 as general purpose input
R/W
WCLK2 as General Purpose Output
0: WCLK2 General Purpose Output is '0'
1: WCLK2 General Purpose Output is '1'
Book 0 / Page 4 / Register 70: BCLK2 (Input or Output) Pin Control - 0x00 / 0x04 / 0x46 (B0_P4_R70)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5-D2
R
00
Reserved. Write only reset values
BCLK2 Pin Control
R/W
00 01
0000: BCLK2 pin Disabled (Input and Output buffers powered down)
0001: BCLK2 pin acts as ASI Secondary BCLK as defined in B0_P4_R26_D2
0010: BCLK2 pin is used as General Purpose Input (GPI) or chip input for any other purpose.
0011: BCLK2 pin Output = General Purpose Output
0100: BCLK2 pin Output = CLKOUT Output
0101: BCLK2 pin Output = INT1 Interrupt Output
0110: BCLK2 pin Output = INT2 Interrupt Output
0111-1000: Reserved. Do not use.
1001: BCLK2 pin Output = SAR ADC interrupt as defined in B0_P3
1010: BCLK2 pin Output = ADC_MOD_CLK Output for digital microphone
1011-1101: Reserved. Do not use.
1110: BCLK2 pin Output = L3, R3 Data Output for ASI1 (Multi-pin mode only)
1111: Reserved. Do not use.
D1
D0
R
X
0
BCLK2 Input Pin State, used along with BCLK2 as general purpose input
R/W
BCLK2 as General Purpose Output
0: BCLK2 General Purpose Output is '0'
1: BCLK2 General Purpose Output is '1'
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Book 0 / Page 4 / Register 71: DOUT2 (Output) Pin Control - 0x00 / 0x04 / 0x47 (B0_P4_R71)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
D5
R
00
1
Reserved. Write only reset values.
R/W
DOUT2 Bus Keeper Control
0: DOUT2 Bus Keeper Enabled
1: DOUT2 Bus Keeper Disabled
D4-D1
R/W
0 001
DOUT2 Pin Control
0000: DOUT2 pin disabled
0001: DOUT2 pin Output = ASI2 Data Output
0010: DOUT2 pin Output = General Purpose Output
0011: Reserved. Do not use.
0100: DOUT2 pin Output = INT1 Interrupt
0101: DOUT2 pin Output = INT2 Interrupt
0110: DOUT2 pin is SAR ADC interrupt as defined in B0_P3
0111-1001: Reserved. Do not use.
1010: DOUT2 pin Output = ADC_MOD_CLK Output for digital microphone
1011-1100: Reserved. Do not use.
1101: DOUT2 pin Output = L2, R2 Data Output for ASI1 (Multi-pin mode only)
1110-1111: Reserved. Do not use
D0
R/W
0
DOUT2 as General Purpose Output
0: DOUT2 General Purpose Output is '0'
1: DOUT2 General Purpose Output is '1'
Book 0 / Page 4 / Register 72: DIN2 (Input) Pin Control - 0x00 / 0x04 / 0x48 (B0_P4_R72)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values
DIN2 Pin Control
D6-D5
R/W
01
00: DIN2 Disabled with input buffer powered down.
01: DIN2 Enabled with auto-power-down of input buffer if not actively used by the device.
Applicable for DIN2 used as Data Input of ASI1 and ASI2, Dig_Mic_In, Low-Frequency Clock Input
(LFR_CLKIN) or ISR interrupt for miniDSP.
10: DIN2 Enabled with input buffer powered on. Required for DIN2 used as a General Purpose
Input and applicable for DIN2 used as Data Input of ASI1 and ASI2, Dig_Mic_In, Low-Frequency
Clock Input (LFR_CLKIN) or ISR interrupt for miniDSP.
11: Reserved. Do not use.
D4
R
R
X
DIN2 Input Pin State, used along with DIN2 as general purpose input
Reserved. Write only reset values.
D3-D0
0000
Book 0 / Page 4 / Register 73-74: Reserved Register - 0x00 / 0x04 / 0x49-0x4A (B0_P4_R73-74)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000
0100
Reserved. Write only reset values
Book 0 / Page 4 / Register 75: Reserved Register - 0x00 / 0x04 / 0x4B (B0_P4_R75)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0010
0010
Reserved. Write only reset values.
Book 0 / Page 4 / Register 76: Reserved Register - 0x00 / 0x04 / 0x4C (B0_P4_R76)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0010
0000
Reserved. Write only reset values
212
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Book 0 / Page 4 / Register 77-85: Reserved Registers - 0x00 / 0x04 / 0x4D-0x55 (B0_P4_R77-85)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values
Book 0 / Page 4 / Register 86: GPIO1 (Input or Output) Pin Control - 0x00 / 0x04 / 0x56 (B0_P4_R86)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values
GPIO1 Pin Control
D6-D2
R/W
000 00
00000: GPIO1 pin input or output disabled.
00001: GPIO1 pin = Input Mode, which can be used for Data Input for ASI1, digital microphone
input, clock input, general purpose input or ISR interrupt to miniDSP
00010: Reserved. Do not use.
00011: GPIO1 pin = General Purpose Output
00100: GPIO1 pin = CLKOUT Output
00101: GPIO1 pin = INT1 Interrupt Output
00110: GPIO1 pin = INT2 Interrupt Output
00111-01000: Reserved. Do not use.
01001: GPIO1 pin = SAR ADC interrupt as defined in B0_P3
01010: GPIO1 pin = ADC_MOD_CLK Output for digital microphone
01011: GPIO1 pin = Bit-Banged General Purpose Output (Value set in B0_P4_R104_D0)
01100-01101: Reserved. Do not use.
01110: GPIO1 pin = L3, R3 Data Output for ASI1 (Multi-pin mode only)
01111: GPIO1 pin = L4, R4 Data Output for ASI1 (Multi-pin mode only)
10000-10100: Reserved. Do not use.
10101: GPIO1 pin = ASI3 Bit Clock Output
10101: Reserved. Do not use.
10110: GPIO1 pin = ASI1 ADC Word Clock Output
10111: GPIO1 pin = ASI1 ADC Bit Clock Output
11000: GPIO1 pin = ASI2 ADC Word Clock Output
11001: GPIO1 pin = ASI2 ADC Bit Clock Output
11010-11111: Reserved. Do not use.
D1
D0
R
X
0
GPIO1 Input Pin state, used along with GPIO1 as general purpose input
R/W
GPIO1 as General Purpose Output
0: GPIO1 pin is driven to '0' in general purpose output mode
1: GPIO1 pin is driven to '1' in general purpose output mode
Book 0 / Page 4 / Register 87: GPIO2 (Input or Output) Pin Control - 0x00 / 0x04 / 0x57 (B0_P4_R87)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values
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Book 0 / Page 4 / Register 87: GPIO2 (Input or Output) Pin Control - 0x00 / 0x04 / 0x57
(B0_P4_R87) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D2
R/W
000 00
GPIO2 Pin Control
00000: GPIO2 pin input or output disabled.
00001: GPIO2 pin = Input Mode, which can be used for Data Input for ASI1, digital microphone
input, general purpose input or ISR interrupt to miniDSP.
00010: Reserved. Do not use.
00011: GPIO2 pin = General Purpose Output
00100: GPIO2 pin = CLKOUT Output
00101: GPIO2 pin = INT1 Interrupt Output
00110: GPIO2 pin = INT2 Interrupt Output
00111-01000: Reserved. Do not use.
01001: GPIO2 pin = SAR ADC interrupt as defined in B0_P3
01010: GPIO2 pin = ADC_MOD_CLK Output for digital microphone
01011: GPIO2 pin = Bit-Banged General Purpose Output (Value set in B0_P4_R104_D1)
01100: Reserved. Do not use.
01101: GPIO2 pin = L2, R2 Data Output for ASI1 (Multi-pin mode only)
01110: GPIO2 pin = L3, R3 Data Output for ASI1 (Multi-pin mode only)
01111: GPIO2 pin = L4, R4 Data Output for ASI1 (Multi-pin mode only)
10000-10011: Reserved. Do not use.
10100: GPIO2 pin = ASI3 Word Clock Output
10101: Reserved. Do not use.
10110: GPIO2 pin = ASI1 ADC Word Clock Output
10111: GPIO2 pin = ASI1 ADC Bit Clock Output
11000: GPIO2 pin = ASI2 ADC Word Clock Output
11001: GPIO2 pin = ASI2 ADC Bit Clock Output
11010-11111: Reserved. Do not use.
D1
D0
R
X
0
GPIO2 Input Pin state, used along with GPIO2 as general purpose input
R/W
GPIO2 as General Purpose Output
0: GPIO2 pin is driven to '0' in general purpose output mode
1: GPIO2 pin is driven to '1' in general purpose output mode
Book 0 / Page 4 / Register 88: GPIO3 (Input or Output) Pin Control - 0x00 / 0x04 / 0x58 (B0_P4_R88)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values
GPIO3 Pin Control
D6-D2
R/W
000 00
00000: GPIO3 pin input or output disabled.
00001: GPIO3 pin = Input Mode, which can be used for Data Input for ASI1, General Purpose
Input, ADC Clock Inputs for any ASI, digital microphone input, or ISR interrupt to miniDSP.
00010-00100: Reserved. Do not use.
00101: GPIO3 pin = INT1 interrupt
00110: GPIO3 pin = INT2 interrupt
00111-01001: Reserved. Do not use.
01010: GPIO3 pin = ADC_MOD_CLK Output for digital microphone
01011: GPIO3 pin = Bit-Banged General Purpose Output (Value set in B0_P4_R104_D2)
01100-10101: Reserved. Do no use.
10110: GPIO3 pin = ASI1 ADC Word Clock Output
10111: GPIO3 pin = ASI1 ADC Bit Clock Output
11000: GPIO3 pin = ASI1 ADC Word Clock Output
11001: GPIO3 pin = ASI2 ADC Bit Clock Output
11010-11111: Reserved. Do not use.
D1
D0
R
R
X
0
GPIO3 Input Pin state, used along with GPIO3 as general purpose input
Reserved. Write only reset values
Book 0 / Page 4 / Register 89: GPIO4 (Input or Output) Pin Control - 0x00 / 0x04 / 0x59 (B0_P4_R89)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values
214
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 89: GPIO4 (Input or Output) Pin Control - 0x00 / 0x04 / 0x59
(B0_P4_R89) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D6-D2
R/W
000 00
GPIO4 Pin Control
00000: GPIO4 pin input or output disabled.
00001: GPIO4 pin = Input Mode, which can be used for ADC Clock Inputs for any ASI, digital
microphone input, or general purpose input.
00010-00100: Reserved. Do not use.
00101: GPIO4 pin = INT1 interrupt
00110: GPIO4 pin = INT2 interrupt
00111-01001: Reserved. Do not use.
01010: GPIO4 pin = ADC_MOD_CLK Output for digital microphone
01011: GPIO4 pin = Bit-Banged General Purpose Output (Value set in B0_P4_R104_D3)
01100-10101: Reserved. Do not use.
10110: GPIO4 pin = ASI1 ADC Word Clock Output
10111: GPIO4 pin = ASI1 ADC Bit Clock Output
11000: GPIO4 pin = ASI1 ADC Word Clock Output
11001: GPIO4 pin = ASI2 ADC Bit Clock Output
11010-11100: Reserved. Do not use.
11101: GPIO4 pin = ASI3 Data Output
11110-11111: Reserved. Do not use.
D1
D0
R
R
X
0
GPIO4 Input Pin state, used along with GPIO4 as general purpose input
Reserved. Write only reset values.
Book 0 / Page 4 / Register 90: GPIO5 (Input or Output) Pin Control - 0x00 / 0x04 / 0x5A (B0_P4_R90)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values
GPIO5 Pin Control
D6-D2
R/W
000 00
00000: GPIO5 pin input or output disabled.
00001: GPIO5 pin = Input Mode, which can be used for Data Input for ASI1, or digital microphone
input.
00010-01001: Reserved. Do not use.
01010: GPIO5 pin = ADC_MOD_CLK Output for digital microphone
01011-11100: Reserved. Do not use.
11101: GPIO5 pin = ASI3 Data Output
11110-11111: Reserved. Do not use.
D1
D0
R
X
0
GPIO5 Input Pin state, used along with GPIO5 as general purpose input
R/W
GPIO5 as General Purpose Output
0: GPIO5 pin is driven to '0' in general purpose output mode
1: GPIO5 pin is driven to '1' in general purpose output mode
Book 0 / Page 4 / Register 91: Reserved Register - 0x00 / 0x04 / 0x5B (B0_P4_R91)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000
0000
Reserved. Write only reset values
Book 0 / Page 4 / Register 92-95: Reserved Registers - 0x00 / 0x04 / 0x5C-0x5F (B0_P4_R92-95)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values
Book 0 / Page 4 / Register 96: MISO_GPO1 (Output) Pin Control - 0x00 / 0x04 / 0x60 (B0_P4_R96)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D5
R
000
Reserved. Write only reset values
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Book 0 / Page 4 / Register 96: MISO_GPO1 (Output) Pin Control - 0x00 / 0x04 / 0x60
(B0_P4_R96) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D4-D1
R/W
0 001
MISO_GPO1 Pin Control
0000: MISO_GPO1 pin output disabled
0001: MISO_GPO1 pin is used for data output in SPI interface (MISO), is disabled for I2C interface
0010: MISO_GPO1 pin is General Purpose Output
0011: MISO_GPO1 pin is CLKOUT Output
0100: MISO_GPO1 pin is INT1 Interrupt Output
0101: MISO_GPO1 pin is INT2 Interrupt Output
0110: MISO_GPO1 pin is SAR ADC interrupt as defined in B0_P3
0111: MISO_GPO1 pin is ADC_MOD_CLK Output for Digital Microphone
1000-1100: Reserved. Do not use.
1101: MISO_GPO1 pin is L2, R2 Data Ouput for ASI1 (Multi-pin mode only)
1110: MISO_GPO1 pin is L3, R3 Data Ouput for ASI1 (Multi-pin mode only)
1111: Reserved. Do not use.
D0
R/W
0
MISO_GPO1 as General Purpose Output
0: MISO_GPO1 General Purpose Output Value = 0
1: MISO_GPO1 General Purpose Output Value = 1
Book 0 / Page 4 / Register 97-99: Reserved Registers - 0x00 / 0x04 / 0x61-0x63 (B0_P4_R97-99)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 4 / Register 100: Digital Microphone Clock Control - 0x00 / 0x04 / 0x64 (B0_P4_R100)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
1
Digital Microphone 1 Left Channel Clock Edge
0: Digital Microphone 1 Left Channel is latched on Rising Edge of ADC_MOD_CLK
1: Digital Microphone 1 Left Channel is latched on Falling Edge of ADC_MOD_CLK
D6
Digital Microphone 1 Right Channel Clock Edge
0: Digital Microphone 1 Right Channel is latched on Rising Edge of ADC_MOD_CLK
1: Digital Microphone 1 Right Channel is latched on Falling Edge of ADC_MOD_CLK
D5-D4
D3
R
00
0
Reserved. Write only reset values.
R/W
Digital Microphone 2 Left Channel Clock Edge
0: Digital Microphone 2 Left Channel is latched on Rising Edge of ADC_MOD_CLK
1: Digital Microphone 2 Left Channel is latched on Falling Edge of ADC_MOD_CLK
D2
R/W
R
1
Digital Microphone 2 Right Channel Clock Edge
0: Digital Microphone 2 Right Channel is latched on Rising Edge of ADC_MOD_CLK
1: Digital Microphone 2 Right Channel is latched on Falling Edge of ADC_MOD_CLK
D1-D0
00
Reserved. Write only reset values.
Book 0 / Page 4 / Register 101: Digital Microphone 1 Input Pin Control - 0x00 / 0x04 / 0x65 (B0_P4_R101)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0011
Digital Microphone 1 Left Data Input Control
0000: Left Channel Input is on GPIO1 pin
0001: Left Channel Input is on GPIO2 pin
0010: Left Channel Input is on GPIO3 pin
0011: Left Channel Input is on GPIO4 pin
0100: Left Channel Input is on GPIO5 pin
0101-0111: Reserved. Do not use.
1000: Left Channel Input is on DIN1 pin
1001: Left Channel Input is on DIN2 pin
1010-1111: Reserved. Do not use.
216
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TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 101: Digital Microphone 1 Input Pin Control - 0x00 / 0x04 / 0x65
(B0_P4_R101) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D0
R/W
0011
Digital Microphone 1 Right Data Input Control
0000: Right Channel Input is on GPIO1 pin
0001: Right Channel Input is on GPIO2 pin
0010: Right Channel Input is on GPIO3 pin
0011: Right Channel Input is on GPIO4 pin
0100: Right Channel Input is on GPIO5 pin
0101-0111: Reserved. Do not use.
1000: Right Channel Input is on DIN1 pin
1001: Right Channel Input is on DIN2 pin
1010-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 102: Digital Microphone 2 Input Pin Control - 0x00 / 0x04 / 0x66 (B0_P4_R102)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0100
Digital Microphone 2 Left Data Input Control
0000: Left Channel Input is on GPIO1 pin
0001: Left Channel Input is on GPIO2 pin
0010: Left Channel Input is on GPIO3 pin
0011: Left Channel Input is on GPIO4 pin
0100: Left Channel Input is on GPIO5 pin
0101-0111: Reserved. Do not use.
1000: Left Channel Input is on DIN1 pin
1001: Left Channel Input is on DIN2 pin
1010-1111: Reserved. Do not use.
D3-D0
R/W
0100
Digital Microphone 2 Right Data Input Control
0000: Right Channel Input is on GPIO1 pin
0001: Right Channel Input is on GPIO2 pin
0010: Right Channel Input is on GPIO3 pin
0011: Right Channel Input is on GPIO4 pin
0100: Right Channel Input is on GPIO5 pin
0101-0111: Reserved. Do not use.
1000: Right Channel Input is on DIN1 pin
1001: Right Channel Input is on DIN2 pin
1011-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 103: Reserved Register - 0x00 / 0x04 / 0x67 (B0_P4_R103)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 4 / Register 104: Bit-Bang Output - 0x00 / 0x04 / 0x68 (B0_P4_R104)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3
R
0000
0
Reserved. Write only reset values.
R/W
GPIO4 Bit Bang Data Output
0: GPIO4 Bit Bang Data Output = 0
1: GPIO4 Bit Bang Data Output = 1
D2
D1
D0
R/W
R/W
R/W
0
0
0
GPIO3 Bit Bang Data Output
0: GPIO3 Bit Bang Data Output = 0
1: GPIO3 Bit Bang Data Output = 1
GPIO2 Bit Bang Data Output
0: GPIO2 Bit Bang Data Output = 0
1: GPIO2 Bit Bang Data Output = 1
GPIO1 Bit Bang Data Output
0: GPIO1 Bit Bang Data Output = 0
1: GPIO1 Bit Bang Data Output = 1
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Book 0 / Page 4 / Register 105-106: Reserved Registers - 0x00 / 0x04 / 0x69-0x6A (B0_P4_R105-106)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 4 / Register 107: Bit-Bang Input - 0x00 / 0x04 / 0x6B (B0_P4_R107)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3
R
R
XXXX
X
Reserved. Write only reset values.
GPIO4 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R89_D1)
0: GPIO4 Bit Bang Data Input = 0
1: GPIO4 Bit Bang Data Input = 1
D2
D1
D0
R
R
R
X
X
X
GPIO3 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R88_D1)
0: GPIO3 Bit Bang Data Input = 0
1: GPIO3 Bit Bang Data Input = 1
GPIO2 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R87_D1)
0: GPIO2 Bit Bang Data Input = 0
1: GPIO2 Bit Bang Data Input = 1
GPIO1 Bit Bang Data Input (Input Buffer value also shown in B0_P4_R86_D1)
0: GPIO1 Bit Bang Data Input = 0
1: GPIO1 Bit Bang Data Input = 1
Book 0 / Page 4 / Register 108-112: Reserved Registers - 0x00 / 0x04 / 0x6C-0x70 (B0_P4_R108-112)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 4 / Register 113: Bit-Bang miniDSP Output Control - 0x00 / 0x04 / 0x71 (B0_P4_R113)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
D6
R
0
0
Reserved. Write only reset values.
R/W
0: Use B0_P4_R104 for bit-bang of outputs GPIO1, GPIO2, GPIO3, GPIO4 or GPIO6
1: Use miniDSP_D port for bit-bang of outputs GPIO1, GPIO2, GPIO3, GPIO4 or GPIO6
D5-D0
R
00 0000
Reserved. Write only reset values.
Book 0 / Page 4 / Register 114: Reserved Register - 0x00 / 0x04 / 0x72 (B0_P4_R114)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 0 / Page 4 / Register 115: ASI1, ADC Bit Clock and ADC Word Clock Output - 0x00 / 0x04 / 0x73
(B0_P4_R115)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0000
ASI1_ADC_BCLK_OUT mux control used for 6-wire ASI1 mode with ADC Bit Clock as output:
0000: ASI1_ADC_BCLK_OUT = ASI1 Bit Clock Divider Output (ASI1_BDIV_OUT)
0001: Reserved. Do not use.
0010: ASI1_ADC_BCLK_OUT = ASI2 Bit Clock Divider Output (ASI2_BDIV_OUT)
0011: ASI1_ADC_BCLK_OUT = ASI2 Bit Clock Input (ASI2_BCLK)
0100: ASI1_ADC_BCLK_OUT = ASI3 Bit Clock Divider Output (ASI3_BDIV_OUT)
0101: ASI1_ADC_BCLK_OUT = ASI3 Bit Clock Input (ASI3_BCLK)
0110: Reserved. Do not use.
0111: ASI1_ADC_BCLK_OUT = ASI2 ADC Bit Clock Output (ASI2_ADC_BCLK)
1000-1111: Reserved. Do not use.
218
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Book 0 / Page 4 / Register 115: ASI1, ADC Bit Clock and ADC Word Clock Output - 0x00 / 0x04 / 0x73
(B0_P4_R115) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D0
R/W
0000
ASI1_ADC_WCLK_OUT mux control used for 6-wire ASI1 mode with ADC Word Clock as output:
0000: ASI1_ADC_WCLK_OUT = Generated DAC_FS
0001: ASI1_ADC_WCLK_OUT = Generated ADC_FS
0010: ASI1_ADC_WCLK_OUT = ASI1 Word Clock Divider Output (ASI1_WDIV_OUT)
0011: Reserved. Do not use.
0100: ASI1_ADC_WCLK_OUT = ASI2 Word Clock Divider Output (ASI2_WDIV_OUT)
0101: ASI1_ADC_WCLK_OUT = ASI2 Word Clock Input (ASI2_WCLK)
0110: ASI1_ADC_WCLK_OUT = ASI3 Word Clock Divider Output (ASI3_WDIV_OUT)
0111: ASI1_ADC_WCLK_OUT = ASI3 Word Clock Input (ASI3_WCLK)
1000: Reserved. Do not use.
1001: ASI1_ADC_WCLK_OUT = ASI2 ADC Word Clock
1010-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 116: ASI2, ADC Bit Clock and ADC Word Clock Output - 0x00 / 0x04 / 0x74
(B0_P4_R116)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
R/W
0000
ASI2_ADC_BCLK_OUT mux control used for 6-wire ASI1 mode with ADC Bit Clock as output:
0000: ASI2_ADC_BCLK_OUT = ASI1 Bit Clock Divider Output (ASI1_BDIV_OUT)
0001: ASI2_ADC_BCLK_OUT = ASI1 Bit Clock Input (ASI1_BCLK)
0010: ASI2_ADC_BCLK_OUT = ASI2 Bit Clock Divider Output (ASI2_BDIV_OUT)
0011: Reserved. Do not use.
0100: ASI2_ADC_BCLK_OUT = ASI3 Bit Clock Divider Output (ASI3_BDIV_OUT)
0101: ASI2_ADC_BCLK_OUT = ASI3 Bit Clock Input (ASI3_BCLK)
0110: ASI2_ADC_BCLK_OUT = ASI1 ADC Bit Clock Output (ASI1_ADC_BCLK)
0111-1111: Reserved. Do not use.
D3-D0
R/W
0000
ASI2_ADC_WCLK_OUT mux control used for 6-wire ASI1 mode with ADC Word Clock as output:
0000: ASI2_ADC_WCLK_OUT = Generated DAC_FS
0001: ASI2_ADC_WCLK_OUT = Generated ADC_FS
0010: ASI2_ADC_WCLK_OUT = ASI1 Word Clock Divider Output (ASI1_WDIV_OUT)
0011: ASI2_ADC_WCLK_OUT = ASI1 Word Clock Input (ASI1_WCLK)
0100: ASI2_ADC_WCLK_OUT = ASI2 Word Clock Divider Output (ASI2_WDIV_OUT)
0101: Reserved. Do not use.
0110: ASI2_ADC_WCLK_OUT = ASI3 Word Clock Divider Output (ASI3_WDIV_OUT)
0111: ASI2_ADC_WCLK_OUT = ASI3 Word Clock Input (ASI3_WCLK)
1000: ASI2_ADC_WCLK_OUT = ASI1 ADC Word Clock
1001-1111: Reserved. Do not use.
Book 0 / Page 4 / Register 117: ASI3, ADC Bit Clock and ADC Word Clock Output - 0x00 / 0x04 / 0x75
(B0_P4_R117)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3-D0
R/W
R/W
0000
0000
Reserved. Write only default values.
Reserved. Write only default values
Book 0 / Page 4 / Register 118: miniDSP Data Port Control - 0x00 / 0x04 / 0x76 (B0_P4_R118)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
D6
R
0
0
Reserved. Write only reset values.
R/W
ADC miniDSP Data Output Configuration
0: Independent Left and Right Channels for ADC miniDSP output
1: Left Channel of ADC miniDSP output copied to Right Channel miniDSP output that is
miniDSP_A_DataOutput[2] = miniDSP_A_DataOutput[1]
D5-D4
R/W
00
miniDSP_D_DataInput_1 Configuration
00: miniDSP_D_DataInput_1[1:8] receives data from ASI1_DataInput[1:8]
01: miniDSP_D_DataInput_1[1:2] receives data from ASI2_DataInput[1:2]
10: miniDSP_D_DataInput_1[1:2] receives data from ASI3_DataInput[1:2]
11: miniDSP_D_DataInput_1[1:8] receives data from miniDSP_A_DataOutput[1:8] (ADC-to-DAC
Loopback)
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Book 0 / Page 4 / Register 118: miniDSP Data Port Control - 0x00 / 0x04 / 0x76 (B0_P4_R118) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D2
R/W
01
miniDSP_D_DataInput_2 Configuration
00: miniDSP_D_DataInput_2[1:2] receives data from ASI1_DataInput[1:2]
01: miniDSP_D_DataInput_2[1:2] receives data from ASI2_DataInput[1:2]
10: miniDSP_D_DataInput_2[1:2] receives data from ASI3_DataInput[1:2]
11: Reserved. Do not use.
D1-D0
R/W
10
miniDSP_D_Data Input 3 Configuration
00: miniDSP_D_DataInput_3[1:2] receives data from ASI1_DataInput[1:2]
01: miniDSP_D_DataInput_3[1:2] receives data from ASI2_DataInput[1:2]
10: miniDSP_D_DataInput_3[1:2] receives data from ASI3_DataInput[1:2]
11: Reserved. Do not use.
Book 0 / Page 4 / Register 119: Digital Audio Engine Synchronization Control - 0x00 / 0x04 / 0x77
(B0_P4_R119)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D6
R/W
00
DAC Engine Synchronization:
00: Enable DAC engine syncing using ASI1
01: Enable DAC engine syncing using ASI2
10: Enable DAC engine syncing using ASI3
11: Disable DAC engine syncing with miniDSP_D_in data frame from ASI mux at power up.
Recommended to disable sync when not using programmble mode for miniDSP_D (when
B0_P0_R60_D[4:0] /= "0 0000")
D5-D4
D3-D0
R/W
R
00
ADC Engine Synchronization:
00: Enable ADC engine syncing using ASI1
01: Enable ADC engine syncing using ASI2
10: Enable ADC engine syncing using ASI3
11: Disable ADC engine syncing with miniDSP_A_in data frame from ASI mux at power up
0000
Reserved. Write only reset values.
Book 0 / Page 4 / Register 120-127: Reserved Registers - 0x00 / 0x04 / 0x78-0x7F (B0_P4_R120-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx Reserved. Write only reset values.
8.6.6 Book 0 Page 252
Book 0 / Page 252 / Register 0: Page Select Register - 0x00 / 0xFC / 0x00 (B0_P252_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Book 0 / Page 252 / Register 1: SAR Buffer Mode Data (MSB) and Buffer Flags - 0x00 / 0xFC / 0x01
(B0_P252_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
R
R
0
1
Buffer-Full Flag
0: 64-sample Buffer is not filled
1: 64-sample Buffer has been filled
D6
D5
Buffer-Empty Flag
0: Buffer still contains un-read data
1: Buffer is empty (contains no un-read data)
X
Reserved. Write only reset values.
220
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Book 0 / Page 252 / Register 1: SAR Buffer Mode Data (MSB) and Buffer Flags - 0x00 / 0xFC / 0x01
(B0_P252_R1) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D4
R
X
Data Identification:
0: VBAT or IN1R/AUX2 data found in SAR Buffer Data (that is B0_P252_R1_D[3:0] and
B0_P252_R2_D[7:0].
1: IN1L/AUX1 or TEMP data found in SAR Buffer Data (that is B0_P252_R1_D[3:0] and
B0_P252_R2_D[7:0].
D3-D0
R
XXXX
SAR ADC Buffer Mode Data (11:8) - Reading this register will return MSB 4 bits of SAR Buffer
Mode data (based on Read Pointer).
Book 0 / Page 252 / Register 2: SAR Buffer Mode Data (LSB) - 0x00 / 0xFC / 0x02 (B0_P252_R2)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx SAR ADC Buffer Mode Data (7:0) - Reading this register will return LSB 8 bits of SAR Buffer Mode
data (based on Read Pointer).
Book 0 / Page 252 / Register 3-127: Reserved Registers - 0x00 / 0xFC / 0x03-0x7F (B0_P252_R3-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
8.6.7 Book 20 Page 0
Book 20 / Page 0 / Register 0: Page Select Register - 0x14 / 0x00 / 0x00 (B20_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 20 / Page 0 / Register 1-126: Reserved Registers - 0x14 / 0x00 / 0x01-0x7E (B20_P0_R1-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 20 / Page 0 / Register 127: Book Selection Register - 0x14 / 0x00 / 0x7F (B20_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
8.6.8 Book 20 Page 1-26
Book 20 / Page 1-26 / Register 0: Page Select Register - 0x14 / 0x01-0x1A / 0x00 (B20_P1-26_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
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Book 20 / Page 1-26 / Register 1-7: Reserved Registers - 0x14 / 0x01-0x1A / 0x01-0x07 (B20_P1-26_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 20 / Page 1-26 / Register 8-127: ADC Fixed Coefficients C(0:767) - 0x14 / 0x01-0x1A / 0x08-0x7F
(B20_P1-26_R8-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of ADC Fixed Coefficient. Refer to Table "ADC Fixed Coefficient Map" for details.
8.6.9 Book 40 Page 0
Book 40 / Page 0 / Register 0: Page Select Register - 0x28 / 0x00 / 0x00 (B40_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 40 / Page 0 / Register 1: ADC Adaptive CRAM Configuration Register - 0x28 / 0x00 / 0x01
(B40_P0_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3
R
R
0000
Reserved. Write only reset values.
0
0
miniDSP_A Generated Flag for toggling MSB Bit of Coefficient Address
D2
R/W
ADC Adaptive Filtering Control
0: Adaptive Filtering disabled for ADC
1: Adaptive Filtering enabled for ADC
D1
D0
R
0
0
ADC Adaptive Filter Buffer Control Flag
0: In adaptive filter mode, ADC miniDSP accesses ADC Coefficient Buffer-A, and control interface
accesses ADC Coefficient Buffer-B
1: In adaptive filter mode, ADC miniDSP accesses ADC Coefficient Buffer-B, and control interface
accesses ADC Coefficient Buffer-A
R/W
ADC Adaptive Filter Buffer Switch control
0: ADC Coefficient Buffers will not be switched at next frame boundary
1: ADC Coefficient Buffers will be switched at next frame boundary, if in adaptive filtering mode.
This will self clear on switching.
Book 40 / Page 0 / Register 2-126: Reserved Registers - 0x28 / 0x00 / 0x02-0x7E (B40_P0_R2-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 40 / Page 0 / Register 127: Book Selection Register - 0x28 / 0x00 / 0x7F (B40_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
222
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8.6.10 Book 40 Page 1-17
Book 40 / Page 1-17 / Register 0: Page Select Register - 0x28 / 0x01-0x11 / 0x00 (B40_P1-17_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 40 / Page 1-17 / Register 1-7: Reserved Registers - 0x28 / 0x01-0x11 / 0x01-0x07 (B40_P1-17_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 40 / Page 1-17 / Register 8-127: ADC Adaptive Coefficients C(0:509) - 0x28 / 0x01-0x11 / 0x08-0x7F
(B40_P1-17_R8-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of ADC Coefficients. Refer to Tables "ADC Adaptive Coefficient Buffer-A Map"
and "ADC Adaptive Coefficient Buffer-B Map" for details in adaptive mode. If these coefficients are
set to fixed mode, ADC Coefficients are one contiguous block.
8.6.11 Book 40 Page 18
Book 40 / Page 18 / Register 0: Page Select Register - 0x28 / 0x12 / 0x00 (B40_P18_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 40 / Page 18 / Register 1-7: Reserved Registers - 0x28 / 0x12 / 0x01-0x07 (B40_P18_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 40 / Page 18 / Register 8-15: ADC Adaptive Coefficients C(510:511) - 0x28 / 0x12 / 0x08-0x0F
(B40_P18_R8-15)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of ADC Coefficients. Refer to Tables "ADC Adaptive Coefficient Buffer-A Map"
and "ADC Adaptive Coefficient Buffer-B Map" for details in adaptive mode. If these coefficients are
set to fixed mode, ADC Coefficients are one contiguous block.
Book 40 / Page 18 / Register 16-127: Reserved Registers - 0x28 / 0x12 / 0x10-0x7F (B40_P18_R16-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
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8.6.12 Book 60 Page 0
Book 60 / Page 0 / Register 0: Page Select Register - 0x3C / 0x00 / 0x00 (B60_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 60 / Page 0 / Register 1-126: Reserved Registers - 0x3C / 0x00 / 0x01-0x7E (B60_P0_R1-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 60 / Page 0 / Register 127: Book Selection Register - 0x3C / 0x00 / 0x7F (B60_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
8.6.13 Book 60 Page 1-35
Book 60 / Page 1-35 / Register 0: Page Select Register - 0x3C / 0x01-0x23 / 0x00 (B60_P1-35_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 60 / Page 1-35 / Register 1-7: Reserved Registers - 0x3C / 0x01-0x23 / 0x01-0x07 (B60_P1-35_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 60 / Page 1-35 / Register 8-127: DAC Fixed Coefficients C(0:1023) - 0x3C / 0x01-0x23 / 0x08-0x7F
(B60_P1-35_R8-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of DAC Fixed Coefficient. Refer to Table "DAC Fixed Coefficient Map" for details.
8.6.14 Book 80 Page 0
Book 80 / Page 0 / Register 0: Page Select Register - 0x50 / 0x00 / 0x00 (B80_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
224
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Book 80 / Page 0 / Register 1: DAC Adaptive Coefficient Bank 1 Configuration Register - 0x50 / 0x00 /
0x01 (B80_P0_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3
R
R
0000
Reserved. Write only reset values.
0
0
miniDSP_D Generated Flag for toggling MSB Bit of Coefficient Address
D2
R/W
DAC Bank 1 Adaptive Filtering Control
0: Adaptive Filtering disabled for DAC Adaptive Coefficient Bank 1
1: Adaptive Filtering enabled for DAC Adaptive Coefficient Bank 1
D1
D0
R
0
0
DAC Bank 1 Adaptive Filter Buffer Control Flag
0: In adaptive filter mode, DAC miniDSP accesses DAC Coefficient Bank 1 Buffer-A, and control
interface accesses DAC Coefficient Bank 1 Buffer-B
1: In adaptive filter mode, DAC miniDSP accesses DAC Coefficient Bank 1 Buffer-B, and control
interface accesses DAC Coefficient Bank 1 Buffer-A
R/W
DAC Bank 1 Adaptive Filter Buffer Switch control
0: DAC Coefficient Bank 1 Buffers will not be switched at next frame boundary
1: DAC Coefficient Bank 1 Buffers will be switched at next frame boundary, if in adaptive filtering
mode. This will self clear on switching.
Book 80 / Page 0 / Register 2-126: Reserved Registers - 0x50 / 0x00 / 0x02-0x7E (B80_P0_R2-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 80 / Page 0 / Register 127: Book Selection Register - 0x50 / 0x00 / 0x7F (B80_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
8.6.15 Book 80 Page 1-17
Book 80 / Page 1-17 / Register 0: Page Select Register - 0x50 / 0x01-0x11 / 0x00 (B80_P1-17_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 80 / Page 1-17 / Register 1-7: Reserved Registers - 0x50 / 0x01-0x11 / 0x01-0x07 (B80_P1-17_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 80 / Page 1-17 / Register 8-127: DAC Adaptive Coefficient Bank 1 C(0:509) - 0x50 / 0x01-0x11 / 0x08-
0x7F (B80_P1-17_R8-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of DAC Adaptive Coefficient Bank 1. Refer to Tables "DAC Adaptive Coefficient
Bank 1 Buffer-A Map" and "DAC Adaptive Coefficient Bank 1 Buffer-B Map" for details in adaptive
mode. If these coefficients are set to fixed mode, these DAC Coefficients are one contiguous block.
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8.6.16 Book 80 Page 18
Book 80 / Page 18 / Register 0: Page Select Register - 0x50 / 0x12 / 0x00 (B80_P18_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 80 / Page 18 / Register 1-7: Reserved Registers - 0x50 / 0x12 / 0x01-0x07 (B80_P18_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 80 / Page 18 / Register 8-15: DAC Adaptive Coefficient Bank 1 C(510:511) - 0x50 / 0x12 / 0x08-0x0F
(B80_P18_R8-15)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of DAC Adaptive Coefficient Bank 1. Refer to Tables "DAC Adaptive Coefficient
Bank 1 Buffer-A Map" and "DAC Adaptive Coefficient Bank 1 Buffer-B Map" for details in adaptive
mode. If these coefficients are set to fixed mode, these DAC Coefficients are one contiguous block.
Book 80 / Page 18 / Register 16-127: Reserved Registers - 0x50 / 0x12 / 0x10-0x7F (B80_P18_R16-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
8.6.17 Book 82 Page 0
Book 82 / Page 0 / Register 0: Page Select Register - 0x52 / 0x00 / 0x00 (B82_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 82 / Page 0 / Register 1: DAC Adaptive Coefficient Bank 2 Configuration Register - 0x52 / 0x00 /
0x01 (B82_P0_R1)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D4
D3
R
R
0000
Reserved. Write only reset values.
0
0
miniDSP_D Generated Flag for toggling MSB Bit of Coefficient Address
D2
R/W
DAC Coefficient Bank 2 Adaptive Filtering Control
0: Adaptive Filtering disabled for DAC Adaptive Coefficient Bank 2
1: Adaptive Filtering enabled for DAC Adaptive Coefficient Bank 2
D1
D0
R
0
0
DAC Coefficient Bank 2 Adaptive Filter Buffer Control Flag
0: In adaptive filter mode, DAC miniDSP accesses DAC Coefficient Bank 2 Buffer-A, and control
interface accesses DAC Coefficient Bank 2 Buffer-B
1: In adaptive filter mode, DAC miniDSP accesses DAC Coefficient Bank 2 Buffer-B, and control
interface accesses DAC Coefficient Bank 2 Buffer-A
R/W
DAC Coefficient Bank 2 Adaptive Filter Buffer Switch control
0: DAC Coefficient Bank 2 Buffers will not be switched at next frame boundary
1: DAC Coefficient Bank 2 Buffers will be switched at next frame boundary, if in adaptive filtering
mode. This will self clear on switching.
226
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Book 82 / Page 0 / Register 2-126: Reserved Registers - 0x52 / 0x00 / 0x02-0x7E (B82_P0_R2-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only reset values.
Book 82 / Page 0 / Register 127: Book Selection Register - 0x52 / 0x00 / 0x7F (B82_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
8.6.18 Book 82 Page 1-17
Book 82 / Page 1-17 / Register 0: Page Select Register - 0x52 / 0x01-0x11 / 0x00 (B82_P1-17_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 82 / Page 1-17 / Register 1-7: Reserved Registers - 0x52 / 0x01-0x11 / 0x01-0x07 (B82_P1-17_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 82 / Page 1-17 / Register 8-127: DAC Adaptive Coefficient Bank 2 C(0:509) - 0x52 / 0x01-0x11 / 0x08-
0x7F (B82_P1-17_R8-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of DAC Adaptive Coefficient Bank 2. Refer to Tables "DAC Adaptive Coefficient
Bank 2 Buffer-A Map" and "DAC Adaptive Coefficient Bank 2 Buffer-B Map" for details in adaptive
mode. If these coefficients are set to fixed mode, these DAC Coefficients are one contiguous block.
8.6.19 Book 82 Page 18
Book 82 / Page 18 / Register 0: Page Select Register - 0x52 / 0x12 / 0x00 (B82_P18_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 82 / Page 18 / Register 1-7: Reserved Registers - 0x52 / 0x12 / 0x01-0x07 (B82_P18_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 82 / Page 18 / Register 8-15: DAC Adaptive Coefficient Bank 2 C(510:511) - 0x52 / 0x12 / 0x08-0x0F
(B82_P18_R8-15)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 24-bit coefficients of DAC Adaptive Coefficient Bank 2. Refer to Tables "DAC Adaptive Coefficient
Bank 2 Buffer-A Map" and "DAC Adaptive Coefficient Bank 2 Buffer-B Map" for details in adaptive
mode. If these coefficients are set to fixed mode, these DAC Coefficients are one contiguous block.
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Book 82 / Page 18 / Register 16-127: Reserved Registers - 0x52 / 0x12 / 0x10-0x7F (B82_P18_R16-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
8.6.20 Book 100 Page 0
Book 100 / Page 0 / Register 0: Page Select Register - 0x64 / 0x00 / 0x00 (B100_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 100 / Page 0 / Register 1-46: Reserved Registers - 0x64 / 0x00 / 0x01-0x2E (B100_P0_R1-46)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 100 / Page 0 / Register 47: Non-Programmable Override Options - 0x64 / 0x00 / 0x2F (B100_P0_R47)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1
R
0000 00
0
Reserved. Write only reset values.
W
0: Use the hardwired IADC and DECIM value for the specific non-programmable mode
1: Use IADC value and DECIM value from register B100_P0_R48-50 for the non-programmable
mode
D0
R
0
Reserved. Write only reset values.
Book 100 / Page 0 / Register 48: ADC miniDSP_A Instruction Control Register 1 - 0x64 / 0x00 / 0x30
(B100_P0_R48)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D0
R/W
000 0001 ADC miniDSP IADC (14:8) Control. (Use only when ADC miniDSP_A is in use for signal
processing, that is B0_P0_R61_D[4:0]=00000.)
ADC miniDSP IADC(14:0)
000 0000 0000 0000: ADC miniDSP IADC=32768
000 0000 0000 0001: ADC miniDSP IADC = 1
000 0000 0000 0010: ADC miniDSP IADC = 2
...
111 1111 1111 1110: ADC miniDSP IADC = 32766
111 1111 1111 1111: ADC miniDSP IADC = 32767
Note: IADC should be a integral multiple of DECIM (B100_P0_R50_D[3:0])
Note: B100_P0_R48 takes effect after programming B100_P0_R49 in the immediate next
control command.
228
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Book 100 / Page 0 / Register 49: ADC miniDSP_A Instruction Control Register 2 - 0x64 / 0x00 / 0x31
(B100_P0_R49)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 ADC miniDSP IADC (14:8) Control. (Use only when ADC miniDSP_A is in use for signal
processing, that is B0_P0_R61_D[4:0]=00000.)
ADC miniDSP IADC(14:0)
000 0000 0000 0000: ADC miniDSP IADC=32768
000 0000 0000 0001: ADC miniDSP IADC = 1
000 0000 0000 0010: ADC miniDSP IADC = 2
...
111 1111 1111 1110: ADC miniDSP IADC = 32766
111 1111 1111 1111: ADC miniDSP IADC = 32767
Note: IADC should be a integral multiple of DECIM (B100_P0_R50_D[3:0])
Note: B100_P0_R48 takes effect after programming B100_P0_R49 in the immediate next
control command.
Book 100 / Page 0 / Register 50: ADC miniDSP_A CIC Input and Decimation Ratio Control Register - 0x64
/ 0x00 / 0x32 (B100_P0_R50)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: FIFO at CIC output is bypassed.
1: FIFO at CIC output is not bypassed. THIS BIT SHOULD ALWAYS BE WRITTEN TO 1 AT
INITIALIZATION
D6-D4
D3-D0
R/W
R/W
0
Reserved. Write only default values
0100
ADC miniDSP Decimation factor Control. (Use only when ADC miniDSP_A is in use for signal
processing, that is B0_P0_R61_D[4:0]=00000.)
(B0_P0_R61)
0000: Decimation factor in ADC miniDSP = 16
0001: Decimation factor in ADC miniDSP = 1
0010: Decimation factor in ADC miniDSP = 2
...
1110: Decimation factor in ADC miniDSP = 14
1111: Decimation factor in ADC miniDSP = 15
Book 100 / Page 0 / Register 51-59: Reserved Registers - 0x64 / 0x00 / 0x33-0x3B (B100_P0_R51-59)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 100 / Page 0 / Register 60: ADC miniDSP_A Secondary CIC Input Control - 0x64 / 0x00 / 0x3C
(B100_P0_R60)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
0
0: FIFO at CIC2 output is bypassed.
1: FIFO at CIC2 output is not bypassed.
D6-D0
R/W
000 0000 Reserved. Write only reset values.
Book 100 / Page 0 / Register 61: miniDSP_A to Audio Serial Interface Handoff Control - 0x64 / 0x00 / 0x3D
(B100_P0_R61)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0
0: miniDSP_A to ASI1 handoff synchronizer logic is initiated based on instruction counter-3
1: miniDSP_A to ASI1 handoff synchronizer logic is initiated based on interrupt port. Use only if
B0_P0_R61_D[4:0] = "0 0000".
D6
0: miniDSP_A to ASI2 handoff synchronizer logic is initiated based on instruction counter-3
1: miniDSP_A to ASI2 handoff synchronizer logic is initiated based on interrupt port. Use only if
B0_P0_R61_D[4:0] = "0 0000".
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Book 100 / Page 0 / Register 61: miniDSP_A to Audio Serial Interface Handoff Control - 0x64 / 0x00 / 0x3D
(B100_P0_R61) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D5
R/W
0
0: miniDSP_A to ASI3 handoff synchronizer logic is initiated based on instruction counter-3
1: miniDSP_A to ASI3 handoff synchronizer logic is initiated based on interrupt port. Use only if
B0_P0_R61_D[4:0] = "0 0000".
D4-D0
R/W
0 0000
Reserved. Write only reset values.
Book 100 / Page 0 / Register 62-126: Reserved Registers - 0x64 / 0x00 / 0x3E-0x7E (B100_P0_R62-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 100 / Page 0 / Register 127: Book Selection Register - 0x64 / 0x00 / 0x7F (B100_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
8.6.21 Book 100 Page 1-52
Book 100 / Page 1-52 / Register 0: Page Select Register - 0x64 / 0x01-0x34 / 0x00 (B100_P1-52_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 100 / Page 1-52 / Register 1-7: Reserved Registers - 0x64 / 0x01-0x34 / 0x01-0x07 (B100_P1-52_R1-
7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values
Book 100 / Page 1-52 / Register 8-127: miniDSP_A Instructions - 0x64 / 0x01-0x34 / 0x08-0x7F (B100_P1-
52_R8-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
xxxx xxxx 32 bit instructions for ADC miniDSP engine. For details refer to Table "ADC miniDSP Instruction
Map". These instructions control the operation of ADC miniDSP mode. When the fully
programmable miniDSP mode is enabled and ADC channel is powered up, the read and write
access to these registers is disabled.
8.6.22 Book 120 Page 0
Book 120 / Page 0 / Register 0: Page Select Register - 0x78 / 0x00 / 0x00 (B120_P0_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
230
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Book 120 / Page 0 / Register 1-46: Reserved Registers - 0x78 / 0x00 / 0x01-0x2E (B120_P0_R1-46)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only reset values.
Book 120 / Page 0 / Register 47: Non-Programmable Override Options - 0x78 / 0x00 / 0x2F (B120_P0_R47)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D2
D1
R
0000 00
0
Reserved. Write only reset values.
W
0: Use the hardwired IDAC and INTERP value for the specific non-programmable mode
1: Use IDAC value and INTERP value from register B120_P0_R48-50 for the non-programmable
mode
D0
R
0
Reserved. Write only reset values.
Book 120 / Page 0 / Register 48: DAC miniDSP_D Instruction Control Register 1 - 0x78 / 0x00 / 0x30
(B120_P0_R48)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R
0
Reserved. Write only reset values.
D6-D0
R/W
000 0010 DAC miniDSP IDAC (14:8) Control. (Use only when DAC miniDSP_D is in use for signal
processing, that is B0_P0_R60_D[4:0]=00000.)
DAC miniDSP IDAC(14:0)
000 0000 0000 0000: DAC miniDSP IDAC = 32768
000 0000 0000 0001: DAC miniDSP IDAC = 1
000 0000 0000 0010: DAC miniDSP IDAC = 2
...
111 1111 1111 1110: DAC miniDSP IDAC = 32766
111 1111 1111 1111: DAC miniDSP IDAC = 32767
Note: IDAC should be a integral multiple of INTERP (B120_P0_R50_D[3:0])
Note: B120_P0_R48 takes effect after programming B120_P0_R49 in the immediate next
control command.
Book 120 / Page 0 / Register 49: DAC miniDSP_D Instruction Control Register 2 - 0x78 / 0x00 / 0x31
(B120_P0_R49)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 DAC miniDSP IDAC (7:0) Control. (Use only when DAC miniDSP_D is in use for signal processing,
that is B0_P0_R60_D[4:0]=00000.)
DAC miniDSP IDAC(14:0)
000 0000 0000 0000: DAC miniDSP IDAC = 32768
000 0000 0000 0001: DAC miniDSP IDAC = 1
000 0000 0000 0010: DAC miniDSP IDAC = 2
...
111 1111 1111 1110: DAC miniDSP IDAC = 32766
111 1111 1111 1111: DAC miniDSP IDAC = 32767
Note: IDAC should be a integral multiple of INTERP (B120_P0_R50_D[3:0])
Note: B120_P0_R49 should be programmed immediately after B120_P0_R48.
Book 120 / Page 0 / Register 50: DAC miniDSP_D Interpolation Factor Control Register - 0x78 / 0x00 /
0x32 (B120_P0_R50)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7
R/W
R/W
0
0: FIFO at modulator input is bypassed
1: FIFO at modulator input is not bypassed. THIS BIT SHOULD ALWAYS BE WRITTEN TO 1 AT
INITIALIZATION
D6-D4
000
Reserved. Write only default values.
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Book 120 / Page 0 / Register 50: DAC miniDSP_D Interpolation Factor Control Register - 0x78 / 0x00 /
0x32 (B120_P0_R50) (continued)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D3-D0
R/W
1000
miniDSP_D interpolation factor control. (Use only when DAC miniDSP is in use for signal
processing, that is B0_P0_R60_D[4:0]=00000.)
0000: Interpolation Ratio in DAC MAC Engine = 16
0001: Interpolation Ratio in DAC MAC Engine = 1
0010: Interpolation Ratio in DAC MAC Engine = 2
...
1110: Interpolation Ratio in DAC MAC Engine = 14
1111: Interpolation Ratio in DAC MAC Engine = 15
Book 120 / Page 0 / Register 51-126: Reserved Registers - 0x78 / 0x00 / 0x33-0x7E (B120_P0_R51-126)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
xxxx xxxx Reserved. Write only default values.
Book 120 / Page 0 / Register 127: Book Selection Register - 0x78 / 0x00 / 0x7F (B120_P0_R127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 0000 0000: Book 0 selected
0000 0001: Book 1 selected
...
1111 1110: Book 254 selected
1111 1111: Book 255 selected
8.6.23 Book 120 Page 1-103
Book 120 / Page 1-103 / Register 0: Page Select Register - 0x78 / 0x01-0x67 / 0x00 (B120_P1-103_R0)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
0000 0000 Page Select Register
0-255: Selects the Register Page for next read or write command.
Refer Table "Summary of Memory Map" for details.
Book 120 / Page 1-103 / Register 1-7: Reserved Registers - 0x78 / 0x01-0x67 / 0x01-0x07 (B120_P1-
103_R1-7)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R
0000 0000 Reserved. Write only default values
Book 120 / Page 1-103 / Register 8-127: miniDSP_D Instructions - 0x78 / 0x01-0x67 / 0x08-0x7F (B120_P1-
103_R8-127)
READ/
WRITE
RESET
VALUE
BIT
DESCRIPTION
D7-D0
R/W
XXXX
XXXX
32 bit instructions for DAC miniDSP engine. For details refer to Table "DAC miniDSP Instruction
Map". These instructions control the operation of DAC miniDSP mode. When the fully
programmable miniDSP mode is enabled and DAC channel is powered up, the read and write
access to these registers is disabled.
8.6.24 ADC Coefficients
Table 53. ADC Fixed Coefficient Map
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C0
C1
20
20
1
1
8
Coef(23:16)
Coef(23:16)
Coef(15:8)
Coef(15:8)
Coef(7:0)
Coef(7:0)
Reserved.
Reserved.
12
232
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Table 53. ADC Fixed Coefficient Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
..
..
..
..
..
..
C29
C30
20
20
1
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
2
..
..
C59
C60
20
20
2
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
3
..
..
C89
C90
20
20
3
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
4
..
..
C119
C120
20
20
4
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
5
..
..
C149
C150
20
20
5
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
6
..
..
C179
C180
20
20
6
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
7
..
..
C209
C210
20
20
7
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
8
..
..
C239
C240
20
20
8
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
9
..
..
C269
C270
20
20
9
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
10
..
..
C299
C300
20
20
10
11
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C329
C330
20
20
11
12
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C359
C360
20
20
12
13
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C389
C390
20
20
13
14
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C419
C420
20
20
14
15
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C449
C450
20
20
15
16
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C479
20
16
124
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Copyright © 2014, Texas Instruments Incorporated
233
TLV320AIC3268
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www.ti.com.cn
Table 53. ADC Fixed Coefficient Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C480
20
17
..
8
Coef(23:16)
..
Coef(15:8)
..
Coef(7:0)
..
Reserved.
..
..
C509
C510
20
20
17
18
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C539
C540
20
20
18
19
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C569
C570
20
20
19
20
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C599
C600
20
20
20
21
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C629
C630
20
20
21
22
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C659
C660
20
20
22
23
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C689
C690
20
20
23
24
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C719
C720
20
20
24
25
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C749
C750
20
20
25
26
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C767
20
26
76
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Table 54. ADC Adaptive Coefficient Buffer-A Map
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C0
C1
40
40
1
1
..
1
2
..
2
3
..
3
4
..
4
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
12
..
C29
C30
40
40
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C59
C60
40
40
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C89
C90
40
40
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C119
234
40
124
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Table 54. ADC Adaptive Coefficient Buffer-A Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C120
40
5
..
5
6
..
6
7
..
7
8
..
8
9
..
9
8
Coef(23:16)
..
Coef(15:8)
..
Coef(7:0)
..
Reserved.
..
..
C149
C150
40
40
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C179
C180
40
40
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C209
C210
40
40
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C239
C240
40
40
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C255
40
68
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Table 55. ADC Adaptive Coefficient Buffer-B Map
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C0
C1
40
40
9
72
76
..
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
9
..
C13
C14
40
40
9
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
10
..
..
C43
C44
40
40
10
11
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C73
C74
40
40
11
12
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C103
C104
40
40
12
13
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C133
C134
40
40
13
14
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C163
C164
40
40
14
15
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C193
C194
40
40
15
16
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C223
C224
40
40
16
17
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C253
40
17
124
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Copyright © 2014, Texas Instruments Incorporated
235
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Table 55. ADC Adaptive Coefficient Buffer-B Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C254
C255
40
40
18
18
8
Coef(23:16)
Coef(23:16)
Coef(15:8)
Coef(15:8)
Coef(7:0)
Coef(7:0)
Reserved.
Reserved.
12
8.6.25 ADC Defaults
Table 56. Default values of ADC Coefficients in Buffers
A and B
ADC Buffer-
A,B
Default Value at reset
Coefficients
C0
00000000H
01170000H
01170000H
7DD30000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
04280000H
01000000H
C1
C2
C3
C4
C5,C6
C7
C8,..,C11
C12
C13,..,C16
C17
C18,..,C21
C22
C23,..,C26
C27
C28,..,C35
C36
C37,C38
C39
C40,..,C43
C44
C45,..,C48
C49
C50,..,C53
C54
C55,..,C58
C59
C60,..,C253
C254
C255
8.6.26 DAC Coefficients
Table 57. DAC Fixed Coefficient Map
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C0
C1
60
60
1
1
8
Coef(23:16)
Coef(23:16)
Coef(15:8)
Coef(15:8)
Coef(7:0)
Coef(7:0)
Reserved.
Reserved.
12
236
Copyright © 2014, Texas Instruments Incorporated
TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Table 57. DAC Fixed Coefficient Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
..
..
..
..
..
..
C29
C30
60
60
1
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
2
..
..
C59
C60
60
60
2
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
3
..
..
C89
C90
60
60
3
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
4
..
..
C119
C120
60
60
4
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
5
..
..
C149
C150
60
60
5
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
6
..
..
C179
C180
60
60
6
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
7
..
..
C209
C210
60
60
7
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
8
..
..
C239
C240
60
60
8
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
9
..
..
C269
C270
60
60
9
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
10
..
..
C299
C300
60
60
10
11
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C329
C330
60
60
11
12
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C359
C360
60
60
12
13
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C389
C390
60
60
13
14
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C419
C420
60
60
14
15
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C449
C450
60
60
15
16
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C479
60
16
124
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Copyright © 2014, Texas Instruments Incorporated
237
TLV320AIC3268
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
www.ti.com.cn
Table 57. DAC Fixed Coefficient Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C480
60
17
..
8
Coef(23:16)
..
Coef(15:8)
..
Coef(7:0)
..
Reserved.
..
..
C509
C510
60
60
17
18
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C539
C540
60
60
18
19
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C569
C570
60
60
19
20
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C599
C600
60
60
20
21
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C629
C630
60
60
21
22
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C659
C660
60
60
22
23
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C689
C690
60
60
23
24
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C719
C720
60
60
24
25
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C749
C750
60
60
25
26
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C779
C780
60
60
26
27
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C809
C810
60
60
27
28
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C839
C840
60
60
28
29
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C869
C870
60
60
29
30
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C899
C900
60
60
30
31
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C929
C930
60
60
31
32
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
238
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Table 57. DAC Fixed Coefficient Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C959
C960
60
60
32
33
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C989
C990
60
60
33
34
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C1019
C1020
60
60
34
35
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C1023
60
35
20
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Table 58. DAC Adaptive Coefficient Bank 1 Buffer-A Map
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C0
C1
80
80
1
1
..
1
2
..
2
3
..
3
4
..
4
5
..
5
6
..
6
7
..
7
8
..
8
9
..
9
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
12
..
C29
C30
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C59
C60
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C89
C90
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C119
C120
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C149
C150
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C179
C180
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C209
C210
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C239
C240
80
80
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C255
80
68
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Table 59. DAC Adaptive Coefficient Bank 1 Buffer-B Map
Coef No Book No
C0 80
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
9
72
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Copyright © 2014, Texas Instruments Incorporated
239
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Table 59. DAC Adaptive Coefficient Bank 1 Buffer-B Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C1
80
9
76
..
Coef(23:16)
..
Coef(15:8)
..
Coef(7:0)
..
Reserved.
..
..
C13
C14
80
80
9
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
10
..
..
C43
C44
80
80
10
11
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C73
C74
80
80
11
12
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C103
C104
80
80
12
13
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C133
C134
80
80
13
14
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C163
C164
80
80
14
15
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C193
C194
80
80
15
16
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C223
C224
80
80
16
17
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C253
C254
C255
80
80
80
17
18
18
124
8
Coef(23:16)
Coef(23:16)
Coef(23:16)
Coef(15:8)
Coef(15:8)
Coef(15:8)
Coef(7:0)
Coef(7:0)
Coef(7:0)
Reserved.
Reserved.
Reserved.
12
Table 60. DAC Adaptive Coefficient Bank 2 Buffer-A Map
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C0
C1
82
82
1
1
..
1
2
..
2
3
..
3
4
..
4
5
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
12
..
C29
C30
82
82
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C59
C60
82
82
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C89
C90
82
82
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C119
C120
82
82
124
8
Coef(23:16)
Coef(23:16)
Coef(15:8)
Coef(15:8)
Coef(7:0)
Coef(7:0)
Reserved.
Reserved.
240
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TLV320AIC3268
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ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
Table 60. DAC Adaptive Coefficient Bank 2 Buffer-A Map (continued)
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
..
5
6
..
6
7
..
7
8
..
8
9
..
9
..
..
..
..
..
C149
C150
82
82
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C179
C180
82
82
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C209
C210
82
82
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C239
C240
82
82
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C255
82
68
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
Table 61. DAC Adaptive Coefficient Bank 2 Buffer-B Map
Coef No Book No
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
C0
C1
82
82
9
72
76
..
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
9
..
C13
C14
82
82
9
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
10
..
..
C43
C44
82
82
10
11
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C73
C74
82
82
11
12
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C103
C104
82
82
12
13
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C133
C134
82
82
13
14
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C163
C164
82
82
14
15
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C193
C194
82
82
15
16
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C223
C224
82
82
16
17
..
124
8
Coef(23:16)
Coef(23:16)
..
Coef(15:8)
Coef(15:8)
..
Coef(7:0)
Coef(7:0)
..
Reserved.
Reserved.
..
..
C253
C254
82
82
17
18
124
8
Coef(23:16)
Coef(23:16)
Coef(15:8)
Coef(15:8)
Coef(7:0)
Coef(7:0)
Reserved.
Reserved.
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Table 61. DAC Adaptive Coefficient Bank 2 Buffer-B Map (continued)
Coef No Book No
C255 82
Page No
Base
Register
Base Register + Base Register + 1 Base Register + 2 Base Register + 3
0
18
12
Coef(23:16)
Coef(15:8)
Coef(7:0)
Reserved.
8.6.27 DAC Defaults
Table 62. Default values of DAC Coefficients Bank 1 and Bank 2 in Buffers A
and B
DAC Buffer-A,B Coefficients
Default Value at reset
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FFFFF00H
00000000H
7FF70000H
80090000H
7FEF0000H
00110000H
7FDE0000H
00000000H
01180000H
04400000H
C0
C1
C2,C3
C4
C5,..,C8
C9
C10,..,C13
C14
C15,..,C18
C19
C20,..,C23
C24
C25,..,C28
C29
C30,..,C35
C36
C37,C38
C39
C40,..,C43
C44
C45,..,C48
C49
C50,..,C53
C54
C55,..,C58
C59
C60,..,C63
C64
C65,..,C70
C71
C72
C73
C74,C75
C76
C77,..,C253
C254
C255
242
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TLV320AIC3268
www.ti.com.cn
ZHCSC47A –JANUARY 2014–REVISED FEBRUARY 2014
9 Applications and Implementation
9.1 Application Information
The TLV320AIC3268 is a highly integrated stereo audio codec with integrated miniDSP, mono Speaker amplifier
and mutiple digital audio interfaces. It enables many different types of audio platforms having a need for stereo
audio record and playback and needing to interface with several other devices in the system over multiple digital
audio interfaces.
9.2 Typical Applications
Figure 109 shows a typical circuit configuration for a system utilizing the TLV320AIC3268.
Note: VBAT is used for
voltage measurement .
System
Battery
PERIPHERAL
DEVICE 1
PERIPHERAL
DEVICE 2
HOST PROCESSOR
Control
Interface
BATT_VDD
1mF
10kW
+1.8VD1
Audio
Interface
Audio
Interface
Audio Interface
LOL
LOR
Stereo
Differential
Lineout
VREF_SAR
1mF
VREF_AUDIO
ASI1
ASI2
ASI3
1mF
RECP
RECM
1mF
1mF
MICDET
Analog_In1
IN1R/AUX2
IN2L
2.2kW
0.1mF
MICBIAS_EXT
Analog_In2
Analog_In3
Analog_In4
Analog_In5
Analog_In6
Analog_In7
IN1L/AUX1
HPL
1mF
1mF
1mF
1mF
1mF
IN2R
HPR
Headset
IN3L
HPVSS_SENSE
AGND at Connector
IN3R
+1.8VA
CPVDD_18
CPFCP
10mF
0.1mF
IN4R
IN4L
2.2mF
X7R Type
To Internal
Mic
MICBIAS
CPFCM
VNEG
MICBIAS_VDD
BATT _VDD
1mF
2.2mF
X7R Type
0.1mF
8W
(Opt.)
SPKP
SPKM
10mF
DVDD _18
DVDD _18
DVDD _18
0.1mF
0.1mF
SPK_V
SVDD
+1.8VD1
2W
0.1mF
10mF
0.1mF
0.1mF
1mF
0.1mF
0.1mF
1mF +1.8VD2
0.1mF
1mF
10mF
0.1mF 0.1mF 0.1mF 0.1mF
BATT _VDD
+1.8VA
Figure 109. Typical Circuit Configuration
9.2.1 Design Requirements
9.2.1.1 Charge Pump Flying and Holding Capacitor
The TLV320AIC3268 features a built in charge-pump to generate a negative supply rail, VNEG from CPVDD_18.
This negative voltage is used by the headphone amplifier to enable driving the output signal biased around
ground potential. For proper operation of the charge pump and headphone amplifier, it is recommended that the
flying capacitor connected between CPFCP and CPFCM terminals and the holding capacitor connected between
VNEG and ground be of X7R type. It is recommended to use 2.2µF as capacitor values. Failure to use X7R type
capacitor can result in degraded performance of charge pump and headphone amplifier.
9.2.1.2 Reference Fitlering Capacitor
The TLV320AIC3268 has a built-in bandgap used to generate reference voltages and currents for the device. To
acheive high SNR, the reference voltage on VREF_AUDIO should be filtered using a 1µF capacitor from
VREF_AUDIO terminal to ground.
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Typical Applications (continued)
The built-in SAR ADC in TLV320AIC3268 can operate with either internally generated reference voltage or
externally provided reference voltage. When used with internal reference, the reference voltage on VREF_SAR
should be filtered with a 1µF capacitor for filtering noise as well as reference stability.
9.2.1.3 Micbias
The TLV320AIC3268 has a built-in bias voltage output for biasing of microphones. No intentional capacitors
should be connected directly to either MICBIAS or MICBIAS_EXT outputs for filtering.
9.2.1.4 Power Supply
The TLV320AIC3268 needs several power supplies for it's operation.
The SVDD input is used to power the speaker amplifier. This includes the power required for internal circuits as
well as the power delivered to the speaker load. It is recommended that this supply is directly connected to
battery, for systems where battery rail is in the range of 2.7V to 5.5V.The peak switching current on this power
can exceed 1A. MICBIAS_VDD can be tapped from same source that is used for SVDD.
The AVDDx_18, HVDD_18 and CPVDD_18 power inputs are used to power the analog circuits including analog
to digital converters, digital to analog converters, programmable gain amplifiers, headphone amplifiers, charge
pump etc. The analog blocks in TLV320AIC3268 have high power supply rejection ratio, however it is
recommended that these supplies be powered by well regulated power supplies like low dropout regulators
(LDO) for optimal performance. When these power terminals are driven from a common power source, the
current drawn from the source will depend upon blocks enabled inside the device. However as an example when
all the internal blocks powered are enabled the source should be able to deliver 150mA of current.
The RECVDD_33 powers the receiver amplifier of TLV320AIC3268. When the receiver amplifier is used in
differential lineout mode, then the RECVDD_33 could be connected to the same supply as AVDDx_18 terminals.
When the receiver amplifier is used to drive mono receiver speakers in BTL mode, the RECVDD_33 supply could
consume approximately 150mA of peak current.
The DVDD_18 powers the digital core of TLV320AIC3268, including the minIDSP, audio serial interfaces (ASI),
control interfaces (SPI or I2C), clock generation and PLL. The DVDD_18 power can be driven by high efficiency
switching regulators or low drop out regulators. When the miniDSP_a and miniDSP_D are enabled in
programmable mode and operated at peak frequencies, the supply source should be able to able to deliver
approx 100mA of current. When the PRB modes are used instead of programmable miniDSP mode, then the
peak current load on DVDD_18 supply source could be approximately 20mA.
The IOVDD1_33 and IOVDD2_33 power the digital input and digital output buffers of TLV320AIC3268. The
current consumption of this power depends on configuration of digital terminals as inputs or outputs. When the
digital terminals are configured as outputs, the current consumption would depend on switching frequency of the
signal and the load on the output terminal, which depends on board design and input capacitance of other
devices connected to the signal .
Refer to Figure 109 for recommendations on decoupling capacitors.
9.2.2 Detailed Design Procedure
9.2.2.1 Analog Input Connection
The analog inputs to TLV320AIC3268 should be ac-coupled to the device terminals to allow decoupling of signal
source's common mode voltage with that of TLV320AIC3268's common mode voltage. The input coupling
capacitor in combination with the selected input impedance of TLV320AIC3268 forms a high-pass filter.
Fc = 1/(2*π*ReqCc)
Cc = 1/(2*π*ReqFc)
(22)
(23)
For high fidelity audio recording application it is desirable to keep the cutoff frequency of the high pass filter as
low as possible. For single-ended input mode, the equivalent input resistance Req can be calculated as
Req = Rin* (1 + 2g)/(1+g)
(24)
where g is the analog PGA gain calculated in linear terms.
g = 10000 * 2floor(G/6)/Rin
(25)
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Typical Applications (continued)
where G is the analog PGA gain programmed in B0_P1_R59-60 (in dB) and Rin is the value of the resistor
programmed in B0_P1_R52-53 and B0_P1_R55-56 and assumes Rin = Rcm (as defined in B0_P1_R54 and
B0_P1_R57). For differential input mode, Req can be calculated as:
Req = Rin
(26)
where Rin is the value of the resistor programmed in B0_P1_R52-54 and B0_P1_R55-57, assuming symmetrical
inputs.
Signal Connector
Device Analog Input
C
c
Req
Rpd
Figure 110. Analog Input Connection With Pull-down Resistor
When the analog signal is connected to the system through a connector such as audio jack, it is recommended
to put a pull-down resistor on the signal as shown in Figure 111. The pulldown resistor helps keep the signal
grounded and helps improve noise immunity when no source is connected to the connector. The pulldown
resistor value should be chosen large enough to avoid loading of signal source.
Each analog input of the TLV320AIC3268 is capable of handling signal amplitude of 0.5Vrms. If the input signal
source can drive signals higher than the maximum value, an external resistor divider network as shown in
Figure 111 should be used to attenuate the signal to less than 0.5Vrms before connecting the signal to the
device. The resistor values of the network should be chosen to provide desired attenuation as well as
Equation 27.
R1|| R2<< Req
(27)
Device Analog Input
Signal Connector
R1
Cc
Req
R2
Figure 111. Analog Input Connection With Resistor Divider Network
Certain non audio applications require supporting of high impedance sources. The TLV320AIC3268 supports a
high-input impedance mode on IN1L/AUX1 and IN1R/AUX2 terminals, for such use cases. See High Impedance
Input Mode for more details. For such cases the input coupling capacitor can be eliminated from design.
Whenever any of the analog input terminals IN1L_AUX1, IN2L, IN3L, IN4L, IN1R_AUX2, IN2R, IN3R or IN4R are
not used in an application, it is recommended to short the unused input terminals together and connect them to
ground using a small capacitor (example 0.1µF). If VBAT is not used in an application, then it can be shorted to
ground.
9.2.2.2 Analog Output Connection
The line outputs of the TLV320AIC3268 drive a signal biased around the device common mode voltage. To avoid
loading the common mode with the load, it is recommended to connect the single-ended load through an ac-
coupling capacitor. The ac-coupling capacitor in combination with the load impedance forms a high pass filter.
Fc = 1/(2*π*RLCc)
Cc = 1/(2*π*RLFc)
(28)
(29)
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Typical Applications (continued)
For high fidelity playback, the cutoff frequency of the resultant high-pass filter should be kept low. For example
with RL of 10kΩ, using 1µF coupling capacitor results in a cut-off frequency of 8Hz.
For differential lineout configurations, the load should be directly connected between the differential outputs, with
no coupling capacitor.
The TLV320AIC3268 supports headphone in single-ended configuration and drives the signal biased around
ground. The headphone load can be directly connected between device terminals and ground.
The TLV320AIC3268 supports BTL load for receiver and speaker amplifier. The load can be directly connected
between the differential output terminals of receiver and speaker amplifier.
Whenver any of the analog output terminals LOL, LOR, RECP, RECM, HPL, HPR, SPKP or SPKM are not used
in an application, they should be left open or not connected.
9.2.2.3 EMI Passive Devices
The TLV320AIC3268 does not need filters for the functioning of it's speaker amplifier.
However depending on the board layout and system level EMI requirements, an optional EMI filter consisting of
ferrite beads and capacitors may be used as shown in and and labelled as optional. The ferrite beads if used
should be capable of handing peak currents for desired power delivery into speakers. If EMI passives are not
used, ferrite bead should be replaced with a short and the capacitor not installed.
9.2.3 Application Performance Plots
Figure 112 shows the excellent low-distortion performance of the TLV320AIC3268 in a system over the 20Hz to
20kHz audio spectrum.
±10
±30
±50
±70
±90
±110
20
200
2000
Frequency (Hz)
Conditions: Differential Lineout, Rload=10kΩ, CM=0.9V, Input Amplitude=-3dBFS
20000
C014
Figure 112. Total Harmonic Distortion + Noise versus Input Frequency
Figure 113 shows the distortion performance of the TLV320AIC3268 in a system over the input amplitude range.
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Typical Applications (continued)
0
±20
±40
±60
±80
±100
±70
±60
±50
Input Amplitude (dBFS)
Conditions: Differential Lineout, Rload=10kΩ, CM=0.9V
±40
±30
±20
±10
0
C013
Figure 113. Total Harmonic Distortion + Noise versus Input Amplitude
9.3 Initialization Setup
The TLV320AIC3268 has multiple power supply domains to support various functions. Before the device is fully
functional, all the power supplies must be enabled. The section Power On Sequence describes the supported
power supply sequencing for TLV320AIC3268.
9.3.1 Power On Sequence
There are two recommended power sequence possible for TLV320AIC3268:
1) Speaker/Microphone Supplies, then Digital Supplies, then Analog Supplies
2) Speaker/Microphone Supplies, then Digital and Analog Supplies
The first power on sequence is useful if the end system uses separate analog and digital supplies. This is useful
to improve the efficiency of the digital rails by using a DC/DC converter, while keeping the analog supplies clean
by using a low-dropout regulator (LDO). While it is recommended to separate analog and digital supplies, if all
the 1.8V supplies (analog and digital) must be tied together, the second power sequence can be utilized.
9.3.1.1 Power On Sequence 1 - Separate Digital and Analog Supplies
Figure 114 shows a timing diagram for the case where all supplies are provided separately. In such case, the
depicted sequence should be used. The dashed lines marked in blue color refer to an internally supplied voltage.
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Initialization Setup (continued)
SVDD, SPK_V,
tS-I
MICBIAS_VDD
IOVDD1_33
tI-D
tI1-I2
IOVDD2_33
DVDD_18
tD-A
AVDD1_18, AVDD2_18,
AVDD4_18, AVDD_18,
HVDD_18
tA-C
CPVDD_18
RECVDD_33
RESET
tD-R
tR-P
tD-P
Write to
Registers
Disable AVDD weak connection to DVDD
(Write ‘0’ to B0_P1_R1_D3)
Enable External Analog Power Supplies
(Write ‘0’ to B0_P1_R1_D2)
Figure 114. Analog Supplies provided after Digital Supplies
SVDD, SPK_V, and MICBIAS_VDD should be provided first. Next, IOVDD1_33 and IOVDD2_33 should be
provided, and DVDD_18 can be provided at the same time as these IOVDDx_33 supplies. Since, by default,
DVDD_18 is weakly connected to AVDD1_18 by a 10kΩ resistor, AVDDx_18 and HVDD_18 (it is recommended
to connect these five supplies together) will ramp up to the DVDD_18 voltage once DVDD_18 is provided at
approximately 5*10k*CAVDD seconds, where CAVDD are the sum of the decoupling capacitors on the AVDDx_18
and HVDD_18 terminals. For CAVDD = 1uF, the charging time is approximately 50ms. Parameter tD-A allows
analog supplies to be stable before analog supplies are provided. To prevent high currents from DVDD_18 to the
1.8V and 3.3V analog supplies (that is AVDDx_18, HVDD_18, RECVDD_33), these analog supplies cannot be
externally driven low by the external power source. This means that the external power source should be either
high impedance or have a weak pull-down before being enabled.
Ensure that CPVDD_18 supply is provided either at same time as analog supplies or later. After RESET is
released (or a software reset is performed), no register writes should be performed within 1ms.
Table 63. Power Supply Timing Parameters
Parameter
Minimum
Typical
Maximum
Comments
tS-I
0
0
Time between SVDD/SPK_V/MICBIAS_VDD is provided and IOVDD1_33
is provided.
tI-D
0
0
0
0
Time between IOVDD1_33 is provided and DVDD_18 is provided.
Time between IOVDD1_33 is provided and IOVDD2_33 is provided.
tI1-I2
Before
DVDD_18
provided
tD-A
5*10k*CAVDD 5*10k*CAVDD
Time between DVDD_18 is provided and the 1.8V and 3.3V analog
supplies (AVDDx_18, HVDD_18, AVDD3_33, RECVDD_33) are provided.
AVDDx_18 must be internally present before changing to external 1.8V
analog supplies to prevent pop at headphone outputs.
tA-C
0
0
Time between AVDDx_18 supplies are provided and CPVDD_18 is
provided.
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Initialization Setup (continued)
Table 63. Power Supply Timing Parameters (continued)
Parameter
Minimum
Typical
Maximum
Comments
tD-R
10ns
10ns
Time between DVDD_18 (and IOVDD1_33) is provided and reset can be
released.
tD-P
tR-P
10ms
1ms
10ms
1ms
Time between DVDD_18 (and IOVDD1_33) is provided and when
registers can be written to enable the external 1.8V analog supplies.
Time between release of the reset and when registers can be written (that
is to enable the external 1.8V analog supplies).
9.3.1.2 Power On Sequence 2 - Shared 1.8V Analog Supplies
If desired, the analog supplies (AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18 and HVDD_18) could also be
externally supplied at the same time as DVDD_18. In this case, the weak pullup is not utilized. This is shown in
Figure 115.
SVDD, SPK_V,
tS-I
MICBIAS_VDD
IOVDD1_33
tI-D
tI1-I2
IOVDD2_33
DVDD_18
tD-A
AVDD1_18, AVDD2_18,
AVDD4_18, AVDD_18,
HVDD_18
tA-C
CPVDD_18
RECVDD_33
/RESET
tD-R
tR-P
tD-P
Write to
Registers
Disable AVDDx_18 weak connection to
DVDD_18 (Write ‘0’ to B0_P1_R1_D3)
Enable External Analog Power Supplies
(Write ‘0’ to B0_P1_R1_D2)
Figure 115. Simultaneous Powerup of Digital and Analog 1.8V Supplies
After RESET is released (or a software reset is performed), no register writes should be performed within 1ms.
Table 64. Power Supply Timing Parameters
Parameter
Minimum
Typical
Maximum
Comments
tS-I
0
0
Time between SVDD/SPK_V/MICBIAS_VDD is provided and IOVDD1_33
is provided.
tI-D
0
0
0
0
Time between IOVDD1_33 is provided and DVDD_18 is provided.
Time between IOVDD1_33 is provided and IOVDD2_33 is provided.
tI1-I2
Before
DVDD_18
provided
tA-C
0
0
Time between AVDDx_18 supplies are provided and CPVDD_18 is
provided.
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Table 64. Power Supply Timing Parameters (continued)
Parameter
Minimum
Typical
Maximum
Comments
tD-R
10ns
10ns
Time between DVDD_18 (and IOVDD1_33) is provided and reset can be
released.
tD-P
tR-P
10ms
1ms
10ms
1ms
Time between DVDD_18 (and IOVDD1_33) is provided and when
registers can be written to enable the external 1.8V analog supplies.
Time between release of the reset and when registers can be written (that
is to enable the external 1.8V analog supplies).
When the TLV320AIC3268 is controlled over a shared I2C bus, it is recommended that any I2C communication
be attempted only after the IOVDDx_33 and DVDD_18 rails have been powered up and the hardware reset
signal applied. If I2C communication is attempted before this requirement, even with other devices on the same
I2C bus, error conditions may occur.
9.3.2 Reset
The TLV320AIC3268 internal logic must be initialized to a known condition for proper device function. To initialize
the device in its default operating condition, the hardware reset terminal (RESET) must be pulled low for at least
10ns. For this initialization to work, both the IOVDDx_33 and DVDD_18 supplies must be powered up. It is
recommended that while the DVDD_18 supply is being powered up, the RESET terminal be pulled low.
The device can also be reset via software reset. Writing '1' into B0_P0_R1_D0 resets the device. After a device
reset, all registers are initialized with default values as listed in the Register Map section.
After hardware or software reset, the TLV320AIC3268 is in a sleep mode, when all the blocks and functions are
disabled. In this mode however the control interface, SPI or I2C remains enabled, allowing an external host
controller to configure the device. The blocks inside the TLV320AIC3268 must be configured for desired function
by writing into the control registers.
Given below are some of the typical configurations that are needed to be done before enabling TLV320AIC3268.
However the list of configurations is not unique or comprehensive and the requirements must be determined per
the application requirements.
•
•
•
Wait for Lockout time. See Device Startup Lockout Times for details.
Configuration of FIFO's. See Setting Device FIFOs for details.
Configure the device for PRB modes or programmable miniDSP modes for ADC and DAC.
–
For PRB modes, program the coefficients of user programmable filters, including setup adaptive
coefficient updates if necessary.
–
For programmable miniDSP mode, configure the instruction and coefficient memory for miniDSP.
•
•
•
•
•
Configure the oversampling rates, AOSR and DOSR, and power tune modes for ADCs and DACs.
Configure the clock dividers and PLL, if required. See Clock Generation and PLL for details.
Configure the Audio Serial Interfaces (ASI).
Configure the device common mode voltages. See Setting Device Common Mode Voltage for details.
Configure the analog signal routing to ADCs and from DACs, volume controls and power up the relevant
blocks.
Some device configurations require wait times after register configuration, to take effect. See Analog and
Reference Startup and PLL Startup for details. Table 42 describes internal flags which can be used to check
device status in response to device configurations or input signals.
The details of control registers for device configurations are described in Register Maps.
9.3.3 Device Startup Lockout Times
After the TLV320AIC3268 is initialized through hardware reset at power-up or software reset, the internal
registers are initialized to default values. This initialization takes place within 1ms after pulling the RESET signal
high. During this initialization phase, no register-read or register-write operation should be performed on ADC or
DAC coefficient buffers. Also, no block within the codec should be powered up during the initialization phase.
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9.3.4 Analog and Reference Startup
The TLV320AIC3268 uses an external VREF_AUDIO terminal for decoupling the reference voltage used for the
data converters and other analog blocks. VREF_AUDIO terminal requires a minimum 1µF decoupling capacitor
from VREF_AUDIO to VSS. In order for any analog block to be powered up, the Analog Reference block must be
powered up. By default, the Analog Reference block will implicitly be powered up whenever any analog block is
powered up, or it can be powered up independently. Detailed descriptions of Analog Reference including fast
power-up options are provided in Reference Voltage. During the time that the reference block is not completely
powered up, subsequent requests for powering up analog blocks (for example PLL) are queued, and executed
after the reference power up is complete.
When analog inputs are routed to the ADC PGA, approximately 2ms of wait is required to enable charging up of
input coupling capacitor before the routing is enabled.
9.3.5 PLL Startup
Whenever the PLL is powered up, a startup delay of approx 1ms is involved after the power up command of the
PLL and before the clocks are available to the codec. This delay is to ensure stable operation of PLL and clock-
divider logic.
9.3.6 Setting Device Common Mode Voltage
The TLV320AIC3268 allows the user to set the common mode voltage for analog inputs to 0.75V or 0.9V by
programming B0_P1_R8_D2. The input common-mode voltage of 0.9V works best when the analog supply
voltage is centered around 1.8V or above, and offers the highest possible performance. For analog supply
voltages below 1.8V, a common mode voltage of 0.75V must be used.
Table 65. Input Common Mode voltage and Input Signal Swing
Input Common Mode
Voltage (V)
AVdd (V)
Channel Gain
(dB)
Single-Ended Input Swing for
Differential Input Swing for
0dBFS output signal (VRMS)
0dBFS output signal (VRMS
)
0.75
0.90
>1.5
–2
0
0.375
0.5
0.75
1.0
1.8 … 1.95
NOTE
The input common mode setting is common for DAC playback and Analog Bypass path
9.3.7 Setting Device FIFOs
The TLV320AIC3268 features FIFO between CIC filters and miniDSP_A and miniDSP_D and DAC modulators.
These FIFO's allow ease of programming of signal processing functions within the miniDSP by allowing easier
interface with other blocks. However use of these FIFOs adds to group delay in the channel and should be
bypassed for delay sensitive applications along with appropriate care taken in miniDSP programming. By default
the FIFO between CIC filter and miniDSP_A is disabled and is recommended to be enabled by writing
B64_P0_R32_D7 as '1'. Similarly by default the FIFO between miniDSP_D and DAC modulator is disabled and is
recommended to be enabled by writing B120_P0_R50_D7 as '1'.
The TLV320AIC3268 has a feature which allows the miniDSP instruction frame to be synchronized with ASI's
data frame. For miniDSP_D, the synchronization is done with ASI1's data frame by default. However when the
TLV320AIC3268 is used with PRB modes for playback, it is recommended to disable miniDSP_D's
synchronization with ASI data frame by programming B0_P4_R119_D[7:6] as "11".
9.3.8 Miscellaneous
When enabling headphone amplifiers, it is recommended to program B0_P1_R77_D0 as '1' before powering up
headphone amplifier.
10 Power Supply Recommendations
See Power Supply for details about driving power supplies. See Power On Sequence for details on sequencing
of power supplies.
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11 Layout
11.1 Layout Guidelines
Each system design and PCB layout is unique; layout should be carefully reviewed in the context of a specific
PCB design. However, the following guidelines can optimize TLV320AIC3268 performance:
•
•
•
The TLV320AIC3268 thermal pad also serves as a device ground connection. Connect the thermal pad to the
ground plane using multiple VIAS to minimize impedance between device ground and PCB ground. The
TLV320AIC3268 has only one ground terminal. The digital ground and analog ground planes on the PCB
should be shorted to each other close the TLV320AIC3268 thermal pad.
The decoupling capacitors for the power supplies should be placed close to the device terminals. Figure 109
shows the recommended decoupling capacitors for the TLV320AIC3268. For SVDD, place the 10µF bulk
decoupling capacitor near where battery supply enters the PCB, and place the smaller 0.1µF and 1µF
decoupling capacitors closer to the device terminals.
Place the flying capacitor between CPFCP and CPFCM near the device terminals, with no VIAS between the
device terminals and the capacitor. Similarly, keep the decoupling capacitor on VNEG near the device
terminal with minimal VIAS between the device terminals, capacitor and PCB ground.
•
•
The TLV320AIC3268 internal voltage references must be filtered using external capacitors. Place the filter
capacitors on VREF_AUDIO and VREF_SAR near the device terminals for optimal performance.
The TLV320AIC3268 reduces crosstalk by a separate ground sense signal for the headphone jack. To
optimize crosstalk performance, use a separate trace from the HPVSS_SENSE terminal to the headphone-
jack ground terminal, with no other ground connections along the length.
•
•
The parasitic capacitance to ground plane should be minimized for SPKP and SPKM signals. Keep the signal
routing for SPKP and SPKM as short as possible for optimal performance of the speaker amplifier.
For analog differential audio signals, the signals should be routed differentially on the PCB for better noise
immunity. Avoid crossing of digital and analog signals to avoid undesirable crosstalk.
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11.2 Layout Example
Ground Plane
+1.8V
+3.3V
+1.8V
+1.8V
VSYS
AVDD 4_18
VSYS
SPK_V
VREF_SAR
DVDD_18
VREF_AUDIO
AVDD_18
1
= Via
+3.3V
= Ground Plane
+1.8V
+3.3V
+VDD
= Power Plane/ Inner Layer
= 0402 Footprint
= 0603 Footprint
= Optional Component
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12 器件和文档支持
12.1 社区资源
E2E™ 音频转换器论坛
TI E2E 社区
12.2 Trademarks
E2E is a trademark of Texas Instruments, Inc..
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
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13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV320AIC3268IRGCR
TLV320AIC3268IRGCT
ACTIVE
ACTIVE
VQFN
VQFN
RGC
RGC
64
64
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
AIC3268
AIC3268
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV320AIC3268IRGCR
TLV320AIC3268IRGCT
VQFN
VQFN
RGC
RGC
64
64
2000
250
330.0
180.0
16.4
16.4
9.3
9.3
9.3
9.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV320AIC3268IRGCR
TLV320AIC3268IRGCT
VQFN
VQFN
RGC
RGC
64
64
2000
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064H
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
7.4 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219011/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
7.4)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(3.45) TYP
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(
0.2) TYP
VIA
33
16
32
17
(1.16) TYP
(3.45) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219011/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(0.58)
36X ( 0.96)
33
16
17
32
(0.58)
(1.16)
TYP
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219011/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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