TLV3602DGKR [TI]
具有推挽输出的 2.5ns 双通道高速轨至轨比较器 | DGK | 8 | -40 to 125;
| 型号： | TLV3602DGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有推挽输出的 2.5ns 双通道高速轨至轨比较器 | DGK | 8 | -40 to 125 比较器 |
| 文件： | 总43页 (文件大小：2550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
TLV360x 具有2.5ns 传播延迟的325MHz 高速比较器
1 特性
3 说明
• 快速传播延迟：2.5 ns
• 低过驱动分散：600 ps
• 高切换频率：325 MHz
• 窄脉宽检测功能：1.25ns
• 推挽式输出
• 宽电源电压范围：2.4 V 至5.5 V
• 输入共模范围超出两个电源轨200 mV
• 低输入失调电压：±5mV
• 输出端已知启动条件
TLV360x 是一款 325MHz 高速比较器，具有轨到轨输
入和2.5ns 的传播延迟。这两款比较器可快速响应，并
具有宽工作电压范围，非常适合激光雷达、测距仪和线
路接收器中的窄信号脉冲检测和数据与时钟恢复应用。
与替代高速差分输出比较器相比，TLV360x 系列的推
挽（单端）输出可以简化 I/O 接口的板对板布线并节省
相关成本，同时能够降低功耗。它们可以直接连接下游
电路中的大多数现行数字控制器和IO 扩展器。
• TLV3603(E) 具体特性：
TLV3601 采用 5 引脚 SC70 和 SOT23 封装，因此非
常适合空间受限的设备，这些设备可从比较器的快速响
应时间中受益。TLV3603(E) 采用 6 引脚 SC70 封装，
速度和尺寸与 TLV3601 相同，同时提供可调迟滞控制
和锁存功能等附加特性。TLV3602 是 TLV3601 的双通
道版本，采用8 引脚VSSOP 和WSON 封装。
– 可调迟滞控制引脚
– 锁存功能
• TLV3603E 工作温度范围更宽
– -55°C 至125°C
• 封装：TLV3601 (SC70-5)、(SOT23-5)，
TLV3603(E) (SC70-6)，
器件信息
封装(1)
封装尺寸（标称值）
1.25mm x 2.00mm
2.90mm x 1.60mm
器件型号
TLV3601
TLV3602 (VSSOP-8)、(WSON-8)
• 功能安全型
SC70 (5)
– 可提供用于功能安全系统设计的文档
[TLV3601/2]
– 可提供用于功能安全系统设计的文档[TLV3603]
SOT-23 (5)
SC70 (6)
TLV3603(E)
TLV3602
1.25mm x 2.00mm
3.00mm x 3.00mm
VSSOP (8)
2 应用
2.00mm x 2.00mm
WSON (8)（预发
布）
• 激光测距仪
• 时钟和数据恢复
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 示波器和逻辑分析仪中的高速触发器功能
• 激光雷达中的距离感测
• 无人机视觉
• 高速差分线路接收器
TLV3601
(TLV3602 per Channel)
VCC
TLV3603
V+
+
+
–
OPA858
TLV3603
+
OUT
OUT
LE/HYST
–
+
TDC
LE/HYST
VEE
VEE
功能方框图
VBIAS
VREF
TLV3603 应用电路
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Device Support........................................................28
11.2 接收文档更新通知................................................... 28
11.3 支持资源..................................................................28
11.4 Trademarks............................................................. 28
11.5 静电放电警告...........................................................28
11.6 术语表..................................................................... 28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Diagrams ........................................................9
6.7 Typical Characteristics.............................................. 11
7 Detailed Description......................................................19
7.1 Overview...................................................................19
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................19
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (November 2022) to Revision E (March 2023)
Page
• 通篇添加了 TLV3603E........................................................................................................................................1
Changes from Revision C (July 2022) to Revision D (November 2022)
Page
• 删除了 TLV3602 VSSOP 封装的“预发布”状态...............................................................................................1
Changes from Revision B (November 2021) to Revision C (July 2022)
Page
• 为TLV3602 添加了VSSOP 和WSON 封装选项（处于“预发布”状态）........................................................1
• 删除了 TLV3601 SOT-23 封装的“预发布”状态...............................................................................................1
Changes from Revision A (August 2021) to Revision B (November 2021)
Page
• 从 TLV3603 中删除了“预发布”....................................................................................................................... 1
• 添加了 TLV3601 的DBV 封装预发布选项..........................................................................................................1
• Added typical performance curves....................................................................................................................11
Changes from Revision * (June 2021) to Revision A (August 2021)
Page
• 量产数据发布......................................................................................................................................................1
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
5 Pin Configuration and Functions
OUT
VEE
1
2
3
5
4
VCC
IN+
IN-
图5-1. DCK, DBV Package
5-Pin SC70, SOT-23
Top View
VCC
LE/HYS
6
5
1
2
3
OUT
VEE
4
IN+
IN-
图5-2. DCK Package
6-Pin SC70
Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
IN+
TLV3601
TLV3603(E)
3
4
3
4
I
I
Non-inverting input
Inverting input
IN–
Output
(Push-pull)
OUT
1
1
O
VEE
2
5
-
2
6
5
I
I
I
Negative power supply
Positive power supply
VCC
LE/HYS
Adjustable hysteresis control and latch
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
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IN1+
1
2
3
4
8
7
6
5
V+
OUT1
OUT2
V-
IN1–
IN2–
IN2+
图5-3. TLV3602 DGK, DSG Packages
8-Pin VSSOP, WSON
表5-2. Pin Functions: TLV3602 (Dual)
PIN
I/O
DESCRIPTION
NAME
NO.
IN1+
1
I
I
Noninverting input, channel 1
Inverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Output, channel 1
2
3
4
7
6
5
8
IN1–
IN2–
IN2+
OUT1
OUT2
V-
I
I
O
O
P
Output, channel 2
Negative (lowest) supply or ground
V+
P
-
Positive (highest) supply
Connect directly to V- pin
Thermal PAD
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
6
UNIT
V
Input Supply Voltage: VCC –VEE
Input Voltage (IN+, IN–)(2)
VCC + 0.3
V
V
EE –0.3
V
Differential Input Voltage (VDI = IN+ –IN–)
Output Voltage (OUT)(3)
–(VCC –VEE + 0.3) + (VCC –VEE + 0.3)
VCC + 0.3
V
V
V
EE –0.3
EE –0.3
Latch and Hysteresis Control (LE/HYS)
VCC + 0.3
±10
V
Current into Input pins (IN+, IN–, LE/HYS)(2)
Current into Output pins (OUT)(3)
Junction temperature, TJ
mA
mA
°C
°C
±50
150
Storage temperature, Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
(3) Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.3 V beyond the supply rails
must be current-limited to 50 mA or less.
6.2 ESD Ratings
VALUE
UNIT
TLV3601(DCK), TLV3603
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±2000
±1000
Electrostatic
V(ESD)
V
discharge
TLV3601(DBV)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001((1))
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002((2))
±2000
±750
Electrostatic
V(ESD)
V
V
discharge
TLV3602
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001((1))
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002((2))
±2000
±1000
Electrostatic
V(ESD)
discharge
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.4
MAX
UNIT
5.5
VCC + 0.3
VCC + 0.3
125
V
V
Input Supply Voltage: VCC –VEE
Input Voltage Range (IN+, IN–)
Latch and Hysteresis Control (LE/HYS)
Ambient temperature, TA
VEE –0.3
VEE –0.3
–40
V
°C
°C
Ambient temperature, TA (TLV3603E)
125
–55
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
6.4 Thermal Information
TLV3601
DBV (SOT-23)
5 PINS
TLV3601
DCK (SC70)
5 PINS
TLV3602
DGK (VSSOP)
8 PINS
TLV3602
DSG (WSON)
8 PINS
TLV3603 (E)
THERMAL METRIC
DCK (SC70)
6 PINS
UNIT
RθJA Junction-to-ambient thermal resistance
Rθ
176.5
187.5
170.5
64.9
165.1
°C/W
°C/W
Junction-to-case (top) thermal resistance
74.7
N/A
139.2
N/A
61.7
N/A
83.9
5.5
129.1
N/A
JC(top
)
Rθ
Junction-to-case (bottom) thermal
resistance
°C/W
JC(bot
tom)
RθJB Junction-to-board thermal resistance
43.4
16.7
65.8
43.0
92.4
8.9
32.0
2.1
58.9
39.4
°C/W
°C/W
Junction-to-top characterization
ψJT
parameter
Junction-to-board characterization
parameter
43.1
65.5
90.8
32.0
58.7
°C/W
ψJB
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
6.5 Electrical Characteristics
VCC = 2.5, 3.3 and 5 V, VEE = 0 V, VCM = VEE + 300 mV, CL = 5 pF probe capacitance, typical at TA = 25°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Input Characteristics
VIO
Input offset voltage
Input offset voltage
Input offset voltage drift
±0.5
±0.5
±3.0
5
mV
mV
TA = –40°C to +125℃
–5
VIO (TLV3603E)
dVIO/dT
10
TA = –55°C to +125℃
–10
μV/°C
Input common mode voltage
range
VCM
VCC + 0.2
V
V
TA = –40℃to +125℃
V
V
EE –0.2
Input common mode voltage
range
VCM (TLV3603E)
VCC + 0.2
5(1)
TA = –55℃to +125℃
TA = –40℃to +125℃
EE –0.2
VHYST (TLV3601/2) Input hysteresis voltage
1.5
3
1
mV
pF
CIN
Input capacitance
RDM
Input differential mode resistance
Input common mode resistance
Input bias current
67
5
kΩ
MΩ
uA
uA
uA
dB
dB
RCM
IB
1
5
5
TA = –40℃to +125℃
TA = –55℃to +125℃
IB (TLV3603E)
IOS
Input bias current
1
Input offset current
±0.03
80
80
CMRR
Common-mode rejection ratio
Power-supply rejection ratio
VCM = VEE –0.2V to VCC + 0.2V
PSRR
VCC = 2.4 to 5.5V
DC Output Characteristics
ISOURCE = 1 mA
TA = –40℃to +125℃
VOH
Output high voltage from VCC
60
60
80
80
80
80
mV
mV
mV
mV
mA
mA
mA
mA
ISOURCE = 1 mA
TA = –55℃to +125℃
VOH (TLV3603E)
VOL
Output high voltage from VCC
Output low voltage from VEE
Output low voltage from VEE
ISINK = 1 mA
TA = –40℃to +125℃
60
60
30
30
30
30
ISINK = 1 mA
TA = –55℃to +125℃
VOL (TLV3603E)
ISC_SOURCE
Output Short-Circuit Current -
Source
10
10
10
10
TA = –40℃to +125℃
TA = –55℃to +125℃
TA = –40℃to +125℃
TA = –55℃to +125℃
ISC_SOURCE (TLV360 Output Short-Circuit Current -
3E)
Source
Output Short-Circuit Current -
Sink
ISC_SINK
ISC_SINK (TLV3603E Output Short-Circuit Current -
)
Sink
Power Supply
Output being high
TA = –40℃to +125℃
ICC (TLV3601)
ICC (TLV3602)
ICC (TLV3603)
ICC (TLV3603E)
quiescent current
4.9
4.9
5.7
7
7
mA
mA
mA
Output being high
TA = –40℃to +125℃
quiescent current per channel
quiescent current
Output being high
TA = –40℃to +125℃
7.8
7.8
Output being high
TA = –55℃to +125℃
quiescent current
5.7
2.1
mA
V
VPOR (postive)
AC Characteristics
tPD
Power-On Reset Voltage
Propagation delay
Propagation delay
VOVERDRIVE = VUNDERDRIVE = 50mV
2.5
3.5(1)
4.5(1)
ns
ns
VOVERDRIVE = VUNDERDRIVE = 50mV
TA = –40℃to +125℃
tPD
VOVERDRIVE = VUNDERDRIVE = 50mV
TA = –55℃to +125℃
tPD (TLV3603E)
Propagation delay
4.5((1))
ns
ps
Channel-to-channel propagation VCM = VCC/2, VOVERDRIVE = VUNDERDRIVE
delay skew((2))
50mV, 50 MHz Squarewave
=
ΔtPD (TLV3602
only)
24
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
VCC = 2.5, 3.3 and 5 V, VEE = 0 V, VCM = VEE + 300 mV, CL = 5 pF probe capacitance, typical at TA = 25°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tCM_DISPERSION
Common dispersion
Overdrive dispersion
Underdrive dispersion
Rise time
VCM varied from VEE to VCC
80
ps
tOD_DISPERSION
Overdrive varied from 10 mV to 125 mV
Underdrive varied from 10mV to 125 mV
10% to 90%
600
330
0.75
0.75
ps
tUD_DISPERSION
ps
tR
tF
ns
Fall time
90% to 10%
ns
VIN = 100mVP-P
fIN = 100MHz, Jitter BW = 10Hz –50MHz
,
tJITTER
RMS Jitter
4
325
ps
MHz
ns
VIN = 200 mVPP Sine Wave,
When output high reaches 90% of VCC - VEE
or output low reaches 10% of VCC - VEE
fTOGGLE
Input toggle frequency
Minimum allowed input pulse
width
VOVERDRIVE = VUNDERDRIVE = 50mV
PWOUT = 90% of PWIN
PulseWidth
1.25
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
6.5 Electrical Characteristics (continued)
VCC = 2.5, 3.3 and 5 V, VEE = 0 V, VCM = VEE + 300 mV, CL = 5 pF probe capacitance, typical at TA = 25°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Latching/Adjustable Hysteresis
VHYST
VHYST
VHYST
VHYST
VIH_LE
Input hysteresis voltage
VHYST = Logic High
0
3
mV
mV
mV
mV
V
Input hysteresis voltage
Input hysteresis voltage
Input hysteresis voltage
LE pin input high level
RHYST = Floating
30
60
RHYST = 150 kΩ
RHYST = 56 kΩ
VEE + 1.5
VEE + 1.5
TA = –40℃to +125℃
TA = –55℃to +125℃
TA = –40℃to +125℃
TA = –55℃to +125℃
VIH_LE (TLV3603E) LE pin input high level
VIL_LE LE pin input low level
VIL_LE (TLV3603E) LE pin input low level
V
VEE + 0.35
VEE + 0.35
V
V
VLE = VCC
TA = –40℃to +125℃
IIH_LE
LE pin input leakage current
LE pin input leakage current
LE pin input leakage current
LE pin input leakage current
15
15
40
40
uA
uA
uA
uA
VLE = VCC
TA = –55℃to +125℃
IIH_LE (TLV3603E)
VLE = VEE
,
IIL_LE
TA = –40℃to +125℃
VLE = VEE
,
IIL_LE (TLV3603E)
TA = –55℃to +125℃
tSETUP
tHOLD
tPL
Latch setup time
Latch hold time
ns
ns
ns
–1.4
7.2
7
Latch to OUT delay
(1) Ensured by characterization
(2) Differential propagation delay is defined as the larger of the two:
ΔtPDLH = tPDLH(MAX) –tPDLH(MIN)
ΔtPDHL = tPDHL(MAX) –tPDHL(MIN)
where (MAX) and (MIN) denote the maximum and minimum values
of a given measurement across the different comparator channels.
6.6 Timing Diagrams
VOVERDRIVE
VUNDERDRIVE
IN-
VUNDERDRIVE
VOVERDRIVE
IN+
tPLH
tPHL
tR
tF
90%
50%
10%
VOUT
图6-1. General Timing Diagram
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English Data Sheet: SNOSDB1
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V
OD = 125mV
V
OD = 10mV
IN-
IN+
DISPERSION
VOUT
图6-2. Overdrive Dispersion
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6.7 Typical Characteristics
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
2
1.5
1
3.2
3.1
3
0.5
0
-0.5
-1
2.9
VCC = 2.5V
VCC = 3.3V
VCC = 5V
For 33 units
2.8
-1.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
图6-4. TLV3601 Hysteresis vs. Temperature
图6-3. TLV3601 Offset vs. Temperature
1.8
1.4
1
0.6
0.2
-0.2
-0.6
-1
For 33 units
-0.2 0.1 0.4 0.7
1
1.3 1.6 1.9 2.2 2.5 2.7
Input Common-Mode Voltage (V)
图6-6. TLV3601 Hysteresis vs. Common-Mode, 2.5 V
图6-5. TLV3601 Offset vs. Common-Mode, 2.5 V
1.8
5
4.5
4
1.4
1
3.5
3
0.6
0.2
-0.2
-0.6
-1
2.5
2
1.5
-40C
1
0.5
0
25C
85C
125C
For 33 units
2.8 3.3
-0.2
0.3
0.8
1.3
1.8
2.3
2.8
3.3
-0.2
0.3
0.8
1.3
1.8
2.3
Input Common Mode Voltage (V)
Input Common-Mode Voltage (V)
图6-8. TLV3601 Hysteresis vs. Common-Mode, 3.3 V
图6-7. TLV3601 Offset vs. Common-Mode, 3.3 V
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
5
4.5
4
1.8
1.4
1
3.5
3
0.6
0.2
-0.2
-0.6
-1
2.5
2
1.5
1
-40C
25C
85C
0.5
0
125C
For 33 units
-0.2 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.2
Input Common Mode Voltage (V)
-0.2 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.2
Input Common-Mode Voltage (V)
图6-10. TLV3601 Hysteresis vs. Common-Mode, 5 V
图6-9. TLV3601 Offset vs. Common-Mode, 5 V
40
2
38
36
34
32
30
28
26
24
1.5
1
0.5
0
-0.5
-1
VCC = 2.5V
VCC = 3.3V
VCC = 5V
For 33 units
-40 -25 -10
5
20 35 50 65 80 95 110 125
-1.5
Temperature (C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
图6-12. TLV3603 Hysteresis vs. Temperature
图6-11. TLV3603 Offset vs. Temperature
1.8
1.4
1
40
38
36
34
32
30
28
26
24
-40C
25C
85C
125C
0.6
0.2
-0.2
-0.6
-1
For 33 units
-0.2 0.1 0.4 0.7
1
1.3 1.6 1.9 2.2 2.5 2.7
Input Common-Mode Voltage (V)
-0.2 0.1 0.4 0.7
1
1.3 1.6 1.9 2.2 2.5 2.7
Input Common-Mode Voltage (V)
图6-13. TLV3603 Offset vs. Common-Mode, 2.5 V
图6-14. TLV3603 Hysteresis vs. Common-Mode, 2.5 V
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
1.8
1.4
1
40
38
36
34
32
30
28
26
24
-40C
25C
85C
125C
0.6
0.2
-0.2
-0.6
-1
For 33 units
2.8 3.3
-0.2
0.3
0.8
1.3
1.8
2.3
-0.2
0.3
0.8
1.3
1.8
2.3
2.8
3.3
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
图6-15. TLV3603 Offset vs. Common-Mode, 3.3 V
1.8
图6-16. TLV3603 Hysteresis vs. Common-Mode, 3.3 V
40
-40C
25C
85C
125C
38
36
34
32
30
28
26
24
1.4
1
0.6
0.2
-0.2
-0.6
-1
For 33 units
-0.2 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.2
Input Common-Mode Voltage (V)
-0.2 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.2
Input Common-Mode Voltage (V)
图6-17. TLV3603 Offset vs. Common-Mode, 5 V
图6-18. TLV3603 Hysteresis vs. Common-Mode, 5 V
80
70
60
50
40
30
20
10
0
80
-40C
25C
85C
125C
-40C
25C
85C
125C
70
60
50
40
30
20
10
0
0
200
400
600
800
1,000
0
200
400
600
800
1,000
RHYST (k)
RHYST (k)
图6-19. TLV3603 Hysteresis vs. Resistance, 2.5 V
图6-20. TLV3603 Hysteresis vs. Resistance, 3.3 V
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
80
-40C
25C
85C
125C
70
60
50
40
30
20
10
0
0
200
400
600
800
1,000
RHYST (k)
图6-21. TLV3603 Hysteresis vs. Resistance, 5 V
图6-22. Bias Current vs. Input Voltage, 2.5 V
8
6
4
2
0
-2
-4
-6
-8
-40C
25C
85C
125C
-0.2
0.3
0.8
1.3
1.8
2.3
2.8
3.3
Input Voltage (V)
图6-24. Bias Current vs. Input Voltage, 5 V
图6-23. Bias Current vs. Input Voltage, 3.3 V
10
1
100m
10m
1m
-40C
25C
85C
125C
100
1m
10m
100m
Output Sourcing Current (A)
图6-26. Output Voltage vs. Output Sinking Current, 2.5 V
图6-25. Output Voltage vs. Output Sourcing Current, 2.5 V
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
图6-28. Output Voltage vs. Output Sinking Current, 3.3 V
图6-27. Output Voltage vs. Output Sourcing Current, 3.3 V
图6-30. Output Voltage vs. Output Sinking Current, 5 V
图6-29. Output Voltage vs. Output Sourcing Current, 5 V
5.5
5.5
5.3
5.1
5.3
5.1
4.9
4.9
-40C
-40C
4.7
4.7
25C
25C
85C
125C
85C
125C
4.5
4.5
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Supply Voltage (V)
图6-31. TLV3601 Supply Current vs. Voltage (Output Low)
图6-32. TLV3601 Supply Current vs. Voltage (Output High)
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
图6-33. TLV3601 Supply Current vs. Temp (Output Low)
图6-34. TLV3601 Supply Current vs. Temp (Output High)
6.2
6.2
6
6
5.8
5.8
5.6
5.6
-40C
-40C
5.4
5.4
25C
25C
85C
125C
85C
125C
5.2
5.2
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Supply Voltage (V)
图6-35. TLV3603 Supply Current vs. Voltage (Output Low)
图6-36. TLV3603 Supply Current vs. Voltage (Output High)
6.2
6.2
6
5.8
5.6
6
5.8
5.6
5.4
5.4
VCC = 2.5V
VCC = 2.5V
VCC = 3.3V
VCC = 3.3V
VCC = 5V
VCC = 5V
5.2
-40 -25 -10
5.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
5
20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
图6-37. TLV3603 Supply Current vs. Temp (Output Low)
图6-38. TLV3603 Supply Current vs. Temp (Output High)
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
4.5
4
4.5
4
-40C
25C
85C
125C
-40C
25C
85C
125C
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1.5
10
20 30 40 50 70 100
200 300 500 7001000
10
20 30 40 50 70 100
200 300 500 7001000
Input Overdrive (mV)
Input Overdrive (mV)
图6-39. Propagation Delay, Low to High, 2.5 V
图6-41. Propagation Delay, Low to High, 3.3 V
图6-43. Propagation Delay, Low to High, 5 V
图6-40. Propagation Delay, High to Low, 2.5 V
4.5
4
-40C
25C
85C
125C
3.5
3
2.5
2
1.5
10
20 30 40 50 70 100
200 300 500 7001000
Input Overdrive (mV)
图6-42. Propagation Delay, High to Low, 3.3 V
图6-44. Propagation Delay, High to Low, 5 V
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603(E) only), and input overdrive = 50 mV,
unless otherwise noted.
10
8
10
8
6
6
4
4
2
2
tPHL
tPLH
tPHL
tPLH
0
0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Output Capacitive Load (pF)
Output Capacitive Load (pF)
图6-45. Propagation Delay vs. Load Capacitance, 3.3 V
图6-46. Propagation Delay vs. Load Capacitance, 5 V
图6-47. Minimum Pulse Width vs. Temperature
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7 Detailed Description
7.1 Overview
TheTLV360x family are high-speed comparators with single-ended (push-pull) output stages. The fast response
time of these comparators make them well suited for applications that require narrow pulse width detection or
high toggle frequencies. The TLV3601 is available in a 5-pin SC70 and SOT23 package, while the TLV3603(E) is
packaged in a 6-pin SC70. The TLV3602 is a dual channel version of the TLV3601 and is packaged in an 8-pin
VSSOP and WSON package.
7.2 Functional Block Diagram
TLV3601
TLV3603
VCC
VCC
+
+
LE/HYST
VEE
VEE
7.3 Feature Description
The TLV3601,TLV3603(E), and TLV3602 are single and dual channel, high speed comparators with a typical
propagation delay of 2.5 ns and push-pull outputs. The minimum pulse width detection capability is 1.25 ns and
the typical toggle rate is 325 MHz. These comparators are well-suited for distance measurement applications
that utilize a time-of-flight arechitecture as well as systems that suffer from capacitive loading and require data
and clock recovery. In addition to their high speed, the TLV360x family offers rail-to-rail input stages capable of
operating up to 200 mV beyond each power supply rail combined with a maximum 5 mV input offset. The
TLV3603(E) also provides adjustable hysteresis via an external resistor for noise suppression or a latching mode
to hold the output of the comparators.
7.4 Device Functional Modes
The TLV3601 has a single functional mode and is active when the power supply voltage is greater than 2.4V.
The TLV3603(E) has two modes of operation. The first is an active mode where the output reflects the condition
at the inputs when an external resistor is connected to ground on the LE/HYS pin. The second is a latch mode
where the output is held at its last active state when the LE/HYS pin is pulled low. The TLV3603(E) returns to
active mode after a short delay when the pin is pulled high.
7.4.1 Inputs
The TLV360x family features input stages capable of operating 200 mV below negative power supply (ground)
and 200 mV beyond the positive supply voltage, allowing for zero cross detection and maximizing input dynamic
range given a certain power supply. The input stages are protected from conditions where the voltage on either
pin exceeds this level by internal ESD protection diodes to VCC and VEE. To avoid damaging the inputs when
exceeding the recommended input voltage range, an external resistor should be used to limit the current.
7.4.2 Push-Pull (Single-Ended) Output
The TLV360x outputs have excellent drive capability and are designed to connect directly to CMOS logic input
devices. Likewise, the comparator output stages can drive capacitive loads. Transient performance parameters
in the Electrical Characteristics Tables and Typical Characteristics section are for a load of 5pF, corresponding to
a standard CMOS load. Device performance for larger capacitive loads can be found in the typical performance
curves titled Propagation Delay vs Capacitive Load. For optimal speed and performance, output load
capacitance should be reduced as much as possible.
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7.4.3 Known Startup Condition
The TLV360x have a Power-on-Reset (POR) circuit which provides system designers a known start-up condition
for the output of the comparators. When the power supply (VCC) is ramping up or ramping down, the POR circuit
will be active when VCC is below VPOR. When active, the POR circuit holds the output low at VEE. When VCC is
greater than or equal to VPOR as stated in 节6.5 , the comparator output reflects the state of the input pins.
图 7-1 shows how the TLV360x outputs respond for VCC rising. The input is configured with a logic high input to
highlight the transition from the POR circuit control (logic low output) to a standard comparator operation where
the output reflects the input condition. Note how the output goes high when VCC reaches 2.1V.
图7-1. TLV3601/TLV3603 Output for VCC Rising
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Hysteresis
As a result of a comparator’s high open loop gain, there is a small band of input differential voltage where the
output can toggle back and forth between “logic high” and “logic low” states. This can cause design
challenges for inputs with slow rise and fall times or systems with excessive noise. These challenges can be
overcome by adding hysteresis to the comparator.
Since the TLV3601 and TLV3602 only has a minimal amount of internal hysteresis, external hysteresis can be
applied in the form of a positive feedback loop that adjusts the trip point of the comparator depending on its
current output state. See the Implementing Hysteresis section for more details.
The TLV3603(E) on the other hand has a LE/HYS pin that can be used to increase or eliminate the internal
hysteresis of the comparator. In order to increase the internal hysteresis of the TLV3603(E), connect a single
resistor as shown in the adjusting hysteresis figure between the LE/HYS pin and VEE. A curve of hysteresis
versus resistance is provided below to provide guidance in setting the desired amount of hysteresis. Likewise,
for applications where no hysteresis is desired, the LE/HYS pin can be connected to VCC.
VCC
TLV3603
IN+
+
OUT
IN-
LE/HYS
VEE
图8-1. Adjustable Hysteresis with an External Resistor
80
-40C
25C
85C
125C
70
60
50
40
30
20
10
0
0
200
400
600
800
1,000
RHYST (k)
图8-2. VHYST (mV) vs RHYST (kΩ), VCC = 5 V
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8.1.2 Capacitive Loads
For capacitive loads under 100 pF, the propagation delay has minimum change (see Propagation Delay vs.
Capacitive Load). However, excessive capacitive loading under high switching frequencies may increase supply
current, propagation delay, or induce decreased slew rate.
8.1.3 Latch Functionality
The latch pin for the TLV3603(E) holds the output state of the device when the voltage at the LE/HYS pin is a
logic low. This is particularly useful when the output state is intended to remain unchanged. An important
consideration of the latch functionality is the latch hold and setup times. Latch hold time is the minimum time
required (after the latch pin is asserted) for properly latching the comparator output. Likewise, latch setup time is
defined as the time that the input must be stable before the latch pin is asserted low. The figure below illustrates
when the input can transition for a valid latch. Note that the typical setup time in the EC table is negative; this is
due to the internal trace delays of the LE/HYS pin relative to the input pin trace delays. A small delay (tPL) in the
output response is shown below when the TLV3603(E) exits a latched output stage.
tSETUP
tHOLD
LE/HYS
Valid Input Transition
Region
Valid Input
Transition Region
Invalid Input
Transition Region
IN
图8-3. Input Change Properly Latched
LE/HYS
IN
tPL
OUT
图8-4. Latch Disable with Input Change
8.2 Typical Application
8.2.1 Implementing Hysteresis
A comparator may produce “chatter” (multiple transitions) at the output when there are noise or signal
variations around the reference threshold; this causes the output to change states in rapid random successions
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as the comparator input goes above and below the threshold of the reference. This usually occurs when the
input signal is moving very slowly across the switching threshold of the comparator. This problem can be
prevented by using the internal hysteresis feature of the comparator or by the addition of external hysteresis.
The TLV3603(E) has a LE/HYS pin that allows for variable internal hysteresis depending on the resistor value
connected between the pin and VEE, where increasing the resistance decreases the hysteresis to a minimum
level.
V
CC
5 V
TLV3603
V
IN
+
V
O
V
O
V
V
L
V
REF 2.5 V
H
0 V
2.485 V
2.515 V
LE/HYS
V
R
IN
1
150 kΩ
V
EE
图8-5. Adjustable Hysteresis with a 150kΩ Resistor using TLV3603
Since the TLV3601 and TLV3602 only have a minimal amount of internal hysteresis, external hysteresis can be
added in the form of a positive feedback loop. A non-inverting comparator with hysteresis requires a two-resistor
network and a voltage reference (VREF) at the inverting input, as shown in Figure 8-6.
5 V
V
–
+
REF 2.5 V
V
V
O
A
V
O
V
IN
V
V
L
H
R
60
1
0 V
2.485 V
2.515 V
R
V
IN
2
10 k
图8-6. Non-Inverting Configuration for Hysteresis using TLV3601
8.2.1.1 Design Requirements
For this design, follow these design requirements.
表8-1. Design Parameters
PARAMETER
VALUE
Supply Voltage (VCC
)
5 V
VREF
VHYS
2.5 V
30 mV
2.485 V
2.515 V
Lower Threshold (VL)
Upper Threshold (VH)
8.2.1.2 Detailed Design Procedure
For the TLV3603(E), the hysteresis vs. resistance curve (Figure 8-2) can be used as a guidance to set the
desired amount of hysteresis. Figure 8-2 shows that for a 30-mV hysteresis, a 150 kΩ resistor must be placed
from the LE/HYS pin to VEE.
For the TLV3601 and TLV3602, the following procedure can be used to add external hysteresis for a non-
inverting configuration. Note that VHYST << VREF, so VHYST can be ignored and is not included in the following
equations for simpler calculation.
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The equivalent resistor networks when the output is high and low are shown in Figure 8-7.
V
Low
V
High
CC
O
O
V
V
H
R
R
2
1
2
V
= V
V = V
A REF
A
REF
R
R
1
V
L
图8-7. Equivalent Resistor Networks for Non-Inverting Configuration with Hysteresis
When VIN is less than VREF, the output is low. For the output to switch from low to high, VIN must rise above the
VH threshold. Use Equation 1 to calculate VH.
VH = (R1 x VREF/R2) + VREF
(1)
When VIN is greater than VREF, the output is high. For the comparator to switch back to a low state, VIN must
drop below the VL threshold. Use Equation 2 to calculate VL.
VL = [VREF (R1 + R2) - VCC x R1] / R2
(2)
The hysteresis of this circuit is the difference between VH and VL, as shown in Equation 3.
ΔVIN = VHYS = (VCC x R1/R2)
(3)
Select a value for R2. Plug in given values for VCC, VREF, VH, and VL . For the given example, R2 = 10 kΩ, and
R1 is solved as 60 Ω.
For more information, please see Application Notes SNOA997 "Inverting Comparator with Hysteresis Circuit",
SBOA313 "Non-Inverting Comparator With Hysteresis Circuit", SBOA219 "Comparator with and without
hysteresis circuit".
8.2.1.3 Application Curve
V
(V)
IN
图8-8. Hysteresis Transfer Curve using TLV3601/TLV3603
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
8.2.2 Optical Receiver
The TLV360x can be used in conjunction with a high speed amplifier such as the OPA858 to create an optical
receiver as shown in the figure below. The photodiode is connected to a bias voltage and is being driven with a
pulsed laser. The OPA858 takes the current conducting through the diode and translates it into a voltage for a
high speed comparator to detect. The comparators will then output the proper output signal according to the
threshold set (VREF).
OPA858
TLV3603
+
+
TDC
LE/HYST
VBIAS
VREF
图8-9. Optical Receiver
8.2.3 Over-Current Latch Condition
When it is important for a system to detect a brief over-current condition, it is advisable to utilize the latching
feature of the TLV3603(E). By latching the comparator output, the MCU is reassured not to miss the over-current
occurrence. The circuit below shows one way to implement the latching function.
When an over-current condition is detected by the TLV3603(E), the output will go high. The occurrence of the
output going high coupled with a logic high from the RESET signal from the MCU will create a logic low signal at
the output of the 2-channel NAND gate. This will cause the output of the TLV3603(E) to be held in a logic high
state (latched), thus allowing the MCU to detect the fault condition regardless of how narrow the over-current
condition persists. The addition of the NAND gate also provides a means of clearing the latch state of the
comparator once the MCU is done processing the event. This is accomplished by the MCU passing a logic low
state to the NAND input causing the LE/HYS pin of the comparator to be returned to a logic high state. The
TLV3603(E) latched status is cleared and the TLV3603(E) output can continue to track the status of the input
pins.
System
IS
TLV3603
+
ALERT
+
MCU
VREF
LE/HYS
RS
RESET
图8-10. Over-Current Latched Output Circuit
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Product Folder Links: TLV3601 TLV3602 TLV3603 TLV3603E
English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
8.2.4 External Trigger Function for Oscilloscopes
Below is a typical configuration for creating an external trigger on oscilliscopes. The user adjusts the trigger level
by programming a DAC that the TLV360x can use as a reference. The input from an oscilloscope channel is then
compared to the trigger reference voltage, and the comparator sends a signal to a downstream FPGA to begin a
capture.
VCC = 5V
+
Trigger Input
+
–
FPGA
TLV3601
-
VIN
DAC
图8-11. External Trigger Function
9 Power Supply Recommendations
The TLV360x are specified for operation from 2.4 V to 5.5 V. While most applications will require single supply
operation where VEE is connected to the ground plane and VCC is connected to the intended power supply
level, the comparators can also be operated with split supplies. One caution when using split supplies is that the
output logic levels are determined by the VCC and VEE levels. For example, if split supplies of +/- 2.5V are
used, the output levels will be 2.5V and -2.5V accordingly. In addition, the logic level of the LE/HYS pin will also
be referenced to VEE. This means that the external hysteresis resistor on the TLV3603(E) needs to be
connected between the LE/HYS pin and VEE (not to ground) for proper operation.
Regardless of single supply or split supply operation, proper decoupling capacitors are required. It is
recommended to use a scheme of multiple, low-ESR ceramic capacitors from the supply pins to the ground
plane for optimum performance. A good combination would be 100 pF, 10 nF, and 1 uF with the lowest value
capacitor closest to the comparator.
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.
1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding
(use of a ground plane) helps maintain specified device performance.
Likewise, high performance board materials such as Rogers or high speed FR4 is also recommended.
2. Place a decoupling capacitor (100-pF ceramic, surface-mount capacitor) between VCC and
VEE as close to the device as possible. Using multiple bypass capacitors in different decade ranges such as
100-pF, 100-nF, and 1-µF provides the best noise reduction across frequency ranges.
3. On the inputs and the output, keep lead lengths as short and minimize capacitive coupling to the traces by
having a keepout area around the traces that is 3x the width of the traces. It is also recommended to keep
inputs away from the output.
4. Solder the device directly to the PCB rather than using a socket.
10.2 Layout Example
图10-1. TLV3603 Layout Example
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Product Folder Links: TLV3601 TLV3602 TLV3603 TLV3603E
English Data Sheet: SNOSDB1
TLV3601, TLV3602, TLV3603, TLV3603E
ZHCSKO5E –JUNE 2021 –REVISED APRIL 2023
www.ti.com.cn
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LIDAR Pulsed Time of Flight Reference Design
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TLV3601 TLV3602 TLV3603 TLV3603E
English Data Sheet: SNOSDB1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV3601DBVR
TLV3601DBVT
TLV3601DCKR
TLV3601DCKT
TLV3602DGKR
TLV3602DGKT
TLV3603DCKR
TLV3603DCKR-ET
TLV3603DCKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DGK
DGK
DCK
DCK
DCK
5
5
5
5
8
8
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-55 to 125
-40 to 125
3601
3601
1JF
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SC70
1JF
VSSOP
VSSOP
SC70
3602
3602
1JI
3000 RoHS & Green
3000 RoHS & Green
SC70
1P9
1JI
SC70
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Apr-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV3601, TLV3602, TLV3603 :
Automotive : TLV3601-Q1, TLV3602-Q1, TLV3603-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV3601DBVR
TLV3601DBVT
TLV3601DCKR
TLV3601DCKT
TLV3602DGKR
TLV3602DGKT
TLV3603DCKR
TLV3603DCKR-ET
TLV3603DCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DGK
DGK
DCK
DCK
DCK
5
5
5
5
8
8
6
6
6
3000
250
180.0
180.0
180.0
180.0
330.0
330.0
180.0
180.0
180.0
8.4
8.4
3.2
3.2
3.2
3.2
2.3
2.3
3.4
3.4
2.3
2.3
2.3
1.4
1.4
4.0
4.0
4.0
4.0
8.0
8.0
4.0
4.0
4.0
8.0
8.0
Q3
Q3
Q3
Q3
Q1
Q1
Q3
Q3
Q3
3000
250
8.4
2.47
2.47
5.3
1.25
1.25
1.4
8.0
SC70
8.4
8.0
VSSOP
VSSOP
SC70
2500
250
12.4
12.4
8.4
12.0
12.0
8.0
5.3
1.4
3000
3000
250
2.47
2.47
2.47
1.25
1.25
1.25
SC70
8.4
8.0
SC70
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV3601DBVR
TLV3601DBVT
TLV3601DCKR
TLV3601DCKT
TLV3602DGKR
TLV3602DGKT
TLV3603DCKR
TLV3603DCKR-ET
TLV3603DCKT
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DGK
DGK
DCK
DCK
DCK
5
5
5
5
8
8
6
6
6
3000
250
210.0
210.0
183.0
183.0
366.0
366.0
183.0
183.0
183.0
185.0
185.0
183.0
183.0
364.0
364.0
183.0
183.0
183.0
35.0
35.0
20.0
20.0
50.0
50.0
20.0
20.0
20.0
3000
250
SC70
VSSOP
VSSOP
SC70
2500
250
3000
3000
250
SC70
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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