TLV3604DCKT [TI]
TLV3604, TLV3605 800-ps High-Speed RRI Comparator with LVDS Outputs;
| 型号： | TLV3604DCKT |
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TEXAS INSTRUMENTS |
| 描述： | TLV3604, TLV3605 800-ps High-Speed RRI Comparator with LVDS Outputs |
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TLV3604,TLV3605
SNOSDA2C – AUGUST 2020 – REVISED APRIL 2021
TLV3604, TLV3605 800-ps High-Speed RRI Comparator with LVDS Outputs
to detect narrow pulse widths of just 600 ps. This
1 Features
combination of low variation in propagation delay due
to input overdrive and the ability to detect narrow
pulses improve system performance and extend
distance range in Time-of-Flight (ToF) applications.
•
•
•
•
•
•
•
•
Low propagation delay: 800 ps
Low overdrive dispersion: 350 ps
Quiescent Current: 12.1 mA
High toggle frequency: 1.5 GHz / 3.0 Gbps
Narrow pulse width detection capability: 600 ps
LVDS output
Supply range: 2.4 V to 5.5 V
Input common-mode range extends 200 mV
beyond both rails
The Low-Voltage-Differential-Signal (LVDS) output of
the TLV3604 and TLV3605 also helps increase data
throughput and optimizes power consumption. The
complementary outputs reduce EMI by suppressing
common mode noise on each output. The LVDS
output is designed to drive and interface directly with
downstream devices that accept a standard LVDS
input, such as high-speed FPGAs and CPUs.
•
•
Low input offset voltage: ±5 mV
Packages: 6-Pin SC70, 12-Pin QFN (3 mm × 3
mm)
The TLV3604 is in a tiny 6 pin SC-70 package, which
makes it easier for space sensitive applications such
as an optical sensor module. The TLV3605 maintains
the same performance as the TLV3604, and offers
adjustable hysteresis control, shutdown, and latching
features in a 12 pin QFN package making it
an excellent choice for test and measurement
applications.
2 Applications
•
•
•
Distance sensing in LIDAR
Time-of-Flight sensors
High speed trigger function in oscilloscope and
logic analyzer
•
•
High speed differential line receiver
Drone vision
Device Information
3 Description
PART NUMBER
TLV3604
TLV3605
PACKAGE (1)
BODY SIZE (NOM)
The TLV3604 and TLV3605 are 800-ps, high-speed
comparators with LVDS outputs and rail-to-rail inputs.
These features, along with an operating voltage range
of 2.4 V to 5.5 V and a high toggle frequency of 3
Gbps, make the TLV3604 and TLV3605 well suited for
LIDAR, clock and data recovery applications, and test
and measurement systems.
SC70 (6)
QFN (12)
1.25 mm × 2.00 mm
3.00 mm × 3.00 mm
1. For all orderable packages, see the orderable
addendum at the end of the datasheet.
Likewise, the TLV3604 and TLV3605 have strong
input overdrive performance of 350 ps and are able
VCCI/VCCO
VCCI
VCCO
LVDS
+
–
+
–
LVDS
SHDN
TLV3604
TLV3605
R
LE/HYS
VEE
VEE
Functional Block Diagram
TpLH v. Overdrive Dispersion
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV3604, TLV3605
SNOSDA2C – AUGUST 2020 – REVISED APRIL 2021
www.ti.com
Table of Contents
1 Features ...........................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics (VCCI = VCCO = 2.5 V to
5 V) ...............................................................................6
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................12
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 15
9 Power Supply Recommendations................................18
10 Layout...........................................................................19
10.1 Layout Guidelines................................................... 19
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................21
11.1 Device Support........................................................21
11.2 Receiving Notification of Documentation Updates..21
11.3 Support Resources................................................. 21
11.4 Trademarks............................................................. 21
11.5 Electrostatic Discharge Caution..............................21
11.6 Glossary..................................................................21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2020) to Revision C (April 2021)
Page
•
•
Updated Typical Performance Curves................................................................................................................8
Updated Latch Functionality............................................................................................................................. 13
Changes from Revision A (August 2020) to Revision B (December 2020)
Page
•
APL to RTM release............................................................................................................................................1
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5 Pin Configuration and Functions
OUT+
1
2
3
6
5
4
OUTÞ
VCCI/VCCO
INÞ
VEE
IN+
Figure 5-1. DCK Package
6-Pin SC70
Top View
12 11 10
9
8
7
VEE
VCCO
1
2
3
LE/HYS
SHDN
VCCI
VEE
4
5
6
Figure 5-2. RVK Package
12-Pin QFN
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
IN+
TLV3604
TLV3605
3
4
1
6
2
5
5
-
4
I
I
Non-inverting input
Inverting input
IN–
6
OUT+
OUT–
VEE
12
O
O
I
Non-inverting output
Inverting output
10
3, 5, 9, 11
Negative power supply
VCCI
2
1
7
8
I
Positive input section power supply
Positive output section power supply
Shutdown control, active low
VCCO
SHDN
LE/HYS
I
I
-
I
Adjustable hysteresis control and latch
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
Input Supply Voltage: VCCI – VEE
Output Supply Voltage: VCCO – VEE
Supply Voltage Difference: VCCI – VCCO
Input Voltage (IN+, IN–)(2)
6
6
–0.3
V
–6
6
V
VEE – 0.3
–(VCCI + 0.3)
VEE – 0.3
VEE – 0.3
VEE – 0.3
–10
VCCI + 0.3
+(VCCI + 0.3)
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
+10
V
Differential Input Voltage (VDI = IN+, IN–)
Output Voltage (OUT+, OUT–)(3)
Shutdown Enable (SHDN)
V
V
V
Latch and Hysteresis Control (LE/HYS)
Current into Input pins (IN+, IN–, SHDN, LE/HYS)(2)
Current into Output pins (OUT+, OUT–)(3)
Junction temperature, TJ
V
mA
mA
°C
°C
–10
+10
150
Storage temperature, Tstg
–65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails or 6
V, whichever is lower, must be current-limited to 10 mA or less.
(3) Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.3 V beyond the supply rails
must be current-limited to 10 mA or less.
6.2 ESD Ratings
VALUE
±1500
±2000
±1000
UNIT
TLV3604 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
TLV3605 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standaed ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.4
MAX
UNIT
Input Supply Voltage: VCCI – VEE
Output Supply Voltage: VCCO – VEE
Input Voltage Range (IN+, IN–)
Shutdown Enable (SHDN)
5.5
5.5
V
V
2.4
VEE – 0.3
VEE – 0.3
VEE – 0.3
–40
VCCI + 0.3
VCCO + 0.3
VCCO + 0.3
125
V
V
Latch and Hysteresis Control (LE/HYS)
Ambient temperature, TA
V
°C
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6.4 Thermal Information
TLV3604
DCK (SC70)
6 PINS
TLV3605
THERMAL METRIC
RVK (WQFN)
12 PINS
85.8
UNIT
RθJA
Junction-to-ambient thermal resistance
170.3
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
134.5
71.6
Rθ
Junction-to-case (bottom) thermal resistance
N/A
15.1
°C/W
JC(bottom)
RθJB
ψJT
Junction-to-board thermal resistance
63.3
43.7
63.1
52.7
4.1
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
52.7
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6.5 Electrical Characteristics (VCCI = VCCO = 2.5 V to 5 V)
VCCI = VCCO = 2.5 to 5 V, VEE = 0 V, VCM = VEE + 300 mV, RLOAD = 100 Ω, CL = 1 pF probe capacitance, typical at TA = 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Input Characteristics
VCCI = VCCO = 2.5 V and 5 V
TA = –40°C to +125℃
(1)
VIO
Input offset voltage
-5
±0.5
5
mV
V
Input common mode voltage
range
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
VCM
VEE – 0.2
VCCI + 0.2
VHYST
CIN
Input hysteresis voltage
0
1
mV
pF
Input capacitance
RDM
RCM
Input differential mode resistance
Input common mode resistance
67
5
kΩ
MΩ
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
IB
Input bias current
Input offset current
-5
-1
-1
5
1
uA
uA
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
IOS
VCCI = VCCO = 2.5 V and 5 V
VCM = VEE – 0.2V to VCCI + 0.2V,
TA = –40℃ to +125℃
CMRR (1)
PSRR (1)
Common-mode rejection ratio
Power-supply rejection ratio
50
55
80
80
dB
dB
VCCI = VCCO = 2.5 V to 5 V,
TA = –40℃ to +125℃
DC Output Characteristics
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
VOCM
Output common mode voltage
1.125
1.2
1.375
50
V
mV
Output common mode voltage
mismatch
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
ΔVOCM
VOCM_PP
VOD
Peak-to-Peak output common
mode voltage
20
mVpp
mV
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
Differential output voltage
250
350
450
10
Differential output voltage
mismatch
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
ΔVOD
mV
Power Supply
ICC (TLV3604)
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
Total quiescent current
12.1
7.5
16.5
10.5
7.0
mA
mA
mA
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
ICCI (TLV3605)
Input stage quiescent current
Output stage quiescent current
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
ICCO (TLV3605)
AC Characteristics
tPD
5.2
VOVERDRIVE = VUNDERDRIVE = 50mV, 50 MHz
Squarewave
Propagation delay
800
40
ps
ps
VOVERDRIVE = VUNDERDRIVE = 50mV, 50 MHz
Squarewave
tPD_SKEW
Propagation delay skew
tCM_DISPERSION
Common dispersion
Overdrive dispersion
Underdrive dispersion
Rise time
VCM varied from VEE to VCCI
200
350
200
350
350
1.5
ps
ps
tOD_DISPERSION
Overdrive varied from 10 mV to 250 mV
Underdrive varied from 10mV to 250 mV
20% to 80%
tUD_DISPERSION
ps
tR
ps
tF
Fall time
80% to 20%
ps
fTOGGLE
TR
Input toggle frequency
Toggle Rate
VIN = 200 mVPP Sine Wave, 50% Output swing
VIN = 200 mVPP Sine Wave, 50% Output swing
GHz
Gbps
3.0
Minimum allowed input pulse
width
VOVERDRIVE = VUNDERDRIVE = 50mV
PWOUT = 90% of PWIN
PulseWidth
600
ps
Latching/Adjustable Hysteresis (TLV3605 only)
VHYST
VHYST
Input hysteresis voltage
Input hysteresis voltage
RHYST = Floating
RHYST = 150 kΩ
0
mV
mV
30
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6.5 Electrical Characteristics (VCCI = VCCO = 2.5 V to 5 V) (continued)
VCCI = VCCO = 2.5 to 5 V, VEE = 0 V, VCM = VEE + 300 mV, RLOAD = 100 Ω, CL = 1 pF probe capacitance, typical at TA = 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VHYST
VIH_LE
Input hysteresis voltage
RHYST = 56 kΩ
60
mV
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
LE pin input high level
1.5
V
V
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
VIL_LE
IIH_LE
IIL_LE
LE pin input low level
0.35
3.5
40
VLE = VCCO
TA = –40℃ to +125℃
LE pin input leakage current
LE pin input leakage current
uA
uA
VLE = VEE
,
TA = –40℃ to +125℃
tSETUP
tHOLD
tPL
Latch setup time
–3
6
ns
ns
ns
Latch hold time
Latch to Q and Q delay
4
Shutdown Characteristics (TLV3605 only)
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
VIH_SD
VIL_SD
SHDN pin input high level
SHDN pin input low level
1.5
V
V
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
0.4
2
VCCI = VCCO = 2.5 V and 5 V
IIH_SD
SHDN pin input leakage current VSD = VCCO
,
uA
uA
TA = –40℃ to +125℃
VCCI = VCCO = 2.5 V and 5 V
IIL_SD
SHDN pin input leakage current VSD = VEE
,
30
TA = –40℃ to +125℃
Input stage quiescent current in
Shutdown mode
VCCI = VCCO = 2.5 V and 5 V
TA = –40℃ to +125℃
ICCI_SD
ICCO_SD
tSLEEP
1.5
mA
uA
ns
Output stage quiescent current in VCCI = VCCO = 2.5 V and 5 V
Shutdown mode
100
TA = –40℃ to +125℃
Sleep time from Active to
Shutdown mode
10% output swing
8
Wake up time from Shutdown
mode
tWAKEUP
VOD = 50 mV, output valid
100
ns
(1) For TLV3605, the VIO is tested with RHYST = 150 KΩ
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6.6 Typical Characteristics
At TA = 25°C, VCCI/VCCO = 2.5 V to 5.0 V, VCM = 0.3V, and input overdrive/underdrive = 50 mV unless otherwise noted.
13
12.8
12.6
12.4
12.2
12
3
2
1
0
-1
-2
-3
VCC = 2.5V
VCC = 3.3V
VCC = 5.0V
11.8
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-0.5
0
0.5
1
1.5
2
2.5
3
VCM (V)
Figure 6-1. IQ vs Temperature
Figure 6-2. VOS vs VCM @ VCC =2.5V - 50 Devices
3
2
3
2
1
1
0
0
-1
-2
-3
-1
-2
-3
-0.5
0
0.5
1
1.5 2
VCM (V)
2.5
3
3.5
4
-0.5
0.5
1.5
2.5
VCM (V)
3.5
4.5
5.5
Figure 6-3. VOS vs VCM @ VCC =3.3V - 50 Devices
-0.6
Figure 6-4. VOS vs VCM @ VCC =5.0V - 50 Devices
3
VCC = 2.5V
VCC = 3.3V
VCC = 5.0V
-0.7
-0.8
-0.9
-1
2
1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
0
-1
-2
-3
-40°C
25°C
85°C
125°C
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-0.5
0
0.5
1
1.5
2
2.5
3
VCM (V)
Figure 6-5. Bias Current vs Temperature
Figure 6-6. Input Bias Current vs VCM @ VCC = 2.5V
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6.6 Typical Characteristics (continued)
At TA = 25°C, VCCI/VCCO = 2.5 V to 5.0 V, VCM = 0.3V, and input overdrive/underdrive = 50 mV unless otherwise noted.
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
-0.5
0
0.5
1
1.5 2
VCM (V)
2.5
3
3.5
4
-0.5
0
0.5
1
1.5
2
2.5
VCM (V)
3
3.5
4
4.5
5
5.5
Figure 6-7. Input Bias Current vs VCM @ VCC = 3.3V
Figure 6-8. Input Bias Current vs VCM @ VCC = 5.0V
1.7
1.7
1.65
1.6
VCC = 2.5V
VCC = 3.3V
VCC = 5.0V
1.65
1.6
1.55
1.5
1.55
1.5
1.45
1.4
1.45
1.4
1.35
-40°C
1.3
1.25
1.2
25°C
85°C
125°C
1.35
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
0.25 0.5 0.75
1
1.25 1.5 1.75
VCM (V)
2
2.25 2.5
D001
Figure 6-9. FToggle vs Temperature
Figure 6-10. Ftoggle vs VCM @ VCC = 2.5V
1.75
1.7
1.65
1.6
1.7
1.65
1.6
1.55
1.5
1.55
1.5
1.45
1.4
1.45
1.4
1.35
1.3
-40°C
-40°C
25°C
85°C
125°C
1.35
1.3
25°C
85°C
125°C
1.25
1.2
1.25
0
0.5
1
1.5
VCM (V)
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
VCM (V)
3
3.5
4
4.5
5
Figure 6-11. Ftoggle vs VCM @ VCC = 3.3V
Figure 6-12. Ftoggle vs VCM @ VCC = 5.0V
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6.6 Typical Characteristics (continued)
At TA = 25°C, VCCI/VCCO = 2.5 V to 5.0 V, VCM = 0.3V, and input overdrive/underdrive = 50 mV unless otherwise noted.
Figure 6-13. TPLH vs VCM @ VCC = 2.5V
Figure 6-14. TPLH vs VCM @ VCC = 3.3V
1000
950
900
850
800
750
700
650
600
550
500
-40°C
25°C
85°C
125°C
-0.5
0
0.5
1
1.5
2
2.5
3
VCM (V)
Figure 6-16. TPHL vs VCM @ VCC = 2.5V
Figure 6-15. TPLH vs VCM @ VCC = 5.0V
1000
950
900
850
800
750
700
650
600
550
500
1000
950
900
850
800
750
700
650
600
550
500
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
-0.5
0
0.5
1
1.5
2
2.5
VCM (V)
3
3.5
4
4.5
5
5.5
-0.5
0
0.5
1
1.5 2
VCM (V)
2.5
3
3.5
4
Figure 6-18. TPHL vs VCM @ VCC = 5.0V
Figure 6-17. TPHL vs VCM @ VCC = 3.3V
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6.6 Typical Characteristics (continued)
At TA = 25°C, VCCI/VCCO = 2.5 V to 5.0 V, VCM = 0.3V, and input overdrive/underdrive = 50 mV unless otherwise noted.
Figure 6-19. TPLH vs Input Overdrive @ VCC = 2.5V
Figure 6-20. TPLH vs Input Overdrive @ VCC = 3.3V
Figure 6-21. TPLH vs Input Overdrive @ VCC = 5.0V
Figure 6-22. TPLH vs Input Underdrive @ VCC = 2.5V
Figure 6-23. TPLH vs Input Underdrive @ VCC = 3.3V
Figure 6-24. TPLH vs Input Underdrive @ VCC = 5.0V
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7 Detailed Description
7.1 Overview
The TLV3604 and TLV3605 are 800-ps, high-speed comparators with LVDS outputs and rail-to-rail inputs. These
features, along with an operating voltage range of 2.4 V to 5.5 V and a high toggle frequency of 3 Gbps,
make the TLV3604 and TLV3605 well suited for LIDAR, clock and data recovery applications, and test and
measurement systems.
7.2 Functional Block Diagram
VCCI/VCCO
VCCI
VCCO
LVDS
+
–
+
–
LVDS
SHDN
TLV3604
TLV3605
R
LE/HYS
VEE
VEE
7.3 Feature Description
The TLV3604 and TLV3605 are single channel, high-speed comparators with rail-to-rail inputs and LVDS
outputs. The rail-to-rail input stage is capable of operating up to 200 mV beyond each power supply rail
with minimal input offset. The TLV3605 has similar performance while providing adjustable hysteresis, latching
function, and shutdown mode.
7.4 Device Functional Modes
The TLV3604 has a single functional mode and is operational when the power supply voltage is greater than
the minimum operating voltage. On the other hand, the TLV3605 has an active and shutdown mode. The
TLV3605 is in shutdown mode when the SHDN pin is logic low. To allow for easy interface with 1.8V FPGAs and
CPUs, The SHDN pin is 1.8 V logic compliant and independent of the comparator power supply.
7.4.1 Rail-to-Rail Inputs
The TLV3604 and TLV3605 feature input stages capable of operating 200mV below or above the power supply
rails, allowing for zero cross detection and maximizing input dynamic range. With low input offset voltage, the
comparators improve system performance in high sensitivity signal detection.
7.4.2 LVDS Output
The TLV3604 and TLV3605 output are LVDS compliant. When the input of the downstream device is terminated
with a 100 Ω resistor, it provides a ±350 mV LVDS swing. Fully differential outputs enable fast digital toggling and
reduce EMI compared to single-ended output standards.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV360x comparators feature rail-to-rail inputs and a LVDS output stage that is well-suited for high speed
applications that require low power consumption. The 800 ps propagation delay of the comparators improve
performance and extend the range for applications involving optical reception, triggers for test and measurement
systems, and transceivers that require a high speed signal to be carried over a certain distance.
8.1.1 Comparator Inputs
The TLV360x is a rail-to-rail input comparator, with an input common-mode range that exceeds the supply rails
by 200 mV for both positive and negative supplies.
8.1.2 Capacitive Loads
Under reasonable capacitive loads, the device maintains specified propagation delay. However, excessive
capacitive loading under high switching frequencies may increase supply current, propagation delay, or induce
decreased slew rate.
8.1.3 Latch Functionality
The latch pin for the TLV3605 holds the output state of the device when the voltage at the LE/HYST pin is less
than 800mV above VEE. This is particularly useful when the output state is intended to remain unchanged. An
important consideration of the latch functionality is the latch hold time. Latch hold time is the minimum time (after
the latch pin is asserted) required for properly latching the comparator output.
tSETUP
tHOLD
LE/HYST
Valid Input Transition
Region
Valid Input
Transition Region
Invalid Input
Transition Region
IN
Figure 8-1. Valid Latch Diagram
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Likewise, latch setup time is defined as the time that the input must be stable before the latch pin is asserted
low. The figure above illustrates when the input can transition for a valid latch. Note that the typical setup time in
the EC table is negative; this is due to the internal trace delays of the LE/HYST pin relative to the input pin trace
delays.
A small delay in the output response is shown below when the TLV3605 exits a latched output stage.
LE/HYS
IN
tPL
OUT
Figure 8-2. Latch Disable with Input Change
8.1.4 Adjustable Hysteresis
As a result of a comparator’s high open loop gain, there is a small band of input differential voltage where the
output can toggle back and forth between “logic high” and “logic low” states. This can cause design challenges
for inputs with slow rise and fall times or systems with excessive noise.
These challenges can be overcome by adding hysteresis to the comparator. Since the TLV3604 does not have
internal hysteresis, external hysteresis can be applied in the form of a positive feedback loop that adjusts the
trip point of the comparator depending on its current output state. See the Typical Application section for more
details.
The TLV3605 on the other hand has a LE/HYST pin that can be used to increase the internal hysteresis of the
comparator. In order to change the internal hysteresis of the TLV3605, connect a single resistor as shown in
the adjusting hysteresis figure between the LE/HYST pin and VEE. A curve of hysteresis versus resistance is
provided below to provide guidance in setting the desired amount of hysteresis.
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VCCI VCCO
IN+
IN-
+
OUTP
OUTN
œ
LE/HYS
TLV3605
R
VEE
Figure 8-3. Adjusting Hysteresis with an External Resistor (R)
Figure 8-4. VHYST (mV) vs RHYST (Ω), VCC = 3.3V
8.2 Typical Application
8.2.1 Non-Inverting Comparator With Hysteresis
A way to implement external hysteresis to the TLV3604 is to add two resistors to the circuit: one in series
between the reference voltage and the inverting pin, and another from the inverting pin to one of the differential
output pins.
VCCI/VCCO
VIN
R1
Q
Q
+
–
VEE
+
–
VREF
R2
GND
Figure 8-5. Non-Inverting Comparator with Hysteresis Circuit
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8.2.1.1 Design Requirements
Table 8-1. Design Parameters
PARAMETER
VALUE
VHYS
20mV
5V
VREF
VT1
VT2
Q
3.6V
3.4V
1.375V
1.025V
Q
8.2.1.2 Detailed Design Procedure
First, create an equation for VT that covers both output voltages when the output is high or low.
VT1 = VREFR2 + QR1
R1+R2 R1+R2
(1)
(2)
VT2 = VREFR2 + QR1
R1+R2 R1+R2
The hysteresis voltage in this network is equal to the difference in the two threshold voltage equations.
VHYS = VT1-VT2
(3)
(4)
(5)
(6)
- VREFR2 - QR1
R1+R2 R1+R2
VHYS = VREFR2 + QR1
R1+R2 R1+R2
VHYS = (Q-Q)R1
R1+R2
VHYS = VODR1
R1+R2
Select a value for R2. Plug in given values for VREF, VT1, VT2, Q, and Q, and solve for R1. For the given
example, R2 = 100 kΩ, and R1 is solved as = 67.37 kΩ.
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8.2.1.3 Application Performance Plots
1.4
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
3.35
3.4
3.45
3.5
3.55
3.6
3.65
VIN (V)
Figure 8-6. Hysteresis Curve for LVDS Comparator
8.2.2 Optical Receiver
The TLV360x can be used in conjunction with a high performance amplifier such as the OPA855 to create an
optical receiver as shown in the Figure 8-7. The photo diode is connected to a bias voltage and is being driven
with a pulsed laser. The OPA855 takes the current conducting through the diode and translates it into a voltage
for a high speed comparator to detect. The TLV360x will then output the proper LVDS signal according to the
threshold set (VREF2).
CF
VCCI/VCCO
RF
-
OPA855
+
OUT+
OUT-
TLV360x
-
+
100O
VREF1
VREF2
VBIAS
Figure 8-7. Optical Receiver
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8.2.3 Logic Clock Source to LVDS Transceiver
The Figure 8-8 shows a logic clock source being terminated and driven with the TLV360x across a CAT6 Cable
to receive an equivalent LVDS clock signal at the receiver end.
CLOCK SOURCE
49.9O
49.9O
OUT+
OUT-
+
+
TLV360x
RJ45 CAT6 CABLE RJ45
TLV360x
-
-
VREF
Figure 8-8. LVDS Clock Transceiver
8.2.4 External Trigger Function for Oscilloscopes
Figure 8-9 is a typical configuration for creating an external trigger on oscilliscopes. The user adjusts the trigger
level, and a DAC converts this trigger level to a voltage the TLV360x can use as a reference. The input voltage
from an oscilloscope channel is then compared to the trigger reference voltage, and the TLV360x sends an
LVDS signal to a downstream FPGA to begin a capture.
VCCI/VCCO
+
+
FPGA
TLV360x
-
VIN
œ
100O
DAC
Trigger Input
Figure 8-9. External Trigger Function
9 Power Supply Recommendations
The TLV3604 and TLV3605 are recommended for operation from 2.4 V to 5.5 V. One benefit of the TLV3605
is that the comparator has separate input and output supply pins (VCCI and VCCO). This provides a system
designer the flexibility of powering the input stage with a higher supply voltage such as 5V to maximize the
dynamic range of the input while powering the output stage with a 2.5V supply to save power. Regardless of the
VCCO supply voltage, the control pins such as LE and SHDN are 1.8V logic compliant.
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10 Layout
10.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.
1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding
(use of a ground plane) helps maintain specified device performance and input/output trace impedances.
2. To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) directly
between VCCI/VCCO and VEE.
3. On the inputs and outputs, utilize matched trace lengths to minimize timing skew. Also, minimize
trace lengths and maximize ground pour spacings around the input and output traces to limit parasitic
capacitance.
4. Solder the device directly to the PCB rather than using a socket.
5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes
minimal degradation to propagation delay when source impedance is low.
6. Use a 100 Ω termination resistor across the device's LVDS outputs.
7. Use higher performance substrate materials such as Rogers or High-Speed FR4.
8. PCB signal layers from the TLV3604EVM are shown for reference.
10.2 Layout Example
Figure 10-1 shows the 4 layer PCB signal routing for the TLV3604EVM as an example for how layout on this
device can be done.
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Figure 10-1. TLV3604EVM Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LIDAR Pulsed Time of Flight Reference Design
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV3604DCKR
TLV3604DCKT
TLV3605RVKR
TLV3605RVKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
RVK
RVK
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1HF
1HF
3605
3605
NIPDAU
NIPDAU
NIPDAU
WQFN
WQFN
12
12
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV3604DCKR
TLV3604DCKT
TLV3605RVKR
TLV3605RVKT
SC70
SC70
DCK
DCK
RVK
RVK
6
6
3000
250
180.0
180.0
330.0
180.0
8.4
8.4
2.47
2.47
3.3
2.3
2.3
3.3
3.3
1.25
1.25
1.1
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q2
WQFN
WQFN
12
12
3000
250
12.4
12.4
12.0
12.0
3.3
1.1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV3604DCKR
TLV3604DCKT
TLV3605RVKR
TLV3605RVKT
SC70
SC70
DCK
DCK
RVK
RVK
6
6
3000
250
183.0
183.0
367.0
210.0
183.0
183.0
367.0
185.0
20.0
20.0
35.0
35.0
WQFN
WQFN
12
12
3000
250
Pack Materials-Page 2
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TLV365DBVR
50-MHz single-supply operational amplifier with rail-to-rail input and output | DBV | 5 | -40 to 125
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