TLV3801-Q1 [TI]

具有 LVDS 输出的汽车类 225ps 高速比较器;


型号：	TLV3801-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有 LVDS 输出的汽车类 225ps 高速比较器比较器
文件：	总27页 (文件大小：2642K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV3801-Q1

ZHCSQK0 –OCTOBER 2022

TLV3801-Q1 具有LVDS 输出的225ps 高速比较器

5.25V 的单电源工作电压范围和 2.7V 至 5.25V 的双电

源工作电压范围，采用业界通用的小型封装承载所有特

性，是激光雷达、差分线路接收器应用以及测试和测量

系统的理想选择。

1 特性

• 低传播延迟：225 ps

• 低过驱动分散：5 ps

• 静态电流：20mA

TLV3801-Q1 具有 5ps 的强大输入过驱性能，并且能

够检测仅 240ps 的窄脉冲宽度。这些器件具有输入过

驱可实现较小传播延迟变化，并且能够检测窄脉冲，是

飞行时间 (ToF) 应用（例如工厂自动化和无人机视觉）

的理想选择。

• 高切换频率：3GHz/6Gbps

• 窄脉宽检测功能：240ps

• LVDS 输出

• 分离输入和输出接地基准

• 单电源电压：2.7V 至5.25V

• 低输入失调电压：±0.5mV

• 内部迟滞：2mV

TLV3801-Q1 的低压差分信号 (LVDS) 输出有助于提高

数据吞吐量并优化功耗。同样，互补输出有助于通过抑

制每个输出上的共模噪声来降低EMI。LVDS 输出旨在

驱动和直接连接可接受标准 LVDS 输入（例如大多数

FPGA 和CPU）的其他应用下游器件。

• 封装：TLV3801（8 引脚WSON）

2 应用

• 激光雷达中的距离感测

• 飞行时间传感器

• 示波器和逻辑分析仪中的高速触发器功能

• 高速差分线路接收器

• 无人机视觉

TLV3801-Q1 采用 8 引脚 WSON 封装，因此非常适合

空间敏感型应用，例如光学传感器模块。

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TLV3801-Q1

WSON (8)

2.00mm × 2.00mm

3 说明

TLV3801-Q1 是具有宽电源电压范围和 3GHz 超高切

换频率的 225ps 高速比较器。这些器件具有 2.7V 至

1.如需了解所有可订购封装，请参阅数据表末尾的可订

购产品附录。

VCC

OUT+

OUT-

OPA858

IN+

IN-

TLV3801

LVDS

–

TLV3801

VEE

V_BIAS

V_REF

GND

TLV3801 光学接收器电路

功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNOSDF4

TLV3801-Q1

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Table of Contents

7.3 Feature Description...................................................12

7.4 Device Functional Modes..........................................12

8 Application and Implementation..................................14

8.1 Application Information............................................. 14

8.2 Typical Application.................................................... 14

8.3 Power Supply Recommendations.............................18

8.4 Layout....................................................................... 19

9 Device and Documentation Support............................20

9.1 Device Support......................................................... 20

9.2 接收文档更新通知..................................................... 20

9.3 支持资源....................................................................20

9.4 Trademarks...............................................................20

9.5 Electrostatic Discharge Caution................................20

9.6 术语表....................................................................... 20

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Thermal Information....................................................4

6.4 Recommended Operating Conditions.........................4

6.5 Electrical Characteristics.............................................5

6.6 Timing Diagrams ........................................................7

6.7 Typical Characteristics................................................8

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................12

Information.................................................................... 20

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

October 2022

Initial Release

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5 Pin Configuration and Functions

OUT-

Out+

VCC

IN+

GND

VEE

IN-

Thermal

Pad

图5-1. WSON Package

8-Pin DSG

Top View

Pin Functions

I/O

DESCRIPTION

NAME

IN+

TLV3801

Non-inverting input

Inverting input

IN–

OUT+

OUT–

Non-inverting output

Inverting output

Negative power supply

V_EE

(If using single supply, connect to GND)

Positive power supply

Ground

V_CC

6, 7

GND

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

5.5

UNIT

Supply voltage: (V_CC–V_EE) and (V_CC–GND) ⁽²⁾

(3)

V_CC+ 0.3

Input pins (IN+, IN–) from V_EE

_EE–0.3

–10

Current into input pins (IN+, IN–)

Output (OUT+, OUT–)

GND

V_CC

+0.5

OUT+ to OUT–

–0.5

°C

Current into output pins (OUT+, OUT–)

Junction temperature, T_J

150

Storage temperature, T_stg

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) VEE less than or equal to GND

(3) Input terminals are diode-clamped to V_EEand V_CC

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), , per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-0111

Electrostatic

discharge

V_(ESD)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Thermal Information

TLV3801-Q1

THERMAL METRIC⁽¹⁾

DSG (WSON)

8-pin

UNIT

R_qJA

Junction-to-ambient thermal resistance

69.4

°C/W

R_qJC(top)

R_qJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

95.7

36.2

3.5

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

y_JB

36.0

9.4

R_qJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

MAX

5.25

UNIT

Single supply operation: V_CC–V_EEwith V_EE= GND

Split supply operation: V_CC–V_EEwith V_EE< GND

Split supply operation: V_CC–GND with V_EE< GND

Input voltage range

2.7

5.25

2.4

5.25

V_EE+ 1.5

–1.5

–40

V_CC+ 0.1

+1.5

Differential Input voltage range

Ambient temperature, T_A

125

°C

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6.5 Electrical Characteristics

For V_CC= 3.3 V, V_EE= GND = 0, V_CM= 2.5 V at T_A= 25°C (Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC Input Characteristics

Input offset

voltage

–5⁽¹⁾

V_OS

±0.5

+5⁽¹⁾

T_A= –40°C to +125°C

Input hysteresis

voltage

V_HYS

Single Supply: V_EE= GND

V_CC–V_EE= 2.7 V to 5.25 V

T_A= –40 °C to +125°C

Common-mode

voltage range

V_CM-Range

V_EE+ 1.5

V_CC

Split Supply: V_EE< GND

V_CC–V_EE= 2.7 V to 5.25 V and V_CC–GND

= 2.4 V to 5.25 V

Common-mode

voltage range

V_CM-Range

V_CC

T_A= –40 °C to +125°C

Common mode

rejection ratio

CMRR

PSRR

V_CM= V_EE+ 1.5V to V_CC

Single Supply: V_EE= GND

V_CC–V_EE= 2.7 V to 5.25 V

Power supply

rejection ratio

Split Supply: V_EE< GND

V_CC–V_EE= 2.7 V to 5.25 V and V_CC–GND

= 2.4 V to 5.25 V

Power supply

rejection ratio

PSRR

I_B

Input bias current

±1

µA

T_A= –40 °C to +125 °C

–10

–4

Input offset

current

I_OS

±0.1

Input capacitance,

common mode

C_IC

DC Output Characteristics

Output common

mode voltage

V_CC- GND ≥2.6 V

T_A= –40℃to +125℃

1.125

0.92

1.25

1.2

1.375

1.29

V_OCM

V_CC- GND < 2.6 V

T_A= –40℃to +125℃

Output common

mode voltage

Output common

mode voltage

mismatch

ΔV_OCM

T_A= –40℃to +125℃

–30

Peak-to-Peak

output common

mode voltage

V_{OCM_PP}

mVpp

Differential output

voltage

V_OD

250

350

450

T_A= –40℃to +125℃

Differential output

voltage mismatch

ΔV_OD

Power Supply

Quiescent current

per comparator

I_Q

26.6

T_A= –40°C to +125°C

AC Characteristics

t_PDPropagation delay

V_OVERDRIVE= 50 mV, V_UNDERDRIVE= 50 mV, 50

MHz Squarewave

225

Temperature

Tempco of t_PDCoefficient of

propagation delay

±0.2

ps/℃

Propagation delay V_OVERDRIVE= 50mV, V_UNDERDRIVE= 50 mV, 50

t_{PD_SKEW}

±2.5

skew

MHz Squarewave

Common mode

dispersion

t_{CM_DISPERSION}

V_CMvaried from V_CM(min) to V_CM(max)

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6.5 Electrical Characteristics (continued)

For V_CC= 3.3 V, V_EE= GND = 0, V_CM= 2.5 V at T_A= 25°C (Unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Overdrive

dispersion

t_{OD_DISPERSION}

Overdrive varied from 20 mV to 100 mV

Overdrive

dispersion

t_{OD_DISPERSION}

t_{UD_DISPERSION}

Overdrive varied from 10 mV to 1 V

Overdrive varied from 20 mV to 100 mV

Overdrive varied from 10 mV to 1 V

Underdrive

dispersion

Underdrive

dispersion

t_R

t_F

Rise time

Fall time

20% to 80%

80% to 20%

135

Input toggle

frequency

f_TOGGLE

V_IN= 200 mV_PPSine Wave, V_OD= 550 mV

V_IN= 200 mV_PPSine Wave, 50% Output swing

2.3

GHz

Input toggle

frequency

Toggle Rate

V_IN= 200 mV_PPSine Wave, V_OD= 550 mV

V_IN= 200 mV_PPSine Wave, 50% Output swing

4.6

Gbps

Minimum allowed V_OVERDRIVE= V_UNDERDRIVE= 50mV

input pulse width PW_OUT= 90% of PW_IN

PulseWidth

240

(1) Ensured by charaterization

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6.6 Timing Diagrams

V_OVERDRIVE

V_UNDERDRIVE

IN-

V_UNDERDRIVE

V_OVERDRIVE

IN+

t_PLH

t_PHL

t_R

t_F

80%

20%

1.25V

V_OUT+

V_OUT-

1.25V

t_PHL

t_PLH

t_PLHD

t_PHLD

V_OD

图6-1. General Timing Diagram

_OD= 100mV

_OD= 20mV

IN-

IN+

DISPERSION

V_OD

图6-2. Overdrive Dispersion

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6.7 Typical Characteristics

At T_A= 25°C, V_CC- V_EE= 3.3 V to 5 V while V_EE= GND = 0, V_CM= 2.5 V, and input overdrive/underdrive = 50 mV, unless

otherwise noted.

1.5

2.4

2.3

2.2

2.1

0.5

1.9

1.8

1.7

1.6

-0.5

-1

For 33 units

-1.5

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (C)

图6-3. Offset vs. Temperature

图6-4. Hysteresis vs. Temperature

1.8

1.4

2.4

2.3

2.2

2.1

0.6

0.2

-0.2

-0.6

-1

1.9

1.8

1.7

1.6

-40C

25C

85C

125C

-1.4

-1.8

For 33 units

3 3.3

1.5

1.8

2.1

2.4

2.7

3.3

1.5

1.8

2.1

2.4

2.7

Input Common-Mode Voltage (V)

图6-6. Hysteresis vs. Common-Mode, 3.3 V

图6-5. Offset vs. Common-Mode, 3.3 V

1.8

1.4

2.4

2.3

2.2

2.1

0.6

0.2

-0.2

-0.6

-1

1.9

1.8

1.7

1.6

-40C

25C

85C

125C

-1.4

-1.8

For 33 units

4.5 5

1.5

2.5

3.5

4.5

1.5

2.5

3.5

Input Common-Mode Voltage (V)

图6-8. Hysteresis vs. Common-Mode, 5 V

图6-7. Offset vs. Common-Mode, 5 V

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6.7 Typical Characteristics (continued)

At T_A= 25°C, V_CC- V_EE= 3.3 V to 5 V while V_EE= GND = 0, V_CM= 2.5 V, and input overdrive/underdrive = 50 mV, unless

otherwise noted.

21.6

21.2

20.8

20.4

21.6

21.2

20.8

20.4

19.6

19.2

18.8

18.4

19.6

19.2

18.8

18.4

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (C)

图6-9. Supply Current vs. Temperature, Output Low

图6-10. Supply Current vs. Temperature, Output High

-1

-2

-3

-4

-5

-40C

25C

85C

125C

-40C

-3

-4

-5

25C

85C

125C

1.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

1.5 1.8 2.1 2.4 2.7

3.3 3.6 3.9 4.2 4.5 4.8 5

Input Common-Mode Voltage (V)

图6-11. Bias Current vs. Common-Mode, 3.3 V

图6-12. Bias Current vs. Common-Mode, 5 V

250

245

240

235

230

225

220

215

210

205

200

260

255

250

245

240

235

230

225

220

215

210

-40C

25C

85C

125C

25C

85C

125C

1.5

1.8

2.1

2.4

2.7

3.3

1.5

2.5

3.5

4.5

Input Common-Mode Voltage (V)

图6-13. Propagation Delay vs. Common-Mode, 3.3 V

图6-14. Propagation Delay vs. Common-Mode, 5 V

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6.7 Typical Characteristics (continued)

At T_A= 25°C, V_CC- V_EE= 3.3 V to 5 V while V_EE= GND = 0, V_CM= 2.5 V, and input overdrive/underdrive = 50 mV, unless

otherwise noted.

250

245

240

235

230

225

220

215

210

205

200

250

245

240

235

230

225

220

215

210

205

200

-40C

25C

85C

125C

-40C

25C

85C

125C

20 30 40 50 70 100

200 300 500 7001,000

20 30 40 50 70 100

200 300 500 7001,000

Input Overdrive (mV)

Input Underdrive (mV)

图6-16. Propagation Delay vs. Underdrive, 3.3 V

265

图6-15. Propagation Delay vs. Overdrive, 3.3 V

265

260

255

250

245

240

235

230

225

220

215

210

-40C

25C

85C

125C

260

255

250

245

240

235

230

225

220

215

210

25C

85C

125C

20 30 40 50 70 100

200 300 500 7001,000

20 30 40 50 70 100

200 300 500 7001,000

Input Overdrive (mV)

Input Underdrive (mV)

图6-17. Propagation Delay vs. Overdrive, 5 V

图6-18. Propagation Delay vs. Underdrive, 5 V

-5

-10

-15

-20

-25

-10

-15

-20

-25

-40C

25C

85C

125C Referred to 10mV V_OD

20 30 40 50 70 100

200 300 500 7001,000

20 30 40 50 70 100

200 300 500 7001,000

Overdrive Voltage (mV)

图6-19. Dispersion vs. Overdrive, 3.3 V

图6-20. Dispersion vs. Overdrive, 5 V

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6.7 Typical Characteristics (continued)

At T_A= 25°C, V_CC- V_EE= 3.3 V to 5 V while V_EE= GND = 0, V_CM= 2.5 V, and input overdrive/underdrive = 50 mV, unless

otherwise noted.

400

375

350

325

300

275

250

225

200

175

150

400

375

350

325

300

275

250

225

200

175

150

-40C

25C

85C

125C

-40C

25C

85C

125C

1.5

1.8

2.1

2.4

2.7

3.3

1.5

2.5

3.5

4.5

Input Common-Mode Voltage (V)

图6-21. Minimum Pulse Width vs. Common-Mode, 3.3 V

图6-22. Minimum Pulse Width vs. Common-Mode, 5 V

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7 Detailed Description

7.1 Overview

The TLV3801-Q1 is a high-speed comparator with LVDS output. The fast response time of these comparators

make them well suited for applications that require narrow pulse width detection or high toggle frequencies. The

TLV3801-Q1 is available in the 8-pin DSG package.

7.2 Functional Block Diagram

VCC

OUT+

OUT-

IN+

IN-

LVDS

–

TLV3801

VEE

GND

7.3 Feature Description

The TLV3801-Q1 is a single channel, high-speed comparator with a typical propagation delay of 225 ps and

LVDS output. The minimum pulse width detection capability is 240 ps and the typical toggle frequency is 3 GHz

(6 Gbps). These comparators are well suited for distance sensing for LIDAR and time-of-flight applications as

well as for high-speed test and measurement systems. The TLV3801-Q1 has two separate power rails for the

input and the output; this allows the input to be referenced from either single or split supply (VCC and VEE) while

the output is referenced from ground (VCC and GND).

7.4 Device Functional Modes

The TLV3801-Q1 has a single functional mode and is operational on the condition that both the input supply

voltage (VCC - VEE) is greater than or equal to 2.7 V and the output supply voltage (VCC - GND) is greater than

or equal to 2.4 V.

7.4.1 Inputs

The TLV3801-Q1 features an input stage, capable of operating between 1.5 V above VEE and 0.1 V above

VCC, with an internal ESD protection circuit that includes two pairs of front-to-back diodes between IN+ and IN-

as well as two 50 Ω resistors, as shown in 图 7-1. This prevents damage to the input stage by limiting the

differential input voltage to be no more than twice the diode's forward-voltage drop 2 × V_F(2 × 0.7 V).

50 Ω

IN+

INTERNAL

CIRCUITRY

50 Ω

IN-

图7-1. Input Stage Circuitry

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When the differential input voltage exceeds 2 × V_F, the input bias current increases at the input pins IN+ and IN-,

as shown in 方程式1.

Input Current = [(V_IN+- V_IN-) - 2 × V_F] / (2 × 50)

(1)

To avoid damaging the inputs when exceeding the recommended input voltage range, an external resistor

should be used to limit the current. The current should be limited to less than 10 mA.

7.4.2 LVDS Output

The TLV3801-Q1 outputs are LVDS compliant. When the input of the downstream device is terminated with a

100 Ω resistor, the comparators provide a ±350 mV differential swing at an output common-mode voltage of

1.25 V above GND. Fully differential outputs enable fast digital toggling and reduce EMI compared to single-

ended output standards.

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 Capacitive Loads

Under reasonable capacitive loads, the device maintains specified propagation delay. However, excessive

capacitive loading under high switching frequencies may increase supply current, propagation delay, or induce

decreased slew rate.

8.1.2 Hysteresis

As a result of a comparator's high open loop gain, there is a small band of input differential voltage where the

comparator may produce "chatter" which causes the output to toggle back and forth between a “logic high”

and a “logic low”. This can cause design challenges for inputs with slow rise and fall times or systems with

excessive noise. These challenges can be prevented by adding external hysteresis to the comparator.

Since the TLV3801-Q1 only have a minimal amount of internal hysteresis, external hysteresis can be applied in

the form of a positive feedback loop that adjusts the trip point of the comparator depending on its current output

state. See the Non-Inverting Comparator With Hysteresis section for more details.

8.2 Typical Application

8.2.1 Optical Receiver

The TLV3801-Q1 can be used in conjunction with a high performance amplifier such as the OPA858 to create an

optical receiver as shown in the 图8-1. The photodiode operates in photoconductive mode: exposure to light will

cause a reverse current through the photodiode. A bias voltage is applied to the op amp's non-inverting input to

prevent saturation at the negative power supply. The OPA858 takes the current conducting through the diode

and translates it into a voltage for a high speed comparator to detect. The TLV3801-Q1 will then output the

proper LVDS signal according to the threshold set (V_REF).

C_F

R_F

V_CC

V_OUT

OPA858

OUT+

TLV3801

OUT-

100

V_BIAS

V_REF

图8-1. Optical Receiver

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8.2.1.1 Design Requirements

表8-1. Design Parameters

PARAMETER

VALUE

V_CC

V_EE

+5 V

0 V

V_{OUT, SWING}

100 mV

100 µA

159 MHz

I_DIODE

f_p

8.2.1.2 Detailed Design Procedure

Set V_BIASto be in the recommended common-mode voltage range of the OPA858. This is also the minimum

output voltage of the op amp V_{OUT, MIN}as the op amp will attempt to settle at the voltage applied to the non-

inverting input.

The maximum output voltage of the op amp V_{OUT, MAX}can be calculated from the desired output voltage swing

V_{OUT, SWING}and V_{OUT, MIN}, as shown in 方程式2.

V_{OUT, MAX}= V_{OUT, SWING}+ V_{OUT, MIN}

(2)

The gain resistor R_Fis determined by the desired V_{OUT, MAX}and V_{OUT, MIN}and the maximum current I_DIODE

through the diode, as shown in 方程式2.

R_F= (V_{OUT, MAX}- V_{OUT, MIN}) / I_DIODE

(3)

The feedback capacitor, in combinaton with the gain resistor, forms a pole in the frequency response of the

amplifier. The feedback capacitor can be determined by the gain resistor and the desired pole frequency f_p, as

shown in 方程式2.

C_F= 1 / (2 × π× R_Fx f_p)

(4)

Set V_REFto be the switching threshold voltage between V_{OUT, MAX}and V_{OUT, MIN}

Select values for V_BIASand V_REF. Plug in given values for V_{OUT, MAX,}I_DIODE, and f_p. For the given example, V_BIAS

= 1.5 V, V_REF= 1.55 V, and R_F,C_Fis solved as 1 kΩand 1 pF, respectively.

For more information, please refer to the op amp tutorials for stability analysis on the transimpedance amplifier

Spice Stability Analysis and Op Amp Stability. See application note SBOA268A Transimpedance Amplifier

Circuit for more detailed procedures.

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8.2.1.3 Application Performance Plots

图8-2.

8.2.2 Non-Inverting Comparator With Hysteresis

A way to implement external hysteresis to the TLV3801-Q1 is to add two resistors to the circuit: one in series

between the reference voltage and the inverting pin, and another from the inverting pin to one of the differential

output pins.

V_CC

V_IN

–

V_REF

图8-3. Non-Inverting Comparator with Hysteresis Circuit

8.2.2.1 Design Requirements

表8-2. Design Parameters

PARAMETER

VALUE

V_HYS

V_REF

V_T1

V_T2

50 mV

2.5 V

2.34 V

2.29 V

1.425 V

1.075 V

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8.2.2.2 Detailed Design Procedure

First, create an equation for V_Tthat covers both output voltages when the output is high or low.

V_T1= V_REFR₂+ QR₁

R₁+R₂R₁+R₂

(5)

(6)

V_T2= V_REFR₂+ QR₁

R₁+R₂R₁+R₂

The hysteresis voltage in this network is equal to the difference in the two threshold voltage equations.

V_HYS= V_T1-V_T2

(7)

(8)

- V_REFR₂- QR₁

R₁+R₂R₁+R₂

V_HYS= V_REFR₂+ QR₁

R₁+R₂R₁+R₂

V_HYS= (Q-Q)R₁

R₁+R₂

(9)

V_HYS= V_ODR₁

R₁+R₂

(10)

Note that these equations do not take into account the effects of the internal hysteresis and offset voltage of the

comparator. Design parameters will need to be adjusted accordingly.

Select a value for R2. Plug in given values for V_REF, V_T1, V_T2, Q, and Q, and solve for R1. For the given

example, R2 = 50 kΩ, and R1 is solved as = 8.33 kΩ.

8.2.2.3 Application Performance Plots

图8-4. Hysteresis Curve for LVDS Comparator

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8.2.3 Logic Clock Source to LVDS Transceiver

The 图 8-5 shows a logic clock source being terminated and driven with the TLV3801-Q1 across a CAT6 Cable

to receive an equivalent LVDS clock signal at the receiver end.

CLOCK SOURCE

OUT+

OUT-

TLV3801

RJ45 CAT6 CABLE RJ45

TLV3801

V_REF

图8-5. LVDS Clock Transceiver

8.2.4 External Trigger Function for Oscilloscopes

图 8-6 is a typical configuration for creating an external trigger on oscilliscopes. The user adjusts the trigger

level, and a DAC converts this trigger level to a voltage the TLV3801-Q1 can use as a reference. The input

voltage from an oscilloscope channel is then compared to the trigger reference voltage, and the TLV3801-Q1

sends an LVDS signal to a downstream FPGA to begin a capture. It is common to see bipolar inputs in test and

measurement systems such as oscilloscopes; therefore, the TLV3801-Q1 can be configured in split supply so

that the inputs are in the allowable input voltage range.

V_CC= +2.5V

External

Trigger

Amplifier/

Attenuation

Trigger Input

FPGA

TLV3801

GND

V_EE= -2.5V

DAC

图8-6. External Trigger Function

8.3 Power Supply Recommendations

The TLV3801-Q1 has two seperate power rails: VCC - VEE for the input stage and VCC - GND for the output

stage. This allows for both single and split supply capabilities for the input stage with a seperate ground

reference for the LVDS output stage. Split supply operation allows users to apply both positive and negative

(bipolar) voltages to the input pins.

When operating from a single supply, the supply voltage range for both the input and output stage is 2.7 V to

5.25 V. When operating from split supply rails, the supply voltage range for the input stage (VCC - VEE) is 2.7 V

to 5.25 V, and the supply voltage range for the output stage (VCC - GND) is 2.4 V to 5.25 V. The output logic

level is independent of the VCC and VEE levels.

Regardless of single supply or split supply operation, proper decoupling capacitors are required. It is

recommended to use a scheme of multiple, low-ESR ceramic capacitors from the supply pins to the ground

plane for optimum performance. A good combination would be 100 pF, 10 nF, and 1 uF with the lowest value

capacitor closest to the comparator.

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8.4 Layout

8.4.1 Layout Guidelines

Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.

1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding

(use of a ground plane) helps maintain specified device performance.

2. To minimize supply noise for single and split supply, place decoupling capacitor arrays as close as possible

to V_CC

3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback

around the comparator. Keep inputs away from the output.

4. Solder the device directly to the PCB rather than using a socket.

5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)

placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes

some degradation to propagation delay when impedance is low. The topside ground plane runs between the

output and inputs.

6. Use a 100 Ωtermination resistor across the device's LVDS output.

7. Use higher performance substrate materials such as Rogers.

8.4.2 Layout Example

VEE GND

IN-

OUT-

OUT+

IN+

VCC

C₁

图8-7. TLV3801EVM Layout Example

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

LIDAR Pulsed Time of Flight Reference Design

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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15-Oct-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV3801QDSGRQ1

ACTIVE

WSON

DSG

3000 RoHS & Green

Level-2-260C-1 YEAR

-40 to 125

380Q

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV3801-Q1 :

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

15-Oct-2022

Catalog : TLV3801

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

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PACKAGE OUTLINE

DSG0008B

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

0.1 MIN

(0.05)

PIN 1 INDEX AREA

2.1

1.9

SECTION A-A

TYPICAL

0.3

0.2

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

0.9 0.1

6X 0.5

1.5

1.6 0.1

0.3

0.2

0.4

0.2

PIN 1 ID

0.1

0.05

C A B

4222124/E 05/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DSG0008B

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

8X (0.25)

(0.55)

SYMM

(1.6)

6X (0.5)

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222124/E 05/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DSG0008B

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

SYMM

8X (0.25)

(0.45)

SYMM

(0.7)

6X (0.5)

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4222124/E 05/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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