TLV4011QDCKRQ1 [TI]
具有集成基准的汽车类小型比较器 | DCK | 5 | -40 to 125;
| 型号： | TLV4011QDCKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成基准的汽车类小型比较器 | DCK | 5 | -40 to 125 比较器 |
| 文件： | 总23页 (文件大小：1371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV4011-Q1
ZHCSR70 –SEPTEMBER 2020
TLV4011-Q1 具有精密基准的低功耗比较器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
TLV4011-Q1 是一款具有精密集成基准的低功耗、高精
度比较器。可通过将两个外部电阻器连接到输入端，实
现低至1.226V 的可调电压阈值。
– 器件温度等级1：-40°C 至125°C 的环境工作温
度范围
– 器件HBM ESD 分级等级H1C
– 器件CDM ESD 分类等级C6
• 低至1.226V 的可调节阈值
• ±1.5% 阈值电压精度
• 电源电流：3μA
• 开漏输出
• 温度范围：–40°C 至125°C
• 5 引脚SC-70 封装
经过工厂校准的开关阈值和精密迟滞相结合，使得
TLV4011-Q1 非常适合在必须将慢速输入信号转换为纯
净数字输出的严苛、嘈杂环境中进行电压和电流监测。
同样地，输入端的短时毛刺脉冲也得以抑制，因此可确
保稳定的输出运行，不会引起误触发。
上电期间，当电源电压 VDD 大于 0.8V 时，RESET 有
效运行（低电平）。因此，TLV4011-Q1 会监测输入并
使RESET 运行（低电平），同时输入仍保持在阈值电
压 VIT 以下。一旦输入电压升至阈值电压 VIT 以上，
RESET 则不再运行（高电平）。该产品系列专为
1.8V、3.3V、5V 和可调电源电压而设计。
2 应用
• 紧急呼叫(eCall)
• 远程信息处理控制单元
• 车载充电器(OBC) 和无线充电器
• 直流/直流转换器
TLV4011-Q1 采用 5 引脚 SC-70 封装，工作温度范围
为-40°C 至125°C。
器件信息(1)
• 电池管理系统(BMS)
封装尺寸（标称值）
器件型号
TLV4011-Q1
封装
SC-70 (5)
2.00mm × 1.25mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
Vcar_battery
3.3 V
RPU
V+
VDD
R1
SENSE
+
ALERT
œ
RESET
1.226
R2
Micro-controller
TLV4011-Q1
GND
典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBT9
TLV4011-Q1
ZHCSR70 –SEPTEMBER 2020
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Table of Contents
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................9
8 Application and Implementation..................................10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................12
10 Layout...........................................................................13
10.1 Layout Guidelines................................................... 13
10.2 Layout Examples.................................................... 13
11 Device and Documentation Support..........................14
11.1 接收文档更新通知................................................... 14
11.2 支持资源..................................................................14
11.3 Trademarks............................................................. 14
11.4 静电放电警告...........................................................14
11.5 术语表..................................................................... 14
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................5
6.7 Switching Characteristics............................................5
6.8 Dissipation Ratings..................................................... 5
6.9 Timing Diagrams ........................................................6
6.10 Typical Characteristics..............................................7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
Information.................................................................... 15
4 Revision History
DATE
REVISION
NOTES
September 2020
*
Initial release
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5 Pin Configuration and Functions
NC
1
2
5
4
SENSE
GND
3
RESET
VDD
图5-1. DCK Package, 5-Pin SC-70, Top View
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
2
GND
I
O
I
Ground
RESET
SENSE
NC
3
Active-low reset output (open-drain)
Input
5
1
No internal connection
Input supply voltage
—
VDD
4
I
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
7
UNIT
V
VDD
Supply voltage(2)
Voltage applied to all other pins(2)
Maximum low-level output current
Maximum high-level output current
Input clamp current
7
V
IOL
IOH
IIK
5
mA
mA
mA
mA
–5
±10
±10
VI < 0 or VI > VDD
VO < 0 or VO > VDD
IOK
PD
Output clamp current
Continuous total power dissipation
See 节6.8
TA
Operating free-air temperature
125
260
150
°C
°C
°C
–40
–65
Tsolder Soldering temperature
Tstg Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation, the device should not be continuously operated at 7 V for more than
t = 1000 h.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX UNIT
VDD
VI
Supply voltage
1.3
0
6
VDD + 0.3
125
V
V
Input voltage
TA
Operating free-air temperature
°C
–40
6.4 Thermal Information
TLV4011-Q1
DCK (SC-70)
5 PINS
246.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
68.2
78.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJT
77.7
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
VDD = 1.5 V, IOL = 1 mA
VDD = 3.3 V, IOL = 2 mA
VDD = 6 V, IOL = 3 mA
VOL
Low-level output voltage
0.3
V
V
VOL(max) = 0.2 V, IOL = 50 μA, TA
25°C
=
VPOR Power-up reset voltage(1)
Negative-going input
0.8
VIT
SENSE
1.2 1.226 1.244
15
V
threshold voltage(2)
Vhys
II
Hysteresis
TA = 25°C
mV
Input current
SENSE
RESET
25 nA
–25
High-level output
current at RESET
IOH
SENSE = VIT + 0.2 V, VOH = VDD
300 nA
VDD = 3.3 V, Output unconnected
VDD = 6 V, Output unconnected
VI = 0 V to VDD
2
2
1
4
IDD
CI
Supply current
μA
4
Input capacitance
pF
(1) The lowest supply voltage at which RESET (VOL(max) = 0.2 V, IOL = 50 μA) becomes active. tr(VDD) ≥15 μs/V.
(2) To ensure the best stability of the threshold voltage, place a bypass capacitor (ceramic, 0.1-μF) near the supply terminals.
6.6 Timing Requirements
RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C (unless otherwise noted)
MIN
MAX UNIT
tw
Pulse duration
SENSE
VIH = 1.05 × VIT, VIL = 0.95 × VIT
5.5
μs
6.7 Switching Characteristics
RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Propagation (delay) time,
high-to-low-level output
tPHL
tPLH
SENSE to RESET delay
SENSE to RESET delay
VIH = 1.05 × VIT, VIL = 0.95 × VIT
VIH = 1.05 × VIT, VIL = 0.95 × VIT
5
5
100
100
μs
μs
Propagation (delay) time,
low-to-high-level output
6.8 Dissipation Ratings
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
PACKAGE
TA < 25°C
DCK
321 mW
2.6 mW/°C
206 mW
167 mW
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6.9 Timing Diagrams
V
DD
or SENSE
V
IT
+ V
hys
V
IT
0.8 V
RESET
= Undefined
图6-1. Timing Requirements
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6.10 Typical Characteristics
1.60
1.40
1.20
3
2.5
2
V
V
= 1.5 V
DD
= Low
(SENSE)
85°C
1.00
0.80
0.60
25°C
0°C
1.5
1
85°C
25°C
-40
°
C
0°C
0.40
0.20
0
-40 °C
0.5
0
SENSE = GND
RESET = Open
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
IOL – Low-Level Output Current – mA
VDD – Supply Voltage – V
图6-3. Low-Level Output Voltage vs Low-Level
图6-2. Supply Current vs Supply Voltage
Output Current
3.5
0.50
(Expanded View)
V
V
= 1.5 V
V
V
= 6 V
DD
DD
0.45
= Low
= Low
(SENSE)
3
(SENSE)
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
85°C
85°C
25°C
0°C
2.5
2
25°C
0°C
-40 °C
-40 °C
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50
IOL – Low-Level Output Current – mA
0
0.5
1
1.5
2
2.5
3
IOL – Low-Level Output Current – mA
图6-4. Low-Level Output Voltage vs Low-Level
图6-5. Low-Level Output Voltage vs Low-Level
Output Current
Output Current
1
1.0020
V
V
= 6 V
DD
0.9
0.8
0.7
0.6
= Low
(SENSE)
V
= 6 V
DD
1.0015
1.0010
RESET = 100 kW to V
DD
85°C
25°C
0°C
1.0005
1.0000
-40 °C
0.5
0.4
0.3
0.9995
0.9990
0.2
(Expanded View)
0.1
0
0.9985
0.9980
0
2
4
6
8
10 12 14 16 18 20
-40
-20
0
20
40
60
80
IOL – Low-Level Output Current – mA
TA – Free-Air Temperature at SENSE – °C
图6-6. Low-Level Output Voltage vs Low-Level
图6-7. Normalized Input Threshold Voltage vs
Output Current
Free-Air Temperature At Sense
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7 Detailed Description
7.1 Overview
The TLV4011-Q1 is a low-current comparator used to monitor system voltages above 1.226 V. The comparators
assert an active low RESET signal when the SENSE voltages drop below VIT. The RESET output remains low
until the SENSE voltage returns above VIT plus the integrated hysteresis level. The TLV4011-Q1 is also
designed to be immune to short negative transients on the SENSE pin.
7.2 Functional Block Diagram
VPU
VDD
+
t
SENSE
RESET
1.226V
7.3 Feature Description
7.3.1 SENSE Monitoring
The SENSE input is where a system voltage can be monitored. If the voltage on this pin drops below VIT,
RESET is asserted low. The comparator has a built-in hysteresis to ensure smooth RESET assertions and de-
assertions. By connecting a resistor divider network to the SENSE input as shown in the circuit below, VIN is
divided down so RESET will assert when the divided down value of VIN reaches VIT (1.226 V). The TLV4011-Q1
is capable of monitoring any input voltage down to 1.226 V.
VIN
VDD
Rpu
R1
TLV4011
_____
Reset
SENSE
RESET
R2
GND
图7-1. Voltage Monitor
7.3.2 Transient Immunity
The TLV4011-Q1 is immune to short negative transients on the SENSE pin. Sensitivity to transients is dependent
on threshold overdrive as shown in 图7-2 and 图7-3. These graphs show the duration that the transient is below
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VIT compared to the magnitude of the voltage drop below VIT, called the threshold overdrive voltage. Any
combination of transient duration and overdrive voltage which lies above the curves will result in RESET being
asserted low. Any transient which lies below the curves will be ignored by the device.
VDD or SENSE
VIT
Overdrive
Voltage
Transient
Duration
图7-2. SENSE Overdrive Voltage
10
9
8
7
6
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
SENSE – Threshold Overdrive Voltage – V
1
图7-3. Minimum Pulse Duration at Sense vs Sense Threshold Overdrive Voltage
7.4 Device Functional Modes
The SENSE input is used to monitor one supply. When that supply is above the VIT threshold, RESET will be
high. Otherwise, RESET will be low.
表7-1. Function and Truth
Table
TLV4011-Q1
SENSE > VIT
0 (False)
RESET
L
1 (True)
H
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8 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TLV4011-Q1 comparator is designed to assert an active-low RESET signal when the SENSE input drops
below the voltage threshold VIT. The RESET signal remains low until the voltages return above their respective
threshold plus the hysteresis. If additional hysteresis is required, positive feedback can be implemented similar
to how it is done on a discrete comparator. See Application Note for details on how to implement external
hysteresis in a non-inverting configuration.
8.2 Typical Application
8.2.1 Undervoltage Detection
Undervoltage detection is frequently required in battery-powered, portable electronics to alert the system that a
battery voltage has dropped below the usable voltage level. 图8-1 shows a simple undervoltage detection circuit
using the TLV4011-Q1 which is a non-inverting comparator with an integrated 1.226 V reference and an open-
drain output stage. A non-inverting is well suited for this application since the micro-controller requires an active
low signal when an undervoltage level occurs.
VBAT
3.3V
RPU
R1
VDD
V+
SENSE
+
ALERT
t
RESET
1.226
Micro-
controller
R2
GND
图8-1. Undervoltage Detection
8.2.1.1 Design Requirements
For this design, follow these design requirements:
• TLV4011-Q1 operates from the VBAT directly
• Output is level-shifted to the 3.3 V power supply that powers the microcontroller.
• Undervoltage alert is active low.
• Logic low output when VBAT decreases below 2.0V.
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in 图 8-1. Note that VDD of the comparator is connected directly to VBAT (the
battery being monitored) and the output of the comparator is level shifted with its open-drain ouput to 3.3 V
which powers the micro-controller. Resistors R1 and R2 divide down VBAT so that the resistor divided output
equals 1.226 V when VBAT reaches an undervoltage alert level of 2.0 V.
When the battery voltage sags down to 2.0 V, the resistor divider voltage crosses the (VIT = 1.226 V) threshold of
the TLV4011-Q1. This causes the comparator output to transition from a logic high to a logic low. An open-drainj
comparator is selected so the comparator output is compatible with the input logic level of the microcontroller. In
addition, selecting a comparator with an integrated reference value of 1.226 V is favorable because it is the
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closest internal reference option that is less than the critical undervoltage level of 2.0 V. Choosing the internal
reference option that is closest to the critical undervoltage level minimizes the resistor divider ratio which
optimizes the accuracy of the circuit. Error at the falling edge threshold of (VIT) is amplified by the inverse of the
resistor divider ratio. So minimizing the resistor divider ratio is a way of optimizing voltage monitoring accuracy.
方程式1 is derived from the analysis of 图8-1.
(1)
where
• R1 and R2 are the resistor values for the resistor divider connected to SENSE
• VBAT is the voltage source that is being monitored for an undervoltage condition.
• VIT is the falling edge threshold where the comparator output changes state from high to low
Rearranging 方程式1 and solving for R1 yields 方程式2.
(2)
For the specific undervoltage detection of 2.0 V using the TLV4011-Q1, the following results are calculated.
(3)
where
• R2 is set to 1 MΩ
• VBAT is set to 2.0 V
• VIT is set to1.226 V
Choose RTOTAL (R1 + R2) such that the current through the divider is at approximately 100 times higher than the
input bias current (IBIAS). The resistors can have high values to minimize current consumption in the circuit
without adding significant error to the resistive divider.
8.2.1.3 Application Curve
VHYS = 15 mV
1.226 V
SENSE
tPHL
tPLH
3.3 V
0 V
RESET
图8-2. Undervoltage Detection
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8.2.2 Additional Application Information
8.2.2.1 Pull-up Resistor Selection
Since the TLV4011-Q1 has an open drain output, care should be taken in selecting the pull-up resistor (RPU
)
value to ensure proper output voltage levels. First, consider the required output high logic level requirement of
the logic device that is being driven by the comparator when calculating the maximum RPU value. When in a
logic high output state, the output impedance of the comparator is very high but there is a finite amount of
leakage current that needs to be accounted for. Use IOH from the EC Table and the VIH minimum from the logic
device being driven to determine RPU maximum using 方程式4.
(4)
Next, determine the minimum value for RPU by using the VIL maximum from the logic device being driven. In
order for the comparator output to be recognized as a logic low, VIL maximum is used to determine the upper
boundary of the comparator's VOL. VOL maximum for the comparator is available in the EC Table for specific sink
current levels and can also be found from the VOUT versus ISINK curve in the Typical Application curves. A good
design practice is to choose a value for VOL maximum that is 1/2 the value of VIL maximum for the input logic
device. The corresponding sink current and VOL maximum value will be needed to calculate the minimum RPU
.
This method will ensure enough noise margin for the logic low level. With VOL maximum determined and the
corresponding ISINK obtained, the minimum RPU value is calculated with 方程式5.
(5)
Since the range of possible RPU values is large, a value between 5 kΩ and 100 kΩ is generally recommended.
A smaller RPU value provides faster output transition time and better noise immunity, while a larger RPU value
consumes less power when in a logic low output state.
8.2.2.2 Input Supply Capacitor
Although an input capacitor is not required for stability, for good analog design practice, connect a 100 nF low
equivalent series resistance (ESR) capacitor from (VDD) to (GND).
8.2.2.3 Sense Capacitor
Although not required in most cases, for extremely noisy applications, place a 1 nF to 100 nF bypass capacitor
from the comparator input (SENSE) to the (GND) for good analog design practice. This capacitor placement
reduces device sensitivity to transients.
9 Power Supply Recommendations
The TLV4011-Q1 comparator is designed to operate from an input supply from 1.3 V to 6 V. It is recommended
to place a 0.1-µF capacitor from the VDD pin to GND.
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10 Layout
10.1 Layout Guidelines
TI recommends to place the 0.1-µF decoupling capacitor close to the VDD pin. The VDD trace should be able to
carry 6 µA without a significant drop in voltage. Avoid a long trace from the SENSE pin to the resistor divider.
10.2 Layout Examples
NC
SENSE
VDD
C
R1
R2
TLV4011
GND
RESET
CVDD
R
Denotes GND Via
图10-1. Layout Example
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
14
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Product Folder Links: TLV4011-Q1
TLV4011-Q1
ZHCSR70 –SEPTEMBER 2020
www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TLV4011-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV4011QDCKRQ1
ACTIVE
SC70
DCK
5
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1I9
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV4011-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2022
Catalog : TLV4011
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV4011QDCKRQ1
SC70
DCK
5
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SC70 DCK
SPQ
Length (mm) Width (mm) Height (mm)
183.0 183.0 20.0
TLV4011QDCKRQ1
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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