TLV4021R1YKAR [TI]
具有基准电压的低功耗比较器（同相、漏极开路） | YKA | 4 | -40 to 125;
| 型号： | TLV4021R1YKAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有基准电压的低功耗比较器（同相、漏极开路） | YKA | 4 | -40 to 125 比较器 |
| 文件： | 总36页 (文件大小：2217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV4021, TLV4031, TLV4041, TLV4051
SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
TLV40x1 Small-Size, Low-Power Comparator with Precision Reference
1 Features
3 Description
•
•
•
•
Wide supply voltage range: 1.6 V to 5.5 V
Precision References: 0.2 V, 0.5 V, and 1.2 V
Fixed threshold of 3.2 V
Reference accuracy
– 0.5% at 25°C
The TLV40x1 devices are low-power, high-accuracy
comparators with precision references and fast
response. The comparators are available in an ultra-
small, DSBGA package measuring 0.73 mm × 0.73
mm, making the TLV40x1 applicable for space-critical
designs like portable or battery-powered electronics
where low-power and fast response to changes in
operating conditions is required.
– 1% over temperature
•
•
•
•
•
•
•
•
Low quiescent current: 2 µA
Propagation delay: 360 ns
Push-pull and open-drain output options
Known startup conditions
Non-inverting and inverting input options
Precision hysteresis
Temperature range: –40°C to +125°C
Packages:
– 0.73 mm × 0.73 mm DSBGA (4-bump)
– SOT-23 (5-pin)
The factory-trimmed references and precision
hysteresis combine to make the TLV40x1 appropriate
for voltage and current monitoring in harsh, noisy
environments where slow moving input signals must
be converted into clean digital outputs. Similarly, brief
glitches on the input are rejected ensuring stable
output operation without false triggering.
The TLV40x1 are available in multiple configurations
allowing system designers to achieve their desired
output response. For example, the TLV4021 and
TLV4041 offer a non-inverting input, while the
TLV4031 and TLV4051 have an inverting input.
Furthermore, the TLV4021 and TLV4031 feature an
open-drain output stage, while the TLV4041 and
TLV4051 feature a push-pull output stage. Lastly,
each comparator in the TLV40x1 family is available
with a 0.2V, 0.5V, or 1.2V precision reference.
2 Applications
•
•
•
•
•
•
•
•
•
Self-diagnostics
Lithium ion battery monitoring
Battery management and protection
Current and voltage sensing
Analog front end
Power management
Point of load regulators
DC/DC and AC/DC power supplies
System control and monitoring
Device Information
PART NUMBER
PACKAGE (1)
BODY SIZE (NOM)
0.73 mm × 0.73 mm
2.9 mm × 1.6 mm
TLV4021, TLV4031,
TLV4041, TLV4051
DSBGA (4)
TLV4041, TLV4051 SOT-23 (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Non-Inver ng
Inver ng
Fixed Threshold
IN
V+
V+
V+
IN
IN
OUT
OUT
+
–
–
+
–
+
TLV4021
TLV4041
TLV4031
TLV4051
TLV4021S5x
1.2V
REF
REF
V
V
V
TLV40x1 Configurations
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV4021, TLV4031, TLV4041, TLV4051
SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
www.ti.com
Table 3-1. TLV40x1 Truth Table
DEVICE
Input Configuration
Reference
Output Type
Open-Drain
Push-Pull
TLV4021R1
TLV4041R1
TLV4041R5
TLV4021R2
TLV4041R2
TLV4031R1
TLV4051R1
TLV4051R5
TLV4031R2
TLV4051R2
1.2 V
Non-Inverting
0.5 v
0.2 V
Push-Pull
Open-Drain
Push-Pull
Open-Drain
Push-Pull
1.2 V
0.5 V
0.2 V
Inverting
Push-Pull
Open-Drain
Push-Pull
DEVICE
Input Configuration
Fixed Threshold
Output Type
TLV4021S5x
Non-Inverting
3.2 V
Open-Drain
VPU
VPU
VPU
VPU
TLV4041R2
TLV4041R1
TLV4021R2
TLV4021R1
V+
V+
V+
V+
+
–
OUT
+
–
OUT
+
–
OUT
+
–
OUT
IN
IN
IN
IN
1.2V
0.2V
1.2V
0.2V
V
V
V
V
VPU
TLV4051R2
TLV4051R1
TLV4031R2
TLV4031R1
V+
V+
V+
V+
–
–
–
–
OUT
OUT
OUT
OUT
+
+
+
+
IN
IN
IN
IN
1.2V
0.2V
1.2V
0.2V
V
V
V
V
TLV4041R5
TLV4051R5
TLV4021S5x
V+
V+
V+
IN
–
+
–
OUT
OUT
+
IN
IN
+
–
0.5V
0.5V
1.2V
V
V
V
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SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 3
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
7 Typical Characteristics................................................... 8
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 21
9.3 What to Do and What Not to Do............................... 23
10 Power Supply Recommendations..............................24
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................25
12.1 Receiving Notification of Documentation Updates..25
12.2 Support Resources................................................. 25
12.3 Trademarks.............................................................25
12.4 Electrostatic Discharge Caution..............................25
12.5 Glossary..................................................................25
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2020) to Revision C (December 2021)
Page
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document .................1
Added TLV4021S5x throughout the document ..................................................................................................1
Changes from Revision A (May 2019) to Revision B (March 2020)
Page
•
•
•
Added SOT-23 package option with 0.5V reference. .........................................................................................1
Changed configuration diagram and TLV40x1 Truth Table. ...............................................................................1
Added Configuration diagrams for entire TLV40x1 family...................................................................................1
Changes from Revision * (October 2018) to Revision A (May 2019)
Page
•
Changed Product Preview to Production Data .................................................................................................. 1
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SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
www.ti.com
5 Pin Configuration and Functions
Top View
A
B
OUT
IN
V+
V-
1
2
Figure 5-1. YKA Package
4-Bump DSBGA
Top View
Table 5-1. DSBGA Package Pin Functions
PIN
I/O
DESCRIPTION
NAME
OUT
V+
NUMBER
A1
B1
B2
A2
O
P
P
I
Comparator output: OUT is push-pull on TLV4041/4051 and open-drain on TLV4021/4031
Positive (highest) power supply
V–
Negative (lowest) power supply
IN
Comparator input: IN is non-Inverting on TLV4021/4041 and inverting on TLV4031/4051
Top View
V+
V-
1
2
5
4
OUT
IN
3
NC
Figure 5-2. SOT-23 Package
5-pin
Top View
Table 5-2. SOT-23 Pin Functions
PIN
I/O
DESCRIPTION
NAME
V+
NUMBER
1
2
P
P
Positive (highest) power supply
Negative (lowest) power supply
V-
No connect; this pin is not internally connected to the die. It can be grounded if that is preferred in
the system.
NC
3
x
IN
4
5
I
Comparator input: IN is inverting on TLV4031/4051
Comparator output: OUT is push-pull on TLV4041/4051
OUT
O
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SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
V
Supply voltage: VS = (V+) – (V–)
Input voltage (IN) from (V–) (2)
Input Current (IN)(2)
6
6
V
±10
mA
V
TLV4021, TLV4031
Output voltage (OUT) from (V-)
–0.3
–0.3
6
(V+) + 0.3
10
TLV4041, TLV4051
V
Output short-circuit duration(3)
Junction temperature, TJ
Storage temperature, Tstg
s
150
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input terminals are diode-clamped to (V–). Input signals that can swing more than 0.3 V below (V–) must be current-limited to 10 mA or
less.
In addition, IN can be greater than (V+) and OUT as long as it is within the –0.3 V to 6 V range. Input signals that can swing beyond
this range must be current-limited to 10 mA or less.
(3) Short-circuit to ground.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
MAX
UNIT
Supply voltage: VS = (V+) – (V–)
Ambient temperature, TA
5.5
V
–40
125
°C
6.4 Thermal Information
TLV40x1
THERMAL METRIC (1)
YKA (DSBGA)
4 BUMPS
SOT-23 (DBV)
5 PINS
181.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
205.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
1.8
101.1
Junction-to-board thermal resistance
75.3
0.9
52.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.2
ψJB
74.7
N/A
51.6
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VS = 1.8 V to 5 V, typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Postive-going input threshold
voltage
VS = 1.8 V and 5 V, TA = 25°C
1.194
1.2
1.206
VIT+
VIT-
VIT+
VIT-
Postive-going input threshold
voltage
VS = 1.8 V and 5 V, TA = -40℃ to +125℃
VS = 1.8 V and 5 V, TA = 25°C
1.188
1.174
1.168
0.197
0.196
0.177
0.176
1.212
1.186
1.192
0.203
0.204
0.183
0.184
TLV40x1R1
V
Negative-going input
threshold voltage
1.18
0.2
Negative-going input
threshold voltage
VS = 1.8 V and 5 V, TA = -40°C to +125°C
VS = 1.8 V and 5 V, TA = 25°C
Postive-going input threshold
voltage
Postive-going input threshold
voltage
VS = 1.8 V and 5 V, TA = -40℃ to +125℃
VS = 1.8 V and 5 V, TA = 25°C
TLV40x1R2
V
Negative-going input
threshold voltage
0.18
Negative-going input
threshold voltage
VS = 1.8 V and 5 V, TA = -40°C to +125°C
Postive-going input threshold
voltage
(TLV40x1R5 only)
VS = 1.8 V and 5 V, TA = 25°C
0.495
0.49
0.5
0.505
0.51
V
V
V
V
VIT+
Postive-going input threshold
voltage
(TLV40x1R5 only)
VS = 1.8 V and 5 V, TA = -40℃ to +125℃
VS = 1.8 V and 5 V, TA = 25°C
TLV40x1R5
Negative-going input
threshold voltage
(TLV40x1R5 only)
0.4752
0.4704
0.48
0.4848
0.4896
VIT-
Negative-going input
threshold voltage
(TLV40x1R5 only)
VS = 1.8 V and 5 V, TA = -40°C to +125°C
Postive-going input threshold
voltage
VS = 1.8 V and 5 V, TA = 25°C
3.238
3.221
3.184
3.168
3.254
3.2
3.270
3.287
3.216
3.232
V
V
V
VIT+
Postive-going input threshold
voltage
VS = 1.8 V and 5 V, TA = -40℃ to +125℃
VS = 1.8 V and 5 V, TA = 25°C
TLV4021S5x
Negative-going input
threshold voltage
VIT-
Negative-going input
threshold voltage
VS = 1.8 V and 5 V, TA = -40℃ to +125℃
VS = 1.8 V and 5 V, TA = 25℃
V
(2)
(2)
VHYS
VHYS
Input hysteresis voltage
TLV40x1Ry
TLV40x1R5
TLV40x1S5x
20
20
54
mV
mV
Input hysteresis voltage
(TLV40x1R5 only)
VS = 1.8 V and 5 V, TA = 25℃
VHYS
VIN
Input hysteresis voltage
Input voltage range
Input bias current
VS = 1.8 V and 5 V, TA = 25°C
TA = -40℃ to +125℃
Over VIN range
mV
V
V–
5.5
IBIAS
10
pA
Input bias current
(TLV4021S5x only)
IBIAS
IN = 3.3 V
1.65
µA
mV
mV
mV
mV
ISINK = 200 µA, OUT asserted low,
VS = 5 V, TA = –40°C to +125°C
100
400
100
400
Voltage output swing
from (V–)
VOL
ISINK = 3 mA, OUT asserted low,
VS = 5 V, TA = –40°C to +125°C
ISOURCE = 200 µA, OUT asserted high,
VS = 5 V, TA = –40°C to +125°C
Voltage output swing
from (V+)
(TLV4041/4051 only)
VOH
ISOURCE = 3 mA, OUT asserted high,
VS = 5 V, TA = –40°C to +125°C
Open-drain output leakage
current
(TLV4021/4031 only)
VS = 5 V, OUT asserted high
VPULLUP = (V+), TA = 25°C
IO-LKG
20
pA
ISC
ISC
Short-circuit current
Short-circuit current
VS = 5 V, sinking, TA = 25°C
55
50
mA
mA
VS = 5 V, sourcing, TA = 25°C
(TLV4041/4051 only)
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6.5 Electrical Characteristics (continued)
VS = 1.8 V to 5 V, typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.5
5
UNIT
µA
No load, TA = 25°C, Output Low, VS = 1.8 V
2
IQ
Quiescent current
No load, TA = –40°C to +125°C, Output Low, VS = 1.8 V
µA
(1)
VPOR
Power-on reset voltage
1.45
V
(1) See Section 7.4.1 (Power ON Reset) for more details.
(2) See Section 7.4.3 (Switching Thresholds and Hysteresis) for more details.
6.6 Switching Characteristics
Typical values are at TA = 25°C, VS = 3.3 V, CL = 15 pF; Input overdrive = 100 mV for TLV40x1Ry & 5% for
TLV4021S5x, RP=4.99 kΩ for open-drain options (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Midpoint of input to midpoint of output
Midpoint of input to midpoint of output
MIN
TYP
360
360
MAX
UNIT
ns
tPHL
tPLH
Propagation delay, high-to-low (1)
Propagation delay, low-to-high (1)
ns
Propagation delay, high-to-low (1)
(TLV4021S5x only)
tPHL
tPLH
tR
Midpoint of input to midpoint of output
Midpoint of input to midpoint of output
2
2
µs
µs
ns
Propagation delay, low-to-high (1)
(TLV4021S5x only)
Rise time
(TLV4041/4051 only)
20% to 80%
20% to 80%
10
tF
Fall time
10
ns
µs
tON
Power-up time (2)
500
(1) High-to-low and low-to-high refers to the transition at the input.
(2) During power on cycle, VS must exceed 1.6 V for tON before the output will reflect the condition on the input. Prior to tON elapsing, the
output is controlled by the POR circuit.
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7 Typical Characteristics
at TJ = 25°C and VS = 3.3 V (unless otherwise noted)
21000
19500
18000
16500
15000
13500
12000
10500
9000
7500
6000
4500
3000
1500
0
1.2012
1.2009
1.2006
1.2003
1.2
VS = 1.8V
VS = 3.3V
VS = 5.0V
1.1997
1.1994
1.1991
1.1988
1.1985
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
1.198 1.1986 1.1992 1.1998 1.2004 1.201 1.2016
VIT+ (V)
TLV40x1R1
Figure 7-1. Positive Threshold vs Temperature
TLV40x1R1
Figure 7-2. Positive Threshold Histogram
VS = 5 V
1.1811
21000
19500
18000
16500
15000
13500
12000
10500
9000
7500
6000
4500
3000
1500
0
VS = 1.8V
VS = 3.3V
VS = 5.0V
1.1808
1.1805
1.1802
1.1799
1.1796
1.1793
1.179
1.1787
1.1784
1.1781
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
1.1778 1.1784 1.179 1.1796 1.1802 1.1808 1.1814
VIT- (V)
TLV40x1R1
Figure 7-3. Negative Threshold vs Temperature
TLV40x1R1
VS = 5 V
Figure 7-4. Negative Threshold Histogram
20.64
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
VS = 1.8V
VS = 3.3V
VS = 5.0V
20.56
20.48
20.4
20.32
20.24
20.16
20.08
20
19.92
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
17
18
19
20
VHYST (mV)
21
22
23
TLV40x1R1
Figure 7-5. Hysteresis vs Temperature
TLV40x1R1
VS = 5 V
Figure 7-6. Hysteresis Histogram
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7 Typical Characteristics (continued)
at TJ = 25°C and VS = 3.3 V (unless otherwise noted)
0.2004
30000
27000
24000
21000
18000
15000
12000
9000
6000
3000
0
VS = 1.8V
VS = 3.3V
VS = 5.0V
0.20025
0.2001
0.19995
0.1998
0.19965
0.1995
0.19935
0.1992
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0.198 0.1986 0.1992 0.1998 0.2004 0.201 0.2016
VIT+ (V)
TLV40x1R2
Figure 7-7. Positive Threshold vs Temperature
TLV40x1R2
VS = 5 V
Figure 7-8. Positive Threshold Histogram
0.18016
30000
27000
24000
21000
18000
15000
12000
9000
6000
3000
0
VS = 1.8V
VS = 3.3V
VS = 5.0V
0.18008
0.18
0.17992
0.17984
0.17976
0.17968
0.1796
0.17952
0.17944
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0.1776
0.1784
0.1792
0.18
VIT- (V)
0.1808
0.1816
TLV40x1R2
Figure 7-9. Negative Threshold vs Temperature
TLV40x1R2
Figure 7-10. Negative Threshold Histogram
VS = 5 V
20.22
500
450
400
350
300
250
200
150
100
50
VS = 1.8V
VS = 3.3V
VS = 5.0V
20.2
20.18
20.16
20.14
20.12
20.1
20.08
20.06
20.04
20.02
20
0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
17
18
19
20
VHYST (mV)
21
22
23
TLV40x1R2
Figure 7-11. Hysteresis vs Temperature
TLV40x1R2
VS = 5 V
Figure 7-12. Hysteresis Histogram
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7 Typical Characteristics (continued)
at TJ = 25°C and VS = 3.3 V (unless otherwise noted)
3.2545
3.254
25000
22500
20000
17500
15000
12500
10000
7500
5000
2500
0
3.2535
3.253
3.2525
3.252
3.2515
3.251
3.2505
3.25
3.2495
VS = 1.8V
VS = 3.3V
VS = 5.0V
3.249
3.2485
3.248
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
3.2475
3.2505
3.2535
VIT+ (V)
3.2565
3.2595
TLV4021S5x
Figure 7-13. Positive Threshold vs Temperature
TLV4021S5x
Figure 7-14. Positive Threshold Histogram
3.2015
25000
22500
20000
17500
15000
12500
10000
7500
5000
2500
0
3.201
3.2005
3.2
3.1995
3.199
3.1985
3.198
3.1975
3.197
3.1965
3.196
3.1955
3.195
3.1945
VS = 1.8V
VS = 3.3V
VS = 5.0V
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
3.196
3.1975
3.199
3.2005
VIT- (V)
3.202
3.2035
3.205
TLV4021S5x
Figure 7-15. Negative Threshold vs Temperature
TLV4021S5x
Figure 7-16. Negative Threshold Histogram
53.8
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
53.6
53.4
53.2
53
52.8
52.6
52.4
-40°C
25°C
85°C
125°C
1.5
2
2.5
3
3.5
VS (V)
4
4.5
5
5.5
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
Hysteresis (mV)
TLV4021S5x
Figure 7-17. Hysteresis vs Supply Voltage
TLV4021S5x
Figure 7-18. Hysteresis Histogram
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7 Typical Characteristics (continued)
at TJ = 25°C and VS = 3.3 V (unless otherwise noted)
5000
1000
5000
1000
VS = 1.8V
VS = 3.3V
VS = 5V
100
10
100
10
1
0.1
1
-40°C
25°C
85°C
125°C
0.1
0.01
0.001
0.01
0.001
0.1
0.2 0.3
0.5 0.7 1
VIN (V)
2
3
4
5 6 7 8 10
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Figure 7-20. Output Current Leakage vs Temperature
VS = 1.8V to 5V
TLV40x1Ry
Figure 7-19. Bias Current vs Common Mode Voltage
2
1
2
1
0.7
0.5
0.5
0.3
0.2
0.3
0.2
0.1
0.1
0.07
0.05
0.05
0.03
-40°C
0°C
25°C
125°C
-40°C
0°C
25°C
125°C
20 30 50 70100
0.02
0.03
0.02
0.01
0.005
0.01
0.1 0.2 0.3 0.5
1
Output Sinking Current (mA)
2
3 4 567 10
20 30 50 70100
0.1 0.2 0.3 0.5
1
Output Sourcing Current (mA)
2
3 4 567 10
VS = 1.8V
VS = 1.8V
Figure 7-21. Output Voltage vs Output Sinking Current
Figure 7-22. Output Voltage vs Output Sourcing Current
5
5
3
2
3
2
1
1
0.5
0.5
0.3
0.2
0.3
0.2
0.1
0.1
0.05
0.05
0.03
0.03
-40°C
-40°C
0.02
0.01
0.005
0.02
0.01
0.005
0°C
25°C
125°C
0°C
25°C
125°C
0.1 0.2 0.3 0.5
1
Output Sinking Current (mA)
2
3 4 567 10
20 30 50 70100
0.1 0.2 0.3 0.5
1
Output Sourcing Current (mA)
2
3 4 567 10
20 30 50 70100
VS = 3.3V
VS = 3.3V
Figure 7-23. Output Voltage vs Output Sinking Current
Figure 7-24. Output Voltage vs Output Sourcing Current
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7 Typical Characteristics (continued)
at TJ = 25°C and VS = 3.3 V (unless otherwise noted)
10
5
10
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
-40°C
0°C
25°C
125°C
-40°C
0°C
25°C
125°C
0.02
0.01
0.02
0.01
0.005
0.005
0.1 0.2 0.3 0.5
1
Output Sinking Current (mA)
2
3 4 567 10
20 30 50 70100
0.1 0.2 0.3 0.5
1
Output Sourcing Current (mA)
2
3 4 567 10
20 30 50 70100
VS = 5V
VS = 5V
Figure 7-25. Output Voltage vs Output Sinking Current
Figure 7-26. Output Voltage vs Output Sourcing Current
3.2
3
1500
-40°C
25°C
85°C
125°C
1400
1300
2.8
2.6
2.4
2.2
2
1200
1100
1000
900
800
700
600
500
400
300
200
1.8
VS = 1.8V
VS = 3.3V
VS = 5V
1.6
1.4
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
20 40 60 80 100 120 140 160 180 200 220
VOD (mV)
Figure 7-27. Supply Current vs Temperature
VS = 1.8V to 5V
TLV40x1R2
Figure 7-28. Propagation Delay Low-High vs Input Overdrive
2400
2200
2000
1800
1600
1400
1200
1000
800
6
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
5.5
5
4.5
4
3.5
3
2.5
2
600
1.5
1
400
200
0
20 40 60 80 100 120 140 160 180 200 220
VOD (mV)
0
1
2
3
4
5 6
VOD (%)
7
8
9
10 11
VS = 1.8V to 5V
TLV40x1R2
VS = 1.8V to 5V
TLV4021Sx5
Figure 7-29. Propagation Delay High-Low vs Input Overdrive
Figure 7-30. Propagation Delay Low-High vs Input Overdrive
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7 Typical Characteristics (continued)
at TJ = 25°C and VS = 3.3 V (unless otherwise noted)
7.5
7
-40°C
25°C
85°C
125°C
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
1
2
3
4
5 6
VOD (%)
7
8
9
10 11
VS = 1.8V to 5V
TLV4021Sx5
Figure 7-31. Propagation Delay High-Low vs Input Overdrive
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8 Detailed Description
8.1 Overview
The TLV40x1 devices are low-power comparators that are well suited for compact, low-current, precision voltage
detection applications. With high-accuracy, switching thresholds options of 0.2V, 0.5 V, 1.2V, and 3.2V, 2uA of
quiescent current, and propagation delay of 450ns and 2us, the TLV40x1 comparator family enables power
conscious systems to monitor and respond quickly to fault conditions.
The TLV40x1Ry comparators assert the output signal as shown in Table 8-1. VIT+ represents the positive-going
input threshold that causes the comparator output to change state, while VIT- represents the negative-going input
threshold that causes the output to change state. Since VIT+ and VIT- are factory trimmed and warranted over
temperature, the TLV40x1 is equally suited for undervoltage and overvoltage applications. In order to monitor
any voltage above the internal reference voltage, an external resistor divider network is required.
The TLV4021S5x functions similar to the TLV40x1Ry comparators except the resistor divider is internal to the
device. Having the resistor divider internal to the device allows the TLV4021S5x to have switching thresholds
higher than the internal reference voltage of 1.2V without any external components.
Table 8-1. TLV40x1 Truth Table
OUTPUT
DEVICE
(VIT+, VIT-
)
TOPOLOGY
INPUT VOLTAGE
IN > VIT+
OUTPUT LOGIC LEVEL
Output high impedance
Output asserted low
TLV4021R2
TLV4021R1
0.2V, 0.18V
1.2V, 1.18V
Open-Drain
IN < VIT-
TLV4041R2
TLV4041R5
TLV4041R1
0.2V, 0.18V
0.5V, 0.48V
1.2V, 1.18V
IN > VIT+
Output asserted high
Push-Pull
Open-Drain
Push-Pull
IN < VIT-
Output asserted low
IN > VIT+
IN < VIT-
IN > VIT+
Output asserted low
Output high impedance
Output asserted low
TLV4031R2
TLV4031R1
0.2V, 0.18V
1.2V, 1.18V
TLV4051R2
TLV4051R5
TLV4051R1
0.2V, 0.18V
0.5V, 0.48V
1.2V, 1.18V
IN < VIT-
Output asserted high
IN > VIT+
IN < VIT-
Output high impedance
Output asserted low
TLV4021S5x 3.254V, 3.2V
Open-Drain
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8.2 Functional Block Diagram
VPU
VPU
TLV4041R2
TLV4041R1
TLV4021R2
TLV4021R1
V+
V+
V+
V+
+
–
OUT
+
–
OUT
+
–
OUT
+
–
OUT
IN
IN
IN
IN
1.2V
0.2V
1.2V
0.2V
V
V
V
V
VPU
VPU
TLV4051R2
TLV4051R1
TLV4031R2
TLV4031R1
V+
V+
V+
V+
–
–
–
–
OUT
OUT
OUT
OUT
+
+
+
+
IN
IN
IN
IN
1.2V
0.2V
1.2V
0.2V
V
V
V
V
VPU
TLV4041R5
TLV4051R5
TLV4021S5x
V+
V+
V+
IN
–
+
–
OUT
OUT
+
IN
IN
+
–
0.5V
0.5V
1.2V
V
V
V
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8.3 Feature Description
The TLV40x1 is a family of 4-pin, precision, low-power comparators with precision switching thresholds. The
TLV40x1 comparators feature a rail-to-rail input stage with factory programmed switching thresholds for both
rising and falling input waveforms. The comparator family also supports open-drain and push-pull output
configurations as well as non-inverting and inverting inputs.
8.4 Device Functional Modes
8.4.1 Power ON Reset (POR)
The TLV40x1 comparators have a Power-on-Reset (POR) circuit which provides system designers a known
start-up condition for the output of the comparators. When the power supply (VS) is ramping up or ramping down,
the POR circuit will be active when VS is below VPOR. For the TLV4021 and TLV4031, the POR circuit will force
the output to High-Z, and for the TLV4041 and TLV4051, the POR circuit will hold the output low at (V-). When
VS is greater than, or equal to, the minimum recommended operating voltage, the comparator output reflects the
state of the input (IN).
The following pictures represent how the TLV40x1 outputs respond for VS rising and falling. For the comparators
with open-drain outputs (TLV4021/4031), IN is connected to (V-) to highlight the transition from POR circuit
control to standard comparator operation where the output reflects the input condition. Note how the output goes
low when VS reaches 1.45V. Likewise, for the comparators with push-pull outputs (TLV4041/4051), the input is
connected to (V+). Note how the output goes high when VS reaches 1.45V.
5
4.5
4
5
4.5
4
VS
VOUT
VS
VOUT
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
-0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Time (s)
-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05
Time (s)
Figure 8-1. TLV4021/4031 Output for VS Rising
Figure 8-2. TLV4021/4031 Output for VS Falling
5.5
5
5.5
VS
VOUT
5
4.5
4.5
4
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0.5
0
VS
VOUT
0
-0.5
-0.5
-0.5 -0.4 -0.3 -0.2 -0.1
0
Time (s)
0.1 0.2 0.3 0.4 0.5
-0.05
-0.03
-0.01
0.01
Time (s)
0.03
0.05
Figure 8-3. TLV4041/4051 Output for VS Rising
Figure 8-4. TLV4041/4051 Output for VS Falling
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8.4.2 Input (IN)
The TLV40x1 comparators have two inputs: one external input (IN) and one internal input that is connected to
the integrated voltage reference. The comparator rising threshold is trimmed to the reference voltage (VIT+) while
the falling threshold is trimmed to (VIT-). Since the rising and falling thresholds are both trimmed and warranted
in the Electrical Characteristics Table, the TLV40x1 is equally suited for undervoltage and overvoltage detection.
The difference between (VIT+) and (VIT-) is referred to as the comparator hysteresis and is 20 mV for TLV40x1Ry
and 54 mV for TLV4021S5x. The integrated hysteresis makes the TLV40x1 less sensitive to supply-rail noise
and provides stable operation in noisy environments without having to add external positive feedback to create
hysteresis.
The comparator input (IN) is able to swing 5.5 V above (V-) regardless of the device supply voltage. This
includes the instance when no supply voltage is applied to the comparator (VS = 0 V). As a result, the TLV40x1
is referred to as fault tolerant, meaning it maintains the same high input impedance when VS is unpowered or
ramping up. While not required in most cases, in order to reduce sensitivity to transients and layout parasitics for
extremely noisy applications, place a 1 nF to 100 nF bypass capacitor at the comparator input.
For the TLV40x1Ry comparators, the input bias current is typically 10 pA for input voltages between (V-) and
(V+) and the value typically doubles for every 10°C temperature increase. The comparator input is protected
from voltages below (V-) by an internal diode connected to (V-). As the input voltage goes below (V-), the
protection diode becomes forward biased and begins to conduct causing the input bias current to increase
exponentially. A series resistor is recommended to limit the input current when sources have signal content that
is less than (V-).
For the TLV4021S5x, the input bias current is limited by the internal resistor divider with typical impedance of 2M
ohms.
8.4.3 Switching Thresholds and Hysteresis (VHYS
)
The TLV40x1 transfer curve is shown in Figure 8-5.
•
•
•
VIT+ represents the positive-going input threshold that causes the comparator output to change from a logic
low state to a logic high state.
VIT- represents the negative-going input threshold that causes the comparator output to change from a logic
high state to a logic low state.
VHYS represents the difference between VIT+ and VIT- and is 20 mV for TLV40x1Ry and 54 mV for
TLV4021S5x.
VHYS = (VIT+) œ (VIT-
)
VIT-
VIT+
Figure 8-5. Transfer Curve
VIT+ and VIT- have mV's of variation over temperature. The significant portion of the variation of these parameters
is a result of the internal bandgap voltage from which VIT+ and VIT- are derived. The following hysteresis
histograms demonstrate the performance of the TLV40x1 hysteresis circuitry. Since the bandgap reference is
used to set VIT+ and VIT-, each of these parameters have a tendency to error (track) in the same direction. For
example, if VIT+ has a positive 0.5% error, VIT- would have a tendency to have a similar positive percentage
error. As a result, the variation of hysteresis will never be equal to the difference of the highest VIT+ value of its
range and the lowest VIT- value of its range.
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500
450
400
350
300
250
200
150
100
50
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
0
17
18
19
20
VHYST (mV)
21
22
23
17
18
19
20
VHYST (mV)
21
22
23
Figure 8-6. VHYST Histogram (TLV40x1R2, VS=5V)
Figure 8-7. VHYST Histogram (TLV40x1R1, VS=5V)
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
Hysteresis (mV)
Figure 8-8. VHYST Histogram (TLV40x1S5, VS=5V)
8.4.4 Output (OUT)
The TLV4041 and TLV4051 feature a push-pull output stage which eliminates the need for an external pull-up
resistor while providing a low impedance output driver. Likewise, the TLV4021 and TLV4031 feature an open-
drain output stage which enables the output logic levels to be pulled-up to an external source as high as 5.5 V
independent of the supply voltage.
In a typical TLV40x1 application, OUT is connected to an enable input of a processor or a voltage regulator such
as a dc-dc converter or low-dropout regulator (LDO). The open-drain output versions (TLV4021/4031) are used
if the power supply of the comparator is different than the supply voltage of the device being controlled. In this
usage case, a pull-up resistor holds OUT high when the comparator output goes high impedance. The correct
interface-voltage level is provided (also known as level-shifting) by connecting the pull-up resistor on OUT to the
appropriate voltage rail. The TLV4021/4031 output can be pulled up to 5.5 V, independent of the device supply
voltage (VS). However, if level-shifting is not required, the push-pull output versions (TLV4041/4051) should be
utilized in order to eliminate the need for the pull-up resistor.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLV40x1 is a 4-pin, low-power comparator with a precision, integrated reference. The comparators in this
family are well suited for monitoring voltages and currents in portable, battery powered devices.
9.1.1 Monitoring (V+)
Many applications monitor the same rail that is powering the comparator. In these applications the resistor
divider is simply connected to the (V+) rail.
Supply
V+
IN
OUT
ë5
Figure 9-1. Supply Monitoring
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9.1.2 Monitoring a Voltage Other than (V+)
Some applications monitor rails other than the one that is powering the comparator. In these applications the
resistor divider used to set the desired threshold is connected to the rail that is being monitored.
VMON
Supply
V+
TLV40x1
IN
OUT
REF
ë5
Figure 9-2. Monitoring a Voltage Other than the Supply
The TLV40x1Ry can monitor a voltage greater than the maximum (V+) with the use of an external resistor divider
network. Likewise, the TLV40x1 can monitor voltages as low as the internal reference voltage (0.2 V, 0.5 V,
or 1.2 V). The TLV40x1Ry also has the advantage of being able to monitor high impedance sources since the
input bias current of the input (IN) is low. This provides an advantage over voltage supervisors that can only
monitor the voltage rail that is powering them. Supervisors configured in this fashion have limitations in source
impedance and minimum sensing voltage.
9.1.3 VPULLUP to a Voltage Other than (V+)
For applications where the output of the comparator needs to interface with a reset/enable pin that operates
from a different supply voltage, the open-drain comparators (TLV4021/4031) should be selected. In these usage
cases, the output can be pulled up to any voltage that is lower than 5.5V (independent of (V+)). This technique is
commonly referred to as "level-shifting."
VMON
Supply
VPULLUP
(up to 5.5V)
RPULLUP
V+
IN
OUT
ë5
Figure 9-3. Level-Shifting
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9.2 Typical Application
9.2.1 Under-Voltage Detection
Under-voltage detection is frequently required in battery-powered, portable electronics to alert the system that a
battery voltage has dropped below the usable voltage level. Figure 9-4 shows a simple under-voltage detection
circuit using the TLV4041R1 which is a non-inverting comparator with an integrated 1.2 V reference and a push-
pull output stage. The non-inverting TLV4041 option was selected in this example since the micro-controller
required an active low signal when an undervoltage level occurs. However, if an active high signal was required,
the TLV4051 option with an inverting input stage would be utilized.
VBAT
3.3V
R1
V+
V+
TLV4041R1
+
t
ALERT
IN
OUT
1.2V
Micro-
controller
R2
ë5
Figure 9-4. Under-Voltage Detection
9.2.1.1 Design Requirements
For this design, follow these design requirements:
•
•
•
Operate from 3.3 V power supply that powers the microcontroller.
Under-voltage alert is active low.
Logic low output when VBAT is less than 2.0V.
9.2.1.2 Detailed Design Procedure
Configure the circuit as shown in Figure 9-4. Connect (V+) to 3.3 V which also powers the micro-controller.
Resistors R1 and R2 create the under-voltage alert level of 2.0 V. When the battery voltage sags down to 2.0 V,
the resistor divider voltage crosses the (VIT-) threshold of the TLV4041R1. This causes the comparator output
to transition from a logic high to a logic low. The push-pull option of the TLV40x1 family is selected since the
comparator operating voltage is shared with the microcontroller which is receiving the under-voltage alert signal.
The TLV4041 option with the 1.2 V internal reference is selected because it is the closest internal reference
option that is less than the critical under-voltage level of 2.0 V. Choosing the internal reference option that is
closest to the critical under-voltage level minimizes the resistor divider ratio which optimizes the accuracy of
the circuit. Error at the falling edge threshold of (VIT-) is amplified by the inverse of the resistor divider ratio. So
minimizing the resistor divider ratio is a way of optimizing voltage monitoring accuracy.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051
TLV4021, TLV4031, TLV4041, TLV4051
SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
www.ti.com
Equation 1 is derived from the analysis of Figure 9-4.
(1)
where
•
•
•
R1 and R2 are the resistor values for the resistor divider connected to IN
VBAT is the voltage source that is being monitored for an undervoltage condition.
VIT- is the falling edge threshold where the comparator output changes state from high to low
Rearranging Equation 1 and solving for R1 yields Equation 2.
(2)
For the specific undervoltage detection of 2.0 V using the TLV4041R1, the following results are calculated.
(3)
where
•
•
•
R2 is set to 1 MΩ
VBAT is set to 2.0 V
VIT- is set to1.18 V
Choose RTOTAL (R1 + R2) such that the current through the divider is at least 100 times higher than the input bias
current (IBIAS). The resistors can have high values to minimize current consumption in the circuit without adding
significant error to the resistive divider.
9.2.1.3 Application Curve
2.03V
2V
IN
3.3V
OUT
0V
Normal Operating
Voltage
Under-Voltage
Alert
Normal Operating
Voltage
Figure 9-5. Under-Voltage Detection
Copyright © 2021 Texas Instruments Incorporated
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TLV4021, TLV4031, TLV4041, TLV4051
SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
www.ti.com
9.2.2 Additional Application Information
9.2.2.1 Pull-up Resistor Selection
For the TLV4021 (open-drain output versions of the TLV40x1 family), care should be taken in selecting the
pull-up resistor (RPU) value to ensure proper output voltage levels. First, consider the required output high logic
level requirement of the logic device that is being driven by the comparator when calculating the maximum RPU
value. When in a logic high output state, the output impedance of the comparator is very high but there is a finite
amount of leakage current that needs to be accounted for. Use IO-LKG from the EC Table and the VIH minimum
from the logic device being driven to determine RPU maximum using Equation 4.
(4)
Next, determine the minimum value for RPU by using the VIL maximum from the logic device being driven. In
order for the comparator output to be recognized as a logic low, VIL maximum is used to determine the upper
boundary of the comparator's VOL. VOL maximum for the comparator is available in the EC Table for specific sink
current levels and can also be found from the VOUT versus ISINK curve in the Typical Application curves. A good
design practice is to choose a value for VOL maximum that is 1/2 the value of VIL maximum for the input logic
device. The corresponding sink current and VOL maximum value will be needed to calculate the minimum RPU
.
This method will ensure enough noise margin for the logic low level. With VOL maximum determined and the
corresponding ISINK obtained, the minimum RPU value is calculated with Equation 5.
(5)
Since the range of possible RPU values is large, a value between 5 kΩ and 100 kΩ is generally recommended.
A smaller RPU value provides faster output transition time and better noise immunity, while a larger RPU value
consumes less power when in a logic low output state.
9.2.2.2 Input Supply Capacitor
Although an input capacitor is not required for stability, for good analog design practice, connect a 100 nF low
equivalent series resistance (ESR) capacitor from (V+) to (V-).
9.2.2.3 Sense Capacitor
Although not required in most cases, for extremely noisy applications, place a 1 nF to 100 nF bypass capacitor
from the comparator input (IN) to the (V-) for good analog design practice. This capacitor placement reduces
device sensitivity to transients.
9.3 What to Do and What Not to Do
Do connect a 100 nF decoupling capacitor from (V+) to (V-) for best system performance.
If the monitored voltage is noisy, do connect a decoupling capacitor from the comparator input (IN) to (V-).
Don't use resistors for the voltage divider that cause the current through them to be less than 100 times the input
current of the comparator without also accounting for the impact on accuracy.
Don't use a pull-up resistor that is too small because the larger current sunk by the output may exceed the
desired low-level output voltage (VOL).
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051
TLV4021, TLV4031, TLV4041, TLV4051
SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
www.ti.com
10 Power Supply Recommendations
These devices operate from an input voltage supply range between 1.7 V and 5.5 V.
11 Layout
11.1 Layout Guidelines
A power supply bypass capacitor of 100 nF is recommended when supply output impedance is high, supply
traces are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also
recommended when the comparator output drives a long trace or is required to drive a capacitive load. Due
to the fast rising and falling edge rates and high-output sink and source capability of the TLV40x1 output stage,
higher than normal quiescent current can be drawn from the power supply when the output transitions. Under
this circumstance, the system would benefit from a bypass capacitor across the supply pins.
11.2 Layout Example
VBAT
OUT
V+
IN
V-
C1 (0402)
Figure 11-1. Layout Example
Copyright © 2021 Texas Instruments Incorporated
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TLV4021, TLV4031, TLV4041, TLV4051
SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV4021R1YKAR
TLV4021R2YKAR
TLV4021S5MYKAR
TLV4021S5YKAR
TLV4031R1YKAR
TLV4031R2YKAR
TLV4041R1YKAR
TLV4041R2YKAR
TLV4041R5DBVR
TLV4051R1YKAR
TLV4051R2YKAR
TLV4051R5DBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
SOT-23
DSBGA
DSBGA
SOT-23
YKA
YKA
YKA
YKA
YKA
YKA
YKA
YKA
DBV
YKA
YKA
DBV
4
4
4
4
4
4
4
4
5
4
4
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Z
SNAGCU
SNAGCU
6
Q
3000 RoHS & Green SAC396 | SNAGCU
O
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
SNAGCU
SNAGCU
SNAGCU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
1
7
2
8
23XT
C
9
23ZT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2021
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV4021R1YKAR
TLV4021R2YKAR
TLV4021S5MYKAR
TLV4021S5YKAR
TLV4021S5YKAR
TLV4031R1YKAR
TLV4031R2YKAR
TLV4041R1YKAR
TLV4041R2YKAR
TLV4041R5DBVR
TLV4051R1YKAR
TLV4051R2YKAR
TLV4051R5DBVR
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
SOT-23
DSBGA
DSBGA
SOT-23
YKA
YKA
YKA
YKA
YKA
YKA
YKA
YKA
YKA
DBV
YKA
YKA
DBV
4
4
4
4
4
4
4
4
4
5
4
4
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
178.0
180.0
180.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
9.0
8.4
8.4
9.0
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
2.4
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
2.5
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
0.48
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q3
Q1
Q1
Q3
0.84
0.84
2.4
0.84
0.84
2.5
0.48
0.48
1.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV4021R1YKAR
TLV4021R2YKAR
TLV4021S5MYKAR
TLV4021S5YKAR
TLV4021S5YKAR
TLV4031R1YKAR
TLV4031R2YKAR
TLV4041R1YKAR
TLV4041R2YKAR
TLV4041R5DBVR
TLV4051R1YKAR
TLV4051R2YKAR
TLV4051R5DBVR
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
DSBGA
SOT-23
DSBGA
DSBGA
SOT-23
YKA
YKA
YKA
YKA
YKA
YKA
YKA
YKA
YKA
DBV
YKA
YKA
DBV
4
4
4
4
4
4
4
4
4
5
4
4
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
180.0
182.0
182.0
180.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
180.0
182.0
182.0
180.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
18.0
20.0
20.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YKA0004
DSBGA - 0.4 mm max height
SCALE 14.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.4 MAX
C
SEATING PLANE
0.05 C
0.18
0.13
BALL TYP
0.35 TYP
B
A
SYMM
0.35
TYP
D: Max = 0.76 mm, Min = 0.7 mm
E: Max = 0.76 mm, Min = 0.7 mm
1
2
0.25
0.15
C A B
4X
0.015
SYMM
4221909/B 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.2)
(0.35) TYP
2
1
A
B
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
(
0.2)
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221909/B 08/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.21)
(R0.05) TYP
2
1
A
B
SYMM
(0.35)
TYP
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:60X
4221909/B 08/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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