首页 |元器件品牌

TLV5630 [TI]

8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE; 8通道， 12位/ 10位/ 8位， 2.7 V至5.5 V的低功耗数字 - 模拟转换器与电源关闭和内部参考
TLV5630
型号： TLV5630
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
8通道， 12位/ 10位/ 8位， 2.7 V至5.5 V的低功耗数字 - 模拟转换器与电源关闭和内部参考

转换器
文件： 总15页 (文件大小：267K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG  
CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE  
FEATURES  
APPLICATIONS  
•
•
•
•
•
Digital Servo Control Loops  
Digital Offset and Gain Adjustment  
Industrial Process Control  
Machine and Motion Control Devices  
Mass Storage Devices  
•
Eight Voltage Output DACs in One Package  
– TLV5630 . . . 12-Bit  
– TLV5631 . . . 10-Bit  
– TLV5632 . . . 8-Bit  
– 1 µs in Fast Mode  
DW OR PW PACKAGE  
(TOP VIEW)  
– 3 µs in Slow Mode  
•
Programmable Settling Time vs Power  
Consumption  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DGND  
DIN  
SCLK  
FS  
DV  
DD  
– 1 µs in Fast Mode  
DOUT  
LDAC  
MODE  
REF  
OUTD  
OUTC  
OUTB  
OUTA  
– 3 µs in Slow Mode  
– 18 mW in Slow Mode at 3 V  
– 48 mW in Fast Mode at 3 V  
Compatible With TMS320 and SPI Serial Ports  
Monotonic Over Temperature  
Low Power Consumption:  
– 18 mW in Slow Mode at 3 V  
– 48 mW in Fast Mode at 3 V  
Power-Down Mode  
PRE  
OUTE  
OUTF  
OUTG  
OUTH  
AGND  
•
•
•
AV  
DD  
•
•
•
Internal Reference  
Data Output for Daisy-Chaining  
DESCRIPTION  
The TLV5630, TLV5631, and TLV5632 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs  
each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and  
Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.  
Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs,  
and a data output which can be used to cascade multiple devices, and an internal programmable band-gap  
reference.  
The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to  
allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be  
connected to the supply voltage.  
Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V. The  
devices are available in 20-pin SOIC and TSSOP packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2000–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
AVAILABLE OPTIONS  
PACKAGE  
TA  
SOIC (DW)  
TLV5630IDW  
TLV5631IDW  
TLV5632IDW  
TSSOP (PW)  
TLV5630IPW  
TLV5631IPW  
TLV5632IPW  
RESOLUTION  
12  
10  
8
40°C to 85°C  
FUNCTIONAL BLOCK DIAGARAM  
REF  
Band-Gap  
Voltage  
12/10/8  
12/10/8  
12/10/8  
X2  
OUTA  
1 V or 2 V  
(Trimmed)  
with Enable  
DAC A  
Holding  
Latch  
DAC A  
Latch  
2
SCLK  
DIN  
12  
8
DOUT  
FS  
Serial  
Interface  
OUT  
MODE  
PRE  
B, C, D,  
E, F, G  
and H  
DAC B, C, D, E, F, G and H  
Same as DAC A  
LDAC  
Terminal Functions  
TERMINAL  
NAME NO.  
AGND  
I/O  
DESCRIPTION  
10  
11  
1
P
P
P
I
Analog ground  
AVDD  
Analog power supply  
Digital ground  
DGND  
DIN  
2
Digital serial data input  
Digital serial data output  
Digital power supply  
Frame sync input  
DOUT  
DVDD  
FS  
19  
20  
4
O
P
I
LDAC  
MODE  
PRE  
18  
17  
5
I
Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input.  
DSP/µC mode pin. High = µC mode, NC = DSP mode.  
Preset input  
I
I
REF  
16  
3
I/O Voltage reference input/output  
SCLK  
OUTA-OUTH  
I
Serial clock input  
12-15, 6-9  
O
DAC outputs A, B, C, D, E, F, G and H  
2
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature (unless otherwise noted)  
(1)  
UNIT  
7 V  
Supply voltage, (AVDD, DVDD to GND)  
Reference input voltage range  
- 0.3 V to AVDD + 0.3  
- 0.3 V to DVDD + 0.3  
-40°C to 85°C  
-65°C to 150°C  
260°C  
Digital input voltage range  
Operating free-air temperature range, TA  
Storage temperature range, Tstg  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds  
(1) Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating  
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
MIN  
4.5  
2.7  
2
TYP  
5
MAX  
5.5  
UNIT  
V
5-V operation  
3-V operation  
DVDD = 2.7 V  
DVDD = 5.5 V  
DVDD = 2.7 V  
DVDD = 5.5 V  
AVDD = 5 V  
Supply voltage, AVDD, DVDD  
High-level digital input, VIH  
Low-level digital input, VIL  
Reference voltage, Vref  
3
3.3  
V
V
V
V
2.4  
0.6  
1.0  
GND  
GND  
2
2.048  
1.024  
AVDD  
AVDD  
AVDD = 3 V  
Analog output load resistance, RL  
Analog output load capacitance, CL  
Clock frequency, fCLK  
kΩ  
pF  
100  
30  
MHz  
°C  
Operating free-air temperature, TA  
-40  
85  
3
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
ELECTRICAL CHARACTERISTICS  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
POWER SUPPLY  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Fast  
16  
6
21  
8
No load, All inputs = DVDD or GND,  
Vref = 2.048 V,  
IDD  
Power supply current  
mA  
Slow  
Power-down supply  
current  
0.1  
2
µA  
V
POR  
Power on threshold  
Power supply rejection  
ratio  
(1)  
PSRR  
Full scale, See  
50  
dB  
STATIC DAC SPECIFICATIONS  
TLV5630  
TLV5631  
TLV5632  
TLV5630  
12  
10  
Bits  
Bits  
Bits  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
Resolution  
8
Code 40 to 4095  
Code 20 to 1023  
Code 6 to 255  
±2  
±6  
±2  
±1  
±1  
±1  
±1  
INL  
Integral nonlinearity  
TLV5631  
TLV5632  
TLV5630  
Vref = 1 V, 2 V  
Vref = 1 V, 2 V  
±0.5  
±0.3  
±0.5  
±0.1  
±0.1  
Code 40 to 4095  
Code 20 to 1023  
Code 6 to 255  
DNL  
Differential nonlinearity TLV5631  
TLV5632  
Zero scale error (offset error at zero  
scale)  
EZS  
±30  
mV  
Zero scale error temperature coef-  
ficient  
EZS TC  
30  
10  
µV/°C  
%Full  
Scale V  
EG  
Gain error  
±0.6  
EGTC  
Gain error temperature coefficient  
ppm/°C  
OUTPUT SPECIFICATIONS  
VO  
Voltage output range  
RL = 10 kΩ  
0
AVDD-0.4  
V
Output load regulation  
accuracy  
%Full  
Scale V  
RL = 2 kΩ vs 10 kΩ  
±0.3  
REFERENCE OUTPUT  
VREFOU  
Low reference voltage VDD > 4.75 V  
1.010 1.024  
2.020 2.048  
1.040  
2.096  
1
V
V
TL  
VREFOU  
TH  
High reference voltage  
Output source current  
Iref(Sourc  
mA  
e)  
Iref(Sink) Output sink current  
Load capacitance  
-1  
mA  
µF  
(2)  
See  
1
10  
60  
Power supply rejection  
PSRR  
ratio  
dB  
REFERENCE INPUT  
VI  
RI  
Ci  
Input voltage range  
Input resistance  
0
AVDD  
V
50  
10  
kΩ  
Input capacitance  
pF  
Fast  
2.2  
1.9  
MHz  
MHz  
Reference input  
bandwidth  
Vref = 0.4 Vpp + 2.048 Vdc,  
Input code = 0x800  
Slow  
(1) Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) -  
EG(AVDDmin))/VDDmax]  
(2) In parallel with a 100-nF capacitor  
4
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
ELECTRICAL CHARACTERISTICS (continued)  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
(3)  
Reference feedthrough Vref = 2 Vpp at 1 kHz + 2.048 Vdc, See  
DIGITAL INPUTS  
84  
dB  
IIH  
IIL  
CI  
High-level digital input  
current  
VI = DVDD  
1
µA  
µA  
pF  
Low-level digital input  
current  
VI = 0 V  
1
Input capacitance  
8
5
DIGITAL OUTPUT  
VOH  
High-level digital output RL = 10 kΩ  
voltage  
2.6  
V
V
VOL  
Low-level digital output RL = 10 kΩ  
voltage  
0.4  
10  
Output voltage rise  
time  
RL = 10 kΩ, CL = 20 pF, Includes propagation delay  
ns  
ANALOG OUTPUT DYNAMIC PERFORMANCE  
Fast  
Slow  
Fast  
Slow  
Fast  
Slow  
1
3
3
7
1
2
Output settling time, full  
scale  
(4)  
(5)  
(6)  
ts(FS)  
ts(CC)  
SR  
RL = 10 kΩ, CL = 100 pF, See  
µs  
µs  
0.5  
1
Output settling time,  
code to code  
RL = 10 kΩ, CL = 100 pF, See  
RL = 10 kΩ, CL = 100 pF, See  
4
1
10  
3
Slew rate  
V/µs  
(7)  
Glitch energy  
See  
4
nV-s  
dB  
Channel crosstalk  
10 kHz sine, 4 VPP  
90  
(3) Reference feedthrough is measured at the DAC output with an input code = 0x000.  
(4) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of  
0x080 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.  
(5) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one  
count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.  
(6) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.  
(7) Code transition: TLV5630 - 0x7FF to 0x800, TLV5631 - 0x7FCto 0x800, TLV5632 - 0x7F0 to 0x800.  
DIGITAL INPUT TIMING REQUIREMENTS  
PARAMETER  
MIN TYP MAX UNIT  
tsu(FS-CK)  
tsu(C16-FS)  
Setup time, FS low before next negative SCLK edge  
Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising edge  
of FS. µC mode only  
8
ns  
10  
ns  
tsu(FS-C17)  
tsu(CK-FS)  
twL(LDAC)  
tsu(FS-CK)  
twL  
µC mode, setup time, FS high before 17th positive SCLK.  
DSP mode, setup time, SLCK low before FS low.  
LDAC duration low  
10  
5
ns  
ns  
ns  
ns  
10  
8
Setup time, FS low before first negative SCLK edge  
SCLK pulse duration low  
16  
8
tsu(D)  
Setup time, data ready before SCLK falling edge  
Hold time, data held valid after SCLK falling edge  
FS duration high  
ns  
ns  
ns  
ns  
th(D)  
5
twH(FS)  
twL(FS)  
10  
10  
FS duration low  
See AC  
specs  
ts  
Settling time  
5
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
TYPICAL CHARACTERISTICS  
OUTPUT LOAD REGULATION  
OUTPUT LOAD REGULATION  
1
1
V
V
= 5 V,  
= 2 V,  
V
V
= 3 V,  
= 1 V,  
DD  
DD  
0.9  
0.8  
0.7  
0.9  
0.8  
0.7  
ref  
ref  
Zero Scale  
Zero Scale  
Fast  
Fast  
0.6  
0.5  
0.4  
0.6  
0.5  
0.4  
0.3  
0.2  
0.3  
0.2  
0.1  
0
0.1  
0
Slow  
Slow  
0.5  
1.5  
0.5  
1.5  
0
1
2
0
1
2
Sinking Current − mA  
Sinking Current − mA  
Figure 1.  
Figure 2.  
OUTPUT LOAD REGULATION  
OUTPUT LOAD REGULATION  
2.06  
2.055  
2.05  
4.12  
4.11  
4.1  
V
= 5 V,  
= 2 V,  
DD  
V
= 3 V,  
= 1 V,  
DD  
V
ref  
V
ref  
Full Scale  
Full Scale  
Fast  
Slow  
Fast  
Slow  
4.09  
4.08  
4.07  
2.045  
2.04  
2.035  
2.03  
4.06  
4.05  
4.04  
2.025  
0
−0.5 −1  
−1.5 −2  
−2.5 −3  
−3.5 −4  
−0.05 −0.5 −1  
−1.5 −2  
−2.5 −3  
−3.5 −4  
Sourcing Current − mA  
Sourcing Current − mA  
Figure 3.  
Figure 4.  
6
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
TYPICAL CHARACTERISTICS (continued)  
TLV5630 INTEGRAL NONLINEARITY  
vs  
CODE  
4
3
2
1
0
−1  
−2  
−3  
−4  
0
1024  
2048  
3072  
4096  
Code  
Figure 5.  
TLV5630 DIFFERENTIAL NONLINEARITY  
vs  
CODE  
1.0  
0.8  
0.6  
0.4  
0.2  
−0.0  
−0.2  
−0.4  
−0.6  
−0.8  
−1.0  
0
1024  
2048  
3072  
4096  
Code  
Figure 6.  
TLV5631 INTEGRAL NONLINEARITY  
vs  
CODE  
2.0  
1.5  
1.0  
0.5  
0.0  
−0.5  
−1.0  
−1.5  
−2.0  
0
256  
512  
768  
1024  
Code  
Figure 7.  
7
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
TYPICAL CHARACTERISTICS (continued)  
TLV5631 DIFFERENTIAL NONLINEARITY  
vs  
CODE  
1.0  
0.8  
0.6  
0.4  
0.2  
−0.0  
−0.2  
−0.4  
−0.6  
−0.8  
−1.0  
0
256  
512  
Code  
768  
1024  
Figure 8.  
TLV5632 INTEGRAL NONLINEARITY  
vs  
CODE  
0.5  
0.4  
0.3  
0.2  
0.1  
0
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
0
50  
100  
150  
200  
250  
Code  
Figure 9.  
TLV5632 DIFFERENTIAL NONLINEARITY  
vs  
CODE  
0.5  
0.4  
0.3  
0.2  
0.1  
0
−0.1  
−0.2  
−0.3  
−0.4  
−0.5  
0
50  
100  
150  
200  
250  
Code  
Figure 10.  
8
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
PARAMETER MEASUREMENT INFORMATION  
t
wH  
t
wL  
SCLK  
X
1
2
3
4
16  
17  
X
t
h(D)  
t
su(D)  
DIN  
X
D15  
D14  
D13  
D13  
D12  
D12  
D1  
D1  
D0  
X
X
†
†
†
†
†
†
DOUT  
X
D15  
t
D14  
D0  
t
su(FS - C17)  
su(FS - CK)  
t
t
su(C16 - FS)  
wH(FS)  
FS  
(µC mode)  
t
su(CK - FS)  
t
wL(FS)  
FS  
X
(DSP Mode)  
†
Previous input data  
Figure 11. Serial Interface Timing  
t
wL(LDAC)  
LDAC  
OUTx  
±0.5 LSB  
t
s
Figure 12. Output Timing  
9
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
APPLICATION INFORMATION  
GENERAL FUNCTION  
The TLV5630/31/32 are 8-channel, single-supply DACs, based on a resistor string architecture. They consist of a  
serial interface, a speed and power-down control logic, an internal reference, a resistor string, and a rail-to-rail  
output buffer.  
The output voltage (full scale determined by reference) for each channel is given by:  
CODE  
0x1000  
2REF  
[V]  
where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for  
the TLV5630, 0x000 to 0xFFC for the TLV5631, and 0x000 to 0xFF0 for the TLV5632. A power-on-reset initially  
puts the internal latches to a defined state (all bits zero).  
SERIAL INTERFACE  
A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling  
edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC  
holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to  
transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an  
asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.  
For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.  
DSP Mode:  
SCLK  
FS  
DIN  
X
D15  
D14  
D1  
D0  
E15  
E14  
E1  
E0  
X
X
X
F15  
F15  
µC Mode:  
SCLK  
FS  
DIN  
X
D15  
D14  
D1  
D0  
X
E15  
E14  
E1  
E0  
X
X
F15  
F15  
Difference between DSP mode (MODE = N.C. or 0) and µC (MODE = 1) mode:  
•
In µC mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before  
the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS.  
•
•
In DSP mode, FS needs to stay low for 20 ns and can go high before the 16th falling clock edge.  
In DSP mode there needs to be one falling SCLK edge before FS goes low to start the write (DIN) cycle.  
This extra falling SCLK edge has to happen at least 5 ns before FS goes low, tsu(CK-FS) ≥ 5 ns.  
•
In µC mode, the extra falling SCLK edge is not necessary. However, if it does happen, the extra negative  
SCLK edge is not allowed to occur within 10 ns after FS goes HIGH to finish the WRITE cycle (tsu(FS-C17)).  
10  
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
APPLICATION INFORMATION (continued)  
SERIAL CLOCK FREQUENCY AND UPDATE RATE  
The maximum serial clock frequency is given by:  
1
f
+
+ 30 MHz  
sclkmax  
t
) t  
whmin  
wlmin  
The maximum update rate is:  
1
f
+
+ 1.95 MHz  
updatemax  
16 ǒtwhmin  
Ǔ
) t  
wlmin  
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the  
DAC has to be considered also.  
DATA FORMAT  
The 16-bit data word consists of two parts:  
•
•
Address bits (D15…D12)  
Data bits (D11…D0)  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
A3  
A2  
A1  
A0  
Data  
Ax: Address bits. See table.  
REGISTER MAP  
A3  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1  
A0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION  
DAC A  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DAC B  
DAC C  
DAC D  
DAC E  
DAC F  
DAC G  
DAC H  
CTRL0  
CTRL1  
Preset  
Reserved  
DAC A and B  
DAC C and D  
DAC E and F  
DAC G and H  
11  
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
DAC A-H AND TWO-CHANNEL REGISTERS  
Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the  
complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).  
The TLV5630 decodes all 12 data bits. The TLV5631 decodes D11 to D2 (D1 and D0 are ignored). The TLV5632  
decodes D11 to D4 (D3 to D0 are ignored).  
PRESET  
The outputs of all DAC channels can be driven to a predefined value stored in the Preset register by driving the  
PRE input low. The PRE input is asynchronous to the clock.  
CTRL0  
BIT  
D11  
X
D10  
X
D9  
X
D8  
X
D7  
X
D6  
X
D5  
X
D4  
PD  
0
D3  
DO  
0
D2  
R1  
0
D1  
R0  
0
D0  
IM  
0
Function  
Default  
X
X
X
X
X
X
X
PD  
DO  
: Full device power down  
: DOUT enable  
0 = normal  
0 = disabled  
0 = external  
1 = power down  
1 = enabled  
R1:0 : Reference select bits  
1 = external, 2 = internal 1 V, 3 = internal 2 V  
1 = twos complement  
IM  
X
: Input mode  
: Reserved  
0 = straight binary  
If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to  
daisy-chain multiple DACs on one serial bus.  
CTRL1  
BIT  
D11  
X
D10  
X
D9  
X
D8  
X
D7  
PGH  
0
D6  
PEF  
0
D5  
PCD  
0
D4  
PAB  
0
D3  
SGH  
0
D2  
SEF  
0
D1  
SCD  
0
D0  
SAB  
0
Function  
Default  
X
X
X
X
PXY  
SXY  
XY  
: Power Down DACXY  
: Speed DACXY  
0 = normal 1 = power down  
0 = slow 1 = fast  
: DAC pair AB, CD, EF or GH  
In power-down mode, the amplifiers of the selected DAC pair are disabled and the total power consumption of  
the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by setting the PXY  
bit within the data word to 1.  
There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to 1 and  
slow mode is selected by setting SXY to 0.  
12  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2004, Texas Instruments Incorporated  

相关型号：

TLV5630IDW

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5630IDWG4

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5630IDWR

 SERIAL INPUT LOADING, 3us SETTLING TIME, 12-BIT DAC, PDSO20, GREEN, PLASTIC, SOIC-20
TI

TLV5630IDWRG4

 SERIAL INPUT LOADING, 3us SETTLING TIME, 12-BIT DAC, PDSO20, GREEN, PLASTIC, SOIC-20
TI

TLV5630IPW

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5630IPWG4

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5630IPWR

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5630IPWRG4

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5631

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5631IDW

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5631IDWG4

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI

TLV5631IDWR

 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE
TI
©2020 ICPDF网 联系我们和版权申明