TLV6001-Q1 [TI]
汽车级、单路、5.5V、1MHz、RRIO 运算放大器;
| 型号： | TLV6001-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、单路、5.5V、1MHz、RRIO 运算放大器 放大器 运算放大器 |
| 文件： | 总34页 (文件大小：2524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
适用于成本敏感型系统的 TLV600x-Q1 低功耗、轨至轨输入/输出、1MHz
运算放大器
1 特性
TLV600x-Q1 采用稳健耐用的设计，方便电路设计人员
使用：该器件在容性负载高达 150pF 的条件下具有单
位增益稳定性，集成了射频/EMI 抑制滤波器，在过驱
条件下无相位反转，并具有高静电放电 (ESD) 保护
(4kV HBM)。
1
•
符合面向汽车应用的 AEC-Q100 标准
–
–
–
器件温度等级 1：–40°C 至 +125°C，TA
器件 HBM ESD 分类等级 3A
器件 CDM ESD 分类等级 C6
•
•
•
•
•
•
•
•
•
•
适用于成本敏感型系统的通用型放大器
电源电压范围：1.8V 至 5.5V
增益带宽：1MHz
这些器件经过优化，适合在低至 1.8V (±0.9V) 和高达
5.5V (±2.75V) 的电压下工作，并且具有 –40°C 至
+125°C 的额定扩展工作温度范围。
低静态电流：75μA/通道
轨至轨输入和输出
单通道 TLV6001-Q1 采用 SC70-5 封装，双通道
TLV6002-Q1 采用 SOIC 和 VSSOP 封装。
低失调电压：0.75mV
器件信息(1)
单位增益稳定
输入电压噪声密度：1kHz 时为 28nV/√Hz
内部射频和电磁干扰滤波器
器件型号
封装
SC70 (5)
封装尺寸（标称值）
2.00mm × 1.25mm
3.91mm × 4.90mm
3.00mm × 3.00mm
TLV6001-Q1
扩展温度范围：
–40°C 至 125°C
SOIC (8)
TLV6002-Q1
VSSOP (8)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
•
•
针对 AEC-Q100 等级 1 应用进行了 优化
CMRR 和 PSRR 与温度间的关系
电动汽车逆变器
信息娱乐系统
被动安全
110
105
PSRR
100
95
90
车身电子装置和照明
CMRR
85
80
75
70
65
60
3 说明
TLV600x-Q1 系列单通道和双通道运算放大器专为通用
汽车 应用而设计。该系列具有轨至轨输入和输出
(RRIO) 摆幅、低静态电流（典型值为 75µA）、高带
宽 (1MHz) 以及超低噪声（1kHz 时为 28nV/√Hz）等
特性，因此对于需要在成本与性能之间实现良好平衡的
各种 汽车应用（如信息娱乐系统、发动机控制单元和
汽车照明）而言很具有吸引力。低输入偏置电流（典型
值为 ±1pA）使 TLV600x-Q1 适合用于 具有 兆欧级源
阻抗的应用。
-50
-25
0
25
50
75
100
125
C001
Temperature (oC)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS934
TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
目录
7.5 Input and ESD Protection ....................................... 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
8.3 System Examples .................................................. 16
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information: TLV6001-Q1 ........................... 6
6.5 Thermal Information: TLV6002-Q1 ........................... 6
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example: Single Channel.......................... 18
10.3 Layout Example: Dual Channel ............................ 19
11 器件和文档支持 ..................................................... 20
11.1 文档支持................................................................ 20
11.2 相关链接................................................................ 20
11.3 接收文档更新通知 ................................................. 20
11.4 社区资源................................................................ 20
11.5 商标....................................................................... 20
11.6 静电放电警告......................................................... 20
11.7 术语表 ................................................................... 20
12 机械、封装和可订购信息....................................... 21
6.6 Electrical Characteristics: VS = 1.8 V to 5 V (±0.9 V
to ±2.75 V) ................................................................. 7
6.7 Typical Characteristics: Table of Graphs.................. 8
6.8 Typical Characteristics.............................................. 9
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
7
4 修订历史记录
Changes from Original (August 2018) to Revision A
Page
•
•
•
已添加 在数据表中添加了 TLV6002-Q1 器件 ......................................................................................................................... 1
已添加 在整个数据表中添加 TLV6002-Q1 器件的双通道信息................................................................................................ 1
已添加 添加了 TLV600x-Q1 系列的 ESD 分类级别................................................................................................................ 1
2
Copyright © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
5 Pin Configuration and Functions
TLV6001-Q1 DCK Package
5-Pin SC70
Top View
+IN
Vœ
1
2
3
5
V+
+
œ
œIN
4
OUT
Not to scale
Pin Functions: TLV6001-Q1
PIN
I/O
DESCRIPTION
NAME
–IN
NO.
3
I
Inverting input
+IN
1
I
Noninverting input
OUT
V–
4
O
—
—
Output
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
Copyright © 2018, Texas Instruments Incorporated
3
TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
TLV6002-Q1 D, DGK Packages
8-Pin SOIC, VSSOP
Top View
OUT A
1
2
3
4
8
7
6
5
V+
œIN A
+IN A
Vœ
OUT B
œIN B
+IN B
Not to scale
Pin Functions: TLV6002-Q1
PIN
I/O
DESCRIPTION
NAME
–IN A
–IN B
+IN A
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
6
3
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
4
Copyright © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage (V+) – (V–)
Voltage
7
(V+) + 0.5
10
V
Signal input pins, voltage(2)
Signal input pins, current(2)
Output short-circuit(3)
Operating, TA
(V–) – 0.5
–10
Current
mA
°C
Continuous
–40
150
150
150
Temperature
Junction, TJ
Storage, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 3A
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
MAX
UNIT
V
VS
TA
Supply voltage
5.5
Specified temperature
–40
125
°C
Copyright © 2018, Texas Instruments Incorporated
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TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
6.4 Thermal Information: TLV6001-Q1
TLV6001-Q1
DCK (SC70)
5 PINS
281.4
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
91.6
59.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.5
ψJB
58.8
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Thermal Information: TLV6002-Q1
TLV6002-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
131.6
71.4
DGK (VSSOP)
8 PINS
186.0
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
73.2
75.4
107.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
22.7
14.4
ψJB
74.6
105.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
6.6 Electrical Characteristics: VS = 1.8 V to 5 V (±0.9 V to ±2.75 V)(1)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
0.75
2
4.5
mV
µV/°C
dB
dVOS/dT
PSRR
VOS vs temperature
TA = –40°C to +125°C
Power-supply rejection ratio
86
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
TA = 25°C
±1
±1
pA
pA
IOS
INPUT IMPEDANCE
ZID
ZIC
Differential
Common-mode
100 || 1
1 || 5
MΩ || pF
1013Ω || pF
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
No phase reversal, rail-to-rail input
VCM = –0.2 V to 5.7 V
(V–) – 0.2
60
(V+) + 0.2
V
CMRR
76
dB
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ
90
110
65
Phase margin
VS = 5 V, G = 1
°
OUTPUT
RL = 100 kΩ
RL = 2 kΩ
5
75
VO
Voltage output swing from supply rails
mV
100
ISC
RO
Short-circuit current
±15
2300
mA
Open-loop output impedance
Ω
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
1
0.5
5
MHz
V/µs
µs
Slew rate
tS
Settling time
To 0.1%, VS = 5 V, 2-V step , G = +1
NOISE
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
f = 0.1 Hz to 10 Hz
f = 1 kHz
6
28
5
µVPP
en
in
nV/√Hz
fA/√Hz
f = 1 kHz
POWER SUPPLY
VS
IQ
Specified voltage range
1.8 (±0.9)
5.5 (±2.75)
100
V
Quiescent current per amplifier
Power-on time
IO = 0 mA, VS = 5 V
75
10
µA
µs
VS = 0 V to 5 V, to 90% IQ level
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted.
Overtemperature limits are based on characterization and statistical analysis.
版权 © 2018, Texas Instruments Incorporated
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TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
6.7 Typical Characteristics: Table of Graphs
表 1. Table of Graphs
TITLE
FIGURE
图 1
Open-Loop Gain and Phase vs Frequency
Quiescent Current vs Supply Voltage
图 2
Offset Voltage Production Distribution
图 3
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
CMRR and PSRR vs Frequency (RTI)
图 4
图 5
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Input Bias and Offset Current vs Temperature
Open-Loop Output Impedance vs Frequency
Maximum Output Voltage vs Frequency and Supply Voltage
Output Voltage Swing vs Output Current
图 6
图 7
图 8
图 9
图 10
图 11
图 12
图 13
图 14
图 15
图 16
图 17
图 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Small-Signal Step Response, Noninverting (1.8 V)
Small-Signal Step Response, Noninverting (5.5 V)
Large-Signal Step Response, Noninverting (1.8 V)
Large-Signal Step Response, Noninverting (5.5 V)
No Phase Reversal
EMIRR IN+ vs Frequency
8
版权 © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
6.8 Typical Characteristics
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
140
120
100
80
180
135
90
45
0
60
58
56
54
52
50
48
46
44
42
40
Gain
Phase
CL = 10 pF
60
40
20
CL = 100 pF
0
-20
1
10
100
1k
10k 100k 1M
10M 100M
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Frequency (Hz)
C003
Supply Voltage (V)
图 1. Open-Loop Gain and Phase vs Frequency
图 2. Quiescent Current vs Supply
1500
1200
900
9
8
7
6
5
4
3
2
1
0
600
300
0
-300
-600
-900
-1200
-1500
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Common-Mode Voltage (V)
Offset Voltage (mV)
C007
C005
图 3. Offset Voltage Production Distribution
图 4. Offset Voltage vs Common-Mode Voltage
120
100
80
60
40
20
0
+PSRR
CMRR
-PSRR
Time (1 s/div)
10
100
1k
10k
100k
1M
C009
C011
Frequency (Hz)
图 5. CMRR and PSRR vs Frequency (Referred-to-Input)
图 6. 0.1-Hz to 10-Hz Input Voltage Noise
版权 © 2018, Texas Instruments Incorporated
9
TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
1000
100
10
200
150
100
50
VS = 1.8 V
IBN
IBP
0
VS = 5.5 V
IOS
-50
-100
1
1
10
100
1k
10k
100k
C012
-50
-25
0
25
50
75
100
125
C014
Frequency (Hz)
Temperature (oC)
图 7. Input Voltage Noise Spectral Density vs Frequency
图 8. Input Bias and Offset Current vs Temperature
100k
6
5
VS = 5.5 V
4
VS = 1.8 V
VS = 1.8 V
3
10k
2
1
0
VS = 5.5 V
1000
1000
10k
100k
1M
1
10
100
1k
10k
100k
Frequency (Hz)
C016
Frequency (Hz)
C015
图 9. Open-Loop Output Impedance vs Frequency
图 10. Maximum Output Voltage vs Frequency and Supply
Voltage
3
40
G = +10 V/V
2
1
20
G = +1 V/V
o
o
-40 o
C
+125C
+25
C
0
0
-1
-2
-3
G = -1 V/V
-20
10
100
1k
10k
100k
1M
10M
100M
0
5
10
Output Current (mA)
15
20
Frequency (Hz)
C018
C017
图 11. Output Voltage Swing vs Output Current
图 12. Closed-Loop Gain vs Frequency
(Minimum Supply)
10
版权 © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
CL = 100 pF
CL = 100 pF
VIN
VIN
CL = 10 pF
CL = 10 pF
Time (1 µs/div)
C004
Time (1 µs/div)
C023
图 13. Small-Signal Pulse Response (Minimum Supply)
图 14. Small-Signal Pulse Response (Maximum Supply)
VOUT
VOUT
VIN
VIN
Time (2.5 µs/div)
Time (2.5 µs/div)
C024
C025
图 15. Large-Signal Pulse Response (Minimum Supply)
图 16. Large-Signal Pulse Response (Maximum Supply)
120
100
80
60
40
20
0
VOUT
VIN
Time (125 µs/div)
10
100
1000
10000
C028
Frequency (MHz)
C033
图 17. No Phase Reversal
图 18. EMIRR IN+ vs Frequency
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ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
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7 Detailed Description
7.1 Overview
The TLV600x-Q1 family of operational amplifiers is a general-purpose, low-cost family that is designed for a wide
range of portable applications. Rail-to-rail input and output swings, low quiescent current, and wide dynamic
range make the operational amplifier designed to drive sampling analog-to-digital converters (ADCs) and other
single-supply applications.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
12
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ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
7.3 Feature Description
7.3.1 Operating Voltage
The TLV600x-Q1 family is fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V).The Typical
Characteristics section shows parameters that vary with supply voltage.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV600x-Q1 family extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as the Functional Block Diagram section shows. The N-channel pair is active for input
voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel
pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small
transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region
can vary up to 300 mV with process variation. As a result, the transition region (both stages on) can range from
(V+) – 1.7 V to (V+) – 1.5 V on the low end, and up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this
transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation
outside this region.
7.3.3 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the TLV600x-Q1 family delivers a robust output
drive capability. A class AB output stage with common source transistors achieve full rail-to-rail output swing
capability. For resistive loads up to 100 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power supply voltage that is applied. 图 11 shows that different load conditions change the
ability of the amplifier to swing close to the rails.
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the TLV600x-Q1 family is specified in several ways so the best match for a given application can be
used; see the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the
transition region (VCM < (V+) – 1.3 V) is shown. This specification is the best indicator of the capability of the
device when the application requires the use of one of the differential input pairs. Second, the CMRR over the
entire common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen
through the transition region, as 图 4 shows.
7.3.5 Capacitive Load and Stability
The TLV600x-Q1 family is designed to be used in applications where driving a capacitive load is required. As
with all operational amplifiers, there can be specific instances where the TLV600x-Q1 family can become
unstable. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to
consider when establishing if an amplifier is stable in operation. An operational amplifier in the unity-gain (1-V/V)
buffer configuration that drives a capacitive load exhibits a greater tendency for instability than an amplifier that is
operated at a higher noise gain. The capacitive load in conjunction with the op amp output resistance creates a
pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases
as the capacitive loading increases. When operating in the unity-gain configuration, the TLV600x-Q1 family
remains stable with a pure capacitive load up to approximately 1 nF. The equivalent series resistance (ESR) of
some capacitors (CL greater than 1 µF) is sufficient to alter the phase characteristics in the feedback loop such
that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive
increasingly larger capacitance. This increased capability is evident when observing the overshoot response of
the amplifier at higher voltage gains.
版权 © 2018, Texas Instruments Incorporated
13
TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
Feature Description (接下页)
One technique for increasing the capacitive load drive capability of the amplifier when the device operates in a
unity-gain configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as 图 19
shows. This resistor reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
图 19. Improving Capacitive Load Drive
7.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the dc offset observed at the amplifier output can shift from the nominal value
while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions can be affected by EMI, the signal input pins are likely to be the most
susceptible. The TLV600x-Q1 family incorporates an internal input low-pass filter that reduces the amplifiers
response to EMI. This filter provides common-mode and differential mode filtering. The filter is designed for a
cutoff frequency of approximately 35 MHz (–3 dB) with a rolloff of 20 dB per decade.
Texas Instruments developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. 图 18 shows the results of this testing on
the TLV600x-Q1 family. EMI Rejection Ratio of Operational Amplifiers shows detailed information, and is
available for download from www.ti.com.
7.4 Device Functional Modes
The TLV600x-Q1 family has a single functional mode. The device is powered on if the power-supply voltage is
between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
7.5 Input and ESD Protection
The TLV600x-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power supply pins. The ESD protection diodes provide in-circuit, input overdrive protection if the
current is limited to 10 mA, as the Absolute Maximum Ratings lists. 图 20 shows how a series input resistor can
be added to the driven input to limit the input current. The added resistor contributes thermal noise at the
amplifier input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
VOUT
Device
VIN
5 kW
图 20. Input Current Protection
14
版权 © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV600x-Q1 is a low-power, rail-to-rail input and output operational amplifier specifically designed for
portable applications. The device operates from 1.8 V to 5.5 V, is unity-gain stable, and is designed for a wide
range of general-purpose applications. The class AB output stage can drive ≤ 10-kΩ loads connected to any
point between V+ and ground. The input common-mode voltage range includes both rails and allows the
TLV600x-Q1 family to be used in any single-supply application.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as 图 21 shows. An inverting amplifier
takes a positive voltage on the input and outputs a signal inverted to the input, making a negative voltage of the
same magnitude. In the same manner, the amplifier makes negative input voltages positive on the output. To add
amplification, select an input resistor (RI) and a feedback resistor (RF.)
RF
VSUP+
RI
VOUT
+
VIN
VSUPœ
图 21. Application Schematic
8.2.1 Design Requirements
Select a supply voltage value that is larger than the input voltage range and the desired output range. Users
must consider the limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) .
For example, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at ±2.5 V is
sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Use 公式 1 and 公式 2 to calculate the required gain for the inverting amplifier:
VOUT
AV
=
V
IN
(1)
(2)
1.8
AV
=
= -3.6
-0.5
版权 © 2018, Texas Instruments Incorporated
15
TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
Typical Application (接下页)
When the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures the device does not draw too much current. The trade-off is that large resistors
(hundreds of kilohms) draw the smallest current but generate the highest noise. Small resistors (hundreds of
ohms) generate low noise but draw high current. In this example, RI equals 10 kΩ, and RF equals 36 V. 公式 3
determines these values:
RF
AV = -
RI
(3)
8.2.3 Application Curve
2
1.5
1
Input
Output
0.5
0
-0.5
-1
-1.5
-2
Time
图 22. Inverting Amplifier Input and Output
8.3 System Examples
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
To establish this minimum bandwidth, place an RC filter at the noninverting pin of the amplifier, as 图 23 shows.
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
图 23. Single-Pole Low-Pass Filter
16
版权 © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
System Examples (接下页)
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as 图 24 shows. For best results, the amplifier must have a bandwidth that is 8 to 10 times larger than the
filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
R1
R2
Q = Peaking factor
(Butterworth Q = 0.707)
VIN
VOUT
C2
1
2pRC
f
=
-3 dB
RF
RF
RG
=
1
2 -
RG
(
(
Q
图 24. Two-Pole, Low-Pass, Sallen-Key Filter
9 Power Supply Recommendations
The TLV600x-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). The Typical
Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage
or temperature.
CAUTION
Supply voltages larger than 7 V may permanently damage the device. (See the
Absolute Maximum Ratings ).
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
版权 © 2018, Texas Instruments Incorporated
17
TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit and the operational
amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques (available for download from
www.ti.com).
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better
than crossing in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input in order to minimize parasitic capacitance, as shown in 图 25.
Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example: Single Channel
Run the input traces
as far away from
VS+
the supply lines
VIN
as possible.
VSœ
+IN
Vœ
V+
GND
Use a low-ESR,
ceramic bypass
capacitor.
Use a low-ESR,
ceramic bypass
capacitor.
RG
OUT
œIN
VOUT
GND
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
图 25. Operational Amplifier Board Layout for Noninverting Configuration
VIN
+
VOUT
RG
RF
图 26. Schematic Representation of 图 25
18
版权 © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
10.3 Layout Example: Dual Channel
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
图 27. Schematic Representation for 图 25
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
VIN 1
GND
VIN 2
RG
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
图 28. Layout Example
版权 © 2018, Texas Instruments Incorporated
19
TLV6001-Q1, TLV6002-Q1
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
德州仪器 (TI)，《运算放大器的 EMI 抑制比》
德州仪器 (TI)，《电路板布局技巧》
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TLV6001-Q1
TLV6002-Q1
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
20
版权 © 2018, Texas Instruments Incorporated
TLV6001-Q1, TLV6002-Q1
www.ti.com.cn
ZHCSIO7A –AUGUST 2018–REVISED DECEMBER 2018
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV6001QDCKRQ1
TLV6002QDGKRQ1
TLV6002QDRQ1
ACTIVE
ACTIVE
ACTIVE
SC70
VSSOP
SOIC
DCK
DGK
D
5
8
8
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
1B1
NIPDAUAG
NIPDAU
1NX6
V6002Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV6001QDCKRQ1
TLV6002QDGKRQ1
TLV6002QDRQ1
SC70
VSSOP
SOIC
DCK
DGK
D
5
8
8
3000
2500
2500
180.0
330.0
330.0
8.4
2.47
5.3
2.3
3.4
5.2
1.25
1.4
4.0
8.0
8.0
8.0
Q3
Q1
Q1
12.4
12.4
12.0
12.0
6.4
2.1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV6001QDCKRQ1
TLV6002QDGKRQ1
TLV6002QDRQ1
SC70
VSSOP
SOIC
DCK
DGK
D
5
8
8
3000
2500
2500
183.0
366.0
340.5
183.0
364.0
336.1
20.0
50.0
25.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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