TLV62085 [TI]
采用 2x2 QFN 封装的 3A 高效降压转换器;
| 型号： | TLV62085 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2x2 QFN 封装的 3A 高效降压转换器 转换器 |
| 文件： | 总25页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
TLV62085 采用 2mm × 2mm VSON 封装的高效 3A 降压转换器
1 特性
3 说明
1
•
DCS-Control™拓扑
效率高达 95%
TLV62085 器件是一款高频同步降压转换器，经优化具
有小解决方案尺寸和高效率两大优点。该器件具有
2.5V 至 6.0V 的输入电压范围，支持常见的电池技
术。此器件主要用于宽输出电流范围内的高效降压转
换。该转换器在中等程度的负载到高负载时运行于脉宽
调制 (PWM) 模式，并在轻负载时自动进入省电模式运
行，从而在整个负载电流范围内保持高效率。
•
•
•
17μA 工作静态电流
31mΩ 和 23mΩ 功率金属氧化物半导体场效应晶体
管 (MOSFET) 开关
•
•
•
•
•
•
•
•
•
输入电压范围：2.5V 至 6.0V
可调输出电压：0.8V 至 VIN
可在轻载条件下实现高效率的省电模式
可实现 100% 占空比，以确保最低压降
自动切断短路保护功能
输出放电
为了满足系统电源轨的需求，内部补偿电路支持宽范围
的外部输出电容值选项，10µF 到 150uF 甚至更高。
加上其 DCS-Control™架构，出色的负载瞬态性能和精
确的输出电压调整均可实现。此器件采用 2mm x 2mm
VSON 封装。
电源正常输出
热关断保护
器件信息(1)
采用 2mm × 2mm 超薄小外形尺寸无引线 (VSON)
封装
器件型号
TLV62085
封装
VSON (7)
封装尺寸（标称值）
2.00mm × 2.00mm
•
•
如需了解改进的特性集，请参见 TPS62085
借助 WEBENCH® Power Designer 并使用
TLV62085 创建定制设计方案
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
•
电池供电类 应用
负载点
处理器电源
传统硬盘 (HDD)/固态硬盘 (SSD)
垫圈
垫圈
垫圈
典型应用电路原理图
VIN = 5V 时的效率
L1
0.47µH
TLV62085
100
VIN
2.5V to 6V
VOUT
VIN
EN
SW
VOS
FB
1.8V
C1
10µF
C2
22µF
R1
138k
R3
1M
90
80
70
R2
110k
GND
PG
POWER GOOD
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 3.3 V
60
1m
10m
100m
1
5
Load (A)
D008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD63
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Typical Characteristics.............................................. 5
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 8
8
9
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations........................................ 15
11 器件和文档支持 ..................................................... 16
11.1 开发支持................................................................ 16
11.2 文档支持................................................................ 16
11.3 接收文档更新通知 ................................................. 16
11.4 社区资源................................................................ 16
11.5 商标....................................................................... 16
11.6 静电放电警告......................................................... 16
11.7 术语表 ................................................................... 16
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
Changes from Revision A (January 2017) to Revision B
Page
•
已添加 图 3 to power save mode section ............................................................................................................................... 7
Changes from Original (October 2015) to Revision A
Page
•
•
•
已添加 WEBENCH™ 信息和超链接至特性、详细设计流程和器件支持部分 .......................................................................... 1
Added SW (AC) to the Absolute Maximum Rating table ....................................................................................................... 4
已添加 表 1, PG Pin Logic...................................................................................................................................................... 8
2
Copyright © 2015–2018, Texas Instruments Incorporated
TLV62085
www.ti.com.cn
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
5 Pin Configuration and Functions
RLT Package
7-Pin VSON
Top View
1
2
3
4
EN
7
6
5
VIN
SW
PG
FB
GND
VOS
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
EN
1
IN
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the
device. This pin has a pulldown resistor of typically 400 kΩ when the device is disabled.
FB
3
5
2
IN
Feedback pin. Connect a resistor divider to set the output voltage.
Ground pin.
GND
PG
OUT
Power good open drain output pin. The pullup resistor can not be connected to any voltage higher than 6 V. If
unused, leave it floating.
SW
6
7
4
PWR Switch pin of the power stage.
PWR Input voltage pin.
VIN
VOS
IN
Output voltage sense pin. This pin must be directly connected to the output capacitor.
Copyright © 2015–2018, Texas Instruments Incorporated
3
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
– 0.3
– 0.3
– 3
MAX
7
UNIT
VIN, FB, VOS, EN, PG
Voltage at Pins(2)
Temperature
SW (DC)
VIN + 0.3
11
V
SW (AC, less than 100ns)(3)
Operating Junction, TJ
Storage, Tstg
– 40
– 65
150
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
MIN NOM
2.5
MAX UNIT
VIN
Input voltage range
Output voltage range
6
VIN
1
V
V
VOUT
0.8
ISINK_PG Sink current at PG pin
mA
V
VPG
TJ
Pullup resistor voltage
6
Operating junction temperature
–40
125
°C
(1) Refer to Application and Implementation for further information.
6.4 Thermal Information
TLV62085
RLT [VSON]
7 PINS
107.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
66.2
17.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.1
ψJB
17.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2015–2018, Texas Instruments Incorporated
TLV62085
www.ti.com.cn
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
6.5 Electrical Characteristics
TJ = 25 °C, and VIN = 3.6 V, unless otherwise noted.
PARAMETER
SUPPLY
TEST CONDITIONS
MIN
TYP
MAX UNIT
IQ
Quiescent current into VIN
No load, device not switching
17
0.7
2.2
200
150
20
µA
µA
ISD
Shutdown current into VIN
EN = Low
VIN falling
VIN rising
TJ rising
Under voltage lock out threshold
Under voltage lock out hysteresis
Thermal shutdown threshold
Thermal shutdown hysteresis
2.1
2.3
0.4
V
VUVLO
mV
°C
°C
TJSD
TJ falling
LOGIC INTERFACE EN
VIH
VIL
High-level input voltage
Low-level input voltage
VIN = 2.5 V to 6.0 V
VIN = 2.5 V to 6.0 V
EN = High
1.0
V
V
IEN,LKG Input leakage current into EN pin
RPD Pull-down resistance at EN pin
SOFT START, POWER GOOD
0.01
400
µA
kΩ
EN = Low
tSS
Soft start time
Time from EN high to 95% of VOUT nominal
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
Isink = 1 mA
0.8
95%
90%
ms
VPG
Power good threshold
VPG,OL Low-level output voltage
IPG,LKG Input leakage current into PG pin
OUTPUT
0.4
V
VPG = 5.0 V
0.01
µA
PWM mode, 2.5 V ≤ VIN ≤ 6 V
TJ = 0°C to 85 °C
VFB
Feedback regulation voltage
792
800
808
mV
IFB,LKG Feedback input leakage current
RDIS Output discharge resistor
POWER SWITCH
VFB = 1 V
0.01
260
µA
EN = LOW, VOUT = 1.8 V
Ω
High-side FET on-resistance
ISW = 500 mA
ISW = 500 mA
31
23
mΩ
mΩ
A
RDS(on)
Low-side FET on-resistance
High-side FET switch current limit
PWM switching frequency
ILIM
fSW
3.7
4.6
2.4
5.5
IOUT = 1 A
MHz
6.6 Typical Characteristics
5x106
106
105
104
103
VIN = 2.5 V
VIN = 3.6 V
VIN = 6.0 V
1m
10m
100m
1
5
Load (A)
D007
VOUT = 1.2 V
图 1. Switching Frequency
版权 © 2015–2018, Texas Instruments Incorporated
5
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TLV62085 synchronous step-down converter is based on the DCS-Control (Direct Control with Seamless
transition into Power Save Mode) topology. This is an advanced regulation topology that combines the
advantages of hysteretic, voltage, and current mode control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC's
current consumption to achieve high efficiency over the entire load current range. Because DCS-Control supports
both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage. The device offers both excellent DC voltage
and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with
RF circuits.
7.2 Functional Block Diagram
PG
Hiccup
Counter
VFB
VIN
VREF
High Side
Current Sense
Bandgap
Undervoltage Lockout
Thermal Shutdown
EN
400kΩ(1)
SW
MOSFET Driver
Control Logic
GND
VOS
Ramp
Direct Control
and
Compensation
Comparator
Timer
ton
FB
VREF
Error Amplifier
260Ω
DCS - Control TM
Output Discharge
Logic
EN
Note:
(1) When the device is enabled, the 400 kΩ resistor is disconnected.
图 2. Functional Block Diagram
6
版权 © 2015–2018, Texas Instruments Incorporated
TLV62085
www.ti.com.cn
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
7.3 Feature Description
7.3.1 Power Save Mode
As the load current decreases, the TLV62085 enters Power Save Mode (PSM) operation. During Power Save
Mode, the converter operates with reduced switching frequency and with a minimum quiescent current
maintaining high efficiency. Power Save Mode occurs when the inductor current becomes discontinuous. Power
Save Mode is based on a fixed on-time architecture, as related in 公式 1. The switching frequency over the
whole load current range is also shown in 图 1 for a shown typical application.
VOUT
tON = 420 ns´
V
IN
2´IOUT
fPFM
=
V
VIN - VOUT
´
2
tON
IN
´
VOUT
L
(1)
In PSM, the output voltage rises slightly above the nominal output voltage, as shown in 图 10. This effect is
minimized by increasing the output capacitor or inductor value.
During PAUSE period in PSM (shown in 图 3), the device does not change the PG pin state nor does it detect an
UVLO event, in order to achieve a minimum quiescent current and maintain high efficiency at light loads.
VOUT
tPAUSE
IINDUCTOR
tON
图 3. Power Save Mode Waveform Diagram
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
V
= VOUT + IOUT,MAX ´(RDS(on) + RL )
IN,MIN
with
•
•
•
•
VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR)
(2)
7.3.3 Soft Start
The TLV62085 has an internal soft-start circuitry which monotonically ramps up the output voltage and reaches
the nominal output voltage during a soft-start time of typically 0.8 ms. This avoids excessive inrush current and
creates a smooth output voltage slope. It also prevents excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance. The device is able to start into a prebiased output capacitor.
The device starts with the applied bias voltage and ramps the output voltage to its nominal value.
版权 © 2015–2018, Texas Instruments Incorporated
7
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
Feature Description (接下页)
7.3.4 Switch Current Limit and Hiccup Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET is turned on to ramp down the inductor current. When this switch current
limits is triggered 32 times, the device stops switching and enables the output discharge. The device then
automatically starts a new start-up after a typical delay time of 66 µs has passed. This is named HICCUP short-
circuit protection. The device repeats this mode until the high load condition disappears.
7.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the device at voltages lower than VUVLO with a hysteresis of 200 mV.
7.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 Device Functional Modes
7.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN pin
is pulled LOW with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 260 Ω discharges the output through the VOS pin smoothly. The output discharge function also works
when thermal shutdown, UVLO, or short-circuit protection are triggered.
An internal pulldown resistor of 400 kΩ is connected to the EN pin when the EN pin is LOW. The pulldown
resistor is disconnected when the EN pin is HIGH.
7.4.2 Power Good
The TLV62085 has a power good output. The power good goes high impedance once the output is above 95%
of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 6 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. 表 1 shows the
PG pin logic.
表 1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
LOW
EN = High, VFB ≥ VPG
EN = High, VFB ≤ VPG
EN = Low
√
Enable
√
√
√
√
Shutdown
Thermal Shutdown
UVLO
TJ > TJSD
0.5 V < VIN < VUVLO
VIN ≤ 0.5 V
Power Supply Removal
√
8
版权 © 2015–2018, Texas Instruments Incorporated
TLV62085
www.ti.com.cn
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV62085 is a synchronous step-down converter in which output voltage is adjusted by component
selection. The following section discusses the design of the external components to complete the power supply
design for several input and output voltage options by using the typical applications as a reference.
8.2 Typical Application
L1
0.47µH
TLV62085
VIN
VOUT
VIN
EN
SW
VOS
FB
2.5V to 6V
1.8V
C1
10µF
C2
22µF
R1
138k
R3
1M
R2
110k
GND
PG
POWER GOOD
图 4. 1.8-V Output Voltage Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
2.5 V to 6 V
1.8 V
Output voltage
Output current
≤ 3 A
Output ripple voltage
<30 mV
表 3 lists the components used for the example.
(1)
表 3. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
C1
C2
L1
10 µF, Ceramic capacitor, 10 V, X7R, size 0805, GRM21BR71A106ME51L
22 µF, Ceramic capacitor, 6.3 V, X5R, size 0805, GRM21BR60J226ME39L
0.47 µH, Power Inductor, size 4 mm × 4 mm × 1.5 mm, XFL4015-471ME
Depending on the output voltage, 1%, size 0603;
Murata
Murata
Coilcraft
Std
R1
R2
R3
110 kΩ, Chip resistor, 1/16 W, 1%, size 0603;
Std
1 MΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
(1) See Third-Party Products discalimer.
版权 © 2015–2018, Texas Instruments Incorporated
9
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TLV62085 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
–
–
–
–
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand the thermal performance of your board
Export your customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting The Output Voltage
The output voltage is set by an external resistor divider according to 公式 3:
R1
R1
æ
ö
æ
ö
VOUT = VFB ´ 1+
= 0.8 V ´ 1+
ç
÷
ç
÷
R2
R2
è
ø
è
ø
(3)
R2 must not be higher than 180 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity.
8.2.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process, 表 4
outlines possible inductor and capacitor value combinations for most applications.
表 4. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](2)
NOMINAL L [µH](1)
10
22
47
+
100
+
150
+
(3)
0.47
1
+
+
+
+
+
+
2.2
(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and
–30%.
(2) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by
20% and –50%.
(3) Typical application configuration. Other '+' mark indicates recommended filter combinations.
8.2.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, 公式 4 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
where
•
•
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
10
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TLV62085
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ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
•
•
fSW = Switching frequency
L = Inductor value
(4)
TI recommends choosing the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of 公式 4.
A higher inductor value is also useful to lower ripple current but increases the transient response time as well.
The following inductors are recommended to be used in designs.
(1)
表 5. List of Recommended Inductors
INDUCTANCE
[µH]
CURRENT RATING
[A]
DIMENSIONS
DC RESISTANCE
[mΩ typical]
PART NUMBER
L × W × H [mm3]
0.47
0.47
1
6.6
4.7
5.1
4 × 4 × 1.5
3.2 × 2.5 × 1.2
4 × 4 × 2
7.6
21
Coilcraft XFL4015-471
TOKO DFE322512-R47N
Coilcraft XFL4020-102
10.8
(1) See Third-Party Products disclaimer.
8.2.2.5 Capacitor Selection
The input capacitor is the low-impedance energy source for the converter which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed between
VIN and GND as close as possible to those pins. For most applications, 10 μF is sufficient, though a larger value
reduces input current ripple.
The architecture of the TLV62085 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 22 μF; this capacitance can
vary over a wide range as outline in the output filter selection table. Output capacitors above 150uF may be used
with a reduced load current during startup to avoid triggering the short circuit protection.
A feed-forward capacitor is not required for device proper operation.
版权 © 2015–2018, Texas Instruments Incorporated
11
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
8.2.3 Application Curves
VIN = 3.6 V, TA = 25 ºC, unless otherwise noted
100
90
100
90
80
70
60
80
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
1m
10m
100m
1
5
1m
10m
100m
1
5
Load (A)
Load (A)
D001
D002
VOUT = 0.95 V
VOUT = 1.2 V
图 5. Efficiency
图 6. Efficiency
100
100
90
80
70
60
90
80
70
60
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
1m
10m
100m
1
5
1m
10m
100m
1
5
Load (A)
Load (A)
D003
D004
VOUT = 3.3 V
VOUT = 1.8 V
图 7. Efficiency
图 8. Efficiency
1.212
1.212
1.206
1.200
1.194
1.188
1.206
1.200
1.194
1.188
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1m
10m
100m
1
5
Input Voltage (V)
Load (A)
D005
D006
IOUT = 1 A
图 9. Line Regulation
图 10. Load Regulation
12
版权 © 2015–2018, Texas Instruments Incorporated
TLV62085
www.ti.com.cn
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
t -- 500ns/div
t -- 300ns/div
t -- 200μs/div
t -- 200μs/div
Vout (AC, 20mV/div)
Icoil (DC, 1A/div)
Vout (AC, 20mV/div)
Icoil (DC, 1A/div)
SW (DC, 5V/div)
SW (DC, 5V/div)
IOUT = 3 A
VOUT = 1.2 V
IOUT = 0.1 A
VOUT = 1.2 V
图 11. PWM Operation
图 12. PFM Operation
t -- 200μs/div
Load (DC, 2A/div)
EN (DC, 5V/div)
Vout (AC, 50mV/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
IOUT = 0 A to 3 A
VOUT = 1.2 V
ROUT = 0.47 Ω
VOUT = 1.2 V
图 13. Load Sweep
图 14. Start-Up with Load
t -- 5μs/div
EN (DC, 5V/div)
EN (DC, 5V/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 0.5A/div)
VOUT = 1.2 V
ROUT = 0.47 Ω
VOUT = 1.2 V
图 15. Start-Up without Load
图 16. Shutdown with Load
版权 © 2015–2018, Texas Instruments Incorporated
13
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
t -- 5ms/div
t -- 2μs/div
EN (DC, 5V/div)
Load (DC, 2A/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.1V/div)
Icoil (DC, 0.5A/div)
Icoil (DC, 2A/div)
VOUT = 1.2 V
IOUT = 0.5 A to 3 A
VOUT = 1.2 V
图 17. Shutdown without Load
图 18. Load Transient
t -- 3μs/div
t -- 200μs/div
Load (DC, 2A/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
PG (DC, 5V/div)
Vout (DC, 0.1V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
IOUT = 50mA to 3A
VOUT = 1.2 V
ROUT = 0.47 Ω
VOUT = 1.2 V
图 19. Load Transient
图 20. Output Short-Circuit Protection, Entry
t -- 200μs/div
t -- 5μs/div
PG (DC, 5V/div)
PG (DC, 5V/div)
Vout (DC, 0.5V/div)
Vout (DC, 0.5V/div)
Icoil (DC, 2A/div)
Icoil (DC, 2A/div)
ROUT = 0.47 Ω
VOUT = 1.2 V
ROUT = 0.47 Ω
VOUT = 1.2 V
图 21. Output Short-Circuit Protection, Recovery
图 22. Output Short-Circuit Protection,
HICCUP Zoom In
14
版权 © 2015–2018, Texas Instruments Incorporated
TLV62085
www.ti.com.cn
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.5 V to 6 V. Ensure that the input
power supply has a sufficient current rating for the application.
10 Layout
10.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TLV62085
device.
The input and output capacitors and the inductor must be placed as close as possible to the IC. This keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
The low side of the input and output capacitors must be connected directly to the GND pin to avoid a ground
potential shift. The sense traces connected to FB and VOS pins are signal traces. Special care must be taken to
avoid noise being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used
for shielding. Keep these traces away from SW nodes. See 图 23 for the recommended PCB layout.
10.2 Layout Example
L1
VOUT
VIN
C1
C2
Solution Size
62 mm2
GND
R2
R1
图 23. PCB Layout Recommendation
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
The big copper planes connecting to the pads of the IC on the PCB improve the thermal performance of the
device. For more details on how to use the thermal parameters, see the Thermal Characteristics Application
Notes, SZZA017 and SPRA953.
版权 © 2015–2018, Texas Instruments Incorporated
15
TLV62085
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
www.ti.com.cn
11 器件和文档支持
11.1 开发支持
11.1.1 使用 WEBENCH® 工具定制设计方案
请单击此处，借助 WEBENCH®电源设计器并使用 TPS54360 器件创建定制设计方案。
1. 首先输入您的 VIN、VOUT 和 IOUT 要求。
2. 使用优化器拨盘可优化效率、封装和成本等关键设计参数并将您的设计与德州仪器 (TI) 的其他可行解决方案进
行比较。
3. WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
4. 在多数情况下，您还可以：
–
–
–
–
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
5. 有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.1.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
《热工特性应用手册》，SZZA017
《热工特性应用手册》，SPRA953
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
DCS-Control, WEBENCH, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
16
版权 © 2015–2018, Texas Instruments Incorporated
TLV62085
www.ti.com.cn
ZHCSE67B –OCTOBER 2015–REVISED JULY 2018
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2018, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV62085RLTR
TLV62085RLTT
ACTIVE
ACTIVE
VSON-HR
VSON-HR
RLT
RLT
7
7
3000 RoHS & Green
250 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
12Q5
12Q5
Samples
Samples
Call TI | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62085RLTR
TLV62085RLTT
TLV62085RLTT
VSON-
HR
RLT
RLT
RLT
7
7
7
3000
250
180.0
180.0
180.0
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
4.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q2
VSON-
HR
VSON-
HR
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV62085RLTR
TLV62085RLTT
TLV62085RLTT
VSON-HR
VSON-HR
VSON-HR
RLT
RLT
RLT
7
7
7
3000
250
210.0
182.0
210.0
185.0
182.0
185.0
35.0
20.0
35.0
250
Pack Materials-Page 2
PACKAGE OUTLINE
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
1
PIN 1
INDEX AREA
2.1
1.9
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
0.5
0.3
3X
(0.2) TYP
(0.2) TYP
3X 0.5
2X 0.6
1.2
4
5
7
1.5
1
0.3
0.2
0.35
0.25
4X
3X
1.4
1.2
3X
0.1
C A
B
0.1
C A
B
0.05
C
PIN 1 ID
0.05
C
0.5
0.3
4220429/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
℄
(0.6)
1
(0.25)
7
2X (0.6)
PKG
℄
3X (0.5)
3X (0.25)
5
3X (0.3)
4
3X (1.5)
3X (0.6)
(0.9)
(0.45)
LAND PATTERN EXAMPLE
SCALE: 30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
PADS 1 - 4
PADS 5 - 7
SOLDER MASK DETAILS
4220429/A 09/2014
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
5. Vias should not be placed on soldering pads unless they are plugged or plated shut.
www.ti.com
EXAMPLE STENCIL DESIGN
RLT0007A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
℄
6X (0.65)
(0.6)
(0.21)
1
7
EXPOSED METAL
TYP
2X (0.6)
PKG
℄
3X (0.5)
METAL UNDER
SOLDER MASK
TYP
3X (0.21)
6X (0.3)
5
4
3X (0.025)
3X
EXPOSED METAL
3X (0.6)
SOLDER MASK EDGE
TYP
(0.9)
(0.875)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR ALL EXPOSED PADS
85% PRINTED SOLDER COVERAGE BY AREA
SCALE: 40X
4220429/A 09/2014
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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TLV62130ARGTR
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