TLV62095RGTT [TI]
具有 DCS Control 的 4A 同步降压转换器 | RGT | 16 | -40 to 125;
| 型号： | TLV62095RGTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 DCS Control 的 4A 同步降压转换器 | RGT | 16 | -40 to 125 DCS 分布式控制系统 开关 转换器 |
| 文件： | 总29页 (文件大小：1175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
TLV62095 采用 DCS-Control™ 拓扑的 4A 高效降压转换器
1 特性
3 说明
1
•
2.5V 至 5.5V 输入电压范围
DCS-Control™
TLV62095 器件是一款高频同步降压转换器，经优化具
有小解决方案尺寸和高效率两大优点，非常适合电池供
电类 应用。为了最大限度地提高效率，该转换器以
1.4MHz 的标称开关频率在脉宽调制 (PWM) 模式下工
作，并且会在轻负载电流条件下自动进入节能工作模
式。在分布式电源和负载点稳压应用中，该器件允许对
其他电压轨的电压进行跟踪，并且允许采用介于 10µF
至 150µF 范围内甚至更高的输出电容。通过使用
DCS-Control™ 技术，此器件可实现出色的负载静态性
能以及精确的输出电压调节。
•
•
•
•
•
•
•
•
•
•
•
•
•
•
效率高达 95%
省电模式
20µA 运行静态电流
针对最低压降的 100% 占空比
1.4MHz 典型开关频率
0.8V 至 VIN 的可调输出电压
输出放电功能
可调软启动
自动切断短路保护功能
输出电压跟踪
输出电压启动斜坡由软启动引脚控制，可由独立电源供
电运行，也可在跟踪配置下运行。通过配置 EN 和 PG
引脚还可实现电源排序。在节能模式下，该器件静态工
作电流的典型值为 20µA。在整个负载电流范围内，自
动进入省电模式并且以无缝方式保持高效。
与 TLV62090 和 TPS62095 引脚兼容
如需了解改进的特性集，请参见 TPS62095
借助 WEBENCH® Power Designer 并使用
TLV62095 创建定制设计方案
该器件采用 3mm x 3mm 16 引脚超薄四方扁平无引线
(VQFN) 封装。
2 应用范围
•
•
•
•
电视 (TV)、机顶盒 (STB) 和计算机
固态硬盘 (SSD)
器件信息(1)
器件型号
封装
封装尺寸（标称值）
硬盘驱动器 (HDD)
TLV62095
VQFN (16)
3.00mm x 3.00mm
电池供电类 应用
1.8V 输出应用
L1
1.8V 输出应用效率
TLV62095
1mH
Vin
Vout
1.8V
12
11
1
100
2.5V to 5.5V
PVIN
PVIN
SW
SW
R1
2
C1
22mF
C2
2 x 22mF
200k
10
3
16
5
AVIN
DEF
EN
VOS
FB
R2
90
80
70
60
R3
500k
160k
13
4
C5
10nF
PG
SS
Power Good
7
8
9
CP
CN
C4
10nF
6
AGND
PGND PGND
14 15
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
0.001
0.01
0.1
1
5
Load (A)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDD3
TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommend Operating Conditions........................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
8
9
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Applications ................................................ 11
Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
10.3 Thermal Consideration.......................................... 17
11 器件和文档支持 ..................................................... 18
11.1 器件支持................................................................ 18
11.2 接收文档更新通知 ................................................. 18
11.3 社区资源................................................................ 18
11.4 商标....................................................................... 18
11.5 静电放电警告......................................................... 18
11.6 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
Changes from Original (March 2016) to Revision A
Page
•
•
•
已添加 WEBENCH® 信息至特性、详细设计流程和开发支持部分 .......................................................................................... 1
Added SW (AC, less than 10 ns) to the Abolute Maximum Rating table ............................................................................... 4
已添加 表 1, Power Good Pin Logic ..................................................................................................................................... 10
2
Copyright © 2016–2017, Texas Instruments Incorporated
TLV62095
www.ti.com.cn
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
5 Pin Configuration and Functions
16-Pin VQFN with Thermal PAD
RGT
(Top View)
16 15 14 13
SW
SW
PVIN
12
1
2
11
PVIN
AVIN
SS
Exposed
Thermal Pad
DEF
PG
10
9
3
4
5
6
7
8
Pin Functions
PIN
DESCRIPTION
NAME
NO.
SW
1, 2
Switch pin of the power stage.
This pin is used for internal logic and needs to be pulled high. This pin must be connected to the AVIN
pin.
DEF
PG
3
4
Power good open drain output. A pull up resistor can not be connected to any voltage higher than the
input voltage.
FB
5
6
7
8
Feedback pin for regulating the output voltage.
AGND
CP
Analog ground.
Internal charge pump's flying capacitor. Connect a 10nF capacitor between CP and CN.
Internal charge pump's flying capacitor. Connect a 10nF capacitor between CP and CN.
CN
Soft-start control pin. A capacitor is connected to this pin and sets the soft startup time. Leaving this pin
floating sets the minimum start-up time.
SS
9
AVIN
PVIN
10
Analog supply input voltage pin.
Power supply input voltage pin.
11,12
Enable pin. This pin has an active pull down resistor of typically 400kΩ, which is active when EN is low.
To enable the device, this pin needs to be pulled high. Pulling this pin low disables the device.
EN
13
PGND
VOS
14,15
16
Power ground.
Output voltage sense pin. This pin must be directly connected to the output voltage.
Exposed
Thermal Pad
The exposed thermal pad must be connected to AGND. It must be soldered for mechanical reliability.
Copyright © 2016–2017, Texas Instruments Incorporated
3
TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
– 0.3
– 0.3
– 3.0
– 0.3
MAX
7
UNIT
PVIN, AVIN, FB, SS, EN, DEF, VOS
SW (DC), PG
SW (AC, less than 10 ns)(3)
VIN+0.3
10
Voltage at pins(2)
Sink current
V
CN, CP
PG
VIN+7.0
1.0
mA
°C
Operating junction temperature range, TJ
Storage temperature, Tstg
– 40
– 65
150
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
(3) While switching.
6.2 ESD Ratings
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommend Operating Conditions
MIN
2.5
MAX
UNIT
VIN
TJ
Input voltage range
5.5
V
Operating junction temperature
-40
125
°C
6.4 Thermal Information
TLV62095
THERMAL METRIC(1)
UNIT
VQFN (16 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
47
60
RθJC(top)
RθJB
20
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
20
ψJB
RθJC(bot)
5.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016–2017, Texas Instruments Incorporated
TLV62095
www.ti.com.cn
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
6.5 Electrical Characteristics
VIN = 3.6V and TJ = 25°C (unless otherwise noted)
PARAMETER
SUPPLY
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Input voltage range
2.5
5.5
V
Quiescent current into PVIN
and AVIN
IQ
EN = High, Not switching, FB = FB +5%
EN = Low
20
µA
Shutdown current Into PVIN
and AVIN
ISD
0.6
µA
Undervoltage lockout threshold VIN falling
Undervoltage lockout hysteresis
2.1
2.2
200
150
20
2.3
V
mV
ºC
ºC
VUVLO
Thermal shutdown
Temperature rising
TSD
Thermal shutdown hysteresis
CONTROL SIGNAL EN
VH
VL
High level input voltage
VIN = 2.5 V to 5.5 V
VIN = 2.5 V to 5.5 V
EN = GND or VIN
EN = Low
1
0.65
0.60
10
V
V
Low level input voltage
Input leakage current
Pull down resistance
0.4
Ilkg
RPD
100
nA
kΩ
400
SOFT STARTUP
ISS
Softstart current
7.5
µA
POWER GOOD
Output voltage rising
Output voltage falling
I(sink) = 1 mA
95%
90%
VTH_PG Power good threshold
VL
POWER SWITCH
High side FET on-resistance
Low level voltage
0.4
V
ISW = 500 mA
ISW = 500 mA
50
40
mΩ
mΩ
RDS(on)
Low side FET on-resistance
High side FET switch current
limit
ILIM
4.7
5.5
1.4
A
fSW
Switching frequency
IOUT = 3 A
MHz
OUTPUT
VOUT
RDIS
Output voltage range
Output discharge resistor
Feedback regulation voltage
Line regulation
0.8
VIN
V
EN = GND, VOUT = 1.8 V
IOUT = 1 A, PWM mode
200
800
Ω
VFB
792
808
mV
%/V
%/A
VOUT = 1.8 V, PWM operation
VOUT = 1.8 V, PWM operation
0.016
0.04
Load regulation
版权 © 2016–2017, Texas Instruments Incorporated
5
TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
www.ti.com.cn
6.6 Typical Characteristics
80
70
60
50
40
30
80
70
60
50
40
30
20
10
0
20
10
0
Tj = -40°C
Tj = 25°C
Tj = 85°C
Tj = 125°C
Tj = -40°C
Tj = 25°C
Tj = 85°C
Tj = 125°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
D003
D004
图 1. High-Side FET On Resistance
图 2. Low-Side FET On Resistance
1
0.8
0.6
0.4
0.2
0
30
20
10
0
Tj = -40°C
Tj = -40°C
Tj = 0°C
Tj = 25°C
Tj = 85°C
Tj = 0°C
Tj = 25°C
Tj = 85°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Input Voltage (V)
D006
D005
图 4. Shutdown Current
图 3. Quiescent Current
6
版权 © 2016–2017, Texas Instruments Incorporated
TLV62095
www.ti.com.cn
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
7 Detailed Description
7.1 Overview
The TLV62095 synchronous step down converter is based on DCS-Control™ (Direct Control with Seamless
transition into Power Save Mode). This is an advanced regulation topology that combines the advantages of
hysteretic and voltage mode control.
The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal
switching frequency of 1.4 MHz having a controlled frequency variation over the input voltage range. As the load
current decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the
current consumption of the IC to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes using a single building block and therefore has a seamless transition from PWM
to Power Save Mode without effects on the output voltage. The TLV62095 offers excellent DC voltage regulation
and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
7.2 Functional Block Diagram
PVIN PVIN
PG
CP
CN
Charge Pump
for
Gate driver
Hiccup
current limit
#32 counter
VFB
VREF
High Side
Current
Sense
AVIN
EN
Bandgap
Undervoltage
Lockout
Thermal shutdown
M1
SW
SW
(1)
400kW
MOSFET Driver
AGND
DEF
Anti Shoot Through
Converter Control
Logic
2
M
PGND
PGND
VOS
ramp
Direct Control
and
Compensation
Comparator
Timer
ton
Error Amplifier
FB
Vref
0.8V
Vin
DCS - Control™
200Ω
Iss
Voltage clamp
Vref
÷1.56
SS
M3
Output voltage
discharge
logic
EN
Copyright © 2017, Texas Instruments Incorporated
(1) The resistor is disconnected when EN is high.
版权 © 2016–2017, Texas Instruments Incorporated
7
TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
www.ti.com.cn
7.3 Feature Description
7.3.1 PWM Operation
At medium to heavy load currents, the device operates with pulse width modulation (PWM) at a nominal
switching frequency of 1.4 MHz. As the load current decreases, the converter enters power save mode operation
reducing its switching frequency. The device enters power save mode at the boundary to discontinuous
conduction mode (DCM).
7.3.2 Power Save Mode Operation
As the load current decreases, the converter enters Power Save Mode operation. During Power Save Mode, the
converter operates with reduced switching frequency to maintain high efficiency. Power Save Mode is based on
a fixed on-time architecture following 公式 1.
V
OUT
ton =
× 360ns × 2
V
IN
2 × I
OUT
f =
æ
ö
÷
V
IN
- V
OUT
V
IN
- V
ton2 1 +
x
OUT
ç
ç
÷
V
OUT
L
è
ø
(1)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage in PWM mode. This
effect is reduced by increasing the output capacitance or the inductor value. This effect is also reduced by
programming the output voltage of the TLV62095 lower than the target value.
7.3.3 Low Dropout Operation (100% Duty Cycle)
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high
side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve
longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage
where the output voltage falls below its set point is given by:
VIN(min) = VOUT + IOUT x ( RDS(on) + RL )
(2)
Where
RDS(on) = High side FET on-resistance
RL = DC resistance of the inductor
7.4 Device Functional Modes
7.4.1 Enable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low with a shutdown current of typically 0.6 μA. In shutdown mode, the internal power switches as well as
the entire control circuitry are turned off. An internal resistor of 200 Ω discharges the output through the VOS pin
smoothly. An internal pull-down resistor of 400 kΩ is connected to the EN pin when the EN pin is low. The pull-
down resistor is disconnected when the EN pin is high.
7.4.2 Soft Startup (SS) and Hiccup Current Limit During Startup
To minimize inrush current during startup, the device has an adjustable startup time depending on the capacitor
value connected to the SS pin. The device charges the SS capacitor with a constant current of typically 7.5 µA.
The feedback voltage follows this voltage divided by 1.56, until the internal reference voltage of 0.8 V is reached.
The soft startup operation is completed once the voltage at the SS capacitor has reached typically 1.25 V. The
soft startup time is calculated using 公式 3. The larger the SS capacitor, the longer the soft startup time. The
relation between the SS pin voltage and the FB pin voltage is estimated using 公式 4.
1.25V
tSS = CSS
x
7.5μA
(3)
(4)
VSS
VFB
=
1.56
8
版权 © 2016–2017, Texas Instruments Incorporated
TLV62095
www.ti.com.cn
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
Device Functional Modes (接下页)
During startup the switch current limit is reduced to 1/3 of its typical current limit of 5.5A when the output voltage
is less than 0.6V. Once the output voltage exceeds typically 0.6V, the switch current limit is released to its
nominal value. Thus, the device provides a reduced load current of 1.8A when the output voltage is below 0.6V.
Due to this, a small or no startup time may trigger this reduced switch current limit during startup, especially for
larger output capacitor applications. This is avoided by using a larger soft start up capacitance which extends the
soft startup time. See Short Circuit Protection (Hiccup-Mode) for details of the reduced current limit during
startup. Leaving the SS pin floating sets the minimum startup time (around 50 μs).
7.4.3 Voltage Tracking (SS)
The SS pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in 图 5. The internal reference voltage follows the voltage at the SS pin with a fraction of 1.56
until the internal reference voltage of 0.8 V is reached. The device achieves ratiometric or coincidental
(simultaneous) output tracking, as shown in 图 6.
VOUT1
VOUT2
TLV62095
R1
R3
SS
FB
R2
R4
图 5. Output Voltage Tracking
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5 μA soft startup current
into account. 1 kΩ or smaller is a sufficient value for R2.
Voltage
Voltage
VOUT1
VOUT1
VOUT2
VOUT2
R3
R4
R1
1
R3
R4
R1
ö
1
æ
ö
æ
1+
< 1+
´
R2 1.56
1+
= 1+
´
÷
ç
÷
ç
R2 1.56
ø
è
ø
è
t
t
a) Ratiometric Tracking
b) Coincidental Tracking
图 6. Voltage Tracking Options
For decreasing the SS pin voltage, the device doesn't sink current from the output when the device is in power
save mode. So the resulting decrease of the output voltage may be slower than the SS pin voltage if the load is
light. When driving the SS pin with an external voltage, do not exceed the voltage rating of the SS pin which is 7
V.
版权 © 2016–2017, Texas Instruments Incorporated
9
TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
www.ti.com.cn
Device Functional Modes (接下页)
7.4.4 Short Circuit Protection (Hiccup-Mode)
The device is protected against hard short circuits to GND and over-current events. This is implemented by a two
level short circuit protection. During start-up and when the output is shorted to GND, the switch current limit is
reduced to 1/3 of its typical current limit of 5.5 A. Once the output voltage exceeds typically 0.6 V the current limit
is released to its nominal value. The full current limit is implemented as a hiccup current limit. Once the internal
current limit is triggered 32 times, the device stops switching and starts a new start-up sequence after a typical
delay time of 66 µs passed by. The device repeats these cycles until the high current condition is released.
7.4.5 Output Discharge Function
To make sure the device starts up under defined conditions, the output gets discharged via the VOS pin with a
typical discharge resistor of 200 Ω whenever the device shuts down. This happens when the device is disabled
or if thermal shutdown, undervoltage lockout or short circuit hiccup-mode is triggered.
7.4.6 Power Good Output
The power good output is low when the output voltage is below its nominal value. The power good becomes high
impedance once the output is within 5% of regulation. The PG pin is an open drain output and is specified to sink
up to 1mA. This output requires a pull-up resistor to be monitored properly. The pull-up resistor cannot be
connected to any voltage higher than the input voltage of the device. The PG output can be left floating if
unused. 表 1 shows the PG pin logic.
表 1. Power Good Pin Logic
PG Logic Status
Device State
High Impedance
Low
V
FB ≥ VTH_PG
FB ≤ VTH_PG
√
Enable (EN=High)
V
√
√
√
√
Shutdown (EN=Low)
UVLO
0.7 V < VIN ≤ VUVLO
TJ > TSD
Thermal Shutdown
Power Supply Removal
VIN ≤ 0.7 V
√
7.4.7 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts
down the device at input voltages lower than typically 2.2 V with a 200 mV hysteresis.
7.4.8 Thermal Shutdown
The device goes into thermal shutdown once the junction temperature exceeds typically 150°C with a 20°C
hysteresis.
7.4.9 Charge Pump (CP, CN)
The CP and CN pins must attach to an external 10 nF capacitor to complete a charge pump for the gate driver.
This capacitor must be rated for the input voltage. It is not recommended to connect any other circuits to the CP
or CN pins.
10
版权 © 2016–2017, Texas Instruments Incorporated
TLV62095
www.ti.com.cn
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV62095 is a 4-A high frequency synchronous step-down converter optimized for small solution size, high
efficiency and suitable for battery powered applications.
8.2 Typical Applications
8.2.1 1.8-V Output Converter
L1
TLV62095
1mH
Vin
2.5V to 5.5V
Vout
1.8V
12
11
1
PVIN
PVIN
SW
SW
R1
2
C1
22mF
C2
2 x 22mF
200k
10
3
16
5
AVIN
DEF
EN
VOS
FB
R2
R3
500k
160k
13
4
C5
10nF
PG
SS
Power Good
7
8
9
CP
CN
C4
10nF
6
AGND
PGND PGND
14 15
图 7. TLV62095 Typical Application Circuit
8.2.1.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions. For the typical application example, the following input parameters are used.
表 2. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
2.5 V to 5.5 V
1.8 V
Output voltage
Output ripple voltage
Output current rating
< 30 mV
4 A
表 3 shows the list of components for the Application Characteristic Curves.
表 3. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
High efficiency step-down
converter
TLV62095
Texas Instruments
L1
Inductor: 1 µH
Coilcraft XAL4020-102
(6.3V, X5R, 0805)
C1, C2
Ceramic capacitor: 22 μF
版权 © 2016–2017, Texas Instruments Incorporated
11
TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
www.ti.com.cn
表 3. List of Components (接下页)
REFERENCE
C4, C5
DESCRIPTION
Ceramic capacitor, 10 nF
Resistor
MANUFACTURER
Standard
R1, R2, R3
Standard
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62095 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Output Filter
The first step is the selection of the output filter components. To simplify this process, 表 4 outlines possible
inductor and capacitor value combinations.
表 4. Output Filter Selection
OUTPUT CAPACITOR VALUE [µF](2)
INDUCTOR VALUE [µH](1)
10
22
2 x 22
100
150
0.47
1.0
(3)
√
√
√
2.2
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and
–30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by
+20% and –50%.
(3) Typical application configuration. Other check mark indicates alternative filter combinations
8.2.1.2.3 Inductor Selection
The inductor selection is affected by several parameters like inductor ripple current, output voltage ripple,
transition point into Power Save Mode, and efficiency. See 表 5 for typical inductors.
表 5. Inductor Selection
INDUCTOR VALUE
1 µH
COMPONENT SUPPLIER(1)
Coilcraft XAL4020-102
TOKO DFE322512C
SIZE (LxWxH mm)
4.0 x 4.0 x 2.1
Isat / DCR
8.75A / 13.2 mΩ
5.9A / 21 mΩ
0.47 µH
3.2 x 2.5 x 1.2
(1) See Third-Party Products disclaimer
In addition, the inductor has to be rated for the appropriate saturation current and DC resistance (DCR). The
inductor needs to be rated for a saturation current as high as the typical switch current limit of 5.5A or according
to 公式 5 and 公式 6. 公式 5 and 公式 6 calculate the maximum inductor current under static load conditions. The
formula takes the converter efficiency into account. The converter efficiency can be taken from the data sheet
graphs or 80% can be used as a conservative approach. The calculation must be done for the maximum input
voltage where the peak switch current is highest.
12
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TLV62095
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ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
ΔI
L
I
L
= I
OUT
+
2
(5)
(6)
æ
ö
÷
÷
ø
V
V
OUT
η
OUT
x η
ç
ç
è
x
1 -
V
IN
I
= I
OUT
+
L
2 x f x L
where
ƒ = Converter switching frequency (typically 1.4MHz)
L = Inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.80 as a conservative
assumption)
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current. A margin of 20% should be added to cover for load transients during operation.
8.2.1.2.4 Input and Output Capacitor Selection
For best output and input voltage filtering, low ESR (X5R or X7R) ceramic capacitors are recommended. The
input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail
for the device. A 22-μF or larger input capacitor is recommended. The output capacitor value can range from 10
μF up to 150 μF and beyond. Load transient testing and measuring the bode plot are good ways to verify stability
with larger capacitor values.
The recommended typical output capacitor value is 2 x 22 μF (nominal) and can vary over a wide range as
outline in the output filter selection table. Ceramic capacitor have a DC-Bias effect, which has a strong influence
on the final effective capacitance. Choose the right capacitor carefully in combination with considering its
package size and voltage rating.
8.2.1.2.5 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations:
R1
R1
æ
ö
æ
ö
VOUT = VFB
´
1 +
= 0.8 V ´ 1 +
ç
÷
ç
÷
R2
R2
è
ø
è
ø
(7)
(8)
VFB
0.8 V
5 μA
R2 =
=
» 160 kΩ
IFB
æ
ç
è
ö
VOUT
VFB
V
OUT
æ
ö
R1 = R2 ´
-1 = R2 ´
- 1
÷
÷
ç
0.8V
è
ø
ø
(9)
When sizing R2, in order to achieve low quiescent current and acceptable noise sensitivity, use a minimum of 5
µA for the feedback current IFB. Larger currents through R2 improve noise sensitivity and output voltage
accuracy.
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8.2.1.3 Application Performance Curves
TA = 25°C, VIN = 3.6 V, VOUT = 1.8 V, unless otherwise noted.
100
90
100
90
80
70
60
80
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
0.001
0.01
0.1
1
5
0.001
0.01
0.1
1
5
Load (A)
Load (A)
D001
D017
图 8. Efficiency, VOUT = 1.8 V
图 9. Efficiency, VOUT = 1.2 V
100
90
100
90
80
80
70
70
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 4.2 V
VIN = 5.0 V
60
60
0.001
0.01
0.1
1
5
0.001
0.01
0.1
1
5
Load (A)
Load (A)
D018
D019
图 10. Efficiency, VOUT = 2.6 V
图 11. Efficiency, VOUT = 3.3 V
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40èC
TA = 25èC
TA = 85èC
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.001
0.01
0.1
1
5
Input Voltage (V)
D007
Load (A)
D002
图 13. Line Regulation, VOUT = 1.8 V, IOUT = 1.0 A
图 12. Load Regulation, VOUT = 1.8 V, VIN = 3.3 V
14
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TLV62095
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ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
5000
SW = 5V/div
1000
100
10
VOUT = 20 mV/div, AC
ICOIL = 0.5 A/div
VIN = 2.5 V
VIN = 3.6 V
VIN = 5.5 V
1
Time = 1 µs/div
0.001
0.01
0.1
1
5
Load (A)
D008
图 15. Output Ripple, VOUT = 1.8 V, IOUT = 100 mA
图 14. Switching Frequency, VOUT = 1.8 V
SW = 5V/div
VIN = 2V/div
VOUT = 20mV/div, AC
VOUT = 1V/div
ICOIL = 1A/div
ICOIL = 0.5A/div
Time = 0.5 µs/div
Time = 500 µs/div
图 16. Output Ripple, VOUT = 1.8 V, IOUT = 3.5 A
图 17. Startup, Relative to VIN, RLOAD = 1.5 Ω
EN = 5V/div
LOAD = 2A/div
0.1A to 2A load step
VIN = 2V/div
VOUT = 0.1V/div, AC
ICOIL = 2A/div
VOUT = 1V/div
ICOIL = 0.5A/div
Time = 500 µs/div
Time = 10 µs/div
图 18. Startup, Relative to EN, RLOAD = 1.5 Ω
图 19. Load Transient, VOUT = 1.8 V
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TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
www.ti.com.cn
LOAD = 2A/div
VOUT = 1V/div
ICOIL = 2A/div
1A to 3.5A load step
VOUT = 0.1V/div, AC
ICOIL = 2A/div
Time = 10 µs/div
Time = 250 µs/div
图 20. Load Transient, VOUT = 1.8 V
图 21. Short Circuit, HICCUP Protection Entry
VOUT = 1V/div
ICOIL = 2A/div
Time = 250 µs/div
图 22. Short Circuit, HICCUP Protection Exit
9 Power Supply Recommendations
The TLV62095 device has no special requirements for its input power supply. The input power supply's output
current needs to be rated according to the supply voltage, output voltage and output current of the TLV62095.
10 Layout
10.1 Layout Guidelines
•
•
It is recommended to place the input capacitor as close as possible to the IC pins PVIN and PGND.
The VOS connection is noise sensitive and needs to be routed short and direct to the output terminal of the
inductor.
•
•
•
The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a
single point connection at the exposed thermal pad of the package. This minimizes switch node jitter.
The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of
switching waveforms into other traces and circuits.
Refer to 图 23 for an example of component placement, routing and thermal design.
16
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TLV62095
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ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
10.2 Layout Example
L1
R1
AGND
R2
C2
VOUT
C5
FB
AGND
CP
VOS
PGND
PGND
EN
CN
C4
VIN
GND
C1
图 23. TLV62095 PCB Layout
10.3 Thermal Consideration
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component. The Thermal Information table provides the thermal metric of the device
and its package based on JEDEC standard. For more details on how to use the thermal parameters in real
applications, see the application notes: SZZA017 and SPRA953.
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TLV62095
ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
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11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
11.1.2.1 使用 WEBENCH® 工具定制设计方案
请单击此处，借助 WEBENCH® Power Designer 并使用 TLV62095 器件创建定制设计方案。
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
18
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TLV62095
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ZHCSF07A –MARCH 2016–REVISED JANUARY 2017
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2017, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV62095RGTR
TLV62095RGTT
ACTIVE
ACTIVE
VQFN
VQFN
RGT
RGT
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
13O
13O
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62095RGTR
TLV62095RGTT
TLV62095RGTT
VQFN
VQFN
VQFN
RGT
RGT
RGT
16
16
16
3000
250
330.0
180.0
180.0
12.4
12.4
12.5
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV62095RGTR
TLV62095RGTT
TLV62095RGTT
VQFN
VQFN
VQFN
RGT
RGT
RGT
16
16
16
3000
250
552.0
552.0
205.0
346.0
185.0
200.0
36.0
36.0
33.0
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TLV62095RGTR
TLV62095RGTT
RGT
RGT
VQFN
VQFN
16
16
3000
250
381
381
4.83
4.83
2286
2286
0
0
Pack Materials-Page 3
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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