TLV62150ARGTR [TI]
4-17V 1A Step-Down Converter with DCS-Control;
| 型号： | TLV62150ARGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-17V 1A Step-Down Converter with DCS-Control DCS 分布式控制系统 |
| 文件： | 总34页 (文件大小：1801K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
4-17V 1A Step-Down Converter with DCS-Control™
Check for Samples: TLV62150, TLV62150A
1
FEATURES
DESCRIPTION
The TLV62150 is an easy to use synchronous step
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DCS-Control™ Topology
down DC-DC converter optimized for applications
with high power density. A high switching frequency
of typically 2.5MHz allows the use of small inductors
and provides fast transient response as well as high
output voltage accuracy by utilization of the DCS-
Control™ topology.
Input Voltage Range: 4 to 17V
Up to 1A Output Current
Adjustable Output Voltage from 0.9 to 5V
Pin-Selectable Output Voltage (nominal, + 5%)
Programmable Soft Start and Tracking
Seamless Power Save Mode Transition
Quiescent Current of 19µA (typ.)
Selectable Operating Frequency
Power Good Output
With its wide operating input voltage range of 4V to
17V, the devices are ideally suited for systems
powered from either a Li-Ion or other batteries as well
as from 12V intermediate power rails. It supports up
to 1A continuous output current at output voltages
between 0.9V and 5V (with 100% duty cycle mode).
100% Duty Cycle Mode
The output voltage startup ramp is controlled by the
soft-start pin, which allows operation as either a
standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
Enable and open-drain Power Good pins.
Short Circuit Protection
Over Temperature Protection
For Improved Feature Set, see TPS62150
Available in a 3 × 3 mm, QFN-16 Package
In Power Save Mode, the devices show quiescent
current of about 19μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
maintains high efficiency over the entire load range.
In Shutdown Mode, the device is turned off and
shutdown current consumption is less than 2μA.
APPLICATIONS
•
•
Standard 12V Rail Supplies
POL Supply from Single or Multiple Li-Ion
Battery
•
•
•
Embedded Systems
The devices is packaged in a 16-pin QFN package
measuring 3 × 3 mm (RGT).
LDO replacement
Mobile PC's, Tablet, Modems, Cameras
spacing
1 / 2.2 µH
(4 .. 17)V
3.3V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
750k
240k
22uF
TLV62150
SS/TR
DEF
FB
3.3nF
AGND
PGND
FSW
Figure 1. Typical Application and Efficiency
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DCS-Control is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
OUTPUT VOLTAGE
adjustable
PART NUMBER(2)
PACKAGE
16-Pin QFN
16-Pin QFN
ORDERING
TLV62150RGT
TLV62150ARGT
PACKAGE MARKING
TLV62150
TLV62150A(3)
VUCI
VUOI
-40°C to 85°C
adjustable
(1) For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
(2) Contact the factory to check availability of other fixed output voltage versions.
(3) While TLV62150 has PG=High Z, TLV62150A features PG=Low, when device is in shutdown through EN, UVLO or Thermal Shutdown.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.3
-0.3
-0.3
-0.3
MAX
20
UNIT
AVIN, PVIN
V
EN, SS/TR
VIN+0.3
VIN+0.3
7
Pin voltage range(2)
SW
V
V
DEF, FSW, FB, PG, VOS
Power Good sink current PG
10
mA
Operating junction temperature range, TJ
-40
-65
125
150
2
Temperature range
ESD rating(3)
°C
Storage temperature range, Tstg
HBM Human body model
kV
kV
CDM Charge device model
0.5
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TLV62150
THERMAL METRIC(1)
UNITS
RGT 16 PINS
θJA
Junction-to-ambient thermal resistance
29.1
15
θJC(TOP)
θJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
11
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.5
10
ψJB
θJC(BOTTOM)
3.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
17
UNIT
V
Supply Voltage, VIN (at AVIN and P VIN)
Operating free air temperature, TA
Operating junction temperature, TJ
4
–40
–40
85
°C
125
°C
2
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS
over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=AVIN=PVIN=12V and TA=25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input Voltage Range(1)
Operating Quiescent Current
Shutdown Current(2)
4
17
V
µA
µA
V
IQ
EN=High, IOUT=0mA, device not switching
19
27
4
ISD
EN=Low
1.5
2.7
200
160
20
VUVLO
Falling Input Voltage
Hysteresis
2.6
0.9
2.8
Undervoltage Lockout Threshold
mV
TSD
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
°C
CONTROL (EN, DEF, FSW, SS/TR, PG)
High Level Input Threshold Voltage (EN,
DEF, FSW)
VH
V
VL
Low Level Input Threshold Voltage (EN,
DEF, FSW)
0.3
V
ILKG
Input Leakage Current (EN, DEF, FSW)
EN=VIN or GND; DEF, FSW=VOUT or GND
0.01
95
1
98
µA
Rising (%VOUT
)
92
87
VTH_PG Power Good Threshold Voltage
%
Falling (%VOUT
IPG=-2mA
)
90
93
VOL_PG Power Good Output Low
ILKG_PG Input Leakage Current (PG)
0.07
1
0.3
400
2.7
V
VPG=1.8V
nA
µA
ISS/TR
SS/TR Pin Source Current
2.3
1.4
0.9
2.5
POWER SWITCH
High-Side MOSFET ON-Resistance
Low-Side MOSFET ON-Resistance
High-Side MOSFET Forward Current Limit(3) VIN =12V, TA=25°C
V
IN≥6V
IN≥6V
90
40
mΩ
mΩ
A
RDS(ON)
V
ILIMF
1.7
OUTPUT
VREF
Internal Reference Voltage(4)
0.8
1
V
nA
V
ILKG_FB Input Leakage Current (FB)
Output Voltage Range
VFB=0.8V
IN ≥ VOUT
DEF=0 (GND)
DEF=1 (VOUT
100
5.0
V
DEF (Output Voltage Programming)
VOUT
)
VOUT+5%
-2.5
Initial Output Voltage Accuracy(5)
VOUT
PWM mode operation, VIN ≥ VOUT +1V
2.5
%
Load Regulation(6)
Line Regulation(6)
VIN=12V, VOUT=3.3V, PWM mode operation
0.05
0.02
%/A
%/V
4V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 1A, PWM
mode operation
(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into AVIN+PVIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short
Circuit Protection section).
(4) This is the voltage regulated at the FB pin.
(5) This is the accuracy provided by the device itself (line and load regulation effects are not included).
(6) Line and load regulation depend on external component selection and layout (see Figure 16 and Figure 17).
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
DEVICE INFORMATION
RGT PACKAGE
(TOP VIEW)
16
15
14
13
1
2
3
4
12
11
10
9
SW
PVIN
PVIN
AVIN
SS/TR
SW
SW
PG
Exposed
Thermal Pad
5
6
7
8
Terminal Functions
PIN(1)
NAME
I/O
DESCRIPTION
NO.
SW
PG
FB
1,2,3
O
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
4
O
I
Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor; goes high impedance, when device is switched off)
5
6
7
8
Voltage feedback. Connect resistive voltage divider to this pin.
AGND
FSW
DEF
Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz(2) for typical operation)(3)
Output Voltage Scaling (Low = nominal, High = nominal + 5%)(3)
I
I
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise
time. It can be used for tracking and sequencing.
SS/TR
9
I
AVIN
PVIN
EN
10
11,12
13
I
I
I
I
Supply voltage for control circuitry. Connect to same source as PVIN.
Supply voltage for power stage. Connect to same source as AVIN.
Enable input (High = enabled, Low = disabled)(3)
VOS
14
Output voltage sense pin and connection for the control loop circuitry.
Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane(4). Must be soldered to
achieve appropriate power dissipation and mechanical reliability.
PGND
Exposed
Thermal Pad
15,16
(1) For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.
(2) Connect FSW to VOUT or PG in this case.
(3) An internal pull-down resistor keeps logic level low, if pin is floating.
(4) See Figure 38.
4
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
FUNCTIONAL BLOCK DIAGRAM
PG
AVIN
PVIN PVIN
Soft
start
Thermal
Shtdwn
UVLO
PG control
HS lim
comp
EN*
SW
SW
SW
SS/TR
power
control
gate
drive
control logic
DEF*
FSW*
comp
LS lim
direct control
&
compensation
VOS
FB
ramp
_
comparator
timer tON
error
amplifier
+
DCS - ControlTM
* This pin is connected to a pull down resistor internally
(see Detailed Description section).
AGND
PGND PGND
Figure 2. TLV62150
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION
List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
IC
17V, 1A Step-Down Converter, QFN
2.2µH, 0.165 x 0.165 in
10µF, 25V, Ceramic
TLV62150RGT, Texas Instruments
XFL4020-222MEB, Coilcraft
Standard
L1
Cin
Cout
Cs
22µF, 6.3V, Ceramic
Standard
3300pF, 25V, Ceramic
depending on Vout
R1
R2
R3
depending on Vout
100kΩ, Chip, 0603, 1/16W, 1%
Standard
spacing
VIN
L1
VOUT
PVIN
SW
AVIN
VOS
R3
CIN
EN
PG
COUT
R1
R2
TLV62150
SS/TR
DEF
FSW
FB
CSS
AGND
PGND
Figure 3. Measurement Setup
TYPICAL CHARACTERISTICS
Table of Graphs
DESCRIPTION
FIGURE
Efficiency
vs Output Current, vs Input Voltage
4 - 15
vs Output current (Load regulation), vs Input Voltage
(Line regulation)
Output voltage
16, 17
vs Input Voltage
18
19
Switching Frequency
vs Output Current
Quiescent Current
vs Input Voltage
20
Shutdown Current
vs Input Voltage
21
Power FET RDS(on)
Output Voltage Ripple
Maximum Output Current
vs Input Voltage (High-Side, Low-Side)
vs output Current
22, 23
24
vs Input Voltage
25
Power Supply Rejection Ratio (PSSR)
vs Frequency
26, 27
28
PWM-PSM-PWM Mode Transition
Load Transient Response
Startup
29 - 31
32, 33
34
Waveforms
Typical PWM Mode Operation
Typical Power Save Mode Operation
35
6
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=17V
VIN=12V
IOUT=10mA
IOUT=1A
IOUT=1mA
IOUT=100mA
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
7
7
4
8
9
10
11
12
13
14
15
16
17
Input Voltage (V)
G001
G001
Figure 4. Efficiency with 1.25MHz, Vout=5V
Figure 5. Efficiency with 1.25MHz, Vout=5V
EFFICIENCY
vs
EFFICIENCY
vs
INPUT VOLTAGE
OUTPUT CURRENT
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=17V
VIN=12V
IOUT=10mA
IOUT=1A
IOUT=1mA
IOUT=100mA
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
0.1
1
8
9
10
11
12
13
14
15
16
17
Output Current (A)
Input Voltage (V)
G001
G001
Figure 6. Efficiency with 2.5MHz, Vout=5V
Figure 7. Efficiency with 2.5MHz, Vout=5V
EFFICIENCY
vs
EFFICIENCY
vs
INPUT VOLTAGE
OUTPUT CURRENT
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=12V
VIN=17V
VIN=5V
IOUT=1A IOUT=100mA IOUT=10mA
IOUT=1mA
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
Figure 8. Efficiency with 1.25MHz, Vout=3.3V
Figure 9. Efficiency with 1.25MHz, Vout=3.3V
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
EFFICIENCY
EFFICIENCY
vs
vs
OUTPUT CURRENT
100.0
INPUT VOLTAGE
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
90.0
80.0
70.0
60.0
VIN=12V
VIN=17V
IOUT=100mA
IOUT=1mA
50.0
40.0
30.0
20.0
10.0
0.0
VIN=5V
IOUT=10mA
IOUT=1A
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
Figure 10. Efficiency with 2.5MHz, Vout=3.3V
Figure 11. Efficiency with 2.5MHz, Vout=3.3V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=12V
VIN=17V
IOUT=1A
IOUT=100mA
IOUT=10mA
VIN=5V
IOUT=1mA
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
Figure 12. Efficiency with 1.25MHz, Vout=1.8V
Figure 13. Efficiency with 1.25MHz, Vout=1.8V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=12V
VIN=17V
IOUT=1A
IOUT=100mA
IOUT=10mA
VIN=5V
IOUT=1mA
VOUT=0.9V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=0.9V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
Figure 14. Efficiency with 1.25MHz, Vout=0.9V
Figure 15. Efficiency with 1.25MHz, Vout=0.9V
8
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.40
3.35
3.30
3.25
3.20
3.40
3.35
3.30
3.25
3.20
VIN=17V
VIN=12V
IOUT=10mA
IOUT=1mA
VIN=5V
IOUT=1A
IOUT=100mA
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.0001
0.001
0.01
Output Current (A)
0.1
1
4
7
10
13
16
Input Voltage (V)
G001
G001
Figure 16. Output Voltage Accuracy (Load Regulation)
Figure 17. Output Voltage Accuracy (Line Regulation)
SWITCHING FREQUENCY
SWITCHING FREQUENCY
vs
vs
INPUT VOLTAGE
OUTPUT CURRENT
4
4
3.5
3
3.5
3
2.5
2
2.5
2
IOUT=0.5A
IOUT=1A
1.5
1
1.5
1
VIN=12V, VOUT=3.3V
L=2.2uH (XFL4020)
FSW=Low
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.5
0
0.5
0
4
6
8
10
12
14
16
18
0
0.2
0.5
0.8
1
Input Voltage (V)
Output Current (A)
G000
G000
Figure 18. Switching Frequency
Figure 19. Switching Frequency
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
85°C
25°C
85°C
−40°C
12.0
25°C
−40°C
0.0
3.0
6.0
9.0
12.0
15.0
18.0 20.0
3.0
6.0
9.0
15.0
18.0 20.0
Input Voltage (V)
Input Voltage (V)
G001
G001
Figure 20. Quiescent Current
Figure 21. Shutdown Current
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
STATIC DRAIN-SOURCE-RESISTANCE (RDSon
)
STATIC DRAIN-SOURCE-RESISTANCE (RDSon
)
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
200.0
180.0
160.0
140.0
120.0
100.0
80.0
100.0
80.0
60.0
40.0
20.0
0.0
125°C
125°C
85°C
25°C
−10°C
85°C
25°C
−10°C
60.0
−40°C
40.0
−40°C
20.0
0.0
0.0
3.0
6.0
9.0
12.0
15.0
18.0 20.0
0.0
3.0
6.0
9.0
12.0
15.0
18.0 20.0
Input Voltage (V)
Input Voltage (V)
G001
G001
Figure 22. High-Side Switch Resistance
Figure 23. Low-Side Switch Resistance
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
vs
INPUT VOLTAGE
0.05
0.04
0.03
0.02
0.01
0
3
2.5
2
VOUT=3.3V,
L=2.2uH (XFL4020)
Cout=22uF
−40°C
25°C
VIN=17V
VIN=5V
1.5
1
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
85°C
8
0.5
0
VIN=12V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
4
5
6
7
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G000
G000
Figure 24. Output Voltage Ripple
Figure 25. Maximum Output Current
POWER SUPPLY REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN=12V
VIN=5V
VIN=5V
VIN=12V
VIN=17V
VIN=17V
VOUT=3.3V, IOUT=1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
VOUT=3.3V, IOUT=0.1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
G000
G000
Figure 26. Power Supply Rejection Ratio, fSW=2.5MHz
Figure 27. Power Supply Rejection Ratio, fSW=2.5MHz
10
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME
TIME
Figure 28. PWM-PSM-Transition (VIN=12V, VOUT=3.3V with
50mV/div)
Figure 29. Load Transient Response (IOUT= 0.5 to 1 to 0.5 A,
VIN=12V, VOUT=3.3V)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME
TIME
Figure 30. Line Transient Response of Figure 29, rising
edge
Figure 31. Line Transient Response of Figure 29, falling
edge
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME
TIME
Figure 32. Startup into 100mA (VIN=12V, VOUT=3.3V)
Figure 33. Startup into 1A (VIN=12V, VOUT=3.3V)
PWM SIGNALS
POWER SAVE MODE SIGNALS
vs
vs
TIME
TIME
Figure 34. Typical Operation in PWM Mode (IOUT=1A)
Figure 35. Typical Operation in Power Save Mode
(IOUT=10mA)
12
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
DETAILED DESCRIPTION
Device Operation
The TLV62150 synchronous switched mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.
This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.
It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-Control™ supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage.
Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 3
external components. An internal current limit supports nominal output currents of up to 1A.
The TLV62150 offers both excellent DC voltage and superior load transient regulation, combined with very low
output voltage ripple, minimizing interference with RF circuits.
Pulse Width Modulation (PWM) Operation
The TLV62150 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25MHz, selectable with the FSW pin. The frequency variation in PWM is
controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output
current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device
enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output
current becomes smaller than half the inductor's ripple current.
Power Save Mode Operation
The built in Power Save Mode of the TLV62150 is entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
TLV62150 includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated as:
VOUT
tON
=
× 400ns
VIN
(1)
For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using tON, the typical
peak inductor current in Power Save Mode can be approximated by:
(VIN -VOUT
)
ILPSM ( peak )
=
×tON
L
(2)
When VIN decreases to typically 15% above VOUT, the TLV62150 won't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
VIN(min) =VOUT(min) + IOUT (RDS( on ) + RL )
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RL is the DC resistance of the inductor used.
Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. An internal pull-down resistor of about 400kΩ is connected and keeps EN logic low, if
the pin is floating. It is disconnected if the pin is High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
Soft Start / Tracking (SS/TR)
The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 32 and Figure 33 for typical startup operation.
Connecting SS/TR directly to AVIN provides fastest startup behavior. The TLV62150 can start into a pre-biased
output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to turn on until the device's
internal ramp sets an output voltage above the pre-bias voltage. If the device is set to shutdown (EN=GND),
undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low
level. Returning from those states causes a new startup sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage
in both directions up and down (see APPLICATION INFORMATION).
Current Limit And Short Circuit Protection
The TLV62150 devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET will be turned off.
Avoiding shoot through current, the low-side FET will be switched on to sink the inductor current. The high-side
FET will turn on again, only if the current in the low-side FET has decreased below the low side current limit
threshold.
The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to
internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic
current limit can be calculated as follows:
spacing
14
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
VL
L
I peak(typ) = ILIMF
where
+
× tPD
(4)
ILIMF is the static current limit, specified in the ELECTRICAL CHARACTERISTICS,
L is the inductor value,
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch the peak current can be calculated as follows:
+ (VIN -VOUT
)
I peak(typ) = ILIMF
×30ns
L
(5)
Power Good (PG)
The TLV62150 has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and
maintain it's specified logic low level. It is high impedance when the device is turned off due to EN, UVLO or
thermal shutdown. TLV62150A features PG=Low in this case and can be used to actively discharge Vout (see
Figure 48). VIN must remain present for the PG pin to stay Low.
Pin-Selectable Output Voltage (DEF)
The output voltage of the TLV62150 can be increased by 5% above the nominal voltage by setting the DEF pin
to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage
allows adapting the power supply voltage to the variations of the application hardware. More detailed information
on voltage margining using TLV62150 can be found in SLVA489. A pull down resistor of about 400kOhm is
internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating after initially
set to Low. The resistor is disconnected if the pin is set High.
Frequency Selection (FSW)
To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by
connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally
connected to the pin, acting the same way as at the DEF Pin (see above).
Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV.
Thermal Shutdown
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
(1) Maximum allowed voltage is 7V. Therefore, it's recommended to connect it to VOUT or PG, not VIN.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
APPLICATION INFORMATION
The following information is intended to be a guideline through the individual power supply design process.
Programming The Output Voltage
The output voltage of the TLV62150 is adjustable. It can be programmed for output voltages from 0.9V to 5V by
using a resistive divider from VOUT to AGND. The voltage at the FB pin is regulated to 800mV. The value of the
output voltage is set by the selection of the resistive divider from Equation 6 (see ). It is recommended to choose
resistor values which allow a current of at least 2µA, meaning the value of R2 shouldn't exceed 400kΩ. Lower
resistor values are recommended for highest accuracy and most robust design. For applications requiring lowest
current consumption, the use of fixed output voltage versions is recommended.
æVOUT
ö
ç
÷
÷
R1 = R2
-1
ç
VREF
è
ø
(6)
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V.
External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TLV62150 is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter (see Output Filter And Loop Stability section). Table 1 can be used to simplify
the output filter component selection.
Table 1. L-C Output Filter Combinations(1)
4.7µF
10µF
22µF
47µF
100µF
200µF
400µF
0.47µH
1µH
√
√
√
√
√
√
√
√
√
(2)
2.2µH
3.3µH
4.7µH
√
√
√
√
(1) The values in the table are nominal values.
(2) This LC combination is the standard value and recommended for most applications.
spacing
The TLV62150 can be run with an inductor as low as 1µH or 2.2µH. FSW should be set Low in this case.
However, for applications running with the low frequency setting (FSW=High) or with low input voltages, 3.3µH is
recommended. More detailed information on further LC combinations can be found in SLVA463.
Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
spacing
DIL(max)
IL(max) = IOUT(max)
+
2
(7)
VOUT
æ
ö
÷
÷
÷
÷
÷
ø
1-
ç
ç
ç
VIN(max)
DIL(max) = VOUT
×
L(min) × fSW
ç
ç
è
(8)
where
16
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
IL(max) is the maximum inductor current,
ΔIL is the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
fSW is the actual PWM Switching Frequency.
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TLV62150 and are recommended for use:
Table 2. List of Inductors
Type
Inductance [µH]
Saturation Current [A](1) Dimensions [L x B x H] MANUFACTURER
mm
XFL4020-222ME_
XFL3012-222MEC
XFL3012-332MEC
VLS252012T-2R2M1R3
LPS3015-332
2.2 µH, ±20%
2.2 µH, ±20%
3.3 µH, ±20%
2.2 µH, ±20%
3.3 µH, ±20%
3.3 µH, ±20%
2.2 µH, ±20%
2.2 µH, ±20%
3.5
1.6
1.4
1.3
1.4
1.5
1.3
1.5
4 x 4 x 2.1
3 x 3 x 1.2
Coilcraft
Coilcraft
Coilcraft
TDK
3 x 3 x 1.2
2.5 x 2 x 1.2
3 x 3 x 1.4
Coilcraft
Wuerth
744025003
2.8 x 2.8 x 2.8
2 x 2.5 x 1.2
3 x 3 x 1.5
PSI25201B-2R2MS
NR3015T-2R2M
Cyntec
Taiyo Yuden
(1) Lower of IRMS at 40°C rise or ISAT at 30% drop.
spacing
The inductor value also determines the load current at which Power Save Mode is entered:
1
Iload(PSM )
=
DIL
2
(9)
Using Equation 8, this current level can be adjusted by changing the inductor value.
Capacitor Selection
Output Capacitor
The recommended value for the output capacitor is 22µF. The architecture of the TLV62150 allows the use of
tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output
voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
Note: In power save mode, the output voltage ripple depends on the output capacitance, Its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.
Input Capacitor
For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current
ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter
from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it's recommended to place a capacitance of 0.1uF from AVIN to AGND, to avoid
potential noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
Soft Start Capacitor
A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the
output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
2.5mA
[F]
1.25V
CSS = tSS
×
(10)
where
CSS is the capacitance (F) required at the SS/TR pin and
tSS is the desired soft-start ramp time (s).
spacing
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
spacing
Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the
FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 36.
spacing
VFB » 0.64×VSS /TR
(11)
VSS/TR
[V]
1.2
0.8
0.4
VFB [V]
0.2
0.4
0.6
0.8
Figure 36. Voltage Tracking Relationship
Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero,
independent of the tracking voltage. shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.
spacing
18
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
VOUT1
PVIN
AVIN
EN
SW
VOS
PG
TLV62150
SS/TR
DEF
FB
AGND
PGND
FSW
VOUT2
PVIN
AVIN
EN
SW
VOS
PG
R1
R2
TLV62150
SS/TR
DEF
FB
AGND
PGND
FSW
Figure 37. Sequence for Ratiometric and Simultaneous Startup
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as
VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start
up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft
start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing
circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider
tolerance than specified.
Output Filter And Loop Stability
The TLV62150 is internally compensated to be stable with L-C filter combinations corresponding to a corner
frequency to be calculated with Equation 12:
1
fLC
=
2p L × C
(12)
Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TLV62150 includes an internal 25pF feedforward capacitor, connected between the VOS and FB pins. This
capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the
feedback divider, per equation Equation 13 and Equation 14:
spacing
1
fzero
=
2p × R × 25pF
1
(13)
(14)
spacing
f pole
æ
ö
1
1
1
ç
ç
÷
÷
=
×
+
2p × 25pF
R
R
2
è
1
ø
spacing
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
Though the TLV62150 is stable without the pole and zero being in a particular location, adjusting their location to
the specific needs of the application can provide better performance in Power Save mode and/or improved
transient response. An external feedforward capacitor can also be added. A more detailed discussion on the
optimization for stability vs. transient response can be found in SLVA289 and SLVA466.
Layout Considerations
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TLV62150 demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Figure 38 for the recommended layout of the TLV62150, which is designed for common external ground
connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the
PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system
ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output
capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB
resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground
plane.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLAU416. Additionally, the
EVM Gerber data are available for download here, SLVC394.
20
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
GND
R2
R1
8
7
6
5
C
9
4
3
2
1
PG
10
11
12
AVIN
13
14
15
16
CIN
EN
L1
VOUT
COUT
GND
Figure 38. Layout Example
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TLV62150 is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum
output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by
the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of
the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To
get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and
thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal
performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
Application Example As Power LED Supply
The TLV62150 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Since this pin provides 2.5µA, the FB pin voltage can be adjusted by an external resistor
per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TLV62150.
Figure 39 shows an application circuit, tested with analog dimming:
spacing
2.2µH
PVIN
AVIN
EN
SW
VOS
PG
4.7uF
22uF
ADIM
TLV62150
SS/TR
DEF
FB
187k
0.3R
AGND
PGND
FSW
Figure 39. 1A Single LED Power Supply
The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15.
spacing
VFB = 0.64 × 2.5mA × RSS / TR
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used.
More information is available in the Application Note SLVA451.
Application Example As Inverting Power Supply
The TLV62150 can be used as inverting power supply by rearranging external circuitry as shown in Figure 40. As
the former GND node now represents a voltage level below system ground, the voltage difference between VIN
and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).
spacing
VIN +VOUT £VIN max
(16)
spacing
10uF
2.2µH
(4 .. 12)V
PVIN
AVIN
EN
SW
VOS
PG
10uF
680k
130k
TLV62150
22uF
SS/TR
DEF
FB
3.3nF
AGND
PGND
-5V
FSW
Figure 40. –5V Inverting Power Supply
spacing
22
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.
Typical Applications
spacing
spacing
spacing
(5 .. 17)V
1 / 2.2 µH
5V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
680k
130k
22uF
TLV62150
SS/TR
DEF
FB
3.3nF
3.3nF
3.3nF
AGND
PGND
FSW
Figure 41. 5V/1A Power Supply
spacing
spacing
spacing
(4 .. 17)V
1 / 2.2 µH
3.3V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
750k
240k
22uF
TLV62150
SS/TR
DEF
FB
AGND
PGND
FSW
Figure 42. 3.3V/1A Power Supply
spacing
spacing
spacing
(4 .. 17)V
1 / 2.2 µH
2.5V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
510k
240k
22uF
TLV62150
SS/TR
DEF
FB
AGND
PGND
FSW
Figure 43. 2.5V/1A Power Supply
spacing
spacing
spacing
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
(4 .. 17)V
1 / 2.2 µH
1.8V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
300k
240k
22uF
TLV62150
SS/TR
DEF
FB
3.3nF
AGND
PGND
FSW
Figure 44. 1.8V/1A Power Supply
spacing
spacing
(4 .. 17)V
1 / 2.2 µH
1.5V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
130k
150k
22uF
TLV62150
SS/TR
DEF
FB
3.3nF
AGND
PGND
FSW
Figure 45. 1.5V/1A Power Supply
spacing
spacing
(4 .. 17)V
1 / 2.2 µH
1.2V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
75k
22uF
TLV62150
SS/TR
DEF
FB
3.3nF
150k
AGND
PGND
FSW
Figure 46. 1.2V/1A Power Supply
spacing
spacing
(4 .. 17)V
1 / 2.2 µH
1V / 1A
PVIN
AVIN
EN
SW
VOS
PG
100k
10uF
51k
22uF
TLV62150
SS/TR
DEF
FB
3.3nF
200k
AGND
PGND
FSW
Figure 47. 1V/1A Power Supply
24
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
www.ti.com
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
Active Output Discharge
spacing
The TLV62150A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.
Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 48). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10mA.
spacing
(4 .. 17)V
1 / 2.2 µH
Vout / 1A
PVIN
AVIN
EN
SW
VOS
PG
TLV62150A
R3
10uF
R1
R2
22uF
SS/TR
DEF
FB
3.3nF
AGND
PGND
FSW
Figure 48. Discharge Vout through PG pin
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: TLV62150 TLV62150A
TLV62150, TLV62150A
SLVSB71B –FEBRUARY 2012–REVISED JUNE 2013
www.ti.com
REVISION HISTORY
Changes from Original (February 2012) to Revision A
Page
•
•
•
•
•
Added text to Terminal Functions table to clarify Description for AGND, PGND, and Exposed Thermal Pad. ................... 4
Changed Footnote 3 on Terminal Functions table for clarification. ...................................................................................... 4
Added text to Power Save Mode Operation section for clarification. ................................................................................. 13
Changed text in the Layout Considerations section for clarification. .................................................................................. 20
Changed Layout Example figure for clarification. ............................................................................................................... 21
Changes from Revision A (February 2013) to Revision B
Page
•
•
•
•
•
•
•
•
Added new device version TLV62150A to data sheet .......................................................................................................... 1
Added device TLV62150A to Ordering Info table ................................................................................................................. 2
Added text to Power Good section regarding the TLV62150A function. ............................................................................ 15
Added additional option to the footnote for Pin-Selectable Output Voltage (DEF) section. ............................................... 15
Added text to Frequency Selection (FSW) section regarding pin control. .......................................................................... 15
Added text to Tracking Function section for clarification. ................................................................................................... 18
Changed schematic for Figure 40 ....................................................................................................................................... 22
Added application example with regard to new version TLV62150A ................................................................................. 25
26
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2013
PACKAGING INFORMATION
Orderable Device
TLV62150ARGTR
TLV62150ARGTT
TLV62150RGTR
TLV62150RGTT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
QFN
QFN
QFN
QFN
RGT
16
16
16
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
VUOI
VUOI
VUCI
VUCI
ACTIVE
ACTIVE
ACTIVE
RGT
RGT
RGT
250
3000
250
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62150ARGTR
TLV62150ARGTT
TLV62150RGTR
TLV62150RGTT
QFN
QFN
QFN
QFN
RGT
RGT
RGT
RGT
16
16
16
16
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV62150ARGTR
TLV62150ARGTT
TLV62150RGTR
TLV62150RGTT
QFN
QFN
QFN
QFN
RGT
RGT
RGT
RGT
16
16
16
16
3000
250
552.0
552.0
552.0
552.0
367.0
185.0
367.0
185.0
36.0
36.0
36.0
36.0
3000
250
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明