TLV62568PDDCT [TI]
采用 SOT23 或 SOT563 封装的 2.5V 至 5.5V 输入、1A 高效降压转换器 | DDC | 6 | -40 to 125;
| 型号： | TLV62568PDDCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT23 或 SOT563 封装的 2.5V 至 5.5V 输入、1A 高效降压转换器 | DDC | 6 | -40 to 125 转换器 |
| 文件： | 总31页 (文件大小：1621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
TLV62568 采用 SOT 封装的 1A 高效同步降压转换器
1 特性
在中等负载或重载条件下，该器件运行在脉宽调制
1
(PWM) 模式下，开关频率为 1.5MHz。在轻载情况
下，该器件自动进入节能模式 (PSM)，从而在整个负
载电流范围内保持高效率。关断时，流耗减少至 2μA
以下。
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
效率高达 95%
低 RDS(ON)，可在 150mΩ 和 100mΩ 之间切换
输入电压范围：2.5V 至 5.5V
可调输出电压：0.6V 至 VIN
针对轻载效率的省电模式
针对最低压降的 100% 占空比
35µA 静态工作电流
TLV62568 的输出电压可通过一个外部电阻分压器进行
调节。内部软启动电路可限制启动期间的浪涌电流。此
外， 还内置了 诸如输出过流保护、热关断保护和电源
正常输出等其他特性。该器件提供 SOT-23 和
SOT563 两种封装。
1.5MHz 开关频率
电源正常输出指示
过流保护
器件信息(1)
内部软启动
器件型号
TLV62568
封装
SOT-23 (5)
封装尺寸（标称值）
热关断保护
采用小外形尺寸晶体管 (SOT) 封装
与 TLV62569 引脚兼容
借助 WEBENCH® 电源设计器，使用 TLV62568 创
建定制设计方案
2.90mm x 2.80mm
TLV62568P
TLV62568
TLV62568P
SOT-23 (6)
SOT563 (6)
SOT563 (6)
1.60mm x 1.60mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
2 应用
器件比较
•
•
•
•
通用负载点 (POL) 电源
器件编号
功能
封装标记
14VF
9X
网络视频摄像头
机顶盒
TLV62568DBV
TLV62568PDDC
TLV62568DRL
TLV62568PDRL
-
电源正常
-
无线路由器
18L
电源正常
18N
3 说明
TLV62568 器件是一款同步降压 DC-DC 转换器，专门
针对高效和紧凑型解决方案进行了优化。该器件集成的
开关能够提供高达 1A 的输出电流。
M M
简化电路原理图
5V 输入电压下的效率
VIN
VOUT
1.8 V / 1.0 A
TLV62568P
L1
2.2 µH
2.5 V to 5.5 V
100
95
90
85
80
75
70
65
60
VIN SW
C1
4.7 µF
C2
10 µF
C3*
R3
499 kꢀ
R1
200 kꢀ
EN
VPG
PG GND FB
R2
100 kꢀ
C3: Optional
Copyright Ú 2016, Texas Instruments Incorporated
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load (A)
1
D008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSD89
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 8
8
9
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application .................................................... 9
Power Supply Recommendations...................... 14
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations........................................ 15
11 器件和文档支持 ..................................................... 16
11.1 器件支持 ............................................................... 16
11.2 文档支持 ............................................................... 16
11.3 接收文档更新通知 ................................................. 16
11.4 社区资源................................................................ 16
11.5 商标....................................................................... 16
11.6 静电放电警告......................................................... 16
11.7 Glossary................................................................ 17
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
Changes from Revision A (April 2017) to Revision B
Page
•
•
•
•
已将 WEBENCH 链接添加至数据表 ....................................................................................................................................... 1
已更改 TLV62568PDDC 更改为生产状态............................................................................................................................... 1
Added DDC package thermal information.............................................................................................................................. 4
Changed 1.2 V From: MIN value To: MAX value for High-level threshold at EN pin............................................................. 5
Changes from Original (November 2016) to Revision A
Page
•
•
•
•
•
已更改 TLV62568DRL 和 TLV62568PDRL 更改为生产状态。 .............................................................................................. 1
将器件比较表移至第 1 页........................................................................................................................................................ 1
Added DRL package thermal information............................................................................................................................... 4
Added startup time of TLV62568DRL, TLV62568PDRL ....................................................................................................... 5
已添加 TLV62568PDRL layout. ............................................................................................................................................ 15
2
Copyright © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
5 Pin Configuration and Functions
SOT23-5
DBV Package
(Top View)
SOT23-6
DDC Package
(Top View)
SOT563-6
DRL Package
(Top View)
FB
5
VIN
4
FB
6
PG
5
VIN
NC/PG EN SW
4
6
1
5
2
4
3
1
2
3
1
2
3
FB GND VIN
EN
GND
SW
EN
GND
SW
Pin Functions
PIN NUMBER
I/O/PWR
DESCRIPTION
NAME
EN
SOT23-5
SOT23-6 SOT563-6
Device enable logic input. Logic high enables the device, logic low disables
the device and turns it into shutdown. Do not leave floating.
1
2
3
4
1
2
3
4
5
2
4
3
I
GND
SW
PWR
PWR
PWR
Ground pin.
Switch pin connected to the internal FET switches and inductor terminal.
Connect the inductor of the output filter to this pin.
VIN
Power supply voltage input.
Power good open drain output pin for TLV62568P. The pull-up resistor should
not be connected to any voltage higher than 5.5V. If it's not used, leave the
pin floating.
PG
-
5
6
O
Feedback pin for the internal control loop. Connect this pin to an external
feedback divider.
FB
5
-
6
-
1
6
I
No connection pin for TLV62568DRL. The pin can be connected to the output.
Or leave it floating.
NC
O
Copyright © 2016–2017, Texas Instruments Incorporated
3
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3.0
–0.3
–40
MAX
UNIT
V
VIN, EN, PG
6
VIN+0.3
9
SW (DC)
Voltage(2)
V
SW (AC, less than 10 ns)(3)
V
FB
5.5
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Functional operation of the
device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
MIN
2.5
TYP
MAX
5.5
VIN
1
UNIT
V
VIN
Input voltage
VOUT
IOUT
TJ
Output voltage
0.6
V
Output current
A
Operating junction temperature
–40
125
1
°C
mA
ISINK_PG Sink current at PG pin
(1) Refer to the Application and Implementation section for further information.
6.4 Thermal Information
DBV
(5 Pins)
DDC
(6 pins)
DRL
THERMAL METRIC(1)
UNIT
(6 pins)
149.8
45.7
31.1
1.3
RθJA
Junction-to-ambient thermal resistance
191.6
141.4
44.5
34.5
43.9
N/A
121.6
69.1
45.5
22.3
46.0
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
31.7
N/A
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
6.5 Electrical Characteristics
VIN = 5 V, TJ = 25°C, unless otherwise noted
PARAMETER
SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IQ
Quiescent current into VIN pin
Shutdown current into VIN pin
Under voltage lock out
Not switching
EN = 0 V
35
0.1
uA
µA
V
ISD
2
VIN falling
2.3
2.45
VUVLO
Under voltage lock out hysteresis
100
150
130
mV
Junction temperature rising
Junction temperature falling
TJSD
Thermal shutdown threshold
°C
LOGIC INTERFACE
VIH
VIL
High-level threshold at EN pin
2.5 V ≤ VIN ≤ 5.5 V
2.5 V ≤ VIN ≤ 5.5 V
TLV62568DBV
0.95
0.85
700
900
1.2
V
V
Low-level threshold at EN pin
0.4
tSS
Soft startup time
µs
TLV62568DRL, TLV62568PDRL,
TLV62568PDDC
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
ISINK = 1 mA
95%
90%
VPG
Power good threshold, TLV62568P
VPG,OL
IPG,LKG
tPG,DLY
OUTPUT
VFB
Power good low-level output voltage
Input leakage current into PG pin
Power good delay time
0.4
V
VPG = 5 V
0.01
40
µA
µs
VFB falling
Feedback regulation voltage
High-side FET on resistance
Low-side FET on resistance
High-side FET current limit
Switching frequency
0.588
1.5
0.6
150
100
0.612
V
RDS(on)
mΩ
ILIM
fSW
A
VOUT = 1.8 V
1.5
MHz
版权 © 2016–2017, Texas Instruments Incorporated
5
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6.6 Typical Characteristics
50
45
40
35
30
25
10
9
8
7
6
5
4
3
2
1
0
VIN = 2.5V
VIN = 3.6V
VIN = 5.0V
20
15
10
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-10
20
50
80
110
140
Input Voltage (V)
Junction Temperature (°C)
D001
D002
图 1. Quiescent Current vs Input Voltage
图 2. Shutdown Current vs Junction Temperature
0.3
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.2
0.1
0.0
-0.1
-0.2
-0.3
2.5
3.0
3.5
4.0
Input Voltage (V)
4.5
5.0
5.5
D003
图 3. FB Voltage Accuracy
6
版权 © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
7 Detailed Description
7.1 Overview
The TLV62568 is a high-efficiency synchronous step-down converter. The device operates with an adaptive off-
time with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the
required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the
variation of input voltage, output voltage, and load current.
7.2 Functional Block Diagram
PG
VIN
VPG
VFB
Thermal
Shutdown
+
Soft Start
UVLO
œ
GND
EN
FB
Control Logic
Peak Current Detect
VREF
SW
+
_
Gate
Drive
Modulator
VSW
VIN
TOFF
Zero Current Detect
GND
Power Good feature is only available in TLV62568P
GND
Copyright Ú 2016, Texas Instruments Incorporated
图 4. TLV62568 Functional Block Diagram
7.3 Feature Description
7.3.1 Power Save Mode
The device automatically enters Power Save Mode to improve efficiency at light load when the inductor current
becomes discontinuous. In Power Save Mode, the converter reduces switching frequency and minimizes current
consumption. In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect
is minimized by increasing the output capacitor.
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x (RDS(ON) + RL)
where
•
•
RDS(ON) = High side FET on-resistance
RL = Inductor ohmic resistance (DCR)
(1)
7.3.3 Soft Startup
After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output
voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance.
版权 © 2016–2017, Texas Instruments Incorporated
7
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Feature Description (接下页)
The TLV62568 is able to start into a pre-biased output capacitor. The converter starts with the applied bias
voltage and ramps the output voltage to its nominal value.
7.3.4 Switch Current Limit
The switch current limit prevents the device from high inductor current and drawing excessive current from a
battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.
The TLV62568 adopts the peak current control by sensing the current of the high-side switch. Once the high-side
switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down
the inductor current with an adaptive off-time.
7.3.5 Under Voltage Lockout
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down
the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.
7.3.6 Thermal Shutdown
The device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising
threshold, TJSD. Once the junction temperature falls below the falling threshold, the device returns to normal
operation automatically.
7.4 Device Functional Modes
7.4.1 Enabling/Disabling the Device
The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the
device is enabled, the internal power stage starts switching and regulates the output voltage to the set point
voltage. The EN input must be terminated and should not be left floating.
7.4.2 Power Good
The TLV62568P has a power good output. The PG pin goes high impedance once the output is above 95% of
the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.
表 1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
LOW
EN = High, VFB ≥ VPG
EN = High, VFB ≤ VPG
EN = Low
√
Enable
√
√
√
√
Shutdown
Thermal Shutdown
UVLO
TJ > TJSD
1.4 V < VIN < VUVLO
VIN ≤ 1.4 V
Power Supply Removal
√
8
版权 © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VIN
VOUT
1.8 V / 1.0 A
TLV62568P
VIN SW
L1
2.2 µH
2.5 V to 5.5 V
C1
C2
C3*
4.7 µF
10 µF
R3
499 kꢀ
R1
200 kꢀ
EN
VPG
PG GND FB
R2
C3: Optional
100 kꢀ
Copyright Ú 2016, Texas Instruments Incorporated
图 5. TLV62568 1.8-V Output Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
2.5 V to 5.5 V
1.8 V
Input voltage
Output voltage
Maximum output current
1.0 A
表 3 lists the components used for the example.
表 3. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER(1)
C1
C2
4.7 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A475KA73L
10 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A106KE51L
2.2 µH, Power Inductor, SDER041H-2R2MS
Murata
Murata
Cyntec
Std.
L1
R1,R2,R3
C3
Chip resistor,1%,size 0603
Optional, 6.8 pF if it is needed
Std.
(1) See Third-party Products Disclaimer
版权 © 2016–2017, Texas Instruments Incorporated
9
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62568 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting the Output Voltage
An external resistor divider is used to set output voltage according to 公式 2.
When sizing R2, in order to achieve low current consumption and acceptable noise sensitivity, use a maximum of
200 kΩ for R2. Larger currents through R2 improve noise sensitivity and output voltage accuracy but increase
current consumption.
R1
R2
R1
R2
æ
ö
÷
ø
æ
ö
÷
ø
VOUT = VFB ´ 1+
= 0.6V ´ 1+
ç
ç
è
è
(2)
A feed forward capacitor, C3 improves the loop bandwidth to make a fast transient response (shown in 图 19).
6.8-pF capacitance is recommended for R2 of 100-kΩ resistance. A more detailed discussion on the optimization
for stability vs. transient response can be found in SLVA289.
8.2.2.3 Output Filter Design
The inductor and output capacitor together provide a low-pass filter. To simplify this process, 表 4 outlines
possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for
stability by simulation and lab test. Further combinations should be checked for each individual application.
表 4. Matrix of Output Capacitor and Inductor Combinations
COUT [µF](2)
VOUT [V]
L [µH](1)
4.7
10
22
2x 22
100
0.6 ≤ VOUT < 1.2
1
2.2
1
+
++(3)
+
1.2 ≤ VOUT < 1.8
1.8 ≤ VOUT
+
++(3)
+
2.2
1
+
+
+
2.2
++(3)
+
+
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and -30%.
(2) Capacitor tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and -50%.
(3) This LC combination is the standard value and recommended for most applications.
10
版权 © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
8.2.2.4 Inductor Selection
The main parameters for inductor selection is inductor value and then saturation current of the inductor. To
calculate the maximum inductor current under static load conditions, 公式 3 is given:
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
where:
•
•
•
•
IOUT,MAX is the maximum output current
ΔIL is the inductor current ripple
fSW is the switching frequency
L is the inductor value
(3)
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor.
8.2.2.5 Input and Output Capacitor Selection
The architecture of the TLV62568 allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is
recommended to use X7R or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A
low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 4.7-µF input
capacitance is sufficient; a larger value reduces input voltage ripple.
The TLV62568 is designed to operate with an output capacitor of 10 µF to 47 µF, as outlined in 表 4.
版权 © 2016–2017, Texas Instruments Incorporated
11
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
8.2.3 Application Performance Curves
VIN = 5 V, VOUT = 1.8 V, L = 2.2 μH, TA = 25°C, unless otherwise noted.
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
VIN = 2.5 V
VIN = 3.3 V
VIN = 5.0 V
VIN = 2.5 V
VIN = 3.3 V
VIN = 5.0 V
1m
10m
100m
1
1m
10m
100m
1
Load (A)
Load (A)
D004
D005
图 6. 1.2-V Output Efficiency
图 7. 1.8-V Output Efficiency
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
VIN = 3.3 V
VIN = 5.0 V
VIN = 5.0 V
1m
10m
100m
1
1m
10m
100m
1
Load (A)
Load (A)
D007
D006
图 9. 3.3-V Output Efficiency
图 8. 2.5-V Output Efficiency
1.5
1
1.0
0.5
0.5
0
0.0
-0.5
-1
-0.5
VOUT = 1.8 V
VOUT = 3.3 V
IOUT = 0.5A
IOUT = 1.0A
-1.5
-1.0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Load (A)
Input Voltage (V)
D009
D010
VIN = 5 V
VOUT = 1.8 V
图 10. Load Regulation
图 11. Line Regulation
12
版权 © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
2500
2500
2000
1500
1000
500
2000
1500
1000
500
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
0
0
0
2.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Load (A)
1
3
3.5
4
4.5
5
5.5
Input Voltage (V)
D011
D012
VIN = 5 V
IOUT = 0.5 A
图 13. Switching Frequency vs Input Voltage
图 12. Switching Frequency vs Load
VSW
VSW
2V/DIV
2V/DIV
VOUT
10mV/DIV
AC
VOUT
20mV/DIV
AC
ICOIL
ICOIL
0.5A/DIV
0.5A/DIV
Time - 500ns/DIV
Time - 2ꢀs/DIV
D013
D014
IOUT = 0.5 A
IOUT = 0.1 A
图 15. Power Save Mode Operation
图 14. PWM Operation
VEN
VEN
3V/DIV
3V/DIV
VOUT
VOUT
1V/DIV
1V/DIV
ICOIL
ICOIL
1A/DIV
0.5A/DIV
Time - 250ꢀs/DIV
Time - 250ꢀs/DIV
D015
D016
IOUT = 1 A
IOUT = 0.1 A
图 16. Startup with Load
图 17. Startup with Load
版权 © 2016–2017, Texas Instruments Incorporated
13
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
VOUT
0.1V/DIV
VOUT
0.1V/DIV
ICOIL
0.5A/DIV
ICOIL
0.5A/DIV
Time - 10ꢀs/DIV
Time - 10ꢀs/DIV
D017
D018
Load Step 0.3 A to 1 A, 1A/µs slew rate
Load Step 0.3 A to 1 A, 1A/µs slew rate
C3 = 6.8 pF
图 18. Load Transient
图 19. Load Transient with a feed forward capacitor
9 Power Supply Recommendations
The power supply to the TLV62568 must have a current rating according to the supply voltage, output voltage
and output current.
14
版权 © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
10 Layout
10.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TLV62568 device.
•
The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
•
•
•
The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
The sense traces connected to FB are signal traces. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes.
GND layers might be used for shielding.
10.2 Layout Example
GND
L1
VIN
VOUT
R1
R2
PAC101
VIN
PAC601
SW
GND
EN
FB
GND
VIN
PG
EN
SW
FB
C2
C1
C2
C1
PAR202
PAR201
R2
R1
VIN
VOUT
L1
GND
图 20. TLV62568DBV Layout
图 21. TLV62568PDRL Layout
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow,
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component.
Two basic approaches for enhancing thermal performance are listed below:
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Notes SZZA017 and SPRA953.
版权 © 2016–2017, Texas Instruments Incorporated
15
TLV62568, TLV62568P
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 使用 WEBENCH® 工具定制设计方案
单击此处，使用 TLV62568 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 在开始阶段键入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
11.2 文档支持
11.2.1 相关文档
应用报告《半导体和 IC 封装热指标》（文件编号：SPRA953）
应用报告《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》（文件编号：SZZA017）
11.3 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
16
版权 © 2016–2017, Texas Instruments Incorporated
TLV62568, TLV62568P
www.ti.com.cn
ZHCSFQ3B –NOVEMBER 2016–REVISED NOVEMBER 2017
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2016–2017, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV62568DBVR
TLV62568DBVT
TLV62568DRLR
TLV62568DRLT
TLV62568PDDCR
TLV62568PDDCT
TLV62568PDRLR
TLV62568PDRLT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
DRL
DRL
DDC
DDC
DRL
DRL
5
5
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
14VF
14VF
18L
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU | SN
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
SOT-5X3
SOT-5X3
18L
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
(9X9, 9XW)
(9X9, 9XW)
18N
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
18N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Sep-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62568DBVR
TLV62568DBVT
TLV62568DRLR
TLV62568DRLT
TLV62568PDDCR
SOT-23
SOT-23
DBV
DBV
DRL
DRL
DDC
5
5
6
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
3.2
3.2
2.0
2.0
3.2
3.2
3.2
1.8
1.8
3.2
1.4
1.4
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
SOT-5X3
SOT-5X3
3000
250
0.75
0.75
1.4
SOT-23-
THIN
3000
TLV62568PDDCT
SOT-23-
THIN
DDC
6
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV62568PDRLR
TLV62568PDRLT
SOT-5X3
SOT-5X3
DRL
DRL
6
6
3000
250
180.0
180.0
8.4
8.4
2.0
2.0
1.8
1.8
0.75
0.75
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV62568DBVR
TLV62568DBVT
TLV62568DRLR
TLV62568DRLT
TLV62568PDDCR
TLV62568PDDCT
TLV62568PDRLR
TLV62568PDRLT
SOT-23
SOT-23
DBV
DBV
DRL
DRL
DDC
DDC
DRL
DRL
5
5
6
6
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
SOT-5X3
3000
250
SOT-5X3
SOT-23-THIN
SOT-23-THIN
SOT-5X3
3000
250
3000
250
SOT-5X3
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TLV62568PDRLR
采用 SOT23 或 SOT563 封装的 2.5V 至 5.5V 输入、1A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62568PDRLT
采用 SOT23 或 SOT563 封装的 2.5V 至 5.5V 输入、1A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569
采用 SOT23 或 SOT563 封装的 2.5V-5.5V 输入、2A 高效降压转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569A
采用 SOT 封装并具有强制 PWM 的 2A 高效降压转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569ADRLR
采用 SOT 封装并具有强制 PWM 的 2A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569ADRLT
采用 SOT 封装并具有强制 PWM 的 2A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569APDRLR
采用 SOT 封装并具有强制 PWM 的 2A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569APDRLT
采用 SOT 封装并具有强制 PWM 的 2A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569DBVR
采用 SOT23 或 SOT563 封装的 2.5V-5.5V 输入、2A 高效降压转换器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569DBVT
采用 SOT23 或 SOT563 封装的 2.5V-5.5V 输入、2A 高效降压转换器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569DRLR
采用 SOT23 或 SOT563 封装的 2.5V-5.5V 输入、2A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV62569DRLT
采用 SOT23 或 SOT563 封装的 2.5V-5.5V 输入、2A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明