TLV62569APDRLT [TI]
采用 SOT 封装并具有强制 PWM 的 2A 高效降压转换器 | DRL | 6 | -40 to 125;
| 型号： | TLV62569APDRLT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 SOT 封装并具有强制 PWM 的 2A 高效降压转换器 | DRL | 6 | -40 to 125 转换器 |
| 文件： | 总23页 (文件大小：1844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
采用 SOT563 封装并具有强制 PWM 的 TLV6256xA 1A、2A 降压转换器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
强制 PWM 模式可减少输出电压纹波
TLV62568A、TLV62569A 器件是经过优化而具有高效
率和紧凑型解决方案尺寸的同步降压型直流/直流转换
器。该器件集成了输出电流高达 2A 的开关。在整个负
载范围内，该器件将以 1.5MHz 开关频率在脉宽调制
(PWM) 模式下运行。关断时，流耗减少至 2μA 以下。
效率高达 95%
低 RDS(ON) 开关：100mΩ/60mΩ
输入电压范围为 2.5V 至 5.5V
可调输出电压范围为 0.6V 至 VIN
100% 占空比，可实现超低压降
1.5MHz 典型开关频率
内部软启动电路可限制启动期间的浪涌电流。此外，
还内置了 诸如输出过流保护、热关断保护和电源正常
输出等其他特性。该器件采用 SOT563 封装。
电源正常输出
过流保护
器件信息(1)
内部软启动
器件型号
封装
封装尺寸（标称值）
热关断保护
TLV62568ADRL
TLV62568APDRL
TLV62569ADRL
TLV62569APDRL
采用 SOT563 封装
与 TLV62568、TLV62569 引脚对引脚兼容
借助 WEBENCH® 电源设计器创建定制设计方案
SOT563 (6)
1.60mm x 1.60mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
•
•
•
•
•
通用负载点 (POL) 电源
器件比较
STB 和 DVR
器件型号
输出电流
功能
IP 网络摄像头
TLV62568ADRL
TLV62568APDRL
TLV62569ADRL
TLV62569APDRL
-
无线路由器
1A
电源正常
-
固态硬盘 (SSD) – 企业级
2A
电源正常
sp
sp
sp
sp在 5V 输入电压下的效率
sp典型应用原理图
VIN
2.5 V to 5.5 V
VOUT
1.8 V / 2.0 A
100
95
90
85
80
75
70
65
60
TLV62569A
L1
1.0 µH
VIN
SW
C1
4.7 µF
C2
22 µF
C3*
R1
200 kꢀ
EN
GND FB
R2
100 kꢀ
C3: Optional
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
Copyright Ú 2016, Texas Instruments Incorporated
0.0
0.5
1.0
Load (A)
1.5
2.0
D008
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSE95
TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Typical Characteristics.............................................. 5
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagrams ....................................... 6
7.3 Feature Description................................................... 6
7.4 Device Functional Modes.......................................... 7
8
9
Application and Implementation .......................... 8
8.1 Application Information.............................................. 8
8.2 Typical Application .................................................... 8
Power Supply Recommendations...................... 13
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
10.3 Thermal Considerations........................................ 14
11 器件和文档支持 ..................................................... 14
11.1 器件支持 ............................................................... 14
11.2 文档支持 ............................................................... 14
11.3 接收文档更新通知 ................................................. 14
11.4 支持资源................................................................ 14
11.5 商标....................................................................... 15
11.6 静电放电警告......................................................... 15
11.7 Glossary................................................................ 15
12 机械、封装和可订购信息....................................... 15
7
4 修订历史记录
Changes from Revision A (May 2018) to Revision B
Page
•
已更改 Power Good pin sink current capability from 1 mA to 2 mA ...................................................................................... 7
Changes from Original (April 2018) to Revision A
Page
•
已更改 将状态从“预告信息”更改为“生产数据” ........................................................................................................................ 1
2
Copyright © 2018–2020, Texas Instruments Incorporated
TLV62568A, TLV62569A
www.ti.com.cn
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
5 Pin Configuration and Functions
SOT563-6
DRL Package
(Top View)
NC/PG EN SW
6
1
5
2
4
3
FB GND VIN
Pin Functions
SOT563-6
NAME
I/O/PWR
DESCRIPTION
PIN
NUMBER
FB
1
2
3
I
Feedback pin for the internal control loop. Connect this pin to an external feedback divider.
GND
VIN
PWR
PWR
Ground pin.
Power supply voltage input.
Switch pin connected to the internal FET switches and inductor terminal. Connect the inductor of
the output filter to this pin.
SW
EN
PG
NC
4
5
6
6
PWR
Device enable logic input. Logic high enables the device, logic low disables the device and turns
it into shutdown. Do not leave floating.
I
O
-
Power good open drain output pin for TLV62569APDRL. The pull-up resistor should not be
connected to any voltage higher than 5.5V. If it's not used, leave the pin floating.
No connection pin for TLV62569ADRL. The pin can be connected to the output or the ground for
enhancing thermal performance. Or leave it floating.
6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-3.0
-0.3
-40
MAX
UNIT
VIN, EN, PG
6
SW (DC)
Voltage(2)
VIN + 0.3
V
SW (AC, less than 10ns)(3)
9
FB
3
TJ
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
-65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2018–2020, Texas Instruments Incorporated
3
TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
www.ti.com.cn
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
0.6
0
NOM
MAX
UNIT
V
VIN
Input voltage
5.5
VIN
2
VOUT
IOUT
TJ
Output voltage
Output current
Junction temperature
V
A
-40
125
°C
6.4 Thermal Information
TLV62568Ax, TLV62569Ax
(1)
THERMAL METRIC
JEDEC (DRL)
EVM (DRL)
6 PINS
UNIT
6 PINS
142.8
51.1
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
124.8
°C/W
°C/W
°C/W
°C/W
°C/W
(2)
n/a
(2)
28.9
n/a
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.4
1.6
ΨJB
28.7
23.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM.
6.5 Electrical Characteristics
VIN = 5.0 V, TJ = 25 °C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
ISD
Shutdown current into VIN pin
Under voltage lock out
EN = 0 V
0.01
2.3
2
µA
V
VIN falling
2.45
VUVLO
under voltage lock out hysteresis
100
150
130
mV
TJ rising
TJ falling
TJSD
Thermal shutdown
°C
LOGIC INTERFACE
VIH
VIL
High-level input voltage at EN pin
2.5 ≤ VIN ≤ 5.5
2.5 ≤ VIN ≤ 5.5
1.2
V
V
Low-level input voltage at EN pin
0.4
0.4
From EN high to 95% of VOUT
nominal
tSS
Soft startup time
0.9
ms
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
ISINK = 1 mA
95%
90%
VPG
Power good threshold
VPG,OL
IPG,LKG
tPG,DLY
Low-level output voltage at PG pin
Input leakage current into PG pin
Power good delay time
V
VPG = 5 V
100
40
nA
µs
VFB falling
4
Copyright © 2018–2020, Texas Instruments Incorporated
TLV62568A, TLV62569A
www.ti.com.cn
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
Electrical Characteristics (continued)
VIN = 5.0 V, TJ = 25 °C, unless otherwise noted
PARAMETER
OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VFB
IFB
Feedback regulation voltage
Input leakage current into FB pin
High-side FET on resistance
Low-side FET on resistance
0.588
0.6
10
0.612
V
VFB = 0.6 V
nA
100
60
RDS(on)
mΩ
TLV62569A, TLV62569AP
TLV62568A, TLV62568AP
3
2
ILIM
fSW
High-side FET current limit
Switching frequency
A
1.5
MHz
6.6 Typical Characteristics
0.606
0.603
0.600
0.597
0.594
0.5
VIN = 2.5V
VIN = 3.6V
VIN = 5.0V
0.4
0.3
0.2
0.1
0.0
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
2.5
3.0
3.5
4.0
Input Voltage (V)
4.5
5.0
5.5
-40
-20
0
20
40
60
Junction Temperature (°C)
80
100
120
D003
D002
图 2. FB Voltage Accuracy
图 1. Shutdown Current vs Junction Temperature
4.0
3.0
2.5
2.0
1.5
3.5
3.0
2.5
VIN = 2.7V
VIN = 3.6V
VIN = 5.0V
VIN = 2.7V
VIN = 3.6V
VIN = 5.0V
-40
-20
0
20
Junction Temperature (°C)
40
60
80
100
120
-40
-20
0
20
Junction Temperature (°C)
40
60
80
100
120
D020
D021
图 3. Switch Current Limit, TLV62569A
图 4. Switch Current Limit, TLV62568A
版权 © 2018–2020, Texas Instruments Incorporated
5
TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
www.ti.com.cn
7 Detailed Description
7.1 Overview
The device is a high-efficiency synchronous step-down converter. The device operates with an adaptive off time
with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width modulation
(PWM) . Based on the VIN/VOUT ratio, a simple circuit sets the required off time for the low-side MOSFET. It
makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and
load current.
7.2 Functional Block Diagrams
PG
VIN
VPG
VFB
Thermal
Shutdown
+
Soft Start
UVLO
œ
GND
EN
Control Logic
Peak Current Detect
VREF
SW
+
_
Gate
Drive
Modulator
FB
VSW
VIN
TOFF
GND
GND
Copyright Ú 2018, Texas Instruments Incorporated
图 5. TLV62569A Functional Block Diagram
7.3 Feature Description
7.3.1 100% Duty Cycle Low Dropout Operation
The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x (RDS(ON) + RL)
where
•
•
RDS(ON) = High side FET on-resistance
RL = Inductor ohmic resistance (DCR)
(1)
7.3.2 Soft Startup
After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output
voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance.
6
版权 © 2018–2020, Texas Instruments Incorporated
TLV62568A, TLV62569A
www.ti.com.cn
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
Feature Description (接下页)
The device is able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage
and ramps the output voltage to its nominal value.
7.3.3 Switch Current Limit
The switch current limit prevents the device from high inductor current and drawing excessive current from a
battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.
The device adopts the peak current control by sensing the current of the high-side switch. Once the high-side
switch current limit is reached, the high-side switch is turned off and low-side switch is turned on to ramp down
the inductor current with an adaptive off-time.
7.3.4 Under Voltage Lockout
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down
the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.
7.3.5 Thermal Shutdown
The device enters thermal shutdown once the junction temperature exceeds the thermal shutdown rising
threshold, TJSD. Once the junction temperature falls below the falling threshold, the device returns to normal
operation automatically.
7.4 Device Functional Modes
7.4.1 Enabling/Disabling the Device
The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the
device is enabled, the internal power stage starts switching and regulates the output voltage to the set point
voltage. The EN input must be terminated and should not be left floating.
7.4.2 Power Good
The TLV62568AP and TLV62569AP have a power good output. The PG pin goes high impedance once the
output is above 95% of the nominal voltage, and is driven low once the output voltage falls below typically 90%
of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 2 mA. The power good
output requires a pull-up resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for
sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected
when not used.
表 1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
LOW
EN = High, VFB ≥ VPG
EN = High, VFB ≤ VPG
EN = Low
√
Enable
√
√
√
√
Shutdown
Thermal Shutdown
UVLO
TJ > TJSD
1.4 V < VIN < VUVLO
VIN ≤ 1.4 V
Power Supply Removal
√
版权 © 2018–2020, Texas Instruments Incorporated
7
TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VIN
2.5 V to 5.5 V
VOUT
1.8 V / 2.0 A
TLV62569A
L1
1.0 µH
VIN
SW
C1
4.7 µF
C2
22 µF
C3*
R1
200 kꢀ
EN
GND FB
R2
100 kꢀ
C3: Optional
Copyright Ú 2016, Texas Instruments Incorporated
图 6. TLV62569A 1.8-V Output Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.5 V to 5.5 V
1.8 V
Output voltage
Maximum output current
2.0 A
表 3 lists the components used for the example.
表 3. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER(1)
C1
C2
4.7 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A475KA73L
22 µF, Ceramic Capacitor, 6.3 V, X7T, size 0805, GRM21BD70J226ME44
1.0 µH, Power Inductor, size 4mmx4mm, XAL4020-102ME
Chip resistor,1%,size 0603
Murata
Murata
Coilcraft
Std.
L1
R1,R2,R3
C3
Optional, 10 pF if it is needed
Std.
(1) See Third-party Products Disclaimer
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62569A device with the WEBENCH® Power Designer.
8
版权 © 2018–2020, Texas Instruments Incorporated
TLV62568A, TLV62569A
www.ti.com.cn
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting the Output Voltage
An external resistor divider is used to set output voltage according to 公式 2.
When sizing R2, in order to achieve low current consumption and acceptable noise sensitivity, use a maximum of
200 kΩ for R2. Larger currents through R2 improve noise sensitivity and output voltage accuracy but increase
current consumption.
R1
R2
R1
R2
æ
ö
÷
ø
æ
ö
÷
ø
VOUT = VFB ´ 1+
= 0.6V ´ 1+
ç
ç
è
è
(2)
A feed forward capacitor, C3 improves the loop bandwidth to make a fast transient response (shown in 图 24). A
10-pF capacitance is recommended for R2 of 100-kΩ resistance. A more detailed discussion on the optimization
for stability vs. transient response can be found in SLVA289.
8.2.2.3 Output Filter Design
The inductor and output capacitor together provide a low-pass filter. To simplify this process, 表 4 outlines
possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for
stability by simulation and lab test. Further combinations should be checked for each individual application.
表 4. Matrix of Output Capacitor and Inductor Combinations
COUT [µF](2)
VOUT [V]
L [µH](1)
4.7
10
22
47
+
100
0.6 ≤ VOUT < 1.2
1.2 ≤ VOUT
1
1
++(3)
+
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and -30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and -50%.
(3) This LC combination is the standard value and recommended for most applications.
8.2.2.4 Inductor Selection
The main parameters for inductor selection is inductor value and then saturation current of the inductor. To
calculate the maximum inductor current under static load conditions, 公式 3 is given:
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
where:
•
•
IOUT,MAX is the maximum output current
ΔIL is the inductor current ripple
版权 © 2018–2020, Texas Instruments Incorporated
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TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
www.ti.com.cn
•
•
fSW is the switching frequency
L is the inductor value
(3)
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor.
8.2.2.5 Input and Output Capacitor Selection
The architecture of the device allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is
recommended to use X7T or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A
low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 4.7-μF input
capacitance is sufficient; a larger value reduces input voltage ripple.
The device is designed to operate with an output capacitor of 22 µF to 47 µF, as outlined in 表 4.
8.2.3 Application Performance Curves
VIN = 5 V, VOUT = 1.8 V, TA = 25 °C, external components shown in 表 3, unless otherwise noted.
10
8
95
90
85
80
75
70
65
60
55
6
4
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
2
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
0
2.5
3.0
3.5
4.0
Input Voltage (V)
4.5
5.0
5.5
0.0
0.5
1.0
Load (A)
1.5
2.0
D001
D005
VOUT = 0.6 V
图 7. Quiescent Current
图 8. 0.6-V Output Efficiency
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
0.0
0.5
1.0
Load (A)
1.5
2.0
0.0
0.5
1.0
Load (A)
1.5
2.0
D006
D004
图 9. 1.2-V Output Efficiency
图 10. 1.8-V Output Efficiency
10
版权 © 2018–2020, Texas Instruments Incorporated
TLV62568A, TLV62569A
www.ti.com.cn
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
60
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 4.2 V
VIN = 5.0 V
60
0.0
0.5
1.0
Load (A)
1.5
2.0
0.0
0.5
1.0
Load (A)
1.5
2.0
D019
D007
图 11. 2.5-V Output Efficiency
图 12. 3.3-V Output Efficiency
1.00
0.50
100
95
90
85
80
75
70
65
0.00
-0.50
VOUT = 0.6 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 3.3 V
-1.00
60
0.0
0.5
1.0
Load (A)
1.5
2.0
0.0
0.5
1.0
Load (A)
1.5
2.0
D009
D008
VIN = 5 V
图 14. Load Regulation
图 13. 5.0-V Input Efficiency
1.00
0.50
0.00
-0.50
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VOUT = 0.6 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 3.3 V
TA = 25°C
TA = 65°C
TA = 85°C
-1.00
2.5
3.0
IOUT = 1 A
3.5
4.0
Input Voltage (V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
Input Voltage (V)
4.5
5.0
5.5
D010
D019
PG is high
图 15. Line Regulation
图 16. Maximum Output Current at VOUT = 1.8 V
版权 © 2018–2020, Texas Instruments Incorporated
11
TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
www.ti.com.cn
2000
1500
2000
1500
1000
500
0
1000
VOUT = 0.6 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 0.6 V
VOUT = 1.2 V
500
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
0
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
0
0.5
1
Load (A)
1.5
2
D012
D011
IOUT = 1 A
VIN = 5 V
图 18. Switching Frequency vs Input Voltage
图 17. Switching Frequency vs Load
VSW
VSW
5V/DIV
5V/DIV
ICOIL
ICOIL
0.5A/DIV
0.5A/DIV
VOUT
10mV/DIV
AC
VOUT
10mV/DIV
AC
Time - 500ns/DIV
Time - 500ns/DIV
D014
D013
IOUT = 36 mA
IOUT = 1 A
图 19. PWM Operation
图 20. PWM Operation
VEN
VEN
2V/DIV
2V/DIV
VOUT
VOUT
0.5V/DIV
0.5V/DIV
ICOIL
ICOIL
1A/DIV
0.5A/DIV
Time - 200ꢀs/DIV
Time - 500ꢀs/DIV
D015
D016
Load = 0.9 Ω
图 21. Startup and Shutdown with Load
Load = 9 Ω
图 22. Startup and Shutdown with Load
12
版权 © 2018–2020, Texas Instruments Incorporated
TLV62568A, TLV62569A
www.ti.com.cn
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
VOUT
0.1V/DIV
AC
VOUT
0.1V/DIV
AC
ICOIL
ICOIL
0.5A/DIV
0.5A/DIV
Time - 20ꢀs/DIV
Time - 20ꢀs/DIV
D017
D018
Load Step 0 A to 1 A, 1A/μs slew rate
图 23. Load Transient
Load Step 0 A to 1 A, 1A/μs slew rate
C3 = 10 pF
图 24. Load Transient with A Feed Forward Capacitor
9 Power Supply Recommendations
The power supply to the TLV62569A must have a current rating according to the supply voltage, output voltage
and output current.
10 Layout
10.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TLV62569A device.
•
The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
•
•
•
The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
The sense traces connected to FB are signal traces. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes.
GND layers might be used for shielding.
10.2 Layout Example
GND
R1
R2
FB
GND
VIN
PG
EN
SW
C2
C1
VIN
VOUT
L1
图 25. TLV62569APDRL Layout
版权 © 2018–2020, Texas Instruments Incorporated
13
TLV62568A, TLV62569A
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
www.ti.com.cn
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow,
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component.
Two basic approaches for enhancing thermal performance are listed below:
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Notes SZZA017 and SPRA953.
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 开发支持
11.1.2.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 TLV62569A 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 文档支持
11.2.1 相关文档
•
•
德州仪器 (TI)，《半导体和 IC 封装热指标》 应用报告
德州仪器 (TI)，《采用 JEDEC PCB 设计的线性和逻辑封装热工特性》 应用报告
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14
版权 © 2018–2020, Texas Instruments Incorporated
TLV62568A, TLV62569A
www.ti.com.cn
ZHCSI23B –APRIL 2018–REVISED MARCH 2020
11.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2020, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV62568ADRLR
TLV62568ADRLT
TLV62568APDRLR
TLV62568APDRLT
TLV62569ADRLR
TLV62569ADRLT
TLV62569APDRLR
TLV62569APDRLT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
DRL
DRL
DRL
DRL
6
6
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1BE
1BE
1BF
1BF
1BG
1BG
1BH
1BH
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62568ADRLR
TLV62568ADRLT
TLV62568APDRLR
TLV62568APDRLT
TLV62569ADRLR
TLV62569ADRLT
TLV62569APDRLR
TLV62569APDRLT
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
DRL
DRL
DRL
DRL
6
6
6
6
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0.75
0.75
0.75
0.75
0.75
0.75
0.75
0.75
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Nov-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV62568ADRLR
TLV62568ADRLT
TLV62568APDRLR
TLV62568APDRLT
TLV62569ADRLR
TLV62569ADRLT
TLV62569APDRLR
TLV62569APDRLT
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
DRL
DRL
DRL
DRL
6
6
6
6
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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TI
TLV62569PDRLT
采用 SOT23 或 SOT563 封装的 2.5V-5.5V 输入、2A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6256x
TLV6256x 1.5-A High Efficiency Step-Down Converters in SOT-23 5-Pin PackageWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV62585
采用 2x2 QFN 或 SOT563 封装的 2.5V-5.5V 输入、3A 高效降压转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV62585DRLR
采用 2x2 QFN 或 SOT563 封装的 2.5V-5.5V 输入、3A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV62585DRLT
采用 2x2 QFN 或 SOT563 封装的 2.5V-5.5V 输入、3A 高效降压转换器 | DRL | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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